JP2008145893A - Display memory, display device and portable electronic information device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce the power consumption by suppressing unnecessary power consumption even during write of display data in a low gradation display mode. <P>SOLUTION: A first memory A where partial bits such as the most significant bit of bit width of each color data of RGB or the like are stored and a second memory B where the other bits are stored are composed as blocks separate from each other, and the memories A and B can be accessed independently of each other through each of a memory I/F input circuit 11 and a memory I/F output circuit 12. In a normal display mode, the memories A and B are accessed together to read or write data. In the low gradation display mode, only the memory A is accessed to read or write necessary bits, and the memory B is not accessed and is set to a stopped state. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a display memory in which the number of bits is set in accordance with a required display gradation number, a display device such as a liquid crystal display device provided with the display memory, and a mobile phone such as a mobile phone equipped with the display device. Type electronic information equipment.

  In recent years, as a portable electronic information device, especially in a mobile phone, the resolution of display has increased, and the number of memories necessary for display has also increased. For this reason, there is a contradictory tendency of causing an increase in power consumption in a mobile phone whose power consumption is severely limited by battery driving.

  However, in recent mobile phones with cameras, the number of display gradations is increased, but there are cases in which functions are sufficiently achieved by low gradation display of 8 colors (RGB 1 bit each) like text display of e-mails and the like.

  FIG. 2 is a block diagram showing a configuration example of a main part of a TFT (thin film transistor) type liquid crystal display device which is a typical example of a conventional active matrix driving method.

  In FIG. 2, the conventional liquid crystal display device 100 is provided with a liquid crystal display section and a liquid crystal driving circuit (liquid crystal driving section) as a display driving section for driving the liquid crystal display section.

  A TFT type liquid crystal panel 101 is mounted on the liquid crystal display unit. In the liquid crystal panel 101, a liquid crystal display element (not shown) and a counter electrode (common electrode) 102 described later are provided.

  Further, the liquid crystal driving circuit includes a source driver unit 103 and a gate driver unit 104 made of an IC (integrated circuit), a controller 105 for driving and controlling these, and a power supply to the source driver unit 103 and the gate driver unit 104 ( And a liquid crystal driving power source 106 for power supply).

  Display data D and display control signal S 1 are supplied from the controller 105 to the source driver unit 103, and display control signal S 2 is supplied from the controller 105 to the gate driver unit 104. Further, a horizontal synchronization signal (not shown) is supplied to the source driver unit 103 and the gate driver unit 104. Further, a REV signal is supplied from the controller 105 to the liquid crystal driving power source 106.

  In this conventional liquid crystal display device 100, image data (display data) input from the outside is input to the source driver unit 103 as image data D that is a digital signal via the controller 105.

  In the source driver unit 103, the input image data D is time-divided and temporarily latched by the first source driver SD11 to the n-th source driver SD1n, and then D / A (digital / digital) in synchronization with the horizontal synchronizing signal. (Analog) converted.

  In this way, an analog voltage for gradation display (hereinafter referred to as gradation display voltage) obtained by D / A converting the time-divided image data D is supplied via a source signal line (not shown). Then, it is output to the liquid crystal display element of each corresponding pixel portion in the liquid crystal panel 101 and displayed.

  FIG. 3 is a block diagram showing an example of a main configuration of a conventional display memory provided in the controller 105 of FIG.

  3, the conventional display memory 20 provided in the controller 105 of FIG. 2 includes one memory B, a memory I / F (interface) input circuit 21 used when writing image data into the memory B, And a memory I / F (interface) output circuit 22 used when image data is read from the memory B.

  With the above configuration, the memory B can be accessed by a write enable signal from the memory I / F input circuit 21 at the time of data writing, and the memory B can be accessed by a read enable signal from the memory I / F circuit 22 at the time of data reading. Accessible.

  When the controller 105 is designed, the display memory 20 shown in FIG. 3 having a storage capacity corresponding to the required display resolution and the number of colors is configured.

  For example, in QVGA (240 pixels × 320 pixels), in the case of 24-bit color (RGB each 8 bits, 8 × 3 bits), memory of 240 × 24 × 320 = 1,843,200 bits is required. Is done.

  In such a display memory 20, in the case of 24-bit color, RGB 8-bit image data (Rdata 8 bits, Gdata 8 bits, Bdata 8 bits) is input / output to / from the memory B.

  Further, in the all gradation display mode, all bits of each color data are output from the memory I / F output circuit 22. For example, in the low gradation display mode of 8 colors display (RGB each 1 bit), from the memory I / F output circuit 22. Therefore, only the upper one bit is output as the display data, and the remaining lower bits are not output as the display data, thereby reducing the power consumption.

  For example, in a mobile phone, a device has been devised to reduce power consumption by displaying a partial display for displaying a part of the display screen instead of displaying the full screen. In this partial display, time display, e-mail, incoming call information, etc. are displayed. In this case, when displaying an image, 8-color display (1 × 3 bits) is used instead of multicolor display. It is often done. During this partial display, the display screen of the mobile phone is generally in a standby screen state, and the display operation is performed with a minimum amount of power. In the case of partial display, when the display information changes, it is necessary to perform the operation with minimum power consumption.

  However, when all the bits of the RGB data are read from the display memory 20 in the low gradation display mode such as 8-color display capable of reducing power consumption, unnecessary power such as precharging to unnecessary bit lines is generated. End up. By not reading unnecessary bits, it is possible to further reduce power consumption.

Thus, for example, Patent Document 1 discloses a display memory that can reduce wasteful power consumption by performing control so that only necessary bits of image data are read and unnecessary bits are not read. .
JP 2002-40979 A

  However, as described above, in the conventional display memory, as described above, it is unnecessary to read out all the RGB bits from the display memory in the low gradation display mode such as 8-color display capable of reducing power consumption. Power is generated.

  As a solution to this problem, the conventional display memory disclosed in Patent Document 1 has been devised so that unnecessary bits are not read out when reading display data from the display memory. At the time of data writing, even if there are unnecessary bits, display data of all bits is written, and accordingly, unnecessary power is generated.

  The present invention solves the above-mentioned conventional problems, and suppresses unnecessary power consumption even when writing display data in the low gradation display mode, and can further reduce power consumption. It is an object of the present invention to provide a display device such as a liquid crystal display device including a portable electronic information device such as a mobile phone equipped with the display device.

  The display memory of the present invention is a display memory in which the number of bits is set in accordance with a required display gradation number, and a first memory in which some bits of the bit width of each color data are stored, and the remaining other Another memory in which bits are stored is configured as a separate block, and memory access means is provided that allows the first memory and the other memory to be independently accessed when writing and reading data. Therefore, the above object can be achieved.

  Preferably, display data is written to and read from the first memory and the other memory via the memory access means in the normal display mode in the display memory of the present invention, and in the special display mode, Display data is written to and read from only the first memory via the memory access means.

  Further, preferably, in the special display mode of the display memory of the present invention, writing and reading of display data to and from the other memory are stopped by the memory access means.

  Further preferably, when the other memory in the display memory of the present invention is two or more memories including a second memory and another memory, the first memory, the second memory, and the further memory are It is configured as a separate block, and when the data is written to and read from the first memory, the second memory, and the other memory, the memory access means causes the first memory, the second memory, and The other memories can be accessed independently of each other.

  Further preferably, in the display memory of the present invention, in the normal display mode, display data is written to and read from the first memory, the second memory and the other memory via the memory access means. In the first special display mode, display data is written to and read from only the first memory or the second memory via the memory access means, and in the second special display mode, the memory access means Display data is written to and read from only the first memory and the second memory via the.

  Further preferably, in the first special display mode in the display memory according to the present invention, writing and reading of display data to and from the second memory or the first memory and the other memory are stopped by the memory access means. In the second special display mode, writing and reading of display data to and from the other memory is stopped by the memory access means.

  Further preferably, the normal display mode in the display memory of the present invention is a full gradation display mode, and the special display mode is a low gradation display mode.

  Further preferably, the partial bit in the display memory of the present invention is the most significant 1 bit of each color data.

  Further preferably, the partial bits in the display memory of the present invention are the upper 2 bits or the upper 3 bits of each color data.

  Further preferably, each color data in the display memory of the present invention has a respective bit width of 8-bit RGB data, 5-bit, 6-bit and 5-bit RGB data, or 6-bit RGB data. Yes.

  Furthermore, it is preferable that the display memory according to the present invention includes a frame memory for reading and displaying each color data, a partial memory for partial screen display, or a plurality of line memories.

  Further preferably, the memory access means in the display memory according to the present invention comprises: memory input means for writing display data independently into the first memory and the other memory; and the first memory and the harm other memory. Memory output means for reading display data independently from each other.

  Further, preferably, the other memory in the display memory of the present invention is configured as a separate block from one or a plurality of memories.

  The display device of the present invention includes a display panel having a display screen, a source driver and a gate driver for driving the display panel, and supplying display data and display control signals to the source driver and displaying the display on the gate driver. A controller for supplying a control signal, and the display memory of the present invention is provided in the controller, whereby the above object can be achieved.

  According to the portable electronic information device of the present invention, the display memory of the present invention is mounted on a display drive unit of a display device, whereby the above object can be achieved.

  The operation of the present invention will be described below with the above configuration.

  In the present invention, among the bit widths of each color data such as RGB, for example, a first memory in which some bits such as the most significant bit and upper several bits are stored, and other bits in which other remaining bits are stored. The memory is divided into separate blocks. Each memory can be independently accessed at the time of data writing and data reading by memory access means such as a memory I / F input circuit and a memory I / F output circuit.

  In the low gradation display mode such as 8-color display capable of reducing power consumption, if all the RGB bits are written / read out from the display memory, unnecessary power is generated. Therefore, in the present invention, in the special display mode such as the low gradation display mode, only the first memory and / or the second memory are accessed and necessary bits are written and read, and the other memories are not accessed without being accessed. By controlling so that necessary bits are not written / read, further power consumption can be reduced.

  Also, with respect to external display data writing, in a special display mode such as a low gradation display mode, control is performed so that only the first memory is accessed and necessary bits are written, and other memories are not accessed. As a result, wasteful power is not consumed, and power consumption can be reduced.

  As described above, according to the present invention, by storing some bits of display data and other bits in each independently accessible memory configured as a separate block, in the low gradation display mode, The power consumption during reading can be further reduced.

  For example, by storing the most significant bit and other bits in each memory configured as a separate block, only the data of the most significant bit is changed when changing the display in the low-consumption display mode, for example, partial display. Therefore, the power consumption at the time of writing can be further reduced.

  Hereinafter, a case where an embodiment of the display memory of the present invention is used as a frame memory for display will be described in detail with reference to the drawings.

  In the following description, display is performed using 8 bits (16, 777, 216 colors) of RGB color data in the all gradation display mode, and 1 bit is the most significant bit of RGB color data in the low gradation display mode. A case where display is performed using only (eight colors) will be described.

Here, for example, when the display color is 24 bits (8 bits for each of RGB) in the resolution QVGA (240 × 320), the required memory capacity is 40 × 24 × 320 = 1,843,200 bits. This display memory is configured as two blocks as two memories. In the memory A, 1 bit of the most significant bit of RGB is stored, and the data of the remaining 7 bits is stored in the memory B.

  FIG. 1 is a block diagram illustrating a configuration example of a main part of a display memory according to an embodiment of the present invention. In the conventional liquid crystal display device as shown in FIG. 2, this display memory can be provided in, for example, a controller.

  In FIG. 1, a display memory 10 according to this embodiment includes a memory A and a memory B provided as separate blocks, and a memory input unit used when image data (display data) is written in the memory A and the memory B. A memory I / F (interface) input circuit 11 and a memory I / F (interface) output circuit 12 as memory output means used when reading out image data from the memories A and B are provided. 10, the number of bits is set according to the required display gradation number.

  The memory I / F (interface) input circuit 11 and the memory I / F (interface) output circuit 12 constitute a memory access means. The memory A as the first memory and the memory B as the other memory are provided. Thus, they can be accessed independently at the time of data writing and data reading.

  When writing display data to the display memory 10, the memory A and the memory B can be independently accessed by the write enable signal from the memory I / F input circuit 11 to the display memory 10, and the display from the display memory 10 is also possible. When reading data, the memory A and the memory B can be independently accessed by a read enable signal from the memory I / F circuit 12 to the display memory 10.

  Here, in the normal display mode (all gradation display mode), display is performed on the memory A and the memory B via the memory I / F (interface) input circuit 11 and the memory I / F (interface) output circuit 12, respectively. Data is written and read out, and only in the memory A through the memory I / F (interface) input circuit 11 and the memory I / F (interface) output circuit 12 in the special display mode (in the low gradation display mode). Display data is written to and read from the display. Thus, by accessing both memories A and B in the normal display mode and accessing only the memory A in the special display mode, necessary bits can be written and read.

  In this case, in the special display mode (in the low gradation display mode), writing and reading of display data to and from the memory B are stopped by the memory I / F (interface) input circuit 11 and the memory I / F (interface) output circuit 12. It is in a state. Thus, by stopping reading / writing of the memory B in the special display mode, it is possible to reduce power consumption.

  The operation of the above configuration will be described below.

  First, a detailed description will be given of when image data is input to the display memory 10 (when display data is written).

  In this display memory 10, when normal image data is input (in normal display mode and all gradation display mode), both memory A and memory B can be accessed by a write enable signal via the memory I / F input circuit 11. And 8-bit image data (Rdata [7: 0], Gdata [7: 0], and Bdata [7: 0]) of each RGB color is input via the memory I / F input circuit 11, and each RGB color The most significant bit 1-bit data (Rdata7, Gdata7 and Bdata7) is stored in the memory A, and the remaining 7-bit data (Rdata [6: 0], Gdata [6: 0] and Bdata [6: 0]) Is stored in the memory B.

  In the special display mode (in the low gradation display mode) in which low gradation grayscale image data is input, such as in partial display, only the memory A is sent by the write enable signal via the memory I / F input circuit 11. The memory B is set in an accessible state, and the memory B is disabled without outputting the write enable signal and is brought into an access stop state. As described above, since only the memory A performs the writing operation and the memory B is in the writing stopped state, it is possible to reduce the power consumption when storing the image data only in the memory A.

  Next, the image data output time from the display memory 10 (display data read time) will be described in detail.

  In this display memory 10, when normal image data is output (in normal display mode and in all gradation display mode), both memory A and memory B can be accessed by a read enable signal via the memory I / F output circuit 12. State. The output data from the memory A and the output data from the memory B are integrated by the memory I / F output circuit 12 and transmitted to the source driver 103 shown in FIG. 2, and image data (Rdata [7: 0], Gdata [7: 0] and Bdata [7: 0]) are displayed.

  In the special display mode (in the low gradation display mode) in which low gradation 8-color display image data is output, such as during partial display, only the memory A is read by the read enable signal via the memory I / F output circuit 12. The memory B is set in an accessible state, and the memory B is disabled without being output with a read enable signal and is in an access stopped state. Only the memory A storing the most significant bit data is accessed to read the image data (Rdata7, Gdata7 and Bdata7), and is transmitted to the source driver 103 shown in FIG. 2 via the memory I / F output circuit 12. Then, display is performed using image data (Rdata7, Gdata7, and Bdata7).

  As described above, according to the display memory 10 of the present embodiment, among the bit widths of each color data such as RGB, for example, the first memory A storing some bits such as the most significant bit and the remaining other bits are stored. The other memory B (one memory in this embodiment) is configured as a separate block, and the memory I / F input circuit 11 and the memory I / F are respectively connected to the memories A and B. Independently accessible via each output circuit 12. In the normal display mode, both the memories A and B are accessed to perform display data reading and display data writing. Further, in the low gradation display mode, only the memory A is accessed, and display data reading and display data writing of necessary bits are performed. In this case, the memory B is not accessed and is stopped.

  As described above, by disabling the write enable signal and the read enable signal in the low gradation display mode to stop the access to the memory B, the power consumption can be reduced by 8-color display or the like. Power consumption can be reduced during both reading and writing. Therefore, in the display memory 10, unnecessary power consumption can be suppressed in the low gradation display mode, and power consumption can be reduced.

  In this embodiment, the example in which only the most significant 1 bit of each color data is stored in the individual memory A as a partial bit has been described. However, the present invention is not limited to this, and the upper 2 bits or 3 of each color data is included as a partial bit. A memory A that stores bits may be used. This is because 8-bit image data is not necessary for graphic display, comic display, and the like, and even 2-bit to 3-bit image data can often be displayed sufficiently.

  Further, in the present embodiment, the case where the first memory is the memory A (the most significant bit of each color data) and the other memory is the one memory B has been described as being provided as separate blocks. Not limited to this, two or more memories are provided as separate blocks as other memories, and a memory I / F (interface) input circuit 11 is used when writing and reading display data to and from other memories (a plurality of memories). The memory I / F (interface) output circuit 12 may be configured to be independently accessible. For example, when two memories are provided as other memories, the first memory is the memory A (the most significant bit), the other memory B is the second memory A ′ (the next most significant bit), and another As the memory B ′ (remaining other bits), the image data may be stored divided into a total of three memory blocks.

  That is, when the other memory B is two or more memories including the second memory A ′ and the other memory B ′, the first memory A, the second memory A ′, and the other memory B ′ are separated. As a block, the memory I / F (interface) input circuit 11 and the memory I / F (interface) are used when data is written to and read from the first memory A, the second memory A ′, and the other memory B ′. The output circuit 12 allows the first memory A, the second memory A ′, and the other memory B ′ to be accessed independently of each other.

  In the normal display mode, the memory I / F (interface) input circuit 11 and the memory I / F (interface) output circuit 12 are respectively connected to the first memory A, the second memory A ′, and the other memory B ′. Display data is written and read out, and in the first special display mode, the first memory A or the second memory is connected via the memory I / F (interface) input circuit 11 and the memory I / F (interface) output circuit 12, respectively. Display data is written to and read from only A ′. In the second special display mode, the first data is input via the memory I / F (interface) input circuit 11 and the memory I / F (interface) output circuit 12, respectively. Writing display data only to the memory A and the second memory A ′ and It may be configured so that the actual issue is carried out.

  In this case, in the first special display mode, the memory I / F (interface) input circuit 11 and the memory I / F (interface) output circuit 12 cause the second memory A ′ or the first memory A, and further other memory. Writing and reading of display data to and from B ′ are stopped, and in the second special display mode, another memory B ′ is added by the memory I / F (interface) input circuit 11 and the memory I / F (interface) output circuit 12. The display data may be written to and read from the display.

  Furthermore, in this embodiment, each color data is composed of RGB data having a respective bit width of 8 bits. However, the present invention is not limited to this, and each color data is R data having a respective bit width of 5 bits and G data having 6 bits. Or 5 bits of B data, or each color data may be composed of 6 bits of RGB data.

  Further, in the present embodiment, the case where the display memory is a frame memory for reading and displaying each color data has been described. However, the present invention is not limited to this, and the display memory may be a partial memory for displaying a part of the screen. Alternatively, the display memory may be a line memory.

  As mentioned above, although this invention has been illustrated using preferable embodiment of this invention, this invention should not be limited and limited to this embodiment. It is understood that the scope of the present invention should be construed only by the claims. It is understood that those skilled in the art can implement an equivalent range based on the description of the present invention and the common general technical knowledge from the description of specific preferred embodiments of the present invention. Patents, patent applications, and documents cited herein should be incorporated by reference in their entirety, as if the contents themselves were specifically described herein. Understood.

  In the field of a display memory, a display device such as a liquid crystal display device including the display memory, and a portable electronic information device such as a mobile phone equipped with the display device, some bits of image data and others Is stored in each independently accessible memory configured as a separate block, thereby reducing power consumption during writing and reading in the low gradation display mode. For example, by storing the most significant bit and other bits in each memory configured as separate blocks, only the data of the most significant bit is changed when changing the display in the low-consumption display mode, for example, partial display. Therefore, power consumption at the time of writing can be reduced.

It is a block diagram which shows the principal part structural example of the display memory which concerns on embodiment of this invention. It is a block diagram which shows the principal part structural example of the TFT (thin film transistor) system liquid crystal display device which is a typical example of the conventional active matrix drive system. FIG. 3 is a block diagram illustrating a configuration example of a main part of a conventional display memory provided in the controller of FIG. 2.

Explanation of symbols

10 display memory 11 memory I / F input circuit (memory input means)
12 Memory I / F output circuit (memory output means)

Claims (15)

In the display memory where the number of bits is set according to the required display gradation number,
Of the bit width of each color data, a first memory in which some bits are stored and another memory in which other bits are stored are configured as separate blocks. On the other hand, a display memory provided with memory access means that can be independently accessed at the time of data writing and data reading.   In the normal display mode, display data is written to and read from the first memory and the other memory via the memory access means, and in the special display mode, the first memory is sent via the memory access means. The display memory according to claim 1, wherein display data is written to and read from only the display memory.   The display memory according to claim 2, wherein writing and reading of display data to and from the other memory are stopped by the memory access means in the special display mode.   In the case where the other memory is two or more memories including a second memory and another memory, the first memory, the second memory, and the further memory are configured as separate blocks, When writing data to and reading data from one memory, the second memory, and the other memory, the memory access means causes the first memory, the second memory, and the other memory to be independent of each other. The display memory according to claim 1, wherein the display memory is accessible.   In the normal display mode, display data is written to and read from the first memory, the second memory, and the other memory via the memory access means. In the first special display mode, the memory access is performed. Display data is written to and read from only the first memory or the second memory via the means, and in the second special display mode, the first memory and the second memory are sent via the memory access means. The display memory according to claim 4, wherein display data is written to and read from only the display memory.   In the first special display mode, writing and reading of display data to and from the second memory or the first memory and the other memory are stopped by the memory access means, and in the second special display mode. 6. The display memory according to claim 5, wherein writing and reading of display data to and from the further memory are stopped by the memory access means.   The display memory according to claim 2, wherein the normal display mode is a full gradation display mode, and the special display mode is a low gradation display mode.   The display memory according to claim 1, wherein the partial bit is the most significant bit of each color data.   The display memory according to claim 1, wherein the partial bits are upper 2 bits or upper 3 bits of each color data.   10. Each of the color data has a bit width of 8-bit RGB data, 5-bit, 6-bit and 5-bit RGB data, or 6-bit RGB data, respectively. Display memory according to.   11. The display memory according to claim 1, comprising a frame memory for reading and displaying each color data, a partial memory for partial screen display, or a plurality of line memories.   The memory access means is a memory input means for independently writing display data to the first memory and the other memory, and a display data is independently read from the first memory and other harmful memory. The display memory according to claim 1, further comprising: a memory output unit.   The display memory according to claim 1, wherein the other memory is configured as a separate block from one or a plurality of memories.   A display panel having a display screen, a source driver and a gate driver for driving the display panel, and a controller for supplying display data and a display control signal to the source driver and supplying a display control signal to the gate driver And a display memory according to any one of claims 1 to 13 provided in the controller.   A portable electronic information device in which the display memory according to claim 1 is mounted on a display drive unit of a display device.

Images