JP2008020781A - Matrix-type display, display control circuit, and control method therefor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a display control circuit capable of reducing the power consumption of a decode circuit and suppressing a drop of the drive frequency, without having to provide a gray code counter circuit. <P>SOLUTION: An address signal output part 24 equipped to a display control circuit 200 of the active matrix-type display outputs address signals A0, A1, and A2, in a predetermined order stored in a predetermined look-up table beforehand, according to the timing control signal TS from a timing control part 23. The address signals are sequentially selected, starting from the value in which the output value corresponding to a non-existing scanning signal line is deleted, from among the gray codes where it is prescribed that two or more values should not change simultaneously. As a result, the occurrence of a hazard can be suppressed almost completely, the power consumption of the decode circuit due to the wrong selection can be reduced to zero, and a drop of the drive frequency which would occur, when period for driving a non-existing scanning signal line is required can be suppressed. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a matrix display device using a display element such as a liquid crystal, a display control circuit thereof, and a display control method thereof.

  In general, an active matrix liquid crystal display device includes a display unit including two substrates sandwiching a liquid crystal layer, and one of the two substrates has a plurality of data as video signal lines. Lines and a plurality of gate lines as scanning signal lines are arranged in a lattice pattern, and a plurality of pixel formation portions are provided that are arranged in a matrix corresponding to the intersections of the plurality of data lines and the gate lines. Yes. Each pixel formation portion constitutes a display portion of the device. A TFT (Thin Film Transistor) which is a switching element in which a gate terminal is connected to a gate line and a source terminal is connected to a data line, and the TFT And a pixel electrode connected to the drain terminal. The substrate including these pixel formation portions is called a TFT substrate. The other substrate facing the TFT substrate out of the two substrates has a common electrode which is a common electrode provided in common for the plurality of pixel forming portions, and a color filter for forming a display color. (CF: Color Filter). This substrate is called a CF substrate.

  Such an active matrix liquid crystal display device includes a data driver for driving the data line of the display portion, a gate driver for driving the gate line of the display portion, and a common electrode driving circuit for driving the common electrode, , A data driver, a gate driver, and a display control circuit for controlling the common electrode driving circuit.

  In recent years, there is an active matrix type display device using a ferroelectric liquid crystal or a plasma display as an electro-optical element while having a similar configuration. In this display device, pixel brightness obtained by applying drive signals having the same voltage and pulse width may vary depending on variations in the creation conditions of the electro-optic element corresponding to each pixel. For this reason, in the gradation display method in which the display state is set once in one frame period, it may be difficult to obtain the necessary gradation display quality in such an electro-optic element. Therefore, in this active matrix display device, a time-division gray scale display method is employed in which the gray scale display state of the electro-optic element is switched a plurality of times in one frame period to obtain the necessary number of gray scales. There is. In a display device employing this time-division gray scale display method, an arbitrary scanning line is appropriately selected according to the gray scale to be displayed, so that the gate driver cannot use a general shift register, Decode circuits are often used. If this decoding circuit is used, an arbitrary scanning line can be appropriately selected based on scanning line address information to be selected with a simple circuit configuration (see, for example, Patent Document 1).

  However, the active matrix type display device having the gate driver using the decoding circuit is not limited to the one using the time-division gradation display method as described above. Also in a typical active matrix display device, the decode circuit is used instead of the shift register.

  Regardless of whether the time-division gray scale display method is adopted or not, the active matrix display device including the gate driver using the decoding circuit as described above has the following problems caused by the decoding circuit. is there. That is, it is known that a general decoding circuit has a hazard when two or more potentials (corresponding to logic levels) of input signal lines change. Due to this hazard, a scanning line is erroneously selected for a moment in the display device, causing noise and malfunction, and increasing power consumption.

  In order to prevent this hazard, there has conventionally been an active matrix display device that generates an input signal to a decoding circuit by a gray code counter circuit (see, for example, Patent Document 2).

In this Gray code counter circuit, it is known that two or more logical values represented by a signal to be generated do not change at the same time, and it is also known that it can be used for hazard prevention. Therefore, in the active matrix display device provided with the gray code counter circuit, noise and malfunction can be prevented and power consumption can be reduced.
JP 2004-271899 A JP-A-10-170886

However, in the conventional active matrix display device having the gray code counter circuit, 2 ^k scanning signal lines are selected when a k-bit (k is a natural number of 2 or more) input signal is supplied to the decoding circuit. However, when the number of scanning signal lines is (2 ^k −j) (j is a natural number less than 2 ^(k−1) ), erroneous selection of scanning signal lines that do not exist (unnecessary selection operation) Will occur.

  Here, when the scanning signal line is driven so that the erroneously selected period is included in a period where the image data in the image signal does not exist (referred to as a blanking period), no abnormality occurs in the display. . However, since the conventional display device performs an operation of selecting a scanning signal line even during a period that does not contribute to display, wasteful power consumption increases, and a period for driving the scanning signal line that does not contribute to display. Therefore, the driving frequency of the scanning signal line is lowered.

  Accordingly, the present invention provides a display control circuit capable of reducing power consumption of a decoding circuit for driving a scanning signal line and suppressing a decrease in driving frequency without a gray code counter circuit, and a matrix type including the display control circuit. An object is to provide a display device.

The first invention drives (2 ^k −j) (2 is a natural number greater than or equal to 2 and j is a natural number less than 2 ^(k−1)) provided in a matrix display device. A display control circuit for providing an address signal having a k-bit value to a decoding circuit which is a scanning line driving circuit for
While all of the scanning signal lines are driven once every predetermined selection period, the selection period is performed in an order that minimizes the number of times the values of any two or more different bits of the address signal change simultaneously. Address signal output means for outputting an address signal in which the value of one or more bits is changed every time is provided.

According to a second invention, in the first invention,
It said address signal output means, among the gray code counter of k bits of 2 ^k-number of the gray code to be output in order, the scanning signal lines are not driven the j Gray code deleted if applied to the decoding circuit The obtained values are sequentially output as the address signal.

According to a third invention, in the second invention,
The address signal output means stores a value to be sequentially output as the address signal in a predetermined storage means.

A fourth invention is a display control circuit according to any one of the first to third inventions;
A plurality of video signal lines for transmitting a plurality of video signals corresponding to image signals output from the display control circuit;
A plurality of scanning signal lines intersecting with the plurality of video signal lines;
A plurality of pixel forming portions arranged in a matrix corresponding to intersections of the plurality of video signal lines and the plurality of scanning signal lines;
A matrix type display device comprising a drive control circuit for driving the plurality of video signal lines and the plurality of scanning signal lines.

A fifth invention is the fourth invention,
The display control circuit includes:
In the case of a predetermined multi-gradation display mode in which pixel display with more than two gradations is to be performed in the plurality of pixel forming portions, the predetermined based on the time-division gradation display method without outputting address signals in the order. Output address signal,
In a predetermined two-grayscale display mode in which two-gradation pixel display is to be performed in the plurality of pixel forming portions, address signals are output in the order.

According to a sixth invention, in the fifth invention,
Scan line driving for driving (2 ^k −j) (2 is a natural number greater than or equal to 2 and j is a natural number less than 2 ^(k−1)) provided in the matrix display device. A display control method for controlling display by giving an address signal having a k-bit value to a decoding circuit which is a circuit,
While all of the scanning signal lines are driven once every predetermined selection period, the selection period is performed in an order that minimizes the number of times the values of two or more different bits of the address signal change simultaneously. An address signal output step of outputting an address signal in which the value of one or more bits is changed every time is provided.

  According to the first aspect of the present invention, it is possible to substantially suppress the occurrence of a hazard by providing the decoder circuit with the address signal output from the address signal output means without providing the Gray code counter circuit. At the same time, since erroneous selection of non-existing scanning signal lines does not occur, the power consumption of the decoding circuit for driving the non-existing scanning signal lines can be reduced to zero, reducing the power consumption of the entire apparatus. can do. Further, since the period for driving the non-existing scanning signal line is unnecessary, it is possible to suppress a decrease in the driving frequency in the scanning signal line circuit that occurs when the period is necessary.

  According to the second aspect of the invention, the address signal output means sequentially outputs, as an address signal, a value obtained by deleting j gray codes whose scanning signal lines are not driven if the gray code is supplied to the decoding circuit. Therefore, the power consumption of the decoding circuit for driving the j scanning signal lines that do not exist can be reduced to zero, the power consumption can be reduced as a whole device, and the driving frequency in the scanning signal line circuit is lowered. Can be suppressed.

  According to the third aspect, since the value to be output in order as the address signal is stored in the predetermined storage means, the address signal can be easily generated by the address signal output means.

  According to the fourth aspect, the same effect as the first aspect can be achieved in the matrix display device.

  According to the fifth aspect of the invention, the same effect as that of the first aspect of the invention can be achieved in the two gradation display mode in the matrix type display device using the time division gradation display method.

  According to the sixth aspect, the same effect as that of the first aspect can be achieved in the display control method.

<1. Overall Configuration and Operation of Liquid Crystal Display Device>
FIG. 1 is a block diagram showing the overall configuration of an active matrix liquid crystal display device according to an embodiment of the present invention. The liquid crystal display device includes a display control circuit 200, a drive control unit including a source driver (video signal line drive circuit) 300, and a gate driver (scanning signal line drive circuit) 400, and a display unit 500. The display unit 500 includes a plurality (M) of video signal lines SL (1) to SL (M), a plurality (N) of scanning signal lines GL (1) to GL (N), and a plurality of these. A plurality of (M × N) pixels provided corresponding to the intersections of the video signal lines SL (1) to SL (M) and the plurality of scanning signal lines GL (1) to GL (N), respectively. The pixel forming portion corresponding to the intersection of the scanning signal line GL (n) and the video signal line SL (m) is indicated by the reference symbol “P (n, m)”. ), As shown in FIG. 2 and FIG. Here, FIG. 2 schematically shows a configuration of the display unit 500 in the present embodiment, and FIG. 3 shows an equivalent circuit of the pixel formation unit P (n, m) in the display unit 500.

The present invention can be applied to the case where the number of scanning signal lines is (2 ^k −j) (j is a natural number less than 2 ^(k−1)) . The number N of scanning signal lines is seven. The present invention can also be applied to a display device that employs a time-division gray scale display method as will be described later in the main modification, but the display device of the present embodiment will be described below (a liquid crystal layer). A normal gradation display method is employed in which the voltage applied to is appropriately controlled.

  As shown in FIGS. 2 and 3, each pixel forming portion P (n, m) has a video signal passing through the intersection while the gate terminal is connected to the scanning signal line GL (n) passing through the corresponding intersection. The TFT 10 which is a switching element having a source terminal connected to the line SL (m), the pixel electrode Epix connected to the drain terminal of the TFT 10, and the plurality of pixel formation portions P (n, m) (n = 1) To N, m = 1 to M) and a common electrode (also referred to as a “counter electrode”) Ecom, and a plurality of pixel formation portions P (n, m). A liquid crystal layer as an electro-optic element sandwiched between Epix and the common electrode Ecom.

  Each pixel forming portion P (n, m) displays one of red (R), green (G), and blue (B), and has the same color as shown in FIG. Is formed along the video signal lines SL (1) to SL (M) and the direction along the scanning signal lines GL (1) to GL (7). Are arranged in the order of RGB.

  In each pixel formation portion P (n, m), a liquid crystal capacitance is formed by the pixel electrode Epix and a common electrode Ecom that faces the pixel electrode Epix with a liquid crystal layer interposed therebetween, and an auxiliary capacitance Cs is formed in the vicinity thereof.

  When the scanning signal G (n) applied to the scanning signal line GL (n) becomes active, the TFT 10 is selected and becomes conductive. The drive video signal S (m) is applied to the pixel electrode Ep via the video signal line SL (m). As a result, the applied voltage of the driving video signal S (m) (voltage based on the potential of the common electrode Ec) is applied as a pixel value to the pixel forming portion P (n, m) including the pixel electrode Ep. Written.

  The display control circuit 200 receives a display data signal DAT and a timing control signal TS sent from the outside, and controls a digital image signal DV, a source start pulse signal SSP for controlling the timing of displaying an image on the display unit 500, and a source A clock signal SCK, a latch strobe signal LS, and a 3-bit address signal for selecting a scanning signal line to be described later are output. Hereinafter, signals representing each bit of the 3-bit parallel data are referred to as address signals A0, A1, and A2, respectively.

  Here, the display data signal DAT from the outside is a total of 24 bits of parallel consisting of red display data DR, green display data DG, and blue display data DB, which are 8-bit data to be given to each pixel forming unit. Contains data.

  The source driver 300 receives the digital image signal DV, the source start pulse signal SSP, the source clock signal SCK, and the latch strobe signal LS output from the display control circuit 200, and each pixel forming unit P (n, In order to charge the pixel capacity of m), a driving video signal is applied to each video signal line SL (1) to SL (M). At this time, the source driver 300 sequentially holds the digital image signal DV indicating the voltage to be applied to each of the video signal lines SL (1) to SL (M) at the timing when the pulse of the source clock signal SCK is generated. . The held digital image signal DV is converted into an analog voltage at the timing when the pulse of the latch strobe signal LS is generated. The converted analog voltage is applied simultaneously to all the video signal lines SL (1) to SL (M) as drive video signals. That is, in the present embodiment, the line sequential driving method is adopted as the driving method of the video signal lines SL (1) to SL (M).

  Based on the address signals A0, A1, and A2 output from the display control circuit 200, the gate driver 400 decodes the active scanning signals applied to the scanning signal lines GL (1) to GL (7) in a predetermined order. Provide a circuit. This decoding circuit will be described later.

  As described above, the driving video signal is applied to the video signal lines SL (1) to SL (M), and the scanning signal is applied to the scanning signal lines GL (1) to GL (7). The image is displayed on the display unit 500. The common electrode Ecom is supplied with a predetermined voltage by a power supply circuit (not shown) and is held at the common electrode potential Vcom.

<2. Configuration and Operation of Gate Driver and Display Control Circuit>
Next, the configuration and operation of the gate driver 400 and the display control circuit 200 will be described. FIG. 4 is a circuit diagram of the decode circuit 40 included in the gate driver 400 in the present embodiment, and FIG. 5 is a truth table of the decode circuit 40. Further, in order to clarify the characteristics in comparison with the decoding circuit 40, FIGS. 6 and 7 show a circuit diagram and a truth table of a conventional decoding circuit having an input signal of 3 bits and an output signal of 8 bits. FIG. 6 is a circuit diagram of this conventional decoding circuit, and FIG. 7 is a truth table of this conventional decoder circuit.

  As shown in FIG. 4, this decode circuit 40 is different from a conventional decode circuit in which an input signal is 3 bits (A0 to A2) and an output signal is 8 bits (Y0 to Y7). Y0 to Y6), and therefore the value corresponding to the output signal Y7 omitted in the decoding circuit 40 is not described in the truth table shown in FIG. Thus, the reason why the output of the decode circuit 40 is 7 bits is to cope with the number of scanning signal lines being 7. The input signals of the decode circuit 40 are address signals A0, A1, A2.

  FIG. 8 is a block diagram showing a configuration of the display control circuit 200. This display control circuit 200 is stored in an input data storage unit 21 for storing a pixel value (display gradation data) for one frame included in a display data signal DAT given from the outside of the apparatus, and in the input data storage unit 21. A data rearrangement output unit 22 that outputs pixel values to be included in the digital image signal DV in which pixel values (display gradation data) for each row are rearranged in the row order described later, and a timing control unit that performs timing control And an address signal output unit 24 that outputs address signals A0, A1, and A2 to be described later in response to a control signal CT from the timing control unit 23. The input data storage unit 21 stores data in a predetermined storage area in a storage device such as a semiconductor memory (not shown).

  The timing control unit 23 receives a timing control signal TS sent from the outside, and controls the control signal CT for controlling the operations of the data rearrangement output unit 22 and the address signal output unit 24, and the timing for displaying an image on the display unit 500. A source start pulse signal SSP, a source clock signal SCK, and a latch strobe signal LS are output.

  In response to the timing control signal TS from the timing control unit 23, the data rearrangement output unit 22 sets the pixel value for each row stored in the input data storage unit 23 for each row in a predetermined order stored in advance. A read digital image signal DV is output. This order is the order of lines designated by address signals A0, A1, and A2, which will be described later. Here, the first line, the second line, the fourth line, the third line, the seventh line, the sixth line, and the fifth line. It is in order of eyes.

  By this data rearrangement output unit 22, the digital image signal DV is supplied to the source driver 300 (as parallel data of 24 bits in total of 8 bits for each of RGB). In the source driver 300, the digital image signal DV is converted into an analog voltage for each color and applied to all the corresponding video signal lines SL (1) to SL (M) as driving video signals (line sequential). Drive). The voltages applied to the video signal lines SL (1) to SL (M) as driving video signals in this way are active scanning signals G (1) to G (7) by the gate driver 400 (described later). Is applied to the pixel electrode Epix of each pixel formation portion P (n, m) via the TFT 10 which is rendered conductive by application in a predetermined order (as shown in FIG. 10), and the pixel formation portion P ( n, m). An image is displayed by applying the holding voltage in the pixel capacitor to the liquid crystal and controlling the light transmittance of the display unit 500.

  Further, the address signal output unit 24 outputs the address signals A0, A1, A2 in a predetermined order stored in a predetermined look-up table in response to the timing control signal TS from the timing control unit 23. Hereinafter, this lookup table will be described.

  FIG. 9 is a look-up table that sequentially shows the values of the address signals A0, A1, and A2. Note that the values of the rows described with the above values are display rows designated by the corresponding address signals, and correspond to the order stored in advance in the data rearrangement output unit 22.

  Here, the value of this row is uniquely determined by the truth table of the decode circuit 40 shown in FIG. 5 as described in detail later. This truth table is the decode circuit 40 shown in FIG. 4 described above. Therefore, by appropriately changing the design of this circuit configuration, the display lines specified by the address signal can be appropriately determined (for example, in order from the first line or by leaving one line away). it can.

As shown in FIG. 9, this address signal does not increase in order from the lower bit to the higher bit like the output value of a general increment counter, but the output value of a so-called gray code counter (hereinafter, “ It is similar to “Gray Code”. Here, since this gray code is determined so that two or more output values do not change at the same time as described above, the hazard can be prevented, but the number of scanning signal lines is 2 as in the present display device. If the number is not ^k , erroneous selection (unnecessary selection operation) to a scanning signal line that does not exist occurs. Therefore, among the output values of the Gray code, the output values corresponding to the scanning signal lines that do not exist (the logical values of A0, A1, and A2 for driving the scanning signal line GL (8) of the eighth row that does not exist here are “ 1 is stored in the look-up table, and the output values stored in the look-up table are sequentially referred to by the address signal output unit 24 so that the address signals A0, A1 and A2 are generated.

  The gray code-like output value shown in FIG. 9 cannot be generated by the gray code counter circuit, so refer to a storage area in a predetermined storage unit in which the value is stored in the form of the lookup table. A configuration generated by doing so is preferable. The output value may be generated by a special signal output circuit or the like.

  As described above, the address signals A0, A1, A2 output from the address signal output unit 24 are input to the decode circuit 40, and the decode circuit 40 outputs the output signals Y0 to Y6 as shown in FIG. The output signals Y0 to Y6 become scanning signals G (1) to G (7) applied to the scanning signal lines GL (1) to GL (7). Next, the address signals A0, A1, A2 and the scanning signals G (1) to G (7) will be described in detail with reference to FIG.

  FIG. 10 is a timing chart of the address signals A0, A1, A2 and the scanning signals G (1) to G (7). In FIG. 10, when the potential of each signal is High, the active or logical value is “1”, and when Low, the inactive or logical value is “0”. .

  As shown in FIG. 10, since the logical values of the address signals A0, A1, A2 are “0” at time t0, the scanning signal G (1) becomes active. That is, referring to the truth table of the decoding circuit 40 shown in FIG. 5, when the logical values of the address signals A0, A1, A2 are “0”, only the logical value of the output signal Y0 is “1”. Of all the scanning signals, only the scanning signal G (1) corresponding to the output signal Y0 becomes active. Since the scanning signal G (1) is active until the next time t1, the period from the time t0 to the next time t1 is the selection period of the scanning signal line GL (1), and other scanning is performed. The signal lines are also selected during the same selection period.

  Subsequently, when the logical value of the address signal A0 changes from “0” to “1” at time t1 and the logical values of the address signals A1 and A2 remain “0”, the truth of the decoding circuit 40 shown in FIG. As can be seen from the value table, only the scanning signal G (1) becomes active. At this time t1, since two or more values of the address signals A0, A1, A2 are not changed at the same time, no hazard occurs.

  However, at time t2, the logical value of the address signal A0 is changed from “0” to “1”, the logical value of the address signal A1 is changed from “1” to “0”, and the logical value of the address signal A2 is “1”. If it does not change, a hazard occurs because the two address signals A0 and A1 change simultaneously. For example, when the address signal A0 changes after the address signal A1 within a minute time before and after the time t2, the values of the address signals A0, A1, A2 are once set to “0” within the minute time. ”,“ 0 ”,“ 1 ”, and finally changes to“ 1 ”,“ 0 ”,“ 1 ”. In this case, only the scanning signal (2) is temporarily transmitted within the minute time. After becoming active, only the scanning signal (6) becomes active. Therefore, the scanning signal (2) is erroneously output, that is, the scanning signal line GL (2) is erroneously selected. Thereafter, after time t3, signal changes after time t0 are repeated. Note that the occurrence of a hazard at the above time corresponds to an address signal in which the logical values of A0, A1, and A2 for driving the non-existing eighth row scanning signal line GL (8) are “1”. This is because the part has been deleted from the gray code.

  As described above, the configuration of the display control circuit 200 in the present display device cannot completely prevent the hazard. However, as shown in FIG. 10, the hazard is generated between time t0 and time t3, that is, in one frame period. Can occur only once, so that it is possible to suppress the occurrence of hazards much more than when an input signal to the decode circuit is generated by a general increment counter.

<3. Effect>
As described above, the display control circuit and the active matrix display device including the display control circuit according to the present embodiment can hardly suppress the occurrence of a hazard without including the gray code counter circuit.

  In addition, in this embodiment, since the erroneous selection for the non-existing scanning signal line does not occur, the power consumption of the decoding circuit for driving the non-existing scanning signal line can be reduced to zero. As a result, power consumption can be reduced.

  Further, since the period for driving the non-existing scanning signal line is unnecessary, it is possible to suppress a decrease in the driving frequency in the scanning signal line circuit that occurs when the period is necessary.

<4. Modification>
<4.1 Main modifications>
The above embodiment has been described on the premise of a display device that performs gradation display based on pixel values. However, the decode circuit 40 that receives an address signal similar to the gray code generated by the display control circuit 200 is configured as described above. Even in the case of being provided in a display device using a time-division gray scale method different from that of the device, the above-described effects are exhibited in a predetermined case. This will be described in detail below.

  As described above, the gate driver using the decode circuit is different from the gate driver using the shift register in that the address signal value is maintained for an appropriate period, so that the scanning signal line corresponding to the desired row is set in the desired period. You can choose. Therefore, a display device using the time division gray scale method is often provided with a gate driver using a decoding circuit. However, when many gray scales are controlled in a time-sharing manner, scanning signal lines cannot be selected in a fixed order including the order similar to the gray code described above, and in this case, hazards can be prevented. I can't do it.

  However, in particular, a display device used for a mobile phone or the like needs to perform a simple display for a long time in a low power consumption state. In this two-gradation display mode, display is typically performed with only two colors of white (brightest gradation) and black (darkest gradation). Therefore, when the time-division gradation method is used, Even so, display can be performed by selecting the scanning signal lines in a predetermined order. Therefore, a display device using this time-division gradation method is inputted to the decoding circuit in the order similar to the gray code as described in, for example, the lookup table shown in FIG. 9 in the two gradation display mode. Display is performed by sequentially changing each value of the address signal to select scanning signal lines in a predetermined order. With this configuration, it is possible to suppress the occurrence of hazards almost without providing the gray code counter circuit in the two gradation display mode. Further, if it is not the two gradation display mode, the occurrence of a hazard cannot be prevented, but by setting the correspondence between the address signal and the display row as described in the lookup table shown in FIG. The power consumption of the decoding circuit for driving the non-existing scanning signal line can be reduced to zero even in the case of not being in the two gradation display mode, and a period for driving the non-existing scanning signal line is required. A decrease in driving frequency in the scanning signal line circuit that occurs in some cases can be suppressed.

<4.2 Other Modifications>
In this embodiment, the number of scanning signal lines is seven. However, when a k-bit address signal is given to a decoding circuit which is a scanning signal line driving circuit, a display having (2 ^k −j) scanning signal lines. Even if it is an apparatus, there can exist the same effect. This is because if the number of scanning signal lines is the above, erroneous selection (unnecessary selection operation) to j scanning signal lines that do not exist occurs. In this configuration, the address signal output unit 24 outputs j gray codes whose scanning signal lines are not driven if given to the decoding circuit among 2 ^k gray codes to be output in order from the k-bit gray code counter. The values from which are deleted are sequentially output as address signals.

  Note that the active matrix liquid crystal display device has been described above as an example, but the present invention can be applied to a matrix display device using an organic EL element as long as it is a matrix display device. is there.

1 is a block diagram illustrating an overall configuration of an active matrix liquid crystal display device according to an embodiment of the present invention. It is a figure which shows typically the structure of the display part of an active matrix liquid crystal display device. It is a circuit diagram showing an equivalent circuit of a pixel formation portion in an active matrix type liquid crystal display device. It is a circuit diagram of a decoding circuit included in the gate driver in the embodiment. It is a truth table of the decoding circuit in the embodiment. It is a circuit diagram of a conventional decoding circuit. It is a truth table of the conventional decoder circuit. It is a block diagram which shows the structure of the display control circuit in the said embodiment. 5 is a lookup table showing each value of an address signal in order in the embodiment. In the said embodiment, it is a timing diagram of an address signal and a scanning signal.

Explanation of symbols

10 ... TFT (switching element)
DESCRIPTION OF SYMBOLS 21 ... Input data memory | storage part 22 ... Data rearrangement output part 23 ... Timing control part 24 ... Address signal output part 200 ... Display control circuit 300 ... Source driver 400 ... Gate driver 500 ... Display part A0-A2 ... Address signal DAT ... Display Data signal DV ... Digital image signal Clc ... Liquid crystal capacitance Cs ... Parasitic capacitance Ecom ... Common electrode Epix ... Pixel electrode GL (n) ... Scanning signal line (n = 1 to N)
SL (m) Data line (m = 1 to M)
P (n, m): Pixel formation portion (n = 1 to N, m = 1 to M)

Claims (6)

Scan line driving for driving (2 ^k −j) (2 is a natural number greater than or equal to 2 and j is a natural number less than 2 ^(k−1)) provided in the matrix display device. A display control circuit for providing an address signal having a k-bit value to a decoding circuit which is a circuit;
While all of the scanning signal lines are driven once every predetermined selection period, the selection period is performed in an order that minimizes the number of times the values of two or more different bits of the address signal change simultaneously. A display control circuit comprising address signal output means for outputting an address signal in which a value of one or more bits is changed every time. It said address signal output means, among the gray code counter of k bits of 2 ^k-number of the gray code to be output in order, the scanning signal lines are not driven the j Gray code deleted if applied to the decoding circuit The display control circuit according to claim 1, wherein the output values are sequentially output as the address signal.   The display control circuit according to claim 2, wherein the address signal output unit stores a value to be output in order as the address signal in a predetermined storage unit. A display control circuit according to any one of claims 1 to 3,
A plurality of video signal lines for transmitting a plurality of video signals corresponding to image signals output from the display control circuit;
A plurality of scanning signal lines intersecting with the plurality of video signal lines;
A plurality of pixel forming portions arranged in a matrix corresponding to intersections of the plurality of video signal lines and the plurality of scanning signal lines;
A matrix type display device comprising: a drive control circuit for driving the plurality of video signal lines and the plurality of scanning signal lines. The display control circuit includes:
In the case of a predetermined multi-gradation display mode in which pixel display of more than two gradations is to be performed in the plurality of pixel forming portions, the predetermined based on the time-division gradation display method without outputting address signals in the order. Output address signal,
5. The matrix type display according to claim 4, wherein in a predetermined two-gradation display mode in which two-gradation pixel display is to be performed in the plurality of pixel forming portions, address signals are output in the order. apparatus. Scan line driving for driving (2 ^k −j) (2 is a natural number greater than or equal to 2 and j is a natural number less than 2 ^(k−1)) provided in the matrix display device. A display control method for controlling display by giving an address signal having a k-bit value to a decoding circuit which is a circuit,
While all of the scanning signal lines are driven once every predetermined selection period, the selection period is performed in an order that minimizes the number of times the values of two or more different bits of the address signal change simultaneously. A display control method comprising: an address signal output step of outputting an address signal in which a value of one or more bits is changed every time.

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