JP2008137016A - Method for producing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a technique capable of making a semiconductor package into individual pieces at a high speed. <P>SOLUTION: A collectively sealed body 9 is confronted with adsorption blocks KBC; a substrate matrix 1 is placed on the stage; vacuum suction is performed from suction holes KTA, and the collectively sealed body 9 (substrate matrix 1) is adsorbed on the adsorption blocks KBC. In this conditions, a laser LS1 is applied and scanned, and the substrate matrix 1 and the collectively sealed body 9 are cut. During the radiation and scanning of the laser LS1, the dust of the substrate matrix 1 and the collectively sealed body 9 generated during the cutting operation is sucked by vacuum suction by a dust collection groove SJM provided at the stage. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a manufacturing technique of a semiconductor device, and more particularly to a technique that is effective when applied to a process of separating a resin-sealed semiconductor device.

  JP-A-2001-7243 (Patent Document 1) discloses that a glass epoxy substrate to which a plurality of semiconductor chips are fixed and a resin for sealing the plurality of semiconductor chips are irradiated with an excimer laser beam in a vacuum. Techniques for obtaining individual BGA semiconductor devices are disclosed.

  In Japanese Patent Laid-Open No. 2000-277550 (Patent Document 2), a plurality of semiconductor chips arranged on a mounting surface of a substrate are collectively sealed with a transfer mold resin and then adhered to the surface of the transfer mold resin. A technique is disclosed in which a semiconductor device is separated into pieces by attaching a tape and irradiating a laser beam from a surface opposite to the mounting surface of the substrate.

In Japanese Patent Laid-Open No. 2003-249616 (Patent Document 3), a plurality of electronic component chips are mounted on a lead frame, and the plurality of electronic component chips are collectively sealed as an aggregate and processed into a resin sealed body. In the lead cutting method for electronic parts to be performed, a technique is disclosed in which the removal of the resin covering the portion to be cut of each lead and the cutting of the lead exposed by the removal of the resin are performed by one laser irradiation of the same wavelength.
JP 2001-7243 A JP 2000-277550 A JP 2003-249616 A

  In recent years, semiconductor packages have become smaller and thinner, and after mounting a plurality of semiconductor chips (hereinafter simply referred to as chips) on a single wiring board (or lead frame), they are collectively sealed with resin, and then sealed. There has been an increasing demand for semiconductor packages manufactured by cutting and separating a stop resin and a wiring board (or lead frame).

  In the step of cutting and sealing the sealing resin and the wiring substrate (or lead frame), various methods are selected depending on the material of the sealing resin and the wiring substrate (or lead frame) to be cut. For example, when resin sealing is performed using a metal lead frame or a wiring board made of glass epoxy, individualization is performed by blade dicing using a dicer. In addition, when resin sealing is performed using a ceramic wiring board, individualization is performed by breaking using mechanical means such as a clamper or blade dicing using a dicer.

  However, in the case of blade dicing, the blades of the dicer are replaced in accordance with the material of the wiring board (or lead frame) to be separated and the size of the semiconductor package, and the blade rotation speed, feed speed, cut size, etc. It is necessary to set processing conditions. In particular, the blade feeding speed is slow, which is a factor that hinders high-speed machining. Further, when individualization is performed by blade dicing, a large amount of pure water is required, which increases the manufacturing cost of the semiconductor package.

  In addition, in mechanical singulation processing such as blade dicing and breaking that are brought into contact with each other, there is a limit in processing dimensions, and there is a problem that cannot meet the demand for miniaturization of semiconductor packages.

  An object of the present invention is to provide a technique capable of separating a semiconductor package at a high speed.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

1. A method for manufacturing a semiconductor device according to the present invention includes:
(A) preparing a plurality of semiconductor chips;
(B) preparing a mounting substrate partitioned into a plurality of chip mounting areas by dividing lines;
(C) mounting the semiconductor chip on each of the plurality of chip mounting regions;
(D) sealing the plurality of chip mounting regions of the mounting substrate and the plurality of semiconductor chips with a resin;
(E) a step of cutting and irradiating the first laser a plurality of times along the dividing line to cut the resin on the mounting substrate and the dividing line and to separate the semiconductor into a plurality of semiconductor devices;
including.

2. A method for manufacturing a semiconductor device according to the present invention includes:
(A) preparing a plurality of semiconductor chips;
(B) preparing a lead frame mainly composed of metal partitioned into a plurality of chip mounting areas by dividing lines;
(C) mounting the semiconductor chip on each of the plurality of chip mounting regions;
(D) a step of sealing each of the plurality of semiconductor chips with a resin;
(E) scanning and irradiating a first laser along the dividing line to cut the lead frame and singulate into a plurality of semiconductor devices having a plurality of leads having different lengths;
(F) After the step (e), a step of performing non-defective product determination for each of the separated semiconductor devices;
(G) a step of cutting and molding the plurality of leads of the semiconductor device determined to be non-defective in the step (f) so as to have the same length;
including.

  Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  Since the mounting substrate and the sealing resin are cut by laser scanning and irradiation, the semiconductor package can be singulated at high speed.

  A wafer is a single crystal silicon substrate (generally a substantially circular shape) used for manufacturing integrated circuits, an SOI (Silicon On Insulator) substrate, an epitaxial substrate, a sapphire substrate, a glass substrate, other insulating, anti-insulating or semiconductor substrates, etc. These composite substrates are referred to. The term “semiconductor integrated circuit device” as used herein refers not only to a semiconductor integrated circuit device such as a silicon wafer or a sapphire substrate, but also to a TFT (Thin Film Transistor) unless otherwise specified. ) And STN (Super-Twisted-Nematic) liquid crystal or the like made on other insulating substrates such as glass.

  The device surface is a main surface of a wafer on which a device pattern corresponding to a plurality of chip regions is formed by lithography.

  A lead frame refers to a strip-shaped or strip-shaped metal plate used for assembling a device (semiconductor device), and usually a plurality of patterns are connected. In the pattern, die pads, leads, and the like are formed, die bonding, wire bonding, and molding are performed on them, and then divided into devices. A lead frame in which a plurality of die pads, leads, and the like are arranged in a matrix form vertically or horizontally and vertically per lead frame pitch is called a matrix frame.

  The inner lead is a lead portion on the lead frame that is electrically connected to the surface electrode of the chip via a bonding wire or a bump electrode.

  The outer lead is a conductor wiring on the lead frame, which is a lead portion connected to an electrode of a semiconductor package or a substrate.

  The die pad is a flat portion for bonding a die (chip) at the center of the lead frame.

  A multilayer wiring board refers to a board formed by forming insulating layers, conductor layers (wiring), and microvias for interlayer connection for each layer, and stacking the conductor layers while repeating this process. It is used for applications such as an interposer for a semiconductor package on which chips having a reduced size, size and pitch are mounted.

  An interposer or a substrate is a substrate having an external output terminal formed of a semiconductor or an insulator on which electrical wiring is formed. A chip is mounted and wired by bonding or the like.

  A YAG (Yttrium Aluminum Garnet) laser refers to a solid-state laser that uses yttrium, aluminum and garnet doped with neodymium as a laser active substance.

  The laser diode refers to a semiconductor laser that uses a semiconductor as an optical amplification catalyst and has a diode structure and causes laser oscillation by current injection.

  The fundamental wave is a generic name of laser light when oscillated without using a harmonic crystal, and a YAG laser has a wavelength of 1064 nm.

  The second harmonic wave is a general term for a frequency twice the wavelength of the laser fundamental wave (half the wavelength). In the case of a YAG laser, it is 532 nm, which is 1/2 of 1064 nm.

  In the following embodiments, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments. However, unless otherwise specified, they are not irrelevant to each other. There are some or all of the modifications, details, supplementary explanations, and the like.

  Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), especially when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and may be more or less than the specific number.

  Further, in the following embodiments, the constituent elements (including element steps and the like) are not necessarily indispensable unless otherwise specified and apparently essential in principle. Needless to say. In addition, when referring to the constituent elements in the embodiments, etc., “consisting of A” and “consisting of A” do not exclude other elements unless specifically stated that only the elements are included. Needless to say.

  Similarly, in the following embodiments, when referring to the shapes, positional relationships, etc. of the components, etc., the shapes are substantially the same unless otherwise specified, or otherwise apparent in principle. And the like are included. The same applies to the above numerical values and ranges.

  In addition, when referring to materials, etc., unless specified otherwise, or in principle or not in principle, the specified material is the main material, and includes secondary elements, additives It does not exclude additional elements. For example, unless otherwise specified, the silicon member includes not only pure silicon but also an additive impurity, a binary or ternary alloy (for example, SiGe) having silicon as a main element.

  In addition, components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof will be omitted.

  In the drawings used in the present embodiment, even a plan view may be partially hatched to make the drawings easy to see.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

(Embodiment 1)
In the first embodiment, the present invention is applied to a manufacturing method of a MAP (Mold Array Package) type semiconductor package (semiconductor device) that collectively seals a plurality of chips mounted on a wiring board, for example. . Such a first embodiment will be described with reference to FIGS. FIG. 1 is a flowchart for explaining a manufacturing process of the semiconductor package of the first embodiment.

  First, as shown in FIGS. 2 to 4, a wiring board matrix (hereinafter referred to as a board matrix) 1 is prepared. 2 is an overall plan view of the component mounting surface of the substrate matrix (mounting substrate) 1, FIG. 3 is a side view of FIG. 2, FIG. 4 is an overall plan view of the back surface of the substrate matrix 1, and FIG. The expanded sectional view of X1 line is shown, respectively.

  A substrate matrix (base material) 1 is a matrix of a wiring board of a semiconductor device described later, and has an appearance that is, for example, a flat rectangular thin plate. The substrate matrix 1 has a main surface and a back surface on the opposite side. The main surface of the substrate matrix 1 is a component mounting surface on which chips are mounted as described later, and the back surface of the substrate matrix 1 is a bump electrode formation surface on which bump electrodes are formed as described later. A plurality of product areas (chip mounting areas) DR having the same size and shape are arranged adjacent to each other in the vertical and horizontal directions in FIG. Each product region DR is a unit region having a wiring board configuration necessary to configure one semiconductor device. A plurality of guide holes (holes) GH penetrating the main back surface of the substrate matrix 1 are formed in the vicinity of one long side of the outer periphery of the substrate matrix 1. By inserting the guide pin of the molding die for molding into this guide hole GH, it is possible to align the position of the substrate matrix 1 with the lower die of the molding die and place it on the lower die. It has become. Further, a target point TP that is a reference point when the substrate base 1 is cut into individual product region DR units in a later process is given to the back surface of the base substrate 1.

  The substrate matrix 1 has a multilayer wiring structure. FIG. 5 illustrates a four-layer wiring configuration. In FIG. 5, the upper surface of the substrate matrix 1 indicates the component mounting surface, and the lower surface of the substrate matrix 1 indicates the bump electrode formation surface. The substrate matrix 1 is attached to a laminated body formed by alternately stacking insulating base materials (core materials) 2 and wiring layers 3, and upper and lower surfaces (component mounting surface and bump electrode forming surface) of the laminated body. Solder resist 4. The insulating base 2 is made of, for example, a glass / epoxy resin having high heat resistance. The material of the insulating base material 2 is not limited to this, and can be variously changed. For example, a BT resin or an aramid nonwoven fabric material may be used. When BT resin is selected as the material for the insulating base material 2, the heat conductivity is high, so that the heat dissipation can be improved.

  Various wiring patterns 3 </ b> A to 3 </ b> E are formed on each wiring layer 3. Conductive patterns 3A to 3E are patterned by etching, for example, copper (Cu) foil. The conductor pattern 3A of the wiring layer 3 on the component mounting surface is a chip mounting pattern, the conductor pattern 3B is an electrode pattern to which bonding wires are connected, and the conductor pattern 3E facilitates peeling of a sealing resin described later. It is a pattern to make. In addition, a conductor pattern for signal wiring and power supply wiring is formed on the wiring layer 3 on the component mounting surface. A part of the conductor patterns 3A, 3B, 3E, etc. on the component mounting surface is exposed from the solder resist 4, and the exposed surface is subjected to, for example, nickel (Ni) and gold (Au) plating. The conductor pattern 3D of the wiring layer 3 on the bump electrode formation surface is an electrode pattern for bump electrode bonding. In addition, conductor patterns for signal wiring and power supply wiring are also formed on the wiring layer 3 on the bump electrode formation surface. Part of the conductor pattern 3D and the like on the bump electrode formation surface is also exposed from the opening 4A formed in the solder resist 4, and the exposed surface is subjected to, for example, nickel and gold plating. The conductor pattern 3C of the wiring layer 3 in the laminate is a signal and power supply wiring pattern. Each wiring layer 3 is electrically connected through a conductor (copper foil or the like) in the through hole TH.

  The solder resist 4 is also called a solder mask or a stop-off, and prevents the solder from coming into contact with a conductor pattern that does not require soldering during soldering. It has a function as a protective film that protects from molten solder. In addition, prevention of solder bridge between conductors, protection from contamination and moisture, damage prevention, environmental resistance, migration prevention, maintenance of insulation between circuits and short circuit between circuit and other parts (chip, printed wiring board, etc.) It also has a prevention function. The solder resist 4 is made of, for example, a polyimide resin, and is formed in specific regions on the main surface and the back surface of the substrate base 1.

  Next, as shown in FIG. 6, after the chip 6 is mounted on each product region DR on the component mounting surface of the substrate base 1 using an adhesive such as a silver-containing paste (process P1), for example, ultrasonic vibration is performed. The bonding pad of the chip 6 and the conductor pattern 3B on the component mounting surface of the substrate base 1 are electrically connected by the bonding wire 7 made of gold, using a wire bonder that uses both thermocompression bonding and thermocompression bonding (process P2).

  Next, as shown in FIGS. 7 and 8, the plurality of chips 6, the bonding wires 7 and the like on the main surface of the substrate base 1 are collectively sealed with a sealing resin (step P3). 8 shows a cross section taken along the line AA in FIG. 7, but the illustration of the chip 6 and the bonding wire 7 is omitted. Thereby, the collective sealing body 9 including the plurality of chips 6 can be molded on the main surface side of the substrate base body 1.

  Next, as shown in FIGS. 9 and 10, a plurality of spherical solder bumps held by a bump holding tool are immersed in a flux bath, and flux is applied to the surface of the solder bumps. Is temporarily attached to the conductor pattern 3d on the bump electrode forming surface of the substrate matrix 1 using the adhesive force of the flux. The solder bump is made of, for example, lead (Pb) / tin (Sn) solder. As a material for the solder bump, lead-free solder such as tin / silver (Ag) solder may be used. Solder bumps may be connected together for each product region DR, but from the viewpoint of improving the throughput of the solder bump connection process, it is better to connect the solder bumps of a plurality of product regions DR at a time. preferable. Thereafter, the solder bump is heated and reflowed at a temperature of about 220 ° C., for example, to be fixed to the conductor pattern 3D, and the bump electrode 12 is formed. Then, the solder bump connection process is completed by removing the flux residue etc. remaining on the surface of the substrate base 1 using a neutral detergent or the like.

  Next, a symbol representing the product name, use, etc. is given to the collective sealing body 9 by laser (second laser) irradiation (process P4). Here, FIG. 11 is a plan view of a stage (first stage) STG on which the substrate matrix 1 is placed when the symbol is given to the collective sealing body 9, and FIG. 12 and FIG. It is principal part sectional drawing along the BB line and CC line in FIG. In the first embodiment, this stage STG is also used in a process of cutting the substrate base body 1 and the collective sealing body 9 which are subsequent processes.

  The stage STG has a structure in which a plurality of suction blocks KBC corresponding to the number and the planar size of a plurality of product regions DR provided on the substrate matrix 1 are arranged in the housing KT1. In the vicinity of the center of the plane of each suction block KBC, a suction hole KTA for vacuum suction of the substrate matrix 1 by vacuum suction is provided. Two adjacent suction blocks KBC are separated by a dust collection groove (second dust collection port) SJM that collects dust by vacuum suction, and the entire plurality of suction blocks KBC collect dust by vacuum suction. It is surrounded by a dust collector (first dust collector) SJK. In the first embodiment, a vacuum system (not shown) connected to the suction hole KTA and a vacuum system (not shown) connected to the dust collecting groove SJM and the dust collecting port SJK are different systems. . The dust collection by the dust collection groove SJM and the dust collection port SJK will be described in detail when the subsequent step of cutting the substrate base body 1 and the collective sealing body 9 is described.

  As shown in FIGS. 14 and 15, when the above symbols are given to the collective sealing body 9, the substrate base 1 is placed on the stage STG with the lower surface (bump electrode forming surface) facing the suction block KBC. . Next, a rectangular frame type metal clamp KRP is placed on the substrate base 1 in order to prevent displacement of the substrate base 1 on the stage STG during laser irradiation. On the plane, the entirety of a plurality of product regions DR (shown by broken lines in FIG. 14) can be seen in the frame of the clamp KRP. Next, the stage STG is operated and rotated in order to match the relative position and inclination of the substrate base 1 on the plane and the laser irradiator (not shown) for applying the above symbols. The operation direction of the stage STG at this time is the horizontal direction and the vertical direction on the paper surface shown in FIG. 14, and the rotation direction is a horizontal direction with respect to the paper surface shown in FIG. Next, a symbol (second mark) KG is given to the batch sealing body 9 by laser irradiation. The laser irradiation is performed in accordance with the parallel movement of the stage while the stage STG is translated at an equal pitch according to the size of the preset product area DR, and the symbol KG is given for each product area DR. The By giving the symbol KG to the collective sealing body 9 in this way, the substrate mother body 1 and the collective sealing body 9 are cut and divided into individual semiconductor packages, and then the symbol KG is given to the collective sealing body 9 Compared to the case, the time required for applying the symbol KG can be greatly reduced.

  Next, the substrate mother body 1 and the collective sealing body 9 are cut and divided into a plurality of CSP (Chip Size Package) type semiconductor packages (process P5). In the first embodiment, this division work is performed by laser irradiation using the stage STG described with reference to FIGS. Further, a laser oscillator (first laser oscillator) that oscillates a laser during the division work is a laser oscillator (third laser oscillator) that oscillates a laser when the symbol KG is applied to the batch sealing body 9. Is different.

  Here, the cutting process of the substrate mother body 1 and the batch sealing body 9 by the laser irradiation will be described in detail. First, after giving the symbol KG to the collective sealing body 9, as shown in FIG. 16 and FIG. 17, the substrate base 1 is turned over, and the collective sealing body 9 is opposed to the suction block KBC. 1 is placed on the stage STG. At this time, each product region DR is arranged on the corresponding suction block KBC, and a dividing line between adjacent product regions DR (a chain line in FIG. 16 (except for the line BB)) is a dust collecting groove SJM. To be placed on top. Next, vacuum suction is performed from the suction hole KTA, and the collective sealing body 9 (substrate base body 1) is sucked to the suction block KBC. Next, a clamp KRP similar to the above-described clamp KRP is placed on the substrate base 1 in order to prevent displacement of the substrate base 1 on the stage STG during laser irradiation. Next, the stage STG is operated and rotated to match the relative position and inclination of the substrate matrix 1 and the laser irradiator. The operation direction of the stage STG at this time is the left-right direction (X direction) and the vertical direction (Y direction) on the paper surface shown in FIG. 16, and the rotation direction is a direction (θ Direction). For alignment in the X direction, Y direction, and θ direction, an image of the lower surface (bump electrode forming surface) of the substrate base 1 is acquired by a camera CMR disposed on the stage STG, and a plurality of target points ( By analyzing the coordinates (first position) of the first mark) TP, the necessary operation amount and rotation amount of the stage STG can be obtained, and can be performed based on the obtained operation amount and rotation amount. Further, the amount of operation of the stage STG in the Z direction is set so that the laser focus is optimized based on the material and thickness of the substrate matrix 1 and the collective sealing body 9.

  Next, as shown in FIG. 18, the laser (first laser) LS1 is applied to the lower surface (bump electrode forming surface) of the substrate base 1 from the laser irradiator LSK along the dividing line (the chain line in FIG. 16). Then, the substrate mother body 1 and the collective sealing body 9 are cut. 19, FIG. 20 and FIG. 21 are enlarged views of the section of the substrate base 1 and the collective sealing body 9, and FIG. 19 shows the substrate base 1 being cut. Indicates that the collective sealing body 9 is being cut, and FIG. 21 shows the time when the cutting of the substrate mother body 1 and the collective sealing body 9 is completed (laser LS1 is being irradiated). In the first embodiment, the laser LS1 is a second harmonic YAG laser. The installation position of the laser irradiator LSK is fixed, and when the stage STG moves horizontally, the laser LS1 is irradiated along one dividing line (see FIG. 16) connecting two target points TP. ing. In the first embodiment, the laser LS1 irradiates the substrate base 1 and the batch sealing body 9 to be cut under conditions that do not affect the heat of the laser LS1. That is, the conditions are the irradiation intensity of the laser LS1, the number of irradiations, and the horizontal movement speed of the stage STG. For example, when the substrate base 1 and the collective sealing body 9 are cut only by irradiating the laser LS1 once, a method of increasing the irradiation intensity of the laser LS1 or decreasing the horizontal movement speed of the stage STG can be considered. In that case, the amount of heat applied to the substrate matrix 1 and the collective sealing body 9 at a time increases, and there is a concern that the conductor patterns 3A to 3E in the substrate matrix 1 melt and short-circuit. Therefore, in the first embodiment, the irradiation intensity of the laser LS1 and the stage STG which can cut the substrate base 1 and the batch sealing body 9 by the laser LS1 tracing one dividing line a plurality of times (for example, 10 times). Examples of means for suppressing the amount of heat applied to the substrate mother body 1 and the collective sealing body 9 at a time by setting the horizontal movement speed are illustrated. Thereby, the malfunction which the conductor patterns 3A-3E in the board | substrate base | substrate 1 melt | dissolve and it short-circuits can be prevented. Further, the irradiation intensity of the laser LS1 and the horizontal movement speed of the stage STG may be appropriately changed between when the substrate base 1 is cut and when the batch sealing body 9 is cut.

  During the cutting of the substrate matrix 1 and the collective sealing body 9 by the laser LS1, the substrate matrix 1 and the collective sealing generated during the cutting operation by vacuum suction by the dust collection grooves SJM and the dust collection ports SJK provided in the stage STG are provided. The dust of the stationary body 9 is sucked. As a result, it is possible to prevent the dust from adhering to the substrate base body 1 and the collective sealing body 9 after cutting and reducing the yield of the semiconductor package.

  Further, as shown in FIG. 22, the laser irradiator LSK irradiates dry air DA1 together with the laser LS1. The irradiation position of the dry air DA1 to the substrate matrix 1 (collective sealing body 9) is adjusted to coincide with the irradiation position of the substrate matrix 1 (collective sealing body 9) of the laser LS1. By blowing such dry air DA1, overheating of the substrate base 1 (collective sealing body 9) irradiated with the laser LS1 is suppressed, and the conductive patterns 3A to 3E in the substrate base 1 as described above are melted and short-circuited. It is possible to more effectively prevent malfunctions that occur.

  By the way, there is a method of cutting the substrate base 1 and the collective sealing body 9 by blade dicing using a dicer. In the case of blade dicing, a dicer blade is used according to the material of the substrate base 1 and the batch sealing body 9 to be cut and the size of the semiconductor package separated by cutting the substrate base 1 and the batch sealing body 9. It needs to be replaced. Further, when cutting by blade dicing, a large amount of cutting water (pure water) for cooling and chip removal is required. For this reason, there is a problem that the manufacturing cost of the semiconductor package becomes high. Further, it is necessary to set processing conditions such as the blade rotation speed, the feeding speed, and the cutting size, and in particular, the blade feeding speed becomes slow. In addition, there is a possibility that the blade may be clogged by the cutting waste, and in the case of clogging, the cutting process for the dicer maintenance work is hindered in a short time. .

  On the other hand, according to the above-described first embodiment, the material of the substrate base 1 and the collective sealing body 9 to be cut and the size of the semiconductor package separated by cutting the substrate base 1 and the collective sealing body 9 are as follows. Even if it changes, the irradiation intensity of the laser LS1 irradiated from the laser irradiator LSK, the number of irradiations, and the horizontal movement speed of the stage STG are only set as appropriate. In the laser irradiator LSK, although it is necessary to replace the laser diode in the laser irradiator periodically (for example, about 1 to 2 years), the material of the substrate base 1 and the batch sealing body 9 to be cut, and the substrate base There is no need to replace the laser irradiator LSK itself depending on the size of the semiconductor package that is separated by cutting 1 and the collective sealing body 9. Further, dust generated by cutting the substrate matrix 1 and the collective sealing body 9 can be removed by vacuum suction using the dust collection groove SJM and the dust collection port SJK, which is necessary when using a dicer. Pure water is unnecessary. Thereby, the manufacturing cost of the semiconductor package of the first embodiment can be greatly reduced. In addition, since dust generated by the irradiation of the laser LS1 can be removed by vacuum suction using the dust collecting groove SJM and the dust collecting port SJK, problems such as clogging when using a dicer can be prevented. Thereby, since maintenance work can be omitted, it is possible to shorten the time required for the cutting process of the substrate mother body 1 and the collective sealing body 9. Further, by appropriately setting the irradiation intensity of the laser LS1, the number of irradiations, and the horizontal movement speed of the stage STG, the influence of the heat of the laser LS1 on the substrate base body 1 and the batch sealing body 9 to be cut as described above. Not only the conditions do not reach, but also the cutting can be performed at high speed while suppressing the thermal effect.

  Next, as shown in FIG. 23, the separated semiconductor package HPKG is picked up by the suction collet KKR and packed in a tray (step P6). Here, FIG. 24 is a fragmentary cross-sectional view of the suction collet KKR. As shown in FIG. 24, the suction collet KKR includes a resin collet JKR and a nozzle NZR, and is assembled by inserting the tip end NSB of the nozzle NZR into the insertion port SNK of the resin collet JKR. The semiconductor package HPKG is a resin The semiconductor package HPKG is picked up by contact with the collet JKR and vacuum suction. Further, the suction collet KKR is structured such that vacuum is supplied through the vacuum path SKR1 in the nozzle NZR and the vacuum path SKR2 in the resin collet JKR, and the semiconductor package HPKG can be vacuum-sucked.

  In the first embodiment, the above-described stage STG, camera CMR, laser irradiator LSK, and suction collet KKR are collectively formed as a single device (unit). Thereby, the process from the process P4 for assigning the symbol KG to the process P6 for picking up the semiconductor package HPKG and packing the tray can be performed as a consistent process with one apparatus. As a result, the time required for transporting the substrate matrix 1 and the waiting time until each process is performed can be greatly shortened, so that the TAT (Turn Around Time) for manufacturing the semiconductor package of the first embodiment is greatly increased. Can be shortened.

  Next, a sorting process (process P7) is performed on the plurality of semiconductor packages HPKG packed in the tray by an inspection such as an appearance inspection. Thereafter, the semiconductor package HPKG determined to be non-defective is shipped (process P8).

  Here, FIG. 25 is a perspective view of an example of the semiconductor package HPKG, and FIG. 26 is a side view showing a part of the semiconductor package HPKG in FIG. The wiring substrate 1 </ b> A is a member obtained by cutting the substrate base 1. The chip 6 is mounted on the conductor pattern 3A on the component mounting surface of the wiring board 1A with the adhesive 17 such as the silver-containing paste with the main surface facing up. The bonding pad BP on the main surface of the chip 6 is electrically connected to the conductor pattern 3B on the component mounting surface of the wiring board 1A through the bonding wire 7. A sealing body 9A is molded on the component mounting surface of the wiring board 1A, and the chip 6 and the bonding wire 7 are sealed by the sealing body 9A. This sealing body 9A is a member obtained by cutting the collective sealing body 9 described above. On the other hand, the bump electrode 12 is connected to the conductor pattern 3D on the bump electrode forming surface of the wiring board 1A. The conductor pattern 3A and the like on the component mounting surface are electrically connected to the conductor pattern 3D and the bump electrode 12 on the bump electrode formation surface through the conductor pattern 3C and the through hole TH of the wiring board 1A.

(Embodiment 2)
In the second embodiment, the present invention is applied to a method of manufacturing a QFN (Quad Flat Non-lead) type semiconductor package (semiconductor device), for example. Such a second embodiment will be described with reference to FIGS.

  FIG. 27 is a plan view showing an example of the structure of a lead frame (mounting base) 21 made of copper or a copper alloy used for manufacturing the semiconductor package of the second embodiment, and FIG. 28 is a DD in FIG. It is sectional drawing in the position along a line. The semiconductor package of the second embodiment uses a multi-piece lead frame 21 as shown in FIGS. 27 and 28, and molds a plurality of device regions (device regions (chip mounting regions)) 21K in the lead frame 21. A batch molding is performed in which the mold is covered with one cavity of the mold, and then is molded into individual pieces and assembled. Each device region 21K is formed with a plurality of leads 21A, a tab 21E on which a chip is mounted, a suspension lead 21G, and an inner frame portion 21J, and the plurality of device regions 21K are surrounded by an outer frame portion 21H.

  Using the lead frame 21 of the second embodiment as described above, first, as shown in FIGS. 29 and 30, a plurality of tabs on each tab 21 </ b> E of the plurality of device regions 21 </ b> K (see FIG. 27) of the lead frame 21. Die bonding is performed to fix the plurality of chips 6 having the pads. Here, it can be exemplified that the chip 6 is fixed to the tab 21E via a die bond material such as silver paste.

  Next, wire bonding for electrically connecting the pads of the plurality of chips 6 and the leads 21A, which are the plurality of electrode portions of the lead frame 21 corresponding thereto, via the bonding wires 7 is performed. Do. At this time, since the tab 21E is not exposed, the heating by the heater of the bonding stage of the wire bonder is efficiently and more uniformly transmitted to the chip 6 via the tab 21E. As a result, the wire Bonding reliability can be improved.

  Next, as shown in FIGS. 31 and 32, a molding is performed in which a plurality of chips 6, a plurality of bonding wires 7, and a part of leads 21A and tabs 21E of the lead frame 21 are sealed with a sealing resin. Here, one cavity of the mold corresponds to the left half and the right half of the lead frame 21 relatively, and the leads of the plurality of chips 6, the plurality of bonding wires 7 and the lead frame 21 in each cavity. Covering a part of 21A and tab 21E, batch molding is performed to fill the cavity with sealing resin. Thus, a collective sealing body 9 is formed in which a plurality of chips 6 and a plurality of bonding wires 7 are collectively resin-sealed.

  Next, a pretreatment operation for performing cleaning and activation treatment for removing oil, fat, oxide film, rust and the like on the surface of the lead frame 21 exposed from the collective sealing body 9, and a sealing resin burrs After performing the removal process, a plating process is performed to form a film of solder such as tin-bismuth or pure tin on the surface of the lead frame 21 (process P3A (see FIG. 1)).

  Next, as shown in FIG. 33, symbols representing the product name, use, and the like on the collective sealing body 9 by the same process as that described with reference to FIGS. KG is assigned to each device area 21K. As in the first embodiment, the laser irradiation is performed while the stage STG is translated at an equal pitch in accordance with the size of the preset device region 21K (corresponding to the product region DR in the first embodiment). The symbol KG is assigned to each device region 21K. By applying the symbol KG to the batch sealing body 9 in this way, the lead frame 21 and the batch sealing body 9 are cut and divided into individual semiconductor packages, and then the symbol KG is given to the batch sealing body 9. Compared to the case, the time required for applying the symbol KG can be greatly reduced.

  Next, the lead frame 21 and the collective sealing body 9 are cut and divided into a plurality of QFN type semiconductor packages. In the second embodiment, this division work is performed by laser irradiation (see also FIGS. 16 to 22) using the same stage STG as in step P5 described in the first embodiment.

  Here, the cutting process of the lead frame 21 and the collective sealing body 9 by the laser irradiation will be described in detail with reference to FIGS. First, after applying the symbol KG to the batch sealing body 9, the lead frame 21 is turned over, and the batch sealing body 9 is opposed to the suction block KBC (see FIGS. 11 and 12) of the stage STG. The frame 21 is placed on the stage STG. At this time, each device region 21K (corresponding to a planar rectangular region surrounded by a one-dot chain line in FIG. 34) is arranged on the corresponding adsorption block KBC, and a dividing line between adjacent device regions 21K (FIG. 34). The one-dot chain line (except for the DD line) is arranged on the dust collecting groove SJM (see FIGS. 11 and 12). Next, vacuum suction is performed from the suction hole KTA (see FIGS. 11 and 12), and the collective sealing body 9 (lead frame 21) is sucked to the suction block KBC. Next, a clamp KRP (see FIG. 14 and FIG. 15) is placed on the lead frame 21 in order to prevent displacement of the lead frame 21 on the stage STG during laser irradiation. Next, the stage STG is operated and rotated in order to match the relative position and inclination between the lead frame 21 and the laser irradiator LSK. In the first embodiment, the alignment in the X direction, the Y direction, and the θ direction described with reference to FIGS. 16 and 17 is performed by the camera CMR (see FIG. 17) disposed on the stage STG. By obtaining an image (on the opposite side to the surface on which the collective sealing body 9 is formed) and analyzing the coordinates of a plurality of target points TP appearing in the image, the required amount of movement and rotation of the stage STG are obtained. Then, it can be performed based on the obtained operation amount and rotation amount. Further, the operation amount of the stage STG in the Z direction (see FIG. 17) is set so that the laser focus is optimized based on the material and thickness of the lead frame 21 and the batch sealing body 9.

  Next, by irradiating the lower surface of the lead frame 21 with the laser LS1 from the laser irradiator LSK along the above dividing line (one-dot chain line in FIG. 34), the lead frame 21 and the batch sealing body 9 are cut. Divide into individual semiconductor packages HPKG2. In the second embodiment, the two collective sealing bodies 9 formed on one lead frame 21 and the lower lead frame 21 are first cut, and the other is a buffer. That is, after the cutting process for one of the regions RA and RB shown in FIGS. 34 and 35 is completed, the other cutting process is performed. In the second embodiment, the laser LS1 is also a YAG laser. However, when the lead frame 21 is cut, a fundamental wave YAG laser is used, and when the batch sealing body 9 is cut, the second harmonic YAG laser is used. Use a laser. In the second embodiment, the laser irradiator LSK includes a laser oscillator that can oscillate a YAG laser having a different wavelength, or a first laser oscillator that oscillates a fundamental YAG laser and the first laser oscillator. Two laser oscillators of a second laser oscillator that oscillates a second harmonic YAG laser are provided. As in the first embodiment, the installation position of the laser irradiator LSK is fixed, and when the stage STG moves horizontally, the laser LS1 is connected to one target line TP (see FIG. 34). It comes to be irradiated along.

  Also in the second embodiment, the laser LS1 irradiates the substrate base 1 to be cut and the batch sealing body 9 under conditions that do not affect the heat of the laser LS1. That is, the total thickness from the lead frame 21 to the collective sealing body 9 is about 0.8 mm, one device region 21K (a region surrounded by an alternate long and short dash line in FIG. 34) is a plane, and one side is about 3 mm. The following condition can be exemplified as the condition when the rectangle becomes the rectangle. The YAG laser traces 10 times (5 reciprocations) along one dividing line with an output of about 67 W, 3 reciprocations are used for cutting the lead frame 21, and the remaining 2 reciprocations are used to cut the encapsulated body 9 Used for. At that time, the horizontal moving speed of the stage STG, which is the YAG laser tracing speed, is about 60 mm (corresponding to the length of one side of the stage STG) when the lead frame 21 is cut. When the collective sealing body 9 is cut, about 60 mm is set to a speed of moving in about 0.3 seconds. As a result, it is possible to prevent problems such as melting of a plurality of leads 21A in the lead frame 21 and short-circuiting.

  Also in the second embodiment, as in the first embodiment, during the cutting of the lead frame 21 and the collective sealing body 9 by the laser LS1, the dust collection grooves SJM provided in the stage STG and the dust collection Due to the vacuum suction by the mouth SJK, the dust of the lead frame 21 and the batch sealing body 9 generated during the cutting operation is sucked. As a result, it is possible to prevent the dust from adhering to the lead frame 21 and the collective sealing body 9 after cutting and reducing the yield of the semiconductor package.

  Also in the second embodiment, as in the first embodiment, the laser irradiator LSK irradiates the dry air DA1 together with the laser LS1 (see FIG. 22). By blowing such dry air DA1, overheating of the lead frame 21 (collective sealing body 9) irradiated with the laser LS1 is suppressed, and the problem that the lead 21A in the lead frame 21 is melted and short-circuited is further effective. Can be prevented.

  Next, in the same process as in the first embodiment, the separated semiconductor package HPKG2 is picked up by the suction collet KKR (see FIG. 23 and FIG. 24) and packed in a tray.

  Also in the second embodiment, as in the first embodiment, the stage STG, the camera CMR, the laser irradiator LSK, and the suction collet KKR are collectively formed as one device (unit). As a result, the process from adding the symbol KG to the process of picking up the semiconductor package HPKG2 and packing the tray can be performed as one integrated process, so that the manufacturing of the semiconductor package of the second embodiment can be performed. TAT (Turn Around Time) can be greatly shortened. According to the second embodiment, for example, the lead frame 21 and the collective sealing body 9 are cut using a dicer, for example, and the step of applying the symbol KG after being divided into individual semiconductor packages HPKG2. As compared with the above, the TAT for manufacturing the semiconductor package can be reduced to about 1/6.

  Next, the plurality of semiconductor packages HPKG2 packed in the tray are subjected to sorting processing by inspection such as appearance inspection. Thereafter, the semiconductor package HPKG2 determined to be non-defective is shipped.

  Here, FIG. 37 is a plan view of the lower surface of the semiconductor package HPKG2 from which the leads 21A are exposed, and FIG. 38 is a side view of the semiconductor package HPKG2. A sealing body 9A is molded on the tab 21E and the lead 21, and the chip 6 and the bonding wire 7 are sealed by the sealing body 9A. This sealing body 9A is a member obtained by cutting the collective sealing body 9 described above.

(Embodiment 3)
Next, a method for manufacturing the semiconductor device according to the third embodiment will be described.

  FIG. 39 is a plan view showing an example of the structure of a lead frame (mounting substrate) 31 made of copper or a copper alloy used for manufacturing the semiconductor package (semiconductor device) of the third embodiment, and FIG. It is sectional drawing in the position along line EE. The semiconductor package of the present third embodiment is assembled using a multi-piece lead frame 31 as shown in FIGS. In the lead frame 31, a plurality of leads 31A are formed in each region serving as an individual semiconductor package, and the plurality of regions serving as individual semiconductor packages including the plurality of leads 31A are surrounded by an outer frame portion 31H. It is.

  Using the lead frame 31 of the third embodiment as described above, first, as shown in FIGS. 41 and 42, for example, a plurality of leads 31A in each region to be a semiconductor package and the chip 6 are bonded using an adhesive tape. To do. Subsequently, wire bonding for electrically connecting the pads of the plurality of chips 6 and the leads 31 </ b> A as the plurality of electrode portions in the corresponding lead frame 31 via the plurality of bonding wires 7 is performed. Do.

  Next, a mold for sealing the chip 6, the plurality of bonding wires 7 and the plurality of leads 31 </ b> A with a sealing resin is performed for each region to be a semiconductor package. As a result, a sealing body 9A in which the chip 6, the plurality of bonding wires 7 and the plurality of leads 31A are sealed with a resin is formed.

  Next, as shown in FIG. 43, the same steps as those described in the first embodiment with reference to FIG. 11 to FIG. KG is given.

  Next, as shown in FIGS. 44 and 45, the plurality of leads 31A are separated from the outer frame portion 31H by laser irradiation using the transport rail HR and the laser irradiation unit LSU. 45 is a cross section corresponding to the FF line in FIG.

  The laser irradiation unit LSU includes a plurality of (four in FIG. 45) fiber optical systems FK1 to FK4 that irradiate the laser to the cutting position of the lead 31A, and these fiber optical systems FK1 to FK4 are lasers irradiated from each. (First laser) LS1 to LS4 are arranged on the transport rail HR so as to irradiate the correct positions of the corresponding leads 31A. In the third embodiment, the laser emitted from the fiber optical systems FK1 to FK4 is a fundamental YAG laser. The laser irradiation unit LSU includes an oscillation head that oscillates the laser and a branch unit that branches the laser oscillated from the oscillation head to the fiber optical systems FK1 to FK4.

  The transport rail HR includes protrusions TK1 to TK3 extending along the extending direction of the transport rail HR (the transport direction of the lead frame 31) FW (see FIG. 44), and the gap between the protrusions TK1 and TK3 at both ends is provided. These are separated according to the width of the lead frame 31 conveyed on the conveyance rail HR. The transport rail HR has a structure in which the lead frame 31 is transported on the protrusions TK1 to TK3, and is provided with a storage hole SYA that can store a structure separated from the outer frame portion 31H. .

  In the third embodiment, the lead frame 31 is transported on the transport rail HR and the laser is irradiated from the fiber optical systems FK1 to FK4 toward the plurality of leads 31A so that the plurality of leads 31A are outer frame portions. Disconnect from 31H. Since the laser is irradiated while transporting the lead frame 31, the lead 31A is cut by a single laser scan on the lead 31A. The structure composed of the lead 31A, the sealing body 9A, the chip 6, the bonding wire 7, and the like separated from the outer frame portion 31H is dropped and accommodated in the accommodation hole SYA of the transport rail HR. According to an experiment conducted by the present inventor, when the cutting means for the lead 31A using such a laser is applied, the cutting process of the lead 31A is compared with the case where the lead 31A is cut using a mold. It was possible to reduce the time required for the process to about 60% to 70%. As a result, the TAT for manufacturing the semiconductor package of the third embodiment can be shortened. In addition, when the mold is used, maintenance and management of the mold components are required periodically, leading to a problem of increasing the manufacturing cost of the semiconductor package. Since the maintenance and management of such component parts can be omitted or greatly omitted, the manufacturing cost of the semiconductor package can be reduced. In addition, when using a mold, there is a concern that the yield of the semiconductor package may be reduced due to trouble occurring in the mold, but according to the present embodiment 3, such a concern can be resolved, The yield of semiconductor packages can be improved.

  In the third embodiment, for example, as shown in FIG. 46, when the lead 31A is pulled out only in the horizontal direction of the sealing body 9A in a plane, the sealing is performed during the cutting process of the plurality of leads 31A by the laser. The cutting process is performed so that the length of the lead 31A after cutting is different between the right side and the left side of the stationary body 9A. At this time, the lead 31A at the same position always becomes longer (shorter). By using this difference in length as a mark for a specific terminal of the semiconductor package, the non-defective product of the semiconductor package by electrical characteristic inspection or the like is obtained. Sorting can be easily performed.

  Thereafter, as shown in FIG. 47, the semiconductor package HPKG3 of the third embodiment is manufactured by cutting the plurality of leads 31A, aligning them with appropriate lengths, and further shaping them.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  For example, in the first embodiment, the case where the resin substrate matrix is used as the substrate matrix on which the chip is mounted has been described. However, instead of the resin substrate matrix, a ceramic substrate matrix may be used. However, a second harmonic YAG laser is used as a laser for cutting the substrate matrix.

In the above embodiment, the case where the YAG laser is used when cutting the sealing body made of the substrate base, the lead frame, and the sealing resin has been described. However, a CO ₂ laser may be used instead of the YAG laser. . Even when a CO ₂ laser is used, it goes without saying that the output condition of the CO ₂ laser is a condition that does not affect the substrate base or the lead frame.

  The method for manufacturing a semiconductor device of the present invention can be applied to a process of cutting a wiring board (or a lead frame) and a sealing body and dividing them into individual semiconductor packages in a semiconductor package manufacturing process, for example.

It is a flowchart explaining the manufacturing process of the semiconductor device which is Embodiment 1 of this invention. It is a whole top view of the component mounting surface of the wiring board base | substrate used with the manufacturing method of the semiconductor device which is Embodiment 1 of this invention. FIG. 3 is a side view of FIG. 2. It is a whole top view of the back surface of the wiring board base used in the manufacturing method of the semiconductor device which is Embodiment 1 of the present invention. It is an expanded sectional view of the X1-X1 line | wire of FIG. It is principal part sectional drawing explaining the manufacturing process of the semiconductor device which is Embodiment 1 of this invention. It is a top view in the manufacturing process of the semiconductor device which is Embodiment 1 of this invention. It is sectional drawing along the AA line in FIG. It is a top view in the manufacturing process of the semiconductor device which is Embodiment 1 of this invention. It is sectional drawing along the AA line in FIG. It is a top view of the stage which mounts a board | substrate mother body in performing the laser irradiation to a board | substrate mother body in the manufacturing process of the semiconductor device which is Embodiment 1 of this invention. It is sectional drawing along the BB line in FIG. It is sectional drawing along CC line in FIG. It is a top view in the manufacturing process of the semiconductor device which is Embodiment 1 of this invention. It is sectional drawing along the BB line in FIG. It is a top view in the manufacturing process of the semiconductor device which is Embodiment 1 of this invention. It is sectional drawing along the BB line in FIG. FIG. 18 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 17; It is principal part sectional drawing in the manufacturing process of the semiconductor device which is Embodiment 1 of this invention. FIG. 20 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 19; FIG. 21 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 20; It is principal part sectional drawing in the manufacturing process of the semiconductor device which is Embodiment 1 of this invention. It is principal part sectional drawing in the manufacturing process of the semiconductor device which is Embodiment 1 of this invention. It is principal part sectional drawing of the adsorption collet used in the manufacturing process of the semiconductor device which is Embodiment 1 of this invention. 1 is a perspective view of a semiconductor device according to a first embodiment of the present invention. FIG. 26 is a side view showing a part of the semiconductor device of FIG. It is a top view explaining the manufacturing method of the semiconductor device which is Embodiment 2 of this invention. It is sectional drawing along the DD line in FIG. FIG. 28 is a plan view of the semiconductor device during a manufacturing step following that of FIG. 27; FIG. 29 is a cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 28; FIG. 30 is a plan view of the semiconductor device during a manufacturing step following that of FIG. 29; FIG. 31 is a cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 30; FIG. 32 is a plan view of the semiconductor device during the manufacturing process following FIG. 31; It is a top view in the manufacturing process of the semiconductor device which is Embodiment 2 of this invention. FIG. 35 is a cross-sectional view taken along the line DD in FIG. 34. FIG. 36 is a cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 35; It is a top view of the lower surface of the semiconductor device which is Embodiment 2 of this invention. It is a side view of the semiconductor device which is Embodiment 2 of this invention. It is a top view explaining the manufacturing method of the semiconductor device which is Embodiment 3 of this invention. It is sectional drawing along the EE line | wire in FIG. FIG. 40 is a plan view of the semiconductor device in manufacturing process, following FIG. 39; FIG. 41 is a cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 40; FIG. 42 is a plan view of the semiconductor device during a manufacturing step following that of FIG. 41; It is a principal part top view of the conveyance rail used for conveyance of a lead frame in the manufacturing process of the semiconductor device which is Embodiment 3 of this invention. It is sectional drawing along the FF line in FIG. It is a top view in the manufacturing process of a semiconductor device which is Embodiment 3 of this invention. It is sectional drawing in the manufacturing process of the semiconductor device which is Embodiment 3 of this invention.

Explanation of symbols

1 Wiring board matrix (Board matrix (mounting substrate))
1A Wiring board 2 Insulating base material (core material)
3 Wiring Layers 3A-3E Conductor Pattern 4 Solder Resist 4A Opening 6 Chip 7 Bonding Wire 9 Collective Sealing Body 9A Sealing Body 12 Bump Electrode 17 Adhesive 21 Lead Frame (Mounting Base)
21A Lead 21E Tab 21G Hanging lead 21H Outer frame portion 21J Inner frame portion 21K Device area (device area (chip mounting area))
31 Lead frame (mounting substrate)
31A Lead 31H Outer frame BP Bonding pad CMR Camera DA1 Dry air DR Product area (chip mounting area)
FK1 to FK4 Fiber optics GH Guide hole HPKG, HPKG2, HPKG3 Semiconductor package HR Transport rail JKR Resin collet KBC Suction block KG Symbol (2nd mark)
KKR Suction collet KRP Clamp KT1 Housing KTA Suction holes LS1 to LS4 Laser (first laser)
LSK Laser Irradiator LSU Laser Irradiation Unit NSB Tip NZR Nozzles P1 to P8, P3A Process RA, RB Area SJK Dust Collection Port (First Dust Collection Port)
SJM Dust collection groove (second dust collection port)
SKR1, SKR2 Vacuum path SNK Insertion slot STG Stage (first stage)
SYA accommodation hole TH through hole TK1 to TK3 protrusion TP target point (first mark)

Claims (16)

(A) preparing a plurality of semiconductor chips;
(B) preparing a mounting substrate partitioned into a plurality of chip mounting areas by dividing lines;
(C) mounting the semiconductor chip on each of the plurality of chip mounting regions;
(D) sealing the plurality of chip mounting regions of the mounting substrate and the plurality of semiconductor chips with a resin;
(E) a step of cutting and irradiating the first laser a plurality of times along the dividing line to cut the resin on the mounting substrate and the dividing line and to separate the semiconductor into a plurality of semiconductor devices;
A method for manufacturing a semiconductor device, comprising: In the manufacturing method of the semiconductor device according to claim 1,
The mounting substrate is mainly composed of metal,
In the step (e), the first laser when cutting the mounting substrate is a fundamental wave laser, and the first laser when cutting the resin is a second harmonic laser. A method for manufacturing a semiconductor device. The method of manufacturing a semiconductor device according to claim 2.
A method of manufacturing a semiconductor device, wherein the laser irradiation means for irradiating the fundamental laser and the second harmonic laser includes a laser oscillator that performs laser oscillation of different wavelengths. The method of manufacturing a semiconductor device according to claim 2.
Laser irradiation means for irradiating the fundamental laser and the second harmonic laser includes a first laser oscillator that oscillates the fundamental laser and a second laser oscillator that oscillates the second harmonic laser. A method for manufacturing a semiconductor device. In the manufacturing method of the semiconductor device according to claim 1,
The mounting substrate is a resin substrate or a ceramic substrate,
The method for manufacturing a semiconductor device, wherein the first laser used in the step (e) is a second harmonic laser. In the manufacturing method of the semiconductor device according to claim 1,
In the step (e), the first laser scans and irradiates at a scanning speed and irradiation intensity that does not affect the mounting substrate and the resin. In the manufacturing method of the semiconductor device according to claim 1,
In the step (e), dry air is blown onto the irradiation portion of the first laser. The method of manufacturing a semiconductor device according to claim 7.
The step (e) is performed under the condition that the mounting substrate is placed on the first stage, and the mounting substrate is adsorbed on the placement surface of the first stage,
The first stage is provided with a first dust collection port surrounding the mounting surface and the mounting substrate,
The placement surface of the first stage is provided with a second dust collection port under the dividing line of the mounting substrate,
The method of manufacturing a semiconductor device, wherein the step (e) is performed while vacuuming dust generated during the step (e) from the first dust collection port and the second dust collection port. In the manufacturing method of the semiconductor device according to claim 1,
The step (e) is performed under the condition that the mounting substrate is placed on the first stage, and the mounting substrate is adsorbed on the placement surface of the first stage,
The mounting substrate includes a plurality of first marks applied to end portions of the dividing line,
In the step (e), an image of the mounting substrate on the first stage is acquired before the irradiation with the first laser, and the first mark in which the plurality of first marks are arranged from the image. A method of manufacturing a semiconductor device, comprising: recognizing a position and correcting a positional shift and an inclination of the first stage. In the manufacturing method of the semiconductor device according to claim 1,
The method of manufacturing a semiconductor device, wherein the first laser is a YAG laser. In the manufacturing method of the semiconductor device according to claim 1,
further,
(F) applying a second mark by irradiating a second laser to the resin on each of the plurality of chip mounting regions;
(G) a step of picking up each of the separated semiconductor devices;
Including
The steps (e), (f), and (g) include a first laser oscillator that irradiates the first laser, a third laser oscillator that irradiates the second laser, A method of manufacturing a semiconductor device, comprising: using a composite device having an adsorption collet for picking up each of the semiconductor devices. The method of manufacturing a semiconductor device according to claim 11.
The method of manufacturing a semiconductor device, wherein the step (f) is performed before the step (e). In the manufacturing method of the semiconductor device according to claim 1,
further,
(F) applying a second mark by irradiating a second laser to the resin on each of the plurality of chip mounting regions;
(G) a step of picking up each of the separated semiconductor devices;
Including
In the step (e), the step (f) and the step (g), the first laser oscillator for irradiating the first laser and the second laser, and the suction collet for picking up each of the semiconductor devices A method for manufacturing a semiconductor device, comprising: using a composite device including: 14. The method of manufacturing a semiconductor device according to claim 13,
The method of manufacturing a semiconductor device, wherein the step (f) is performed before the step (e). (A) preparing a plurality of semiconductor chips;
(B) preparing a lead frame mainly composed of metal partitioned into a plurality of chip mounting areas by dividing lines;
(C) mounting the semiconductor chip on each of the plurality of chip mounting regions;
(D) a step of sealing each of the plurality of semiconductor chips with a resin;
(E) scanning and irradiating the first laser along the dividing line to cut the lead frame and to separate into a plurality of semiconductor devices having a plurality of terminals having different lengths;
(F) After the step (e), a step of performing non-defective product determination for each of the separated semiconductor devices;
(G) a step of cutting and molding the plurality of leads of the semiconductor device determined to be non-defective in the step (f) so as to have the same length;
A method for manufacturing a semiconductor device, comprising: In the manufacturing method of the semiconductor device according to claim 15,
In the step (f), the terminal of the semiconductor device is identified based on a difference in length of the plurality of terminals.

Images