JP2008122956A - Display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a self-luminous display device that allows even and uniform display to be obtained by reducing display variations among a plurality of pixels, which are caused by the variations of characteristics in a driving thin-film transistor. <P>SOLUTION: The device includes a plurality of pixels having a current-drivenlight-emitting device, and n (n≥2) pieces of thin-film transistors, connected in parallel that supply drive current to each of current-drive light-emitting devices. The n pieces of thin-film transistors, connected in parallel, are arranged inside different pixels, respectively, for example, in pixels that are mutually adjacent. The device includes dummy pixel regions, with at least on one side of the outside of the pixel rows on both sides, in the arrangement direction of the n pieces of thin-film transistors that are connected in parallel and are mutually adjacent. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a display device, and more particularly to the structure of an active matrix organic electroluminescence display.

An active matrix driving organic electroluminescence display (hereinafter referred to as AMOLED) is expected as a flat panel display of the next generation of a conventional liquid crystal display.
Conventionally, as an AMOLED pixel drive circuit, a current is supplied to an organic electroluminescence element (hereinafter simply referred to as an EL element) as disclosed in Japanese Unexamined Patent Publication No. 2000-163014 (first conventional technique). Driving thin film transistor (hereinafter referred to as EL driving TFT), a holding capacitor connected to the gate electrode of the EL driving TFT and holding a video signal voltage, and a switch for supplying the video signal voltage to the holding capacitor A circuit having a two-transistor structure including a thin film transistor (hereinafter referred to as a switch TFT) is known as the most basic pixel circuit.
A major problem with this two-transistor basic pixel circuit is that the threshold of the EL drive TFT is due to the variation in crystallinity of the semiconductor thin film (usually a polycrystalline silicon film) constituting the EL drive TFT. There is image non-uniformity that occurs because the value voltage (Vth) and mobility (μ) vary from pixel to pixel.
Variations in threshold voltage and mobility directly result in variations in the drive current value of the EL element, so that the light emission intensity varies and appears to be fine unevenness on the display. Such display unevenness is particularly problematic during halftone display with a small drive current value.

In order to suppress such display non-uniformity due to variations in the characteristics of the EL drive TFT, several methods have been considered.
For example, in Japanese Patent Laid-Open No. 11-219133, the channel length and the channel width of an EL drive TFT are made sufficiently larger than the average crystal grain size of polycrystalline silicon constituting the EL drive TFT, thereby reducing the drive current value. A method for suppressing variation is disclosed. (Hereinafter referred to as second prior art)
In Japanese Patent Laid-Open No. 2000-3005027, the EL driving TFT is driven as a binary switch that is completely turned off or turned on completely, and the gradation display of the image is performed by changing the light emission time width. A display driving method by so-called pulse width modulation is disclosed. (Hereinafter referred to as the third prior art)
Japanese Patent Laid-Open No. 11-73158 discloses that a plurality of EL elements having different light emitting areas are provided in a unit pixel, and an EL drive TFT is connected to each of the plurality of EL elements. An area gray scale method is disclosed in which a gray scale display is displayed by changing the light emitting area by driving as a binary switch which is turned off or completely turned on. (Hereinafter referred to as the fourth prior art)

USP 6229506B1 discloses a method for reducing variation in driving current by providing a circuit with four TFTs in a pixel and canceling variation in threshold voltage of an EL driving TFT. . (Hereinafter referred to as the fifth prior art)
In JP-A-8-129359, a plurality of EL driving TFTs having different current driving capabilities corresponding to a plurality of gradation currents are connected in parallel to one EL element in each pixel. A method is disclosed in which the EL drive TFT is driven as a binary switch that is completely turned off or completely turned on, and the gradation display is controlled by the gradation current supplied from a plurality of EL drive TFTs. (Hereinafter referred to as the sixth prior art)
Japanese Laid-Open Patent Publication No. 2000-221903 discloses a method of providing two EL drive TFTs in parallel in a pixel, reducing variations in threshold voltage of the EL drive TFTs, and reducing drive current variations. It is disclosed. (Hereinafter referred to as the seventh prior art)

However, the above-described prior art has the following problems.
The second prior art attempts to average out the variation in crystallinity of polycrystalline silicon depending on the location by increasing the TFT size. However, even if the TFT size is increased, it is impossible to make it larger than the pixel pitch.
Therefore, the size of the EL drive TFT that drives the EL element constituting each pixel is limited within the area of the pixel, and the crystallinity of the polycrystalline silicon film varies depending on the location. Variations between the characteristics of the EL drive TFT in the pixel and the characteristics of the EL drive TFT in the adjacent pixel cannot be compensated.
It should be noted that only the crystal variation within the TFT size can be averaged by increasing the TFT size. Therefore, it is difficult to obtain sufficiently uniform display characteristics with the second prior art described above.

The effect of uniformizing the image display by the third prior art has already been demonstrated, and pulse width modulation driving is one of the promising methods for driving AMOLED.
However, as an essential problem of this driving method, since gradation display is performed with light emission pulses developed on the time axis, blurring of an image when a moving image called a pseudo contour is displayed is known.
In addition, since it is necessary to process a short signal pulse corresponding to the digital gradation, the operating frequency of the drive circuit is increased, and the power consumption of the circuit is increased.
Another problem is that the vertical scanning circuit, which is usually a simple circuit, becomes complicated and the circuit area increases.
The fourth prior art has a great effect on the uniformity of image display, but an EL element having an area corresponding to a digital gradation is formed in a unit pixel, and an EL driving TFT corresponding to each is formed. Therefore, it is difficult to increase the number of gradations.
In general, it is known that the light emitting area of the EL element is reduced with the operation time. However, when an EL element having a different light emitting area is used, the EL element having a small area corresponding to the lower bit of the gradation is used with time. There is also a problem that normal gradation becomes difficult with time because it deteriorates in order.

In the fifth prior art, in order to provide a circuit for canceling the threshold voltage of the EL driving TFT, an unnecessary wiring is required in the conventional two-transistor configuration, which causes a problem of a decrease in aperture ratio and a decrease in manufacturing yield.
Further, only the variation in threshold voltage can be canceled, and the variation in mobility remains as it is. For this reason, there is a problem that a sufficient drive current equalizing effect cannot be obtained.
In the sixth prior art, a plurality of EL drive TFTs having a current drive capability corresponding to digital gradation are connected in parallel. However, if the characteristics of the plurality of EL drive TFTs vary, it is difficult to perform normal gradation display. It is clear that it will be. Further, even in this method, the plurality of EL driving TFTs are formed in one pixel, so that there is no effect in reducing display variation among the plurality of pixels.
In the seventh prior art, when the characteristic of one of the two EL drive TFTs connected in parallel changes, the variation in the drive current can be reduced, but the characteristics of the two EL drive TFTs are both When it fluctuates, the variation in drive current cannot be reduced, and since these two EL drive TFTs are formed in one pixel, the display variation among a plurality of pixels can be reduced. Has no effect at all.

The present invention has been made to solve the above-described problems of the prior art, and an object of the present invention is to reduce display variations among a plurality of pixels due to variations in characteristics of driving thin film transistors in a display device. An object of the present invention is to provide a technique that can reduce and obtain uniform display without unevenness.
Another object of the present invention is to provide a technique capable of reducing a voltage drop and power consumption due to resistance of a lead wire of a cathode electrode in a display device.
The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

Of the inventions disclosed in this application, the outline of typical ones will be briefly described as follows.
That is, according to the present invention, a plurality of EL driving TFTs are connected in parallel to a current driven light emitting element arranged in each pixel region, and current is supplied to the current driven light emitting element from a plurality of current supply lines. In addition, the plurality of EL drive TFTs are arranged in a plurality of pixel regions at intervals substantially corresponding to the pixel pitch.
By connecting a plurality of EL drive TFTs in parallel, it is possible to average variations in drive current due to variations in threshold voltage and mobility between the plurality of EL drive TFTs. However, simply by arranging a plurality of EL drive TFTs in parallel, there is no guarantee that variations in drive currents of EL drive TFTs corresponding to a certain pixel and, for example, adjacent pixels will be averaged.
The non-uniformity of display is due to variations in the drive currents of the EL drive TFTs of a plurality of pixels. This is due to spatial variations in the crystallinity of the semiconductor film constituting the TFT and the film quality of the insulating film.

Since the EL drive TFTs are regularly arranged at the same interval as the pixel arrangement pitch, variations in the drive current are caused by the crystallinity of the semiconductor film on the scale of the pixel arrangement pitch and the spatial quality of the film quality of the insulating film. It can be considered that it is caused by variation.
In order to average such variations, it is effective to arrange the plurality of EL driving TFTs spatially dispersed at the pixel arrangement pitch.
Therefore, a plurality of EL driving TFTs are connected in parallel to the current driven light emitting elements arranged in each pixel region, and a current is supplied to the current driven light emitting elements from a plurality of current supply lines, and By disposing the plurality of EL drive TFTs in a plurality of pixel regions at intervals substantially corresponding to the pixel pitch, it is possible to reduce variations in drive current supplied to the current drive type light emitting element corresponding to each pixel. The display can be made uniform.
The effect of averaging by the plurality of EL drive TFTs arranged in a spatial distribution becomes greater as the number of TFTs connected in parallel increases.
Theoretically, the magnitude of the variation in the drive current is predicted to decrease as N increases in inverse proportion to √N, where N is the parallel number. Since the size of the pixel is limited, N = 2 to 12 is a realistic value in the current microfabrication rules for thin film transistors (TFTs).

Further, when the number of TFTs in the pixel increases, it becomes difficult to secure the area of the EL element that contributes to light emission.
In the present invention, the aperture ratio is improved by providing a reflective layer so as to cover at least part of the EL drive TFT and forming a current-driven light-emitting element on the reflective layer.
In addition, since the current from the light emitting elements of all the pixels flows through the cathode wiring of the current-driven light emitting elements arranged in each pixel region, it is important to reduce the resistance of the wiring.
In the present invention, the length of the lead wire electrically connected to the cathode electrodes of the plurality of current-driven light-emitting elements is shortened from the external connection terminal portion to the contact area, and the voltage drop due to the resistance of the lead wire is reduced. And minimize power consumption.
Specific examples are shown in the following embodiments.

The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.
(1) According to the self-luminous display device of the present invention, a uniform display screen without unevenness can be obtained.
(2) According to the self-luminous display device of the present invention, it is possible to reduce the voltage drop and the power consumption due to the resistance of the lead-out wiring of the cathode electrode.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof will be omitted.
[Embodiment 1]
FIG. 1 is a circuit diagram showing an equivalent circuit of a pixel of the display device according to the first embodiment of the present invention, and FIG. 2 is a plan view showing a pixel arrangement of the display device according to the first embodiment of the present invention.
In the self-luminous display device according to the present invention, an organic electroluminescence element (hereinafter simply referred to as an EL element) of each pixel includes three driving thin film transistors (hereinafter referred to as EL driving TFTs) provided in different pixel regions. Driven by.
In the first embodiment, each EL driving TFT is arranged in the pixel, the right adjacent pixel, and the right adjacent pixel.
In FIG. 1, a scanning signal wiring electrode (Gm, G (m + 1)), a video signal wiring electrode (Dn to D (n + 3)), and an anode current supply wiring electrode (A ( Three pixel regions surrounded by (n-1) to A (n + 2)) are shown.

The pixel in the m-th row and the n-th column is defined by a region surrounded by the scanning signal wiring electrode (Gm, G (m + 1)), the video signal wiring electrode Dn, and the anode current supply wiring electrode An.
Within each pixel, a switching thin film transistor (hereinafter referred to as a switch TFT) (Qs (m, n)) and three EL driving TFTs (Qd1 (m, n), Qd2 (m, n), Qd3 (m, n)) and a charge storage capacitor Cst (m, n) are formed.
The anode electrode of the EL element OLED (m, n) is connected to the drain electrode of the EL driving TFT (Qd1 (m, n)) via the EL connection wiring electrode 15.
The EL element OLED (m, n) belonging to the pixel in the m-th row and the n-th column is formed not only in the EL driving TFT (Qd1 (m, n)) in the pixel but also in the adjacent m-row (n + 1) column pixel. The EL driving TFT (Qd2 (m, n + 1)) and the EL driving TFT (Qd3 (m, n + 2)) formed in the m row (n + 2) column pixel are connected in parallel. The anode current supply wiring electrodes (An, A (n + 1), A (n + 2)) are connected so as to be supplied with current.
The gate wiring electrodes 14 of the three EL driving TFTs connected in parallel are all connected to the drain electrodes of the switch TFTs (Qs (m, n)) of the pixels in the m-th row and the n-th column via the connection wiring electrodes 12. It is connected.
A charge storage capacitor Cst (m, n + 2) is formed between the gate electrode node of the three EL driving TFTs and the anode current supply wiring electrode (A (n + 2)), and the gate The voltage of the wiring electrode 14 can be held for a certain period.

In this embodiment, the scanning signal wiring electrodes G are sequentially scanned, and the switch TFT (Qs) to which the scanning signal wiring electrodes G that have become H level are connected is turned on. As a result, the video signal voltage is supplied from the video signal wiring electrode Dn to the charge storage capacitor Cst via the switch TFT (Qs) and held in the charge storage capacitor Cst.
On the basis of the video signal voltage held in the charge storage capacitor Cst, each EL driving TFT (Qd1, Qd2, Qd3) outputs a current corresponding to the video signal voltage held in the charge storage capacitor Cst for one frame. Supply to element OLED.
As a result, the EL element OLED emits light and an image is displayed.
In this embodiment, the gate length and channel length are set so that the current supplied to each EL drive TFT (Qd1, Qd2, Qd3) is substantially the same as the current supplied by a single EL drive TFT. The channel width is set.
In this embodiment, each EL driving TFT (Qd1 (m, n), Qd2 (m, n), Qd3 (m, n)) has a double gate structure, each gate length is 10 μm, total channel length is 20 μm, The channel width was 4 μm.

The current supply from the EL drive TFT (Qd2 (m, n + 1)) and the EL drive TFT (Qd3 (m, n + 2)) to the EL element OLED (m, n) is the source of each EL drive TFT. This is performed by extending the p + type semiconductor layer constituting the electrode and drain electrode as they are and using them as wiring.
By adopting such a configuration, it becomes unnecessary to form an extra contact through hole, so that the area efficiency is improved, and as a result, the aperture ratio is improved.
Looking again at the pixel in the m-th row and the n-th column, of the three EL drive TFTs (Qd1 (m, n), Qd2 (m, n), Qd3 (m, n)), the EL drive TFT (Qd2 (m , n)) drives the EL element OLED (m, n-1) of the pixel in the m-th row (n-1) column, and the EL driving TFT (Qd3 (m, n)) It is provided to drive the EL element OLED (m, n-2) of the pixel in the (n-2) th column.
The charge storage capacitor Cst (m, n) is provided to hold the potential of the gate electrode node of the EL drive TFT (Qd3 (m, n)).
The EL element is formed on the ITO electrode (EL element anode electrode) 13 connected to the EL connection wiring electrode 15 through a contact through hole through an opening formed in the organic insulating film 23.

FIG. 3 is a circuit diagram showing the entire display unit including an equivalent circuit and a drive circuit of the matrix display unit of the display device according to the first embodiment.
As shown in FIG. 3, the matrix display unit includes 600 scanning signal wiring electrodes composed of G1 to G600, 2400 video signal wiring electrodes composed of D1R to D800R, D1G to D800G, and D1B to D800B, and A1R to It consists of 2400 anode current supply wiring electrodes A800R, A1G to A800G, A1B to A800B, and pixels provided in the intersecting regions.
The matrix display unit is driven by a vertical scanning circuit VDRV and a video signal circuit HDRV, and anode current supply wiring electrodes arranged in each pixel are short-circuited (short-circuited) outside the pixel region and connected to an external power source. .
In this embodiment, since the EL drive TFT is arranged in the pixel, the right adjacent pixel, and the right adjacent pixel, two dummy pixel regions are provided outside the rightmost pixel column. It is done.

Two anode current supply wiring electrodes (A02, A03) corresponding to two dummy pixels outside the rightmost pixel column are also provided.
By doing in this way, it becomes possible to supply a prescribed current to the rightmost pixel from the three anode current supply wiring electrodes via the three EL drive TFTs.
Here, as shown in FIG. 3, the three EL driving TFTs are arranged, and the three pixels are arranged in the same direction as the laser scanning direction of the laser used when manufacturing the EL driving TFT. Pixels.
In this way, EL driving TFTs are distributed and arranged in a plurality of pixel areas, and they are connected in parallel to drive one EL element, so that the current of the EL driving TFT is averaged. It is possible to reduce the variation in the driving current during the period and to improve the uniformity of display.
Further, since current is simultaneously supplied from three anode current supply wiring electrodes via three EL drive TFTs to one EL element, disconnection of the anode current supply wiring electrodes and opening of the EL drive TFT are performed. Since redundancy is provided for display defects due to defects, there is also an effect that the manufacturing yield can be improved.

[Embodiment 2]
4 is a circuit diagram showing an equivalent circuit of a pixel of the display device according to the second embodiment of the present invention, and FIG. 5 is a plan view showing a pixel arrangement of the display device according to the second embodiment of the present invention.
As described above, in the self-luminous display device according to the present invention, the EL element of each pixel is driven by the three EL driving TFTs provided in different pixel regions.
In this embodiment, each EL driving TFT is arranged in the pixel and the pixels on both the left and right sides thereof.
FIG. 4 shows scanning signal wiring electrodes (Gm, G (m + 1)), video signal wiring electrodes (D (n-1) to D (n + 2)), and anode current supply wiring, which are part of the TFT matrix. Three pixel regions surrounded by electrodes (A (n-2) to A (n + 1)) are shown.
The pixel in the m-th row and the n-th column is defined by a region surrounded by the scanning signal wiring electrode (Gm, G (m + 1)), the video signal wiring electrode Dn, and the anode current supply wiring electrode An, , Switch TFT (Qs (m, n)), three EL driving TFTs (Qd1 (m, n), Qd2 (m, n), Qd3 (m, n)), and charge storage capacitor Cst (m, n) n) is formed.
The anode electrode of the EL element OLED (m, n) is connected to the drain electrode of the EL drive TFT (Qd2 (m, n)) via the EL connection wiring electrode 15.

The EL element OLED (m, n) belonging to the pixel in the mth row and the nth column is formed not only in the EL driving TFT (Qd2 (m, n)) in the pixel but also in the adjacent mth row (n + 1) column pixel. The EL driving TFT (Qd3 (m, n + 1)) and the EL driving TFT (Qd1 (m, n-1)) formed in the m row (n-1) column pixel are connected in parallel. The three anode current supply wiring electrodes (A (n-1), An, A (n + 1)) are connected so as to be supplied with current.
The gate wiring electrodes 14 of the three EL driving TFTs connected in parallel are all connected to the drain electrode of the switch TFT (Qs (m, n)) of the pixel in the m-th row and the n-th column via the connection wiring electrode 12. It is connected.
A charge storage capacitor Cst (m, n + 1) is formed between the gate electrode node of the three EL driving TFTs and the anode current supply wiring electrode A (n + 1), and the gate wiring electrode The voltage of 14 can be held for a certain period.
Also in this embodiment, the gate length and the channel length are set so that the current supplied to each EL drive TFT (Qd1, Qd2, Qd3) is substantially the same as the current supplied by a single EL drive TFT. The channel width is set.
In this embodiment, each EL driving TFT (Qd1 (m, n), Qd2 (m, n), Qd3 (m, n)) has a double gate structure, each gate length is 10 μm, and the total channel length is 20 μm. The channel width was 4 μm.

The current supply from the EL drive TFT (Qd1 (m, n-1)) and the EL drive TFT (Qd3 (m, n + 1)) to the EL element OLED (m, n) is the source of each EL drive TFT. This is performed by extending the p + type semiconductor layer constituting the electrode and drain electrode as they are and using them as wiring.
By adopting such a configuration, it becomes unnecessary to form an extra contact through hole, so that the area efficiency is improved, and as a result, the aperture ratio is improved.
Looking again at the pixel in the m-th row and the n-th column, of the three EL drive TFTs (Qd1 (m, n), Qd2 (m, n), Qd3 (m, n)), the EL drive TFT (Qd1 (m, n)) , n)) drives the EL element OLED (m, n + 1) of the pixel in the m-th row (n + 1) column, and the EL driving TFT (Qd3 (m, n)) has the m-th row (n -1) It is provided to drive the EL elements OLED (m, n-1) of the pixels in the column.
The charge storage capacitor Cst (m, n) is provided to hold the potential of the gate electrode node of the EL drive TFT (Qd3 (m, n)).
The EL element is formed on the ITO electrode (EL element anode electrode) 13 connected to the EL connection wiring electrode 15 through a contact through hole through an opening provided in the organic insulating film 23.

FIG. 6 shows a circuit diagram of the entire display unit including an equivalent circuit and a drive circuit of the matrix display unit of the display device according to the second embodiment.
As shown in FIG. 6, the matrix display section has 600 scanning signal wiring electrodes composed of G1 to G600, 2400 video signal wiring electrodes composed of D1R to D800R, D1G to D800G, and D1B to D800B, and A1R to A800R. , A1G to A800G, A1B to A800B, and 2400 anode current supply wiring electrodes, and pixels provided in these intersecting regions.
The matrix display unit is driven by a vertical scanning circuit VDRV and a video signal circuit HDRV, and an anode current supply wiring electrode arranged in each pixel is short-circuited outside the pixel region and connected to an external power source.
In this embodiment, since the EL drive TFTs are arranged on the pixel and on both the left and right sides thereof, dummy pixel regions are provided on both sides of the leftmost and rightmost pixel columns, respectively.
Two anode current supply wiring electrodes (A00, A01) corresponding to dummy pixels formed on both sides of the leftmost and rightmost pixel columns are also provided.
By doing so, it becomes possible to supply a prescribed current to the pixels at both the left and right ends from the three anode current supply wiring electrodes via the three EL drive TFTs.

In this way, the EL drive TFTs are distributed and arranged in a plurality of pixel regions, and the currents of the EL drive TFTs are averaged by connecting them in parallel and driving one EL element. Variation in driving current can be reduced, and display uniformity can be improved.
Also, since current is simultaneously supplied from three anode current supply wiring electrodes to three EL drive TFTs for one EL element, disconnection of the anode current supply wiring electrodes and open failure of the EL drive TFT Since it has redundancy with respect to display defects due to the above, there is an effect that the manufacturing yield can be improved.
In the present embodiment, the number of EL drive TFTs to be arranged in parallel is set to 3, and the EL drive TFTs are arranged in the pixel and the pixels on both the left and right sides thereof.
Compared with the above-described embodiment, the EL element OLED (m, n) is obtained from the EL drive TFT (Qd1 (m, n-1)) and the EL drive TFT (Qd3 (m, n + 1)) on both sides. The length of the current supply wiring electrode constituted by the p + type semiconductor layer can be made substantially the same.
As a result, the anode current supply wiring electrode A (n-1) and the wiring by the EL driving TFT and the p + type semiconductor layer from the anode current supply wiring electrode A (n + 1) to the EL element OLED (m, n) The sum of resistance can be made almost the same.
Since the resistance of the p + type semiconductor layer wiring is usually designed to be lower than the on-resistance of the EL driving TFT, the imbalance of the p + type semiconductor layer wiring resistance is not a serious problem, but if the wiring length becomes long, an error occurs. Can be
By disposing the EL drive TFTs in the pixels adjacent to each other as in this embodiment, it is possible to minimize an error due to p + type semiconductor layer wiring resistance imbalance.

FIG. 7 is a cross-sectional view showing a cross-sectional structure taken along the line XX ′ shown in FIG.
As shown in FIG. 7, a 50 nm buffer Si ₃ N ₄ film 200 and a 100 nm buffer SiO ₂ film 2 are formed on an alkali-free glass substrate 1 having a thickness of 0.5 mm and a strain temperature of about 670 ° C. Yes.
These buffer insulating films (200, 2) have a role of preventing diffusion of impurities such as Na from the glass substrate 1.
On the buffer SiO ₂ film 2, a polycrystalline Si (hereinafter referred to as poly-Si) film 30 having a film thickness of 50 nm corresponding to the charge storage capacitance Cst (m, n) is formed. A gate wiring electrode 14 of an EL driving TFT made of Mo is formed on the gate insulating film 20 made of SiO ₂ .
An anode current supply wiring electrode An is formed on the gate wiring electrode 14 of the EL drive TFT via an interlayer insulating film 21 made of SiO _2. The anode current supply wiring electrode An is Mo (110a). , Al (110b), and Mo (110c).

Here, the gate wiring electrode 14 of the EL drive TFT shown in FIG. 7 is overlapped with the anode current supply wiring electrode An, as shown in FIG. 5, the gate wiring electrode 14 of the EL drive TFT (Qd3 (m, n)). As shown in FIG. 5, the portion extending below the anode current supply wiring electrode An is shown, and the poly-Si film 30 shown in FIG. 7 is overlapped with the anode current supply wiring electrode An as shown in FIG. The formed poly-Si film 30 is electrically connected to the anode current supply wiring electrode An through a contact hole (CH0 in FIG. 5).
Therefore, in the present embodiment, the charge storage capacitor Cst (m, n) includes the capacitor element formed by the interlayer insulating film 21 between the anode current supply wiring electrode An and the gate wiring electrode 14, and the gate wiring electrode 14. And a capacitive element formed by the gate insulating film 20 between the poly-Si film 30.
Thus, by forming the charge storage capacitor Cst (m, n) below the anode current supply wiring electrode An, the aperture ratio of the pixel can be improved.
Also, video signal wiring electrodes (Dn, D (n + 1)) are formed on the same layer as the anode current supply wiring electrode An, and the video signal wiring electrodes (Dn, D (n + 1)) are formed. The electrode structure has a three-layer structure made of Mo (11a), Al (11b), and Mo (11c).

These are all covered with a protective insulating film 22 made of Si ₃ N ₄ having a thickness of 200 nm, and an anode electrode 13 made of indium-tin oxide (ITO) is formed thereon.
Further, an organic insulating film 23 mainly composed of polyimide having a film thickness of 2 μm is formed on the anode electrode 13, and an opening is provided in the organic insulating film 23 almost at the center of the anode electrode 13.
A hole transport layer 300 made of triphenyldiamine (TPD) having a film thickness of 150 nm is formed on the anode electrode 13 and the organic insulating film 23, and further a film thickness of 30 nm doped with DCJTB and rubrene is formed thereon. A red EL light-emitting layer 301R made of tris (8-hydroxyquinoline) aluminum (Alq3) and an electron transport layer (not shown) made of Alq3 with a thickness of 30 nm are formed.
A cathode electrode 302 made of Al having a thickness of 150 nm is formed on the electron transport layer through LiF having a thickness of 0.8 nm.
Light emission is caused by radiative recombination of holes injected from the anode electrode 13 and electrons injected from the cathode electrode 302 in the red EL light emitting layer 301R. The generated light is emitted to the glass substrate 1 side.
In adjacent pixels, blue dots and green dots in which a blue EL light emitting layer 301B and a green EL light emitting layer 301G are formed instead of the red EL light emitting layer are arranged.
The blue EL light emitting layer 301B is DPVBi doped with 15 nm thick BCzVBi, and the green EL light emitting layer 301G is Alq3 doped with 30 nm thick coumarin 540.

8 is a cross-sectional view showing a cross-sectional structure cut along the line YY ′ shown in FIG. 5, and FIG. 9 is a cross-sectional view taken along the line ZZ ′ shown in FIG. It is sectional drawing shown.
As described above, the 50 nm buffer Si ₃ N ₄ film 200 and the 100 nm buffer SiO ₂ film 2 are formed on the alkali-free glass substrate 1, and the switch TFT (Qs (m, n)) and the EL are formed thereon. driving TFT (Qd2 (m, n) ) poly-Si film 30 with a thickness of 50nm corresponding to is formed on the poly-Si film 30, the scanning signal lines via the gate insulating film 20 made of SiO ₂ An electrode Gm and a gate wiring electrode 14 of the EL driving TFT are formed. Here, the scanning signal wiring electrode Gm is made of Mo.
The switch TFT (Qs (m, n)) is composed of an N-type TFT, and a video signal wiring electrode Dn is connected to the source electrode thereof through a contact through hole opened in the interlayer insulating film 21, and a drain. Similarly, the connection wiring electrode 12 is connected to the electrode.
As described above, the video signal wiring electrode Dn has a three-layer electrode structure composed of Mo (11a), Al (11b), and Mo (11c). Similarly, the connection wiring electrode 12 also has Mo (12a). ), Al (12b), and Mo (12c).

The other of the connection wiring electrodes 12 is also connected to the gate wiring electrode 14 of the EL driving TFT through a through hole provided in the interlayer insulating film 21, and the signal voltage of the video signal wiring electrode Dn is switched to the switch TFT (Qs ( m, n)) is applied to the gate electrode of the EL drive TFT.
On the other hand, the EL drive TFT (Qd2 (m, n)) is composed of a P-type TFT, and the anode current supply wiring electrode An is connected to the source electrode through a contact through hole opened in the interlayer insulating film 21. Has been.
As described above, the anode current supply wiring electrode An has a three-layer electrode structure made of Mo (110a), Al (110b), and Mo (110c).
The drain electrode of the EL drive TFT (Qd2 (m, n)) is shared with the drain electrodes of the other two adjacent EL drive TFTs (Qd1 (m, n-1), Qd3 (m, n + 1)). The EL connection wiring electrode 15 is connected.
Here, the EL connection wiring electrode 15 has a three-layer electrode structure made of Mo (15a), Al (15b), and Mo (15c).
The anode electrode 13 is connected to the EL connection wiring electrode 15 through a through hole provided in the protective insulating film 22 made of Si ₃ N ₄ having a thickness of 200 nm. An organic LED having the above layer structure is formed on the anode electrode 13.

[Embodiment 3]
FIG. 10 is a circuit diagram showing an equivalent circuit of a pixel of the display device according to the third embodiment of the present invention, and FIG. 11 is a plan view showing a pixel arrangement of the display device according to the third embodiment of the present invention.
In the self-luminous display device of the present embodiment, driving of the EL element OLED (m, n) of m rows and n columns is performed in m rows (n−2) columns, m rows (n−) in addition to m rows and n columns. 1) A configuration in which five parallel EL driving TFTs formed in a total of five pixel regions of columns, m rows (n + 1) columns, and m rows (n + 2) columns are used.
Since the number of parallel is set to 5, the effect of improving uniformity by averaging is greater, and more uniform display characteristics can be obtained.

[Embodiment 4]
FIG. 12 is a circuit diagram showing an equivalent circuit of a pixel of the display device according to the fourth embodiment of the present invention, and FIG. 13 is a plan view showing a pixel arrangement of the display device according to the fourth embodiment of the present invention.
In the self-luminous display device of the present embodiment, driving of the EL element OLED (m, n) of m rows and n columns is performed in m rows (n + 1) columns, m rows (n + 2) columns, in addition to m rows and n columns. In this configuration, six parallel EL driving TFTs are formed in a total of six pixel regions of m rows (n + 3) columns, m rows (n + 4) columns, and m rows (n + 5) columns.
Since the number of parallel is set to 6, the effect of improving uniformity by averaging is greater, and more uniform display characteristics can be obtained.
Further, in this embodiment mode, a configuration is adopted in which light emitted from the EL element is extracted not on the substrate side but on the surface side.
As in this embodiment, when the number of TFTs in a pixel increases, it becomes difficult to ensure the area of the EL element that contributes to light emission.
In such a case, a configuration in which light is extracted to the surface side as in the present embodiment is advantageous.

14 is a cross-sectional view showing a cross-sectional structure taken along the line XX ′ shown in FIG.
As shown in FIG. 14, a 50 nm buffer Si ₃ N ₄ film 200 and a 100 nm buffer SiO ₂ film 2 are formed on an alkali-free glass substrate 1 having a thickness of 0.5 mm and a strain temperature of about 670 ° C. .
A 50 nm thick poly-Si film 30 corresponding to the charge storage capacitor Cst (m, n) is formed on the buffer SiO ₂ film 2, and a gate insulating film made of SiO ₂ is formed on the poly-Si film 30. A gate wiring electrode 14 of an EL driving TFT made of Mo is formed through the film 20.
As shown in FIG. 13, the gate wiring electrode 14 of the EL driving TFT shown in FIG. 14 shows a portion where the gate wiring electrode 14 of the EL driving TFT (Qd3 (m, n)) extends to the lower side of the pixel. Further, as shown in FIG. 13, the poly-Si film 30 shown in FIG. 14 is electrically connected to the anode current supply wiring electrode An through the contact hole.
An anode current supply wiring electrode An is formed on the gate wiring electrode 14 of the EL driving TFT via an interlayer insulating film 21 made of SiO ₂ . The anode current supply wiring electrode An has a three-layer electrode structure made of Mo (110a), Al (110b), and Mo (110c).
A video signal wiring electrode Dn and a reflective film 17 are formed on the same layer as the anode current supply wiring electrode An. The video signal wiring electrode Dn has a three-layer electrode structure made of Mo (11a), Al (11b), and Mo (11c). The reflective film 17 also has an Mo / Al / Mo three-layer electrode structure. Structured.

The reflective film 17 is connected to the anode electrode 13 through through holes (CH1 and CH2 in FIG. 13) provided in the protective insulating film 22 made of Si ₃ N ₄ having a thickness of 200 nm. For example, the reflective film 17 is formed in a region excluding a region where the switch TFT and the EL drive TFT (Qd1 (m, n)) are formed in the pixel of m rows and n columns.
The reflective film 17 has a role of reflecting light emitted from the EL element to the surface side, and stores charge between the poly-Si film 30 when the EL drive TFT (Qd3 (m, n)) is on. A part of the capacitance Cst (m, n) is formed.
Therefore, in the present embodiment, the charge storage capacitor Cst (m, n) includes the capacitive element formed by the gate insulating film 20 between the gate wiring electrode 14 and the poly-Si film 30, the reflective film 17 and the poly film. It is defined by the capacitive element formed by the interlayer insulating film 21 between the Si film 30.
These are all covered with a protective insulating film 22 made of Si ₃ N ₄ having a thickness of 200 nm, and an anode electrode 13 made of indium-tin oxide (ITO) is formed thereon.
Further, an organic insulating film 23 mainly composed of polyimide having a film thickness of 2 μm is formed on the anode electrode 13, and an opening is provided in the organic insulating film 23 almost on the center of the anode electrode 13.
A hole transport layer 300 made of triphenyldiamine (TPD) having a film thickness of 150 nm is formed on the anode electrode 13 and the organic insulating film 23, and further a film thickness of 30 nm doped with DCJTB and rubrene is formed thereon. A red EL light-emitting layer 301R made of tris (8-hydroxyquinoline) aluminum (Alq3) and an electron transport layer (not shown) made of Alq3 with a thickness of 30 nm are formed.

On the electron transport layer, 2,9-dimethyl-4,7diphenyl-1,10-phenanthroline (BCP) having a thickness of 7 nm and ITO having a thickness of 77 nm are formed via LiF having a thickness of 0.8 nm. Thus, a transparent cathode electrode 302 is formed.
Light emission is caused by radiative recombination of holes injected from the anode electrode 13 and electrons injected from the cathode electrode 302 in the red EL light emitting layer 301R. The generated light is emitted to the transparent cathode electrode side.
In adjacent pixels, blue dots and green dots in which a blue EL light emitting layer 301B and a green EL light emitting layer 301G are formed instead of the red EL light emitting layer are arranged.
The blue EL light emitting layer is DPVBi doped with BCzVBi having a thickness of 15 nm, and the green EL light emitting layer is Alq3 doped with coumarin 540 having a thickness of 30 nm.
FIG. 15 is a graph showing the relationship between the number N of EL driving TFTs to be paralleled and the luminance variation between pixels.
As can be seen from the graph of FIG. 15, the luminance variation can be reduced to about ½ of the case of N = 1 when N = 3.
Theoretically, with respect to the parallel number N, it is predicted that the degree of variation decreases in inverse proportion to √N. According to the graph of FIG. 15, the variation reduction effect almost as predicted by theory is obtained.

[Embodiment 5]
Hereinafter, the overall configuration of the display device of the present invention will be described as Embodiment 5 of the present invention with reference to FIGS.
On the glass substrate 1, an active matrix AMX composed of TFTs, a vertical scanning circuit VDRV, and a video signal circuit HDRV are formed.
The cathode electrode 302 of the EL element OLED is connected to the lead-out wiring 401 formed on the glass substrate 1 through the contact hole in the contact area 400 and is connected to the external connection terminal PAD.
The anode current supply wiring electrodes A provided in each column in the pixel are all connected outside the pixel region, and are connected to the external connection terminal PAD by the extraction electrode 402.
The present embodiment is characterized in that the contact area 400 is disposed between the active matrix AMX and the external connection terminal PAD, and the video signal circuit HRDV is disposed on the opposite side of the external connection terminal PAD across the active matrix AMX. There is.
By arranging in this way, the lead-out line 401 from the external connection terminal PAD to the contact area 400 can be shortened, so that the voltage drop and power consumption due to the resistance of the lead-out line can be minimized.
Since current from the EL elements OLED of all pixels flows through the lead-out wiring of the cathode electrode 302, it is important to reduce the resistance of the lead-out wiring.
On the other hand, since the current flowing through the power supply wiring and the ground wiring to the video signal circuit HDRV is smaller than the current of the EL element OLED, even if the wiring length is somewhat longer, it does not cause a big problem.

FIG. 17 is an exploded perspective view showing the entire display device shown in FIG.
On the glass substrate 1 on which the cathode electrode 302 of the EL element OLED is formed, a sealing glass 600 is attached by a seal SHL so that the EL element OLED is not exposed to the outside air.
As the seal SHL, an ultraviolet curable resin in which fiber glass having a diameter of 10 μm was dispersed was used.
The outer shape of the sealing glass and the glass substrate 1 are substantially the same on three sides other than the side from which the external connection terminal PAD is drawn, minimizing the outer dimensions of the entire panel.
18 is a cross-sectional view showing a cross-sectional structure of the display device shown in FIG.
Inside the sealing glass 600 is a convex portion provided on the sealing glass 600 with moisture adsorbing from the outside, chemistry for adsorbing gas released from the material constituting the EL element OLED, and the adsorbent 602. Is held by a tape 601. Calcium oxide (CaO) was used as the chemical adsorbent.
Further, in the cavity inside the sealing glass 600, dry N2 gas from which moisture has been removed up to -78 ° C. is sealed.

[Embodiment 6]
Hereinafter, as a sixth embodiment of the present invention, a manufacturing process of an active matrix substrate of a display device according to a second embodiment of the present invention will be described with reference to FIGS.
First, after cleaning the alkali-free glass substrate 1 having a thickness of 500 μm, a width of 750 mm, and a width of 950 mm and a strain point of about 670 ° C., the film thickness is obtained by a plasma CVD method using a mixed gas of SiH ₄ , NH ₃ and N _2. A 50 nm Si ₃ N ₄ film 200 is formed.
Subsequently, an SiO ₂ film 2 having a thickness of 120 nm is formed by a plasma CVD method using a mixed gas of tetraethoxysilane and O ₂ . Note that the formation temperature is 400 ° C. for both Si ₃ N ₄ and SiO ₂ .
Next, a substantially intrinsic hydrogenated amorphous silicon film 35 is formed on the SiO ₂ film 2 by a plasma CVD method using a mixed gas of SiH ₄ and Ar to a thickness of 50 nm. The film formation temperature was 400 ° C., and the hydrogen amount immediately after film formation was about 5 at%.
Next, the hydrogen in the hydrogenated amorphous silicon film 35 is released by annealing the substrate at 450 ° C. for about 30 minutes.
Next, a 100 nm-thickness SiO ₂ film 201 is formed by plasma CVD using a mixed gas of tetraethoxysilane and O ₂ , and boron (B +) is accelerated by an ion implantation method with an acceleration voltage of 40 KeV and a dose amount. Inject at 5 × 10 ¹² (atoms / cm ² ). Boron is for adjusting the threshold voltage of the TFT. (See Figure 19)

Next, the SiO ₂ film 201 is removed with buffered hydrofluoric acid, and a pulsed excimer laser beam LASER with a wavelength of 308 nm processed into a stripe shape with a short side of 0.3 mm and a long side of 300 mm is moved at a pitch of 10 μm in the short side direction. By irradiating, the amorphous silicon film 35 is irradiated at a fluence of 450 mJ / cm ² , and the amorphous silicon film 35 is melted and recrystallized to obtain a P-type polycrystalline silicon film 30. (See Figure 20)
At this time, variation in TFT characteristics due to variation in crystal quality of polycrystalline silicon in the laser beam scanning direction generally tends to be larger than variation in the direction perpendicular to the beam scanning direction.
For this reason, a larger effect can be obtained by arranging a plurality of EL drive TFTs in parallel in the laser beam scanning direction.
The laser scan direction indicated by the arrows in FIG. 3 or FIG. 6 indicates this, and a plurality of EL drive TFTs are arranged substantially parallel to the laser scan direction. The same applies to the embodiment shown in FIGS.
Next, the P-type polycrystalline silicon film 30 is processed into a predetermined shape by a reactive ion etching method using CF ₄ to obtain a TFT and a wiring pattern other than the TFT (polycrystalline silicon film 30).
Next, a gate insulating film 20 is formed by forming a SiO ₂ film having a thickness of 100 nm by plasma CVD using a mixed gas of tetraethoxysilane and oxygen.

Next, after a 200 nm Mo film is formed by sputtering, a predetermined resist pattern PR is formed on the Mo film by a normal photolithography method, and the Mo film is predetermined by a reactive ion etching method using CF ₄ . The gate electrode 10N of an N-type TFT is obtained by processing into a shape.
Next, phosphorus (P) ions are implanted at an acceleration voltage of 60 KV and a dose of 10 ¹⁵ (atoms / cm ² ) by an ion implantation method while leaving the resist pattern PR used for etching, and the source electrode of the N-type TFT, A drain electrode region is formed. (Refer to the right side of FIG. 21, center)
At this time, the P-type TFT protects the entire element with the pattern of the Mo film and the photoresist film PR so that phosphorus ions are not implanted. (See left side of Fig. 21)
Next, the substrate is treated with a mixed acid while leaving the resist pattern, the processed Mo electrode is side-etched to slim the pattern, the resist is removed, and then the P ions are accelerated by an ion implantation method at an acceleration voltage of 65 KV and a dose. An amount of 2 × 10 ¹³ (atoms / cm ² ) is implanted to form an LDD region of the N-type TFT. The length of the LDD region is controlled by the side etching time by the mixed acid. (See Figure 22)

Next, a predetermined resist pattern is formed on the Mo film, and a wiring pattern (gate wiring electrode 14) other than the gate electrode 10P of the P-type TFT and the TFT is obtained by a reactive ion etching method using CF ₄ .
Using the gate electrode 10P of the P-type TFT as a mask, boron ions are implanted at an acceleration voltage of 40 kV and a dose of 10 ¹⁵ (atoms / cm ² ) to form the source and drain electrode regions of the P-type TFT. At this time, the entire N-type TFT is protected by the photoresist pattern PR, is protected from the etching gas, and boron ions are not implanted. (See Figure 23)
After the photoresist is removed, the substrate is irradiated with light UV from an excimer lamp or a metal halide lamp, and the implanted impurities are activated by a rapid thermal annealing (RTA) method. (See Figure 24)
Next, SiO ₂ having a film thickness of 500 nm is formed by plasma CVD using a mixed gas of tetraethoxysilane and oxygen to form an interlayer insulating film 21.
After forming a predetermined resist pattern, contact through holes are opened in the interlayer insulating film 21 by wet etching using mixed acid.

Subsequently, Mo is deposited in a thickness of 50 nm, Al—Nd alloy is 500 nm, Mo is deposited in a thickness of 50 nm by sputtering, and a predetermined resist pattern is formed. Then, reactive ions using a mixed gas of BCl ₃ and Cl ₂ are used. The image signal wiring electrode D, the anode current supply wiring electrode A, the connection wiring electrode 12 and the EL connection wiring electrode 15 are formed by batch etching by an etching method. (See Figure 25)
Next, a Si ₃ N ₄ film having a thickness of 400 nm is formed as a protective insulating film 22 by plasma CVD using a mixed gas of SiH ₄ , NH _3, and N ₂ .
After forming a predetermined photoresist resist pattern, contact through holes are formed in the protective insulating film 22 by dry etching using SF ₆ .
Subsequently, an ITO film having a thickness of 70 nm is formed by a sputtering method and processed into a predetermined shape by wet etching using a mixed acid, thereby forming the anode electrode 13 of the EL element OLED. (See Figure 26)
Finally, a photosensitive polyimide resin is applied in a thickness of about 3.5 μm by a spin coating method, exposed and developed using a predetermined mask, and a portion of the polyimide resin on which the EL element OLED is formed on the anode electrode Then, the polyimide resin is baked by baking at 350 ° C. for 30 minutes, and the organic insulating film 23 having a film thickness of 2.3 μm is formed. (See Figure 27)

This organic insulating film 23 covers the end portion of the anode electrode 13 so that when an ultra-thin organic film constituting the EL element OLED is formed on the anode electrode, electric field concentration at the end portion of the ITO electrode is formed. The EL element OLED is formed to prevent destruction.
A process of forming an EL element on the active matrix substrate manufactured by the above process will be described below.
The active matrix substrate is set in a vacuum deposition apparatus, and is first introduced into a preheating chamber and baked in vacuum at 200 ° C. for 1 hour to remove moisture adsorbed on the substrate surface and moisture contained in the organic insulating film 23.
Next, ultraviolet light is irradiated at an intensity of 60 mW / cm ^{2 in} an atmosphere containing oxygen for 60 seconds to remove organic substances on the anode electrode surface.
Next, the work function of the anode electrode surface is adjusted by moving the active matrix substrate to the pretreatment chamber and performing O ₂ plasma treatment. The processing conditions are 60 seconds with an RF power of 200 W.
By this treatment, the work function of ITO which is the anode electrode 13 is adjusted to 5.1 to 5.2 eV, the barrier height when holes are injected into the hole transport material is lowered, and the injection efficiency is improved. be able to.

Next, the active matrix substrate is moved to the first vapor deposition chamber, and mask vapor deposition is performed using a mask in which the hole transport layer is formed on the entire surface of the display portion.
As a material for the hole transport layer, triphenyldiamine (TPD) is used. In addition, for example, α-NPD can be used. The film thickness of the hole transport layer is 150 nm.
Next, the active matrix substrate is moved to the second vapor deposition chamber, and RGB light emitting materials are mask vapor deposited.
Each light-emitting material is formed by first aligning the dots that should display blue and the openings of the vapor deposition mask, then forming the blue material, and then shifting the vapor deposition mask by the pitch of one dot in the vapor deposition chamber. Then, the green material is vapor-deposited, and the vapor deposition mask is similarly moved to deposit the red material, whereby a predetermined material is formed at each of the RGB dot positions.
Next, the active matrix substrate is moved to the third vapor deposition chamber, and the cathode electrode 302 is formed.

The cathode electrode 302 is formed by forming 150 nm of Al after forming LiF with a thickness of about 0.8 nm in order to improve the efficiency of electron injection into the organic layer.
Next, the active matrix substrate is moved to the sealing chamber, and the sealing glass that has been baked and dehydrated in advance in the same manner as the active matrix substrate is bonded with an ultraviolet curable resin interposed therebetween, and the ultraviolet rays are bonded from the back of the active matrix substrate. Irradiate light to cure the resin. At this time, a chemical adsorbent is inserted into the gap of the sealing glass.
All steps up to this point after setting the active matrix substrate must be performed so that the active matrix substrate is not exposed to the atmosphere.
Finally, the active matrix substrate to which the sealing glass is bonded is taken out, cut out to a predetermined size, and a driver LSI is mounted to complete the panel.
Although the invention made by the present inventor has been specifically described based on the above-described embodiment, the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the scope of the invention. Of course.

It is a circuit diagram which shows the equivalent circuit of the pixel of the display apparatus of Embodiment 1 of this invention. It is a top view which shows the pixel arrangement | positioning of the display apparatus of Embodiment 1 of this invention. FIG. 3 is a circuit diagram showing a circuit configuration of an entire display unit including an equivalent circuit of a matrix display unit and a drive circuit of the display device according to the first embodiment of the present invention. It is a circuit diagram which shows the equivalent circuit of the pixel of the display apparatus of Embodiment 2 of this invention. It is a top view which shows the pixel arrangement | positioning of the display apparatus of Embodiment 2 of this invention. It is a circuit diagram which shows the circuit structure of the whole display part containing the equivalent circuit of the matrix display part of the display apparatus of Embodiment 2 of this invention, and a drive circuit. FIG. 6 is a cross-sectional view showing a cross-sectional structure taken along the line X-X ′ shown in FIG. 5. FIG. 6 is a cross-sectional view showing a cross-sectional structure taken along the line Y-Y ′ shown in FIG. 5. It is sectional drawing which shows the cross-section which cut | disconnected along the Z-Z 'cutting line shown in FIG. It is a circuit diagram which shows the equivalent circuit of the pixel of the display apparatus of Embodiment 3 of this invention. It is a top view which shows pixel arrangement | positioning of the display apparatus of Embodiment 3 of this invention. It is a circuit diagram which shows the equivalent circuit of the pixel of the display apparatus of Embodiment 4 of this invention. It is a top view which shows pixel arrangement | positioning of the display apparatus of Embodiment 4 of this invention. FIG. 14 is a cross-sectional view showing a cross-sectional structure taken along the line X-X ′ shown in FIG. It is a graph which shows the relationship of the dispersion | variation in the brightness | luminance between pixels, and the number N of the thin-film transistor for organic electroluminescent element driving | operation paralleled. It is a top view which shows the whole structure of the display apparatus of each embodiment of this invention. It is a disassembled perspective view which shows the whole structure of the display apparatus of each embodiment of this invention. It is principal part sectional drawing which shows the cross-section of the display apparatus of each embodiment of this invention. It is a figure for demonstrating the manufacturing process of the display apparatus of Embodiment 2 of this invention. It is a figure for demonstrating the manufacturing process of the display apparatus of Embodiment 2 of this invention. It is a figure for demonstrating the manufacturing process of the display apparatus of Embodiment 2 of this invention. It is a figure for demonstrating the manufacturing process of the display apparatus of Embodiment 2 of this invention. It is a figure for demonstrating the manufacturing process of the display apparatus of Embodiment 2 of this invention. It is a figure for demonstrating the manufacturing process of the display apparatus of Embodiment 2 of this invention. It is a figure for demonstrating the manufacturing process of the display apparatus of Embodiment 2 of this invention. It is a figure for demonstrating the manufacturing process of the display apparatus of Embodiment 2 of this invention. It is a figure for demonstrating the manufacturing process of the display apparatus of Embodiment 2 of this invention.

Explanation of symbols

1 ... glass substrate, 2 ... SiO ₂ buffer layer, 10P ... gate electrode of the P-type TFT, 10 N ... gate electrode of the N-type TFT, 11a, 11c, 12a, 12c, 15a, 15c, 110a, 110c ... Mo, 11b, 12b, 15b, 110b ... Al, 12 ... connection wiring electrode, 13 ... anode electrode, 14 ... gate wiring electrode, 15 ... EL connection wiring electrode, 17 ... reflection film, 20 ... gate insulation film, 21 ... interlayer insulation film, 22 ... protective insulating film, 23 ... organic insulating film, 30 ... polycrystal silicon film, 35 ... hydrogenated amorphous silicon film, 200 ... _Si 3 _{N 4} buffer layer, 300 ... hole transport layer, 301R ... red EL emission layer , 301G: Green EL light emitting layer, 301B: Blue EL light emitting layer, 302: Cathode electrode, 400: Contact region, 401: Cathode lead-out wiring, 402: Annot Current supply wiring electrode lead electrode, 600 ... sealing glass, 601 ... tape, 602 ... chemical adsorbent (CaO), A ... anode current supply wiring electrode, D ... video signal wiring electrode, G ... scanning signal wiring electrode, Qs ... Switch thin film transistor, Qd ... Drive thin film transistor, Cst ... Charge storage capacitor, OLED ... Organic electroluminescence element, PAD ... External connection terminal, AMX ... TFT active matrix, VDRV ... Vertical scanning circuit, HDRV ... Video signal circuit, SHL ... Seal, PR ... photoresist, LASER ... excimer laser light, UV ... ultraviolet lamp light.

Claims (35)

A plurality of pixels having current-driven light-emitting elements;
N (n ≧ 2) thin film transistors connected in parallel for supplying a driving current to each of the current driven light emitting elements,
The display device according to claim 1, wherein the n thin film transistors connected in parallel are arranged in different pixels.   The display device according to claim 1, wherein the n thin film transistors connected in parallel are arranged in pixels adjacent to each other.   The display device according to claim 2, further comprising a dummy pixel region on at least one of the outer sides of the pixel column on both sides in the arrangement direction of the n thin film transistors connected in parallel to each other.   The display device according to claim 2, wherein the n is a number of 3 or more and 12 or less. A plurality of pixels having current-driven light-emitting elements;
N (n ≧ 2) thin film transistors connected in parallel for supplying a driving current to each of the current driven light emitting elements,
The display device according to claim 1, wherein the n thin film transistors connected in parallel are arranged in different pixels in a scanning direction of a laser beam used when forming the thin film transistor.   6. The display according to claim 5, wherein a channel layer of the n thin film transistors connected in parallel is formed of a polycrystalline silicon film formed by irradiating an amorphous silicon film with a laser beam. apparatus.   The display device according to claim 5, wherein the n thin film transistors connected in parallel are arranged in pixels adjacent to each other.   8. The display device according to claim 7, further comprising a dummy pixel region on at least one of the outer sides of the pixel column on both sides in the arrangement direction of the n thin film transistors connected in parallel to each other.   The display device according to claim 7, wherein the n is a number of 3 to 12. A plurality of pixels having current-driven light-emitting elements;
m (m ≧ 2) current supply wiring electrodes;
N (n ≧ 2) thin film transistors connected in parallel to be connected to one of the m current supply wiring electrodes and to supply a driving current to each of the current driven light emitting elements. Prepared,
The display device according to claim 1, wherein the n thin film transistors connected in parallel are connected to different current supply wiring electrodes. The plurality of pixels are arranged in a matrix,
The display device according to claim 10, wherein the m current supply wiring electrodes are provided for each pixel column. A plurality of pixels having current-driven light-emitting elements;
m (m ≧ 2) current supply wiring electrodes;
N (n ≧ 2) thin film transistors connected in parallel to be connected to one of the m current supply wiring electrodes and to supply a driving current to each of the current driven light emitting elements. Prepared,
The n thin film transistors connected in parallel are connected to different current supply wiring electrodes,
The wiring layer for supplying the driving current to each current-driven light emitting element is formed of a semiconductor layer that is formed integrally with the channel layer of each thin film transistor and is electrically connected to the channel layer of each thin film transistor. A display device. The plurality of pixels are arranged in a matrix,
13. The display device according to claim 12, wherein the m current supply wiring electrodes are provided for each pixel column. A plurality of pixels having current-driven light-emitting elements;
N (n ≧ 2) thin film transistors connected in parallel for supplying a driving current to each of the current driven light emitting elements,
A storage capacitor connected to each gate electrode of the n thin film transistors connected in parallel and holding a video signal voltage for controlling a driving current supplied to each current driven light emitting element for one frame;
The display device, wherein the storage capacitor element is disposed in a pixel different from a pixel in which a current-driven light emitting element to which a driving current is supplied by the n thin film transistors connected in parallel is disposed. .   The storage capacitor element is provided in a region outside the light emitting region in a pixel different from a pixel in which a current driven light emitting device to which a driving current is supplied by the n thin film transistors connected in parallel is arranged. The display device according to claim 14. m (m ≧ 2) current supply wiring electrodes,
The display device according to claim 14, wherein the storage capacitor element is disposed below the m current supply wiring electrodes.   One electrode constituting the storage capacitor element is formed integrally with the channel layer of the n thin film transistors connected in parallel and is electrically connected to one of the m current supply wiring electrodes. The display device according to claim 16, comprising a semiconductor layer.   The other electrode constituting the storage capacitor is formed integrally with the gate electrodes of the n thin film transistors connected in parallel, and is electrically connected to the gate electrodes of the n thin film transistors connected in parallel. The display device according to claim 17, comprising a wiring layer connected and facing the semiconductor layer with an insulating film interposed therebetween. The plurality of pixels are arranged in a matrix,
The display device according to claim 16, wherein the m current supply wiring electrodes are provided for each pixel column. Each pixel includes a plurality of pixels having a current-driven light-emitting element and n (n ≧ 2) thin film transistors that supply a drive current to the current-driven light-emitting element.
A display device, comprising: a reflective layer disposed below the current-driven light-emitting element and covering at least part of the n thin film transistors. N thin film transistors connected in parallel for supplying a driving current to each of the current driven light emitting elements,
21. The display device according to claim 20, wherein the n thin film transistors connected in parallel are arranged in different pixels.   21. The display device according to claim 20, wherein the n thin film transistors connected in parallel are arranged in different pixels in a scanning direction of a laser beam used when forming the thin film transistor.   23. The display according to claim 22, wherein a channel layer of the n thin film transistors connected in parallel is formed of a polycrystalline silicon film formed by irradiating a laser beam to an amorphous silicon film. apparatus.   The display device according to claim 21, wherein the n thin film transistors connected in parallel are arranged in pixels adjacent to each other.   25. The display device according to claim 24, wherein a dummy pixel region is provided on at least one of the outer sides of the pixel column on both sides in the arrangement direction of the n thin film transistors connected in parallel to each other.   The display device according to claim 24, wherein the n is a number of 3 to 12. A plurality of pixels each having a current-driven light-emitting element and n (n ≧ 2) thin film transistors that supply a drive current to the current-driven light-emitting element;
A reflective layer disposed under the current-driven light-emitting element and covering at least a part of the n thin film transistors;
m (m ≧ 2) current supply wiring electrodes,
N thin film transistors connected in parallel for supplying a driving current to each of the current driven light emitting elements,
The display device according to claim 1, wherein the n thin film transistors connected in parallel are connected to different current supply wiring electrodes. The plurality of pixels are arranged in a matrix,
28. The display device according to claim 27, wherein the m current supply wiring electrodes are provided for each pixel column. A plurality of pixels each having a current-driven light-emitting element and n (n ≧ 2) thin film transistors that supply a drive current to the current-driven light-emitting element;
A reflective layer disposed under the current-driven light-emitting element and covering at least a part of the n thin film transistors;
m (m ≧ 2) current supply wiring electrodes,
N thin film transistors connected in parallel for supplying a driving current to each of the current driven light emitting elements,
The n thin film transistors connected in parallel are connected to different current supply wiring electrodes,
The wiring layer for supplying the driving current to each current-driven light emitting element is formed of a semiconductor layer that is formed integrally with the channel layer of each thin film transistor and is electrically connected to the channel layer of each thin film transistor. A display device. The plurality of pixels are arranged in a matrix,
30. The display device according to claim 29, wherein the m current supply wiring electrodes are provided for each pixel column. A current-driven light-emitting element; a thin-film transistor that supplies a drive current to the current-driven light-emitting element;
A holding capacitor element connected to the gate electrode of the thin film transistor and holding a video signal voltage for controlling a driving current supplied to the current-driven light emitting element for one frame;
A display device, comprising: a reflective layer disposed under the current-driven light-emitting element and covering the thin film transistor and the storage capacitor element. In each pixel, a plurality of pixels each having a current-driven light-emitting element and n (n ≧ 2) thin film transistors that supply a drive current to the current-driven light-emitting element;
A reflective layer disposed below the current-driven light-emitting element and covering at least a part of the n thin film transistors;
N thin film transistors connected in parallel for supplying a driving current to each of the current driven light emitting elements,
A holding capacitance element connected to each gate electrode of the n thin film transistors connected in parallel, and holding a video signal voltage for controlling a driving current supplied to each current driven light emitting element for one frame;
The storage capacitor element is disposed below the reflective layer in a pixel different from a pixel in which a current-driven light emitting element to which a driving current is supplied by the n thin film transistors connected in parallel is disposed. A display device characterized by that. m (m ≧ 2) current supply wiring electrodes,
One electrode constituting the storage capacitor element is formed integrally with the channel layer of the n thin film transistors connected in parallel and is electrically connected to one of the m current supply wiring electrodes. The display device according to claim 32, comprising a semiconductor layer.   The other electrode constituting the storage capacitor is formed integrally with the gate electrodes of the n thin film transistors connected in parallel, and is electrically connected to the gate electrodes of the n thin film transistors connected in parallel. 34. The display device according to claim 33, comprising a wiring layer connected and facing the semiconductor layer with an insulating film interposed therebetween. A substrate,
A plurality of current-driven light emitting elements provided on the substrate;
An external connection terminal provided on an edge of one side of the substrate;
In a contact region provided between the external connection terminal portion and a region where the plurality of current-driven light-emitting elements are provided, the external connection is electrically connected to cathode electrodes of the plurality of current-driven light-emitting elements. A display device comprising: a lead wiring electrically connected to an arbitrary terminal of the terminal portion.

Images