JP2008118071A - Mounting component, and semiconductor device - Google Patents

Mounting component, and semiconductor device Download PDF

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JP2008118071A
JP2008118071A JP2006302375A JP2006302375A JP2008118071A JP 2008118071 A JP2008118071 A JP 2008118071A JP 2006302375 A JP2006302375 A JP 2006302375A JP 2006302375 A JP2006302375 A JP 2006302375A JP 2008118071 A JP2008118071 A JP 2008118071A
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semiconductor element
die pad
element chip
semiconductor
semiconductor device
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JP4940900B2 (en
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Tadao Hayashi
忠雄 林
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Nichia Chemical Industries Ltd
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Nichia Chemical Industries Ltd
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/48463Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch

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Abstract

<P>PROBLEM TO BE SOLVED: To provide a mounting component that can have high reliability regardless of the size of a semiconductor element chip to be mounted, and to provide a semiconductor device using the mounting component. <P>SOLUTION: The mounting component is provided with a die pad that allows the polygonal bottom of a semiconductor element chip to be secured to a portion of the top surface of an insulating member with a hot-melt metal joining member. The die pad has, at its periphery, multiple elongated portions that correspond to respective bottom end portions of semiconductor chips having similar and different bottom sizes, and the width of each elongated portion is decreased toward the end. A semiconductor device has the mounting component provided with the die pad that allows the polygonal bottom of the semiconductor element chip to be secured to a portion of the top surface of the insulating member with the hot-melt metal joining member. The die pad has, at its periphery, the multiple elongated portions that correspond to the respective bottom end portions of the semiconductor element chip, and the width of each elongated portion is decreased toward to the end. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

本発明は、発光ダイオード(Light Emitting Diode、以下「LED」ともいう)等の半導体チップを搭載するための実装用部品、およびそれを用いた半導体装置に関するものである。 The present invention relates to a mounting component for mounting a semiconductor chip such as a light emitting diode (hereinafter also referred to as “LED”), and a semiconductor device using the same.

従来の半導体素子チップの実装用部品として、絶縁性基板の上面に形成した金属膜によるダイパッドの形状を、搭載する半導体素子チップの形状と相似形状とすることで、セルフアライメント効果により、リフロー時において半導体チップとダイパッド部との各辺をほぼ平行とすることが可能な実装用部品が知られている。 As a conventional semiconductor element chip mounting component, the shape of the die pad made of a metal film formed on the top surface of the insulating substrate is similar to the shape of the semiconductor element chip to be mounted. 2. Description of the Related Art A mounting component that can make each side of a semiconductor chip and a die pad portion substantially parallel is known.

しかしながら、上記の実装用部品において、ダイパッドの形状が半導体チップよりも緩やかに大きな相似形状の場合、半導体素子チップはダイパッド部の上面に沿って中心からずれるように移動してしまい、そのまま固定されてしまうという問題があった。 However, in the mounting component described above, when the die pad has a similar shape that is moderately larger than the semiconductor chip, the semiconductor element chip moves away from the center along the upper surface of the die pad portion and is fixed as it is. There was a problem that.

そこで、ダイパッドの中心から半導体素子チップがずれて固定されることを抑制するため、ダイパッドの矩形における長さ寸法及び幅寸法を半導体素子チップの長さ寸法及び幅寸法の0.50〜1.50倍とする手法が開示されている。さらに、接合部材の盛り上がり高さを低くすることを目的として、ダイパッドの周囲に当該ダイパッドから一体的に外向きに延びた略矩形形状の延長部を部分的に設けることも開示されている。 Therefore, in order to prevent the semiconductor element chip from being fixed while being displaced from the center of the die pad, the length dimension and width dimension of the die pad rectangle are set to 0.50 to 1.50 of the length dimension and width dimension of the semiconductor element chip. A method of doubling is disclosed. Furthermore, for the purpose of reducing the raised height of the joining member, it has also been disclosed that a substantially rectangular extension part extending integrally outward from the die pad is partially provided around the die pad.

特開2003−264267号公報JP 2003-264267 A

しかしながら、上記の構成の実装用部品において、半導体素子チップの底面が前記延長部の少なくとも一部を覆う大きさを有している場合、前記延長部は幅が均一な略矩形形状であることから、半導体素子チップの対角方向へのセルフアライメント効果はほとんど生じず、半導体素子チップをダイパッドの中心に固定することは困難である。 However, in the mounting component having the above configuration, when the bottom surface of the semiconductor element chip has a size that covers at least a part of the extension, the extension has a substantially rectangular shape with a uniform width. The self-alignment effect in the diagonal direction of the semiconductor element chip hardly occurs, and it is difficult to fix the semiconductor element chip to the center of the die pad.

そこで本発明は、搭載する半導体素子チップのサイズに関係なく、信頼性高く実装することが可能な実装用部品およびそれを用いた半導体装置を提供する。 Therefore, the present invention provides a mounting component that can be mounted with high reliability regardless of the size of a semiconductor element chip to be mounted, and a semiconductor device using the same.

本発明の実装用部品は、絶縁性部材の上面の一部に底面が多角形である半導体素子チップの前記底面を加熱溶融性の金属接合部材にて固定することが可能なダイパッドを備えた実装用部品であって、前記ダイパッドは、前記底面のサイズが相似状に異なる複数の半導体素子チップの各底面角にそれぞれ対応する複数の細長部を周縁に有しており、前記細長部の幅は、先端側へ狭くなっていることを特徴とする。 The mounting component of the present invention includes a die pad capable of fixing the bottom surface of a semiconductor element chip having a polygonal bottom surface to a part of the top surface of the insulating member with a heat-meltable metal bonding member. The die pad has a plurality of elongated portions on the periphery corresponding to respective bottom surface angles of a plurality of semiconductor element chips having different sizes of the bottom surfaces, and the width of the elongated portions is , Narrowing toward the tip side.

本発明の半導体装置は、絶縁性部材の上面の一部に底面が多角形である半導体素子チップの前記底面が加熱溶融性の金属接合部材にて固定されたダイパッドを備えた実装用部品を有する半導体装置であって、前記ダイパッドは、前記半導体素子チップの各底面角にそれぞれ対応する複数の細長部を周縁に有しており、前記細長部の幅は、先端側へ狭くなっていることを特徴とする。 A semiconductor device according to the present invention has a mounting component including a die pad in which a bottom surface of a semiconductor element chip having a polygonal bottom surface is fixed to a part of a top surface of an insulating member by a heat-meltable metal bonding member. In the semiconductor device, the die pad has a plurality of elongated portions on the periphery corresponding to the respective bottom corners of the semiconductor element chip, and the width of the elongated portion is narrowed toward the tip side. Features.

また、本発明の実装用部品および半導体装置では、前記細長部は、先端が鋭角であることが好ましい。 In the mounting component and the semiconductor device of the present invention, it is preferable that a tip of the elongated portion has an acute angle.

また、本発明の半導体装置において、前記絶縁性部材の上面と前記金属接合部材との接触角は100度以上であり、前記ダイパッドの上面と前記金属接合部材との接触角は80度以下であることが好ましい。   In the semiconductor device of the present invention, the contact angle between the upper surface of the insulating member and the metal bonding member is 100 degrees or more, and the contact angle between the upper surface of the die pad and the metal bonding member is 80 degrees or less. It is preferable.

特に、本発明の半導体装置において、半導体素子チップが発光素子チップである場合は、各発光装置間における色むらを低減させることができる。 In particular, in the semiconductor device of the present invention, when the semiconductor element chip is a light emitting element chip, color unevenness between the light emitting devices can be reduced.

本発明の実装用部品は、任意の大きさの半導体素子チップに対して良好なセルフアライメント効果を有するダイパッドを備えていることから、搭載する半導体素子チップの大きさに関係なく半導体素子チップを精度よく実装することができる。また、本発明の半導体装置は、半導体素子チップが精度よく実装されていることから、高い信頼性を有している。 The mounting component according to the present invention includes a die pad having a good self-alignment effect with respect to a semiconductor element chip of an arbitrary size, so that the semiconductor element chip is accurate regardless of the size of the mounted semiconductor element chip. Can be implemented well. The semiconductor device of the present invention has high reliability since the semiconductor element chip is mounted with high accuracy.

本発明を実施するための最良の形態を、以下に図面を参照しながら説明する。ただし、以下に示す形態は、本発明の技術的思想を具体化するための実装用部品および半導体装置を例示するものであって、本発明の実装用部品および半導体装置を以下に限定するものではない。また、本明細書は特許請求の範囲に示される部材を、実施の形態の部材に特定するものでは決してない。実施の形態に記載されている構成部品の寸法、材質、形状、その相対的配置等は、特に特定的な記載がない限りは、本発明の範囲をそれのみに限定する趣旨ではなく、単なる説明例にすぎない。なお、各図面が示す部材の大きさや位置関係等は、説明を明確にするため誇張していることがある。さらに以下の説明において、同一の名称、符号については同一もしくは同質の部材を示しており、詳細な説明を適宜省略する。さらに、本発明を構成する各要素は、複数の要素を同一の部材で構成して一の部材で複数の要素を兼用する態様としてもよいし、逆に一の部材の機能を複数の部材で分担して実現することもできる。 The best mode for carrying out the present invention will be described below with reference to the drawings. However, the form shown below exemplifies a mounting component and a semiconductor device for embodying the technical idea of the present invention, and does not limit the mounting component and the semiconductor device of the present invention to the following. Absent. Further, the present specification by no means specifies the members shown in the claims to the members of the embodiments. The dimensions, materials, shapes, relative arrangements, and the like of the components described in the embodiments are not intended to limit the scope of the present invention only to the description unless otherwise specified. It is just an example. Note that the size, positional relationship, and the like of the members shown in each drawing may be exaggerated for clarity of explanation. Further, in the following description, the same name and reference sign indicate the same or the same members, and detailed description will be omitted as appropriate. Furthermore, each element constituting the present invention may be configured such that a plurality of elements are constituted by the same member and the plurality of elements are shared by one member, and conversely, the function of one member is constituted by a plurality of members. It can also be realized by sharing.

本発明の半導体装置は、絶縁性部材101と前記絶縁性部材101の上面に形成された金属からなるダイパッド102とを有する実装用部品を用い、前記ダイパッド102の上面側と半導体素子チップ103の底面側とを加熱溶融性の金属接合部材にて固定したものである。図1乃至図7は、第1乃至第7の実施形態を示す模式的平面図である。図1乃至図4に記載の実装用部品に搭載されている半導体素子チップ103,203,303,404は、それぞれサイズが相似状に異なる略正方形の底面を有する略直方体であり、図5乃至図7に記載の実装用部品に搭載されている半導体素子チップ503,603,703は、それぞれサイズが相似状に異なる略長方形の底面を有する略直方体である。 The semiconductor device of the present invention uses a mounting component having an insulating member 101 and a metal die pad 102 formed on the upper surface of the insulating member 101, and uses the upper surface side of the die pad 102 and the bottom surface of the semiconductor element chip 103. The side is fixed with a heat-meltable metal joining member. 1 to 7 are schematic plan views showing the first to seventh embodiments. The semiconductor element chips 103, 203, 303, and 404 mounted on the mounting components shown in FIGS. 1 to 4 are substantially rectangular parallelepipeds each having a substantially square bottom surface with different sizes. The semiconductor element chips 503, 603, and 703 mounted on the mounting component according to 7 are substantially rectangular parallelepipeds each having a substantially rectangular bottom surface having different sizes.

(絶縁性部材101)
本発明の実装用部品は、絶縁性部材101の上面側に金属製のダイパッド102が形成されている。絶縁性部材101の大きさや形状は、特に限定されるものではなく、例えば、円柱、楕円柱、球、卵形、三角柱、四角柱、多角柱又はこれらに近似する形状等どのような形状でもよい。また、絶縁性部材101は、絶縁性を確保することができるものであれば、どのような材料によって形成されていてもよい。例えば、ポリフタルアミド(PPA)、ポリカーボネート樹脂、ポリフェニレンサルファイド(PPS)、液晶ポリマー(LCP)、ABS樹脂、エポキシ樹脂、フェノール樹脂、アクリル樹脂、PBT樹脂等の樹脂、セラミック、硝子等があげられる。なかでも、後述する接合部材との接触角が90°を超える材料であることが適しており、さらに100°以上の材料を用いることが好ましく、このような材料を選択することにより、半導体素子チップの固定時におけるセルフアライメント効果をより顕著に発現させることができる。また、絶縁性部材101に、着色剤として種々の染料又は顔料等を混合して用いてもよい。例えば、Cr、MnO、Fe、カーボンブラック等があげられる。ここで、本明細書において接触角とは、材料の性質を表すものであり、静止している液体の接合部材の自由上面が固体の上面に接する所で液面と固体面とのなす角度のことをいう。具体的には、接合部材の融点+40〜50℃における静適法によって測定することができる。
(Insulating member 101)
In the mounting component of the present invention, a metal die pad 102 is formed on the upper surface side of the insulating member 101. The size and shape of the insulating member 101 are not particularly limited, and may be any shape such as a cylinder, an elliptical column, a sphere, an oval, a triangular column, a quadrangular column, a polygonal column, or a shape similar to these. . Further, the insulating member 101 may be formed of any material as long as the insulating property can be ensured. Examples thereof include resins such as polyphthalamide (PPA), polycarbonate resin, polyphenylene sulfide (PPS), liquid crystal polymer (LCP), ABS resin, epoxy resin, phenol resin, acrylic resin, PBT resin, ceramic, glass, and the like. Among them, it is suitable that the contact angle with a joining member described later is more than 90 °, and it is preferable to use a material having a contact angle of 100 ° or more. By selecting such a material, a semiconductor element chip is used. The self-alignment effect at the time of fixing can be expressed more significantly. Moreover, you may mix and use various dyes or pigments for the insulating member 101 as a coloring agent. For example, Cr 2 O 3, MnO 2 , Fe 2 O 3, carbon black and the like. Here, the contact angle in this specification represents the property of the material, and is an angle formed between the liquid surface and the solid surface where the free upper surface of the stationary liquid joining member contacts the upper surface of the solid. That means. Specifically, it can be measured by a static method at a melting point of the joining member +40 to 50 ° C.

(ダイパッド102)
絶縁性部材101の上面に形成されたダイパッド102を構成する材料は、少なくともダイパッド102の上面と後述する加熱溶融性の金属接合部材との接触角が90度以下であれば、特に限定されないが、80度以下の材料を用いることが好ましく、より好ましくは60度以下、さらには45度以下の材料であることが好ましい。また、別の観点から、ダイパッド102の上面と前記接合部材との接触角と、絶縁性部材101と前記接合部材との接触角との差は、10度以上であることが好ましく、より好ましくは20度以上、さらに好ましくは30度以上であることが好ましい。これにより、接合部材は、絶縁性部材101よりも濡れ易いダイパッド102の領域に浸潤し、半導体素子チップ101をダイパッドの所望とする領域により容易にアライメントさせることができる。このように、少なくともダイパッドの上面の材料を選択することにより、半導体素子チップ101の固定時におけるセルフアライメント効果をより顕著に発現させることができる。また、半導体発光素子チップを用いる場合、少なくともダイパッドの上面は、半導体素子チップからの光に対して70%以上の光反射率を有していることが好ましく、より好ましくは80%以上、さらに好ましくは85%以上、さらに好ましくは90%以上の光反射率を有するものが好ましい。ここで、本明細書において光反射率とは、村上色彩技術研究所製CMS−35SPの分光光度計を用いたSCI方式にて測定した値をいう。ダイパッド102は、例えば、Al、Ag、Au、Pd等の単層膜又は積層膜により構成することができる。この成膜方法としては、公知の方法、例えば、蒸着、スパッタ法、メッキ法等、種々の方法を利用することができる。
(Die pad 102)
The material constituting the die pad 102 formed on the upper surface of the insulating member 101 is not particularly limited as long as the contact angle between at least the upper surface of the die pad 102 and a heat-meltable metal bonding member described later is 90 degrees or less. It is preferable to use a material of 80 degrees or less, more preferably 60 degrees or less, and further preferably 45 degrees or less. From another viewpoint, the difference between the contact angle between the upper surface of the die pad 102 and the bonding member and the contact angle between the insulating member 101 and the bonding member is preferably 10 degrees or more, more preferably It is preferably 20 degrees or more, more preferably 30 degrees or more. As a result, the bonding member infiltrates into the region of the die pad 102 that is more easily wetted than the insulating member 101, and the semiconductor element chip 101 can be easily aligned with the desired region of the die pad. Thus, by selecting the material of at least the upper surface of the die pad, the self-alignment effect at the time of fixing the semiconductor element chip 101 can be exhibited more significantly. Further, when using a semiconductor light emitting device chip, it is preferable that at least the upper surface of the die pad has a light reflectance of 70% or more, more preferably 80% or more, even more preferably with respect to light from the semiconductor device chip. Is preferably 85% or more, more preferably 90% or more. Here, the light reflectance in this specification refers to a value measured by an SCI method using a CMS-35SP spectrophotometer manufactured by Murakami Color Research Laboratory. The die pad 102 can be composed of a single layer film or a laminated film of Al, Ag, Au, Pd, or the like, for example. As the film forming method, various known methods such as vapor deposition, sputtering, plating, etc. can be used.

本発明のダイパッド102の上面形状は、先端に向かって幅が狭まった形状の細長部を周縁に複数有しており、前記細長部は、リフローの工程の際に、底面のサイズが相似状に異なる複数の半導体素子チップの各底面角にそれぞれ対応する。これにより、半導体素子チップを位置ずれや浮きがなく、厳しい環境下にて使用しても高い信頼性を維持することが可能な状態で固定することができる。ここで、ダイパッド102の細長部は、先端に向かって幅が徐々に狭く構成されていれば特に限定されず、図1や図5に示すに先端に2角を有していてもよく、図2に示すように先端に設けられた各角部に丸みを帯びていてもよい。また、図3や図6のように、搭載する半導体素子チップ303,603の底面がダイパッド302,602に外接する大きさである場合、前記細長部の先端は鋭角であることが好ましい。これにより、半導体素子チップ303,603の底面をダイパッド302,602へ実装する精度をより高めることができる。また、図5乃至図7のように、隣り合う細長部の間に、搭載する半導体素子チップの辺と平行な辺を有していることが好ましく、これにより実装精度をさらに高めることができる。 The top surface shape of the die pad 102 of the present invention has a plurality of elongated portions whose widths are narrowed toward the tip, and the elongated portions have a similar bottom surface size during the reflow process. It corresponds to each bottom corner of a plurality of different semiconductor element chips. As a result, the semiconductor element chip can be fixed in a state in which the semiconductor element chip is not displaced or floated and can maintain high reliability even when used in a severe environment. Here, the elongated portion of the die pad 102 is not particularly limited as long as the width is gradually narrowed toward the tip, and may have two corners at the tip as shown in FIGS. As shown in FIG. 2, each corner provided at the tip may be rounded. 3 and 6, when the bottom surfaces of the semiconductor element chips 303 and 603 to be mounted are sized to circumscribe the die pads 302 and 602, it is preferable that the tip of the elongated portion has an acute angle. Thereby, the precision which mounts the bottom face of semiconductor element chip 303,603 on die pad 302,602 can be raised more. Further, as shown in FIGS. 5 to 7, it is preferable to have a side parallel to the side of the semiconductor element chip to be mounted between the adjacent elongated portions, whereby the mounting accuracy can be further improved.

(導電性部材105)
絶縁性部材101の上面には、ダイパッド102と離間して一対の導電性部材105が形成されており、該導電性部材105はそれぞれ半導体素子チップ103の電極と電気的に接続されている。導電性部材105は、導電性を有していれば特に限定されないが、熱伝導率の比較的大きな材料で形成することが好ましい。例えば、200W/(m・K)程度以上の熱伝導率を有しているもの、比較的大きい機械的強度を有するもの、あるいは打ち抜きプレス加工又はエッチング加工等が容易な材料が好ましい。例えば、銅、アルミニウム、金、銀、タングステン、鉄、ニッケル等の金属又は鉄−ニッケル合金、燐青銅、鉄入り銅等あるいはこれらの上面に銀、アルミニウム、銅、金等の金属メッキ膜が施こされたもの等があげられる。
(Conductive member 105)
A pair of conductive members 105 are formed on the upper surface of the insulating member 101 so as to be separated from the die pad 102, and the conductive members 105 are electrically connected to the electrodes of the semiconductor element chip 103, respectively. The conductive member 105 is not particularly limited as long as it has conductivity, but is preferably formed of a material having a relatively high thermal conductivity. For example, a material having a thermal conductivity of about 200 W / (m · K) or more, a material having a relatively large mechanical strength, or a material that can be easily punched or etched is preferable. For example, metal such as copper, aluminum, gold, silver, tungsten, iron, nickel or iron-nickel alloy, phosphor bronze, iron-containing copper, etc. or a metal plating film such as silver, aluminum, copper, gold, etc. is applied on the upper surface. Scraps etc. are listed.

また、図4に示すように、導電性部材105の一方とダイパッド102とが連結部406にて一体的に繋がっていてもよい。この場合、連結部104は、ダイパッド102の細長部の先端部に設けることが好ましく、これにより連結部104がセルフアライメント効果の妨げとなることを抑制することができる。   As shown in FIG. 4, one of the conductive members 105 and the die pad 102 may be integrally connected by a connecting portion 406. In this case, the connecting portion 104 is preferably provided at the distal end portion of the elongated portion of the die pad 102, which can prevent the connecting portion 104 from hindering the self-alignment effect.

(半導体素子チップ103、303、403、503、603、703)
本発明で用いられる半導体素子チップ103は、従来から知られている半導体素子チップ103のうち、ダイパッド102と固定される底面が多角形であれば特に限定されず、底面と該底面と対向する上面とが同一形状でなくてもよい。また、具体的な材料構成は、例えば、基板上に、InN、AlN、GaN、InGaN、AlGaN、InGaAlN等の窒化物半導体、III−V族化合物半導体、II−VI族化合物半導体等、種々の半導体によって、活性層を含む積層構造が形成されたものがあげられる。基板としては、C面、A面、R面のいずれかを主面とするサファイアやスピネル(MgA1)のような絶縁性基板、また炭化珪素、シリコン、ZnS、ZnO、GaAs、ダイヤモンド;ニオブ酸リチウム、ガリウム酸ネオジウム等の酸化物基板、窒化物半導体基板(GaN、AlN等)等があげられる。半導体の構造としては、MIS接合、PIN接合、PN接合などのホモ構造、ヘテロ結合あるいはダブルヘテロ結合のものがあげられる。また、半導体活性層を量子効果が生ずる薄膜に形成させた単一量子井戸構造、多重量子井戸構造としてもよい。活性層には、Si、Ge等のドナー不純物及び/又はZn、Mg等のアクセプター不純物がドープされる場合もある。得られる発光素子の発光波長は、半導体の材料、混晶比、活性層のInGaNのIn含有量、活性層にドープする不純物の種類を変化させるなどによって、紫外領域から赤色まで変化させることができる。また、本発明に用いられる半導体素子チップ103は、底面と対向する上面側にn電極及びp電極が形成された片面電極のものであってもよいし、上面および底面にそれぞれ各電極が形成された両面電極のものであってもよい。
(Semiconductor element chips 103, 303, 403, 503, 603, 703)
The semiconductor element chip 103 used in the present invention is not particularly limited as long as the bottom surface fixed to the die pad 102 is a polygon among the conventionally known semiconductor element chips 103, and the bottom surface and the top surface facing the bottom surface. And do not have to have the same shape. Further, specific material configurations include various semiconductors such as nitride semiconductors such as InN, AlN, GaN, InGaN, AlGaN, and InGaAlN, III-V group compound semiconductors, and II-VI group compound semiconductors on a substrate. Can be obtained by forming a laminated structure including an active layer. As a substrate, an insulating substrate such as sapphire or spinel (MgA1 2 O 4 ) whose main surface is any one of C-plane, A-plane, and R-plane, silicon carbide, silicon, ZnS, ZnO, GaAs, diamond; Examples thereof include oxide substrates such as lithium niobate and neodymium gallate, and nitride semiconductor substrates (GaN, AlN, etc.). Examples of the semiconductor structure include homostructures such as MIS junctions, PIN junctions, and PN junctions, heterojunctions, and double heterojunctions. Alternatively, the semiconductor active layer may have a single quantum well structure or a multiple quantum well structure in which a thin film in which a quantum effect is generated is formed. The active layer may be doped with donor impurities such as Si and Ge and / or acceptor impurities such as Zn and Mg. The emission wavelength of the resulting light-emitting element can be changed from the ultraviolet region to red by changing the semiconductor material, the mixed crystal ratio, the In content of InGaN in the active layer, the type of impurities doped in the active layer, etc. . The semiconductor element chip 103 used in the present invention may be a single-sided electrode in which an n-electrode and a p-electrode are formed on the upper surface facing the bottom surface, or each electrode is formed on the top surface and the bottom surface. Alternatively, it may be a double-sided electrode.

半導体素子チップ103の底面は、全面又は一部に金属膜を有している。金属膜は、少なくとも最表面が、後述する加熱溶融性の金属接合部材との接触角が90度より大きい材料で、かつ、接合部材より高融点の材料で構成されていることが好ましく、これにより、リフロー時に前記接合材料が半導体素子側へ拡散浸透することを防止することができる。具体的材料としてはAu、Ag、Cu、Ptなどがあげられる。また、成膜方法は、公知の方法、例えば、蒸着、スパッタ法、メッキ法等、種々の方法を利用することができる。金属膜は、蒸着やスパッタ、めっき等により形成することができる。   The bottom surface of the semiconductor element chip 103 has a metal film on the entire surface or a part thereof. At least the outermost surface of the metal film is preferably made of a material having a contact angle larger than 90 degrees with a heat-meltable metal joining member described later, and a material having a higher melting point than the joining member. It is possible to prevent the bonding material from diffusing and penetrating to the semiconductor element side during reflow. Specific materials include Au, Ag, Cu, Pt and the like. As the film forming method, various known methods such as vapor deposition, sputtering, plating, etc. can be used. The metal film can be formed by vapor deposition, sputtering, plating, or the like.

また、半導体発光素子チップを用いる場合、半導体素子チップの底面全体に金属膜を形成するのではなく、前記底面に互いに離間した金属部位を複数設けることが好ましい。これにより、発光素子チップの底面側からの光取り出し効率を高めることができる。また、このような金属部位は、少なくとも半導体発光素子チップの底面と対向する面が半導体発光素子チップからの光に対する反射率が70%以上である光反射性機能を有していることが好ましく、これにより金属部位による光吸収を抑制することができる。また、半導体発光素子チップの底面側に電極が形成されている場合、電極自体を導電性と上記の光反射性機能とを兼ね備えた材料にて構成することもでき、具体的材料としてAl、Ag、Au、Pdなどがあげられる。 Further, when using a semiconductor light emitting element chip, it is preferable not to form a metal film on the entire bottom surface of the semiconductor element chip, but to provide a plurality of metal parts spaced apart from each other on the bottom surface. Thereby, the light extraction efficiency from the bottom surface side of the light emitting element chip can be increased. In addition, it is preferable that such a metal part has a light reflecting function in which at least a surface facing the bottom surface of the semiconductor light emitting element chip has a reflectance of 70% or more with respect to light from the semiconductor light emitting element chip. Thereby, the light absorption by a metal part can be suppressed. Further, when an electrode is formed on the bottom surface side of the semiconductor light emitting element chip, the electrode itself can be made of a material having both conductivity and the above-described light reflecting function. , Au, Pd and the like.

また、上記の光反射性機能を有する部材は、他の部材が混合されると光反射機能を大きく損なってしまう。そこで、半導体発光チップは、半導体素子チップの底面側から、光反射性機能を有する第一の層と、該第一の層を被服するMo、W、Nb、Rh、Ta、Ti等の超高融点材料からなる第二の層と、該第二の層を被覆するAu、Ag、Cu、Pt等の接合部材との濡れ性が良好でかつ高融点材料の材料からなる第三の層と、を有していることが好ましい。これにより、接合部材が光反射性機能を有する第1の層に混入することを抑制することができる。これらの各層は、公知の方法、例えば、蒸着、スパッタ法、メッキ法等、種々の方法を利用して積層することができる。 In addition, the member having the light reflecting function described above significantly impairs the light reflecting function when other members are mixed. Therefore, the semiconductor light emitting chip has a first layer having a light reflecting function from the bottom surface side of the semiconductor element chip, and an ultra-high layer such as Mo, W, Nb, Rh, Ta, and Ti covering the first layer. A third layer made of a material of a high melting point material having good wettability with a second layer made of a melting point material and a joining member such as Au, Ag, Cu, and Pt covering the second layer; It is preferable to have. Thereby, it can suppress that a joining member mixes in the 1st layer which has a light reflectivity function. Each of these layers can be laminated using various methods such as known methods such as vapor deposition, sputtering, and plating.

(加熱溶融性の金属接合部材(図示していない))
加熱溶融性の金属接合部材は、半導体素子チップ103をダイパッド102a,102bに載置、固定するために用いられるものであり、例えば、SnPb系、SnAgCu系、AuSn系、SnZn系、SuCu系等のハンダ材料を好適に使用することができる。なかでも、AuSn系のハンダ材料が半導体装置をリフロー固定する場合に対しての耐熱性と接合信頼性の面で好ましい。また、任意に、これらに、濡れ性又はハンダクラック性を改善する目的で、Bi、In等を添加してもよい。
(Heat-meltable metal joining member (not shown))
The heat-meltable metal bonding member is used for mounting and fixing the semiconductor element chip 103 on the die pads 102a and 102b. For example, SnPb-based, SnAgCu-based, AuSn-based, SnZn-based, SuCu-based, etc. A solder material can be preferably used. Among these, AuSn solder materials are preferable in terms of heat resistance and bonding reliability when a semiconductor device is reflow-fixed. Optionally, Bi, In or the like may be added to these for the purpose of improving wettability or solder cracking property.

(ワイヤ104)
半導体素子チップ101の上面側の電極は、ワイヤ104にて導電性部材105と電気的な接続がとられている。ワイヤ104としては、半導体素子チップ101の電極とのオーミック性が良好であるか、機械的接続性が良好であるか、電気伝導性及び熱伝導性が良好なものであることが好ましい。熱伝導率としては、0.01cal/S・cm・℃/cm程度以上が好ましく、さらに0.5cal/S・cm・℃/cm程度以上がより好ましい。作業性などを考慮すると、ワイヤ104の直径は、10μm〜45μm程度であることが好ましい。このようなワイヤ104としては、例えば、金、銅、白金、アルミニウム等の金属及びそれらの合金があげられる。
(Wire 104)
The electrode on the upper surface side of the semiconductor element chip 101 is electrically connected to the conductive member 105 with a wire 104. The wire 104 preferably has good ohmic properties with the electrodes of the semiconductor element chip 101, good mechanical connectivity, or good electrical and thermal conductivity. The thermal conductivity, preferably 0.01cal / S · cm 2 · ℃ / than about cm further 0.5cal / S · cm 2 · ℃ / cm or higher order is more preferable. Considering workability and the like, the diameter of the wire 104 is preferably about 10 μm to 45 μm. Examples of such a wire 104 include metals such as gold, copper, platinum, and aluminum, and alloys thereof.

本発明の半導体装置は、通常、ダイパッド102の上面に固定された半導体素子チップ103は、導電性部材105と電気的に接続された後、封止部材にて被覆される。これにより、外力、水分等から半導体素子チップを保護することができるとともに、導通手段として用いたワイヤ等を保護することもできる。封止部材の材料としては、エポキシ樹脂、シリコーン樹脂、アクリル樹脂、ユリア樹脂またはこれらの組み合わせ等の耐候性に優れた樹脂又は硝子等があげられる。封止部材は、絶縁性部材101の材料と熱膨張係数の差が小さいものが好ましく、これにより各部材への熱応力による一体性の破壊を抑制することができる。封止部材には、顔料や拡散剤、蛍光物質を含有させてもよい。   In the semiconductor device of the present invention, the semiconductor element chip 103 fixed on the upper surface of the die pad 102 is usually electrically connected to the conductive member 105 and then covered with a sealing member. As a result, the semiconductor element chip can be protected from external force, moisture, and the like, and the wire used as the conduction means can be protected. Examples of the material for the sealing member include resins having excellent weather resistance such as epoxy resins, silicone resins, acrylic resins, urea resins, or combinations thereof, glass, and the like. The sealing member preferably has a small difference in thermal expansion coefficient from the material of the insulating member 101, and can thereby prevent the destruction of integrity due to thermal stress on each member. The sealing member may contain a pigment, a diffusing agent, and a fluorescent material.

半導体素子チップ101として半導体発光素子を用いる場合、封止部材は前記半導体発光素子からの光を透過することが可能な透光性を有していることが必須となる。透光性封止部材に拡散剤や蛍光物質を含有する、もしくは透光性封止部材の最表面に拡散剤を塗布することで、半導体発光素子からの指向性を緩和させ、視野角を増大させることができたり、半導体発光素子から部へ出射される光の波長を変換させたりすることができる。発光素子からの光がエネルギーの高い短波長の可視光の場合、有機蛍光物質であるペリレン系誘導体、ZnCdS:Cu、YAG:Ce、Eu及び/又はCrで賦活された窒素含有CaO−Al−SiOなどの無機蛍光物質など、種々の蛍光物質を好適に用いられる。 In the case where a semiconductor light emitting element is used as the semiconductor element chip 101, it is essential that the sealing member has a light transmitting property capable of transmitting light from the semiconductor light emitting element. The translucent sealing member contains a diffusing agent or a fluorescent material, or the diffusing agent is applied to the outermost surface of the translucent sealing member, thereby reducing the directivity from the semiconductor light emitting element and increasing the viewing angle. Or the wavelength of light emitted from the semiconductor light emitting element to the part can be converted. When the light from the light-emitting element is high-energy short-wavelength visible light, nitrogen-containing CaO—Al 2 O activated with a perylene derivative, ZnCdS: Cu, YAG: Ce, Eu and / or Cr, which is an organic fluorescent material Various fluorescent materials such as an inorganic fluorescent material such as 3- SiO 2 are preferably used.

半導体発光装置において、白色光を得る場合、特にYAG:Ce蛍光物質を利用すると、その含有量によって青色発光素子からの光とその光を一部吸収した前記蛍光物質が発光する補色となる黄色系の光とが混色され、白色系の光を比較的簡単に信頼性良く得ることができる。同様に、Eu及び/又はCrで賦活された窒素含有CaO−Al−SiO蛍光体を利用した場合は、その含有量によって青色発光素子からの光とその光を一部吸収した前記蛍光物質が発光する補色となる赤色系の光とが混色され、白色系の光を比較的簡単に信頼性良く得ることができる。これらの蛍光物質の他に、例えば、特開2005−19646号公報、特開2005−8844号公報等に記載の公知の蛍光物質のいずれをも用いることができる。また、発光素子からの発光と、蛍光物質に波長変換された光との混色によって、所定の色の発光を得る発光装置である場合、絶縁性基板と発光素子との界面に、光反射性のダイパッドが形成されていることによって、発光素子の底面からの光が絶縁性部材を透過することにより生じる発光装置の側面への光の回り込みを低減することができる。これにより、光を適切に混色することができ、色むらの少ない発光を得ることが可能となる。 In a semiconductor light emitting device, when white light is obtained, particularly when a YAG: Ce fluorescent material is used, a yellow color which is a complementary color emitted from the blue light emitting element and the fluorescent material partially absorbing the light depending on its content. Thus, white light can be obtained relatively easily and reliably. Similarly, when a nitrogen-containing CaO—Al 2 O 3 —SiO 2 phosphor activated with Eu and / or Cr is used, the light from the blue light emitting element and part of the light are absorbed depending on the content thereof. Red light, which is a complementary color emitted from the fluorescent material, is mixed, and white light can be obtained relatively easily and with high reliability. In addition to these fluorescent materials, any of the known fluorescent materials described in, for example, Japanese Patent Application Laid-Open Nos. 2005-19646 and 2005-8844 can be used. In the case of a light-emitting device that obtains light of a predetermined color by mixing light emitted from a light-emitting element and light that has been wavelength-converted into a fluorescent material, a light-reflective material is formed at the interface between the insulating substrate and the light-emitting element. By forming the die pad, it is possible to reduce the wraparound of light to the side surface of the light emitting device, which is caused by the light from the bottom surface of the light emitting element being transmitted through the insulating member. As a result, it is possible to mix light appropriately and to obtain light emission with less color unevenness.

また、封止部材の形状は、特に限定されず、封止部材の一部として、又は、封止部材の上面側に付属するように、レンズが設けられていてもよい。例えば、半導体素子チップの上方に、封止部材としてプラスチック又は硝子からなるレンズ等が備えられていてもよいし、半導体素子チップを直接的に覆う封止部材の上方に、別途レンズが設けたれていてもよい。また、半導体発光素子チップを用いる場合、半導体発光素子チップからの光の取り出しを効率的に行うために、絶縁性部材101の上面側に反射部材、反射防止部材、光拡散部材等、種々の部品が備えられていてもよい。 The shape of the sealing member is not particularly limited, and a lens may be provided as part of the sealing member or attached to the upper surface side of the sealing member. For example, a plastic or glass lens or the like may be provided as a sealing member above the semiconductor element chip, or a separate lens may be provided above the sealing member that directly covers the semiconductor element chip. May be. Further, when a semiconductor light emitting element chip is used, various components such as a reflection member, an antireflection member, a light diffusion member, etc. are provided on the upper surface side of the insulating member 101 in order to efficiently extract light from the semiconductor light emitting element chip. May be provided.

産業上の利用分野Industrial application fields

各種トランジスタ、スイッチングダイオード、ツェナーダイオード、可変容量ダイオード、照明用光源、各種インジケーター用光源、車載用光源、ディスプレイ用光源、液晶のバックライト用光源、信号機、車載部品、看板用チャンネルレターなど、種々の光源に使用することができる。   Various transistors, switching diodes, Zener diodes, variable capacitance diodes, illumination light sources, various indicator light sources, in-vehicle light sources, display light sources, liquid crystal backlight light sources, traffic lights, in-vehicle components, signboard channel letters, etc. Can be used for light source.

本発明の実施の形態の半導体装置の概略平面図である。1 is a schematic plan view of a semiconductor device according to an embodiment of the present invention. 本発明の第2の実施の形態の半導体装置の概略平面図である。It is a schematic plan view of the semiconductor device of the 2nd Embodiment of this invention. 本発明の第3の実施の形態の半導体装置の概略平面図である。It is a schematic plan view of the semiconductor device of the 3rd Embodiment of this invention. 本発明の第4の実施の形態の半導体装置の概略平面図である。It is a schematic plan view of the semiconductor device of the 4th Embodiment of this invention. 本発明の第5の実施の形態の半導体装置の概略平面図である。It is a schematic plan view of the semiconductor device of the 5th Embodiment of this invention. 本発明の第6の実施の形態の半導体装置の概略平面図である。It is a schematic plan view of the semiconductor device of the 6th Embodiment of this invention. 本発明の第7の実施の形態の半導体装置の概略平面図である。It is a schematic plan view of the semiconductor device of the 7th Embodiment of this invention.

符号の説明Explanation of symbols

101 絶縁性部材
102 、202、302、402,502,602,702 ダイパッド
103、303、403、503、603、703 半導体素子チップ
104 ワイヤ
105 導電性部材
406 連結部
101 Insulating member 102, 202, 302, 402, 502, 602, 702 Die pad 103, 303, 403, 503, 603, 703 Semiconductor element chip 104 Wire 105 Conductive member 406 Connecting portion

Claims (6)

絶縁性部材の上面の一部に底面が多角形である半導体素子チップの前記底面を加熱溶融性の金属接合部材にて固定することが可能なダイパッドを備えた実装用部品であって、
前記ダイパッドは、前記底面のサイズが相似状に異なる複数の半導体素子チップの各底面角にそれぞれ対応する複数の細長部を周縁に有しており、
前記細長部の幅は、先端側へ狭くなっていることを特徴とする実装用部品。
A mounting component including a die pad capable of fixing the bottom surface of a semiconductor element chip having a polygonal bottom surface to a part of the top surface of the insulating member with a heat-meltable metal bonding member,
The die pad has a plurality of elongated portions on the periphery corresponding respectively to the bottom surface corners of a plurality of semiconductor element chips having different sizes of the bottom surface.
The mounting part according to claim 1, wherein a width of the elongated portion is narrowed toward a distal end side.
前記細長部の先端は、鋭角であることを特徴とする請求項1に記載の実装用部品。 The mounting component according to claim 1, wherein a tip of the elongated portion has an acute angle. 絶縁性部材の上面の一部に底面が多角形である半導体素子チップの前記底面が加熱溶融性の金属接合部材にて固定されたダイパッドを備えた実装用部品を有する半導体装置であって、
前記ダイパッドは、前記半導体素子チップの各底面角にそれぞれ対応する複数の細長部を周縁に有しており、
前記細長部の幅は、先端側へ狭くなっていることを特徴とする半導体装置。
A semiconductor device having a mounting component including a die pad in which a bottom surface of a semiconductor element chip having a polygonal bottom surface on a part of an upper surface of an insulating member is fixed by a heat-meltable metal bonding member,
The die pad has a plurality of elongated portions on the periphery corresponding to the bottom corners of the semiconductor element chip,
2. A semiconductor device according to claim 1, wherein a width of the elongated portion is narrowed toward a distal end side.
前記細長部の先端は、鋭角であることを特徴とする請求項3に記載の半導体装置。 The semiconductor device according to claim 3, wherein a tip of the elongated portion has an acute angle. 前記絶縁性部材の上面と前記金属接合部材との接触角は100度以上であり、前記ダイパッドの上面と前記金属接合部材との接触角は80度以下であることを特徴とする請求項3または4に記載の半導体装置。 The contact angle between the upper surface of the insulating member and the metal bonding member is 100 degrees or more, and the contact angle between the upper surface of the die pad and the metal bonding member is 80 degrees or less. 5. The semiconductor device according to 4. 前記半導体素子チップは、発光素子チップであることを特徴とする請求項3乃至5のいずれかに記載の半導体装置。   The semiconductor device according to claim 3, wherein the semiconductor element chip is a light emitting element chip.
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Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010056399A (en) * 2008-08-29 2010-03-11 Mitsubishi Materials Corp Method of joining substrate and object to be mounted using solder paste having excellent registration
WO2010044239A1 (en) * 2008-10-17 2010-04-22 株式会社小糸製作所 Light-emitting module, method for producing light-emitting module, and lighting unit
JP2010123780A (en) * 2008-11-20 2010-06-03 Sony Corp Mounting substrate, method of manufacturing the same, and display device and method of manufacturing the same
EP2290676A1 (en) * 2008-06-12 2011-03-02 Mitsubishi Materials Corporation Method for joining substrate and object to be mounted using solder paste
JP2014232839A (en) * 2013-05-30 2014-12-11 新電元工業株式会社 Structure and method for connecting electronic component
JP2017212354A (en) * 2016-05-26 2017-11-30 ローム株式会社 LED module
CN109935672A (en) * 2017-12-18 2019-06-25 斯坦雷电气株式会社 Unimount baseplate and semiconductor light-emitting apparatus and its manufacturing method with it
JP2019110204A (en) * 2017-12-18 2019-07-04 スタンレー電気株式会社 Semiconductor light emitting device, general purpose mounting substrate, and method of manufacturing semiconductor light emitting device using the same
WO2021192788A1 (en) * 2020-03-23 2021-09-30 ローム株式会社 Semiconductor device

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002228886A (en) * 2001-01-31 2002-08-14 Kansai Tlo Kk Self alignment structure
JP2003264267A (en) * 2002-03-08 2003-09-19 Rohm Co Ltd Semiconductor device using semiconductor chip
WO2006132130A1 (en) * 2005-06-06 2006-12-14 Rohm Co., Ltd. Semiconductor device, substrate and semiconductor device manufacturing method

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002228886A (en) * 2001-01-31 2002-08-14 Kansai Tlo Kk Self alignment structure
JP2003264267A (en) * 2002-03-08 2003-09-19 Rohm Co Ltd Semiconductor device using semiconductor chip
WO2006132130A1 (en) * 2005-06-06 2006-12-14 Rohm Co., Ltd. Semiconductor device, substrate and semiconductor device manufacturing method

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US9166112B2 (en) 2008-10-17 2015-10-20 Koito Manufacturing Co., Ltd. Light emitting module, method of manufacturing the light emitting module, and lamp unit
CN102187478A (en) * 2008-10-17 2011-09-14 株式会社小糸制作所 Light-emitting module, method for producing light-emitting module, and lighting unit
JPWO2010044239A1 (en) * 2008-10-17 2012-03-15 株式会社小糸製作所 Light emitting module, method for manufacturing light emitting module, and lamp unit
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US8384116B2 (en) 2008-11-20 2013-02-26 Sony Corporation Substrate with chips mounted thereon, method of manufacturing substrate with chips mounted thereon, display, and method of manufacturing display
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