JP2008112274A - Controller and program - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To allow the suppression of a processing delay and the occurrence of useless processing, even if processing in a target is not performed as predicted. <P>SOLUTION: An image processor 100 has a host 10 and a target 20. The host 10 performs various kinds of processing for controlling the image processor 100, and requests the target 20 to perform specific image processing. The target 20 performs image processing requested from the host 10, and upon the completion thereof, transmits an interrupt signal to the host 10. When requesting the target 20 to perform image processing, the host 10 calculates a necessary time in the target 20 for the image processing. Then, the host 10 requests the target 20 to perform the image processing and after the necessary time elapses, processing performed in the host 10 is retreated into a memory 12, and made to wait for the transmission of an interrupt signal. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a control device and a program.

  For example, in an image processing apparatus that performs complex image processing, an arithmetic processing apparatus (DSP or the like) specialized for specific image processing is added to an arithmetic processing apparatus (CPU or the like) that controls the operation of the entire apparatus. In some cases, a configuration to be provided is employed to improve overall processing efficiency. Hereinafter, the former arithmetic processing unit in this configuration is referred to as “host”, and the latter arithmetic processing unit is referred to as “target”.

  When a process is performed using a host and a target, there are interrupt and polling as a method for the host to know the state of the target (see, for example, Patent Documents 1 and 2). The host responds to the interrupt by activating the interrupt handler, but some overhead (temporal load) is generated with the activation of the interrupt handler. Therefore, it can be said that it is preferable to use polling rather than interrupt when processing required for the target occurs many times.

When polling is performed, a time required for the target to perform processing may be predicted on the host side in advance, and the target may be inquired based on the predicted time. In this way, polling can be handled without wasting time in the host.
JP-A-6-19823 JP-A-6-175860

  However, processing at the target is not always performed as predicted, and may take more time than predicted due to unexpected delay factors such as noise. In such a case, if the target is inquired based on the predicted time, the expected information cannot be obtained by one polling, and the inconvenience arises that the polling must be repeated. Then, processing delay and wasteful processing occur in both the host and the target, and processing efficiency decreases.

  The present invention has been made in view of such circumstances, and an object of the present invention is to suppress delays in processing and occurrence of useless processing even when processing at a target is not performed as expected. It is to provide technology to do.

  In order to achieve the above-described object, the present invention is an arithmetic processing device capable of executing a predetermined process, and a connection means for connecting to an arithmetic processing device that transmits an interrupt signal when the processing is completed, Alternatively, an acquisition unit that acquires process type information that specifies the content of a process executed in the arithmetic processing device, and a process that is specified by the process type information acquired by the acquisition unit is executed in the arithmetic processing device. In the case of the predetermined process, a processing request unit that requests the arithmetic processing unit to execute the process via the connection unit, and the predetermined process requested by the processing request unit by the processing unit. A calculation unit that calculates a time required from the start to the end, and an interrupt signal received from the arithmetic processing unit via the connection unit or the acquisition unit. Processing execution means for executing a process to be executed in the own apparatus based on the acquired process type information, and the process execution means causes the processing request means to execute the predetermined process on the arithmetic processing unit. When the process is requested and the process is being executed in the own apparatus, the process request unit requests the execution of the predetermined process until the required time calculated by the calculation unit elapses. When a process being executed is interrupted and then an interrupt signal is received via the connection means, a control device is provided that executes a process corresponding to the predetermined process executed by the arithmetic processing unit.

  According to the present invention, the arithmetic processing device is capable of executing a plurality of the predetermined processes, and includes a plurality of internal processors that execute a plurality of arithmetic processes constituting each of the predetermined processes, And a status register that stores information indicating the state of the internal processor in a storage area corresponding to each internal processor, the processing execution means receives the interrupt signal via the connection means, and The configuration may be such that the predetermined process triggered by the signal is specified based on the required time calculated for the process by the calculation unit.

Further, in this configuration, the process execution means stores a storage area in which information indicating the state of the internal processor used when executing the specified predetermined process is stored in the storage area of the status register May be identified and referenced.
Alternatively, the process execution means acquires the process type information indicating the first process and the second process as the predetermined process by the acquisition means, and performs the first process on the interrupt signal. When specified as a trigger process, the first process is executed in the storage area of the status register during the period after the specification and the arithmetic processing unit is executing the second process. You may refer to the storage area in which information indicating the state of the internal processor used at the time is stored.

  The present invention can also be specified as a program for realizing the functions of the control device described above. For example, the present invention is an arithmetic processing unit capable of executing a predetermined process, and a process for specifying the content of the process to be executed in a computer connected to the arithmetic processing unit that transmits an interrupt signal when the process ends. If the acquisition function for acquiring type information and the process specified by the process type information acquired by the acquisition function are the predetermined process, the calculation process is performed via a connection unit connected to the calculation processing device. A processing request function for requesting the apparatus to execute the processing; a calculation function for calculating a time required for the arithmetic processing apparatus to start from the predetermined processing requested by the processing request function; and Processing to be executed in its own device based on the interrupt signal received from the arithmetic processing device via the connection means or the processing type information acquired by the acquisition function A process execution function to be executed, when the processing request function requests the arithmetic processing device to execute the predetermined process, and the process request function When the execution of the process is requested until the required time calculated by the calculation function elapses, the process being executed is interrupted, and then an interrupt signal is received via the connection means. It can also be specified as a program for realizing a process execution function for executing a process according to the predetermined process executed by the arithmetic processing unit.

  According to the present invention as described above, it is possible to suppress processing delays and useless processing even when processing at the target is not performed as expected.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[Constitution]
FIG. 1 is a block diagram illustrating a configuration of an image processing apparatus 100 according to an embodiment of the present invention. The image processing apparatus 100 constitutes a part of an image forming apparatus such as a printer or a copying machine. Note that the image forming apparatus includes an input device for a user to input an instruction, a communication interface for connecting to a computer device via a network, and the like. As shown in the figure, the configuration of the image processing apparatus 100 is roughly divided into a host 10 that controls the operation of the entire apparatus and a target 20 that executes specific image processing.

  The host 10 includes a controller 11, a memory 12, a target IF (InterFace) 13, and an input / output IF 14. The controller 11 includes an arithmetic processing unit such as a CPU (Central Processing Unit), a ROM (Read Only Memory), an oscillator, and a timer. The controller 11 controls the operation of the entire image forming apparatus by executing a requested process via an input device or a communication interface based on a predetermined program stored in the ROM. Further, the controller 11 realizes a time measurement function using a timer. The timer is configured to notify the arithmetic processing device when a predetermined time instructed from the arithmetic processing device has elapsed (that is, timed out). The memory 12 includes a storage device such as SDRAM (Synchronous Dynamic Random Access Memory) or DDR (Double Data Rate) -SDRAM and functions as a work area of the controller 11. The target IF 13 is an interface for the controller 11 to exchange data with the target 20 and is connected to the target 20 through a plurality of signal lines. Note that a signal line for transmitting an interrupt signal from the target 20 to the host 10 and a signal processing request (command) from the host 10 to the target 20 are transmitted to the plurality of signal lines connected to the target IF 13. A signal line and a signal line for transmitting and receiving data relating to image processing between the host 10 and the target 20 are included. The input / output IF 14 is an interface for acquiring information or image data representing a request from an input / output device or a communication interface, or for supplying information or image data. Information transmitted from the input device or the communication interface specifies what kind of processing is to be executed in the image processing apparatus 100. Therefore, this information is hereinafter referred to as “processing type information”.

  A predetermined priority is assigned to each process to be executed in the image processing apparatus 100. The host 10 is configured to preferentially execute processing with high priority. The priority of each process can be uniquely specified from the process type information. For example, the priority of each process may be stored in advance in the host 10 in association with the process type information, or may be included in the process type information.

  The target 20 includes a processor 21, a memory 22, and a host IF 23. The processor 21 includes an arithmetic processing device such as a DSP (Digital Signal Processor) and an ASIC (Application Specific Integrated Circuit) and an oscillator, and executes predetermined image processing based on supplied data. The processor 21 can execute a plurality of different image processes and can execute a plurality of arithmetic processes in parallel. The memory 22 includes a storage device such as SDRAM or DDR-SDRAM and functions as a work area of the processor 21. The host IF 23 is an interface for the processor 21 to exchange data with the host 10 and is connected to the host 10 through the above-described plurality of signal lines. The processor 21 is configured to transmit an interrupt signal via the host IF 23 when the image processing requested from the host 10 is completed.

  Here, the internal configuration of the processor 21 will be described with reference to FIG. As shown in the figure, the processor 21 includes a plurality of internal processors P1, P11, P12,..., P1m, P2, P3,..., Pn (where m and n are arbitrary natural numbers) and a plurality of status registers R0. , R1, R11, R12,..., R1m, R2, R3,. Each internal processor has one or a plurality of arithmetic units, and each executes a predetermined arithmetic processing. Each status register is a register having a predetermined number of bits, and stores information indicating the status (state) of the internal processor, that is, whether the requested arithmetic processing is normally executed by the internal processor.

  When the value represented by a certain register is “1”, the status register indicates that the arithmetic processing corresponding to the register has been completed normally. When the value represented by a certain register is “2”, the status register corresponds to the register. This indicates that the arithmetic processing to be performed has not ended normally (that is, ended abnormally). In addition, when the value represented by a certain register is “0”, the status register indicates that the internal processor corresponding to the register is not requested to perform arithmetic processing (idle state). A value of “3” indicates that the internal processor corresponding to the register is in a state (busy state) in which arithmetic processing is being executed. That is, in this case, the status register represents the status of one internal processor by a 2-bit storage area.

  The internal processors P1, P11, P12,..., P1m, P2, P3,..., Pn have a relationship that forms a hierarchical structure. In FIG. 2, internal processors P1, P2, P3,..., Pn correspond to the upper layer side, and internal processors P11, P12,..., P1m correspond to the lower layer side with respect to the internal processor P1. Although not shown in the figure, for the internal processors P2, P3,..., Pn, the internal processor corresponding to the lower layer side is associated with that of the internal processor P1. However, the number of internal processors associated with the internal processors P2, P3,..., Pn is not limited to m. Further, although not particularly illustrated, a configuration in which a lower-layer internal processor exists also for the internal processors P11, P12,..., P1m may be employed.

  The status register R0 corresponds to the internal processors P1, P2, P3,. That is, the status register R0 has a storage area of at least 2n bits, and each storage area represents the status of the internal processors P1, P2, P3,. The status register R1 has a storage area of 2 m bits corresponding to the internal processors P11, P12,..., P1m, and each storage area represents the state of the internal processors P11, P12,. The status registers R2, R3,..., Rn have the same structure as the status register R1 described above.

  Note that the image processing executed by the target 20 includes a process in which the time (required time) required from the start to the end thereof can be predicted and a process in which the time is not so. In the present embodiment, the target is To do. For image processing whose required time cannot be predicted, normal interrupt processing may be performed. For example, the required time can be predicted by image processing in which the number of pixels of image data to be output is determined in advance with respect to the number of pixels of input image data. Examples of such image processing include so-called negative / positive inversion processing and sub-sampling processing (thinning-out processing). Here, the negative / positive inversion processing is, for example, when each pixel of input image data is represented by a gradation value N of 8 bits (that is, 256 gradations), all the gradation values are “255-N”. Is a process of converting to "." The sub-sampling process is a process for thinning out the number of pixels of image data at a predetermined rate. In the case of such image processing, it is possible to calculate the required time based on the number of pixels of image data and the number of clock cycles required for processing for each pixel.

[Operation]
Based on the above-described configuration, the image processing apparatus 100 executes various processes. In the image processing apparatus 100, the host 10 mainly performs the processing, but the target 20 executes the part of the processing instead of the host 10. The outline of the operation at this time is as follows. That is, the host 10 of the image processing apparatus 100 first acquires process type information from the input device or the communication interface via the input IF 14, and specifies the content of the process to be executed based on the information. Then, the host 10 executes the process that can be executed by the host 10 by itself, and causes the target 20 to execute the image process that can be executed by the target 20. When the processing at the target 20 is completed, the host 10 further executes processing according to the processing result.

  In order to execute such a series of processes efficiently, the host 10 determines the state of the target 20 as appropriate while executing the processes that can be executed by itself, and images the target 20 as necessary. It is required to execute the process. In the following, operations for the image processing apparatus 100 to efficiently execute the above-described series of processes will be described with reference to three operation examples. Note that the following operation example will be described on the assumption that some processing is being executed in the host 10 when processing type information is supplied.

(1) Operation example 1
FIG. 3 is a flowchart illustrating a first operation example of the image processing apparatus 100 according to the present embodiment. Hereinafter, description will be given with reference to FIG. First, in the image processing apparatus 100, when any request is input from the input device or the communication interface, the controller 11 of the host 10 activates an interrupt handler corresponding to the input, thereby interrupting the process being executed. The processing contents are held in a predetermined area of the memory 12 (step Sa1). That is, the controller 11 saves the process being executed in the memory 12 so that the process can be resumed later.

  Next, the controller 11 acquires process type information corresponding to the input request (step Sa2). If the process type information is acquired, the controller 11 determines whether or not the process specified by the process type information is an image process that can be executed by the target 20 (step Sa3). When the process specified by the process type information is not an image process that can be executed by the target 20 (step Sa3: NO), the controller 11 specifies that this process is to be executed by the host 10, and sets the priority thereof. A corresponding process is executed (step Sa13). Here, when the process specified by the process type information is a process having a higher priority than the process being saved, the controller 11 executes the specified process, and the process specified by the process type information is executed. If the process has a lower priority than the process being saved, the process being saved is resumed, and the specified process is executed after the process is finished. Note that the operation of the controller 11 at this step is the same as that of a normal interrupt process, and thus detailed description thereof is omitted.

  On the other hand, when the process specified by the process type information is an image process that can be executed by the target 20 (step Sa3: YES), the controller 11 calculates the time required for the image process (step Sa4). The required time calculated by the controller 11 at this time is only a predicted value. Therefore, the target 20 may take more time than the required time due to an unexpected delay factor when executing the requested image processing.

  After calculating the required time, the controller 11 causes the timer to start measuring time based on the required time (step Sa5). Subsequently, the controller 11 requests the target 20 to execute the image processing specified by the acquired processing type information (step Sa6). Then, when the request is transmitted to the target 20, the controller 11 reads the data related to the processing saved in the memory 12, and resumes the saved processing (step Sa7).

  When the controller 11 is executing the processing, the image processing on the target 20 is finished. As described above, the timer is configured to notify when the required time is reached. Therefore, the controller 11 determines whether or not there is a time-out notification from the timer before and after the end of the process in the target 20 (step Sa8). When the timer has timed out, that is, when the time since the timer started measurement coincides with the required time described above (step Sa8: YES), the controller 11 interrupts the process being executed again, The processing contents are held in a predetermined area of the memory 12 (step Sa9).

  Here, the controller 11 determines whether or not there is an interrupt signal transmitted from the target 20 (step Sa10). During this time, the controller 11 stands by without performing other processes. When the interrupt signal from the target 20 is received via the target IF 13 (step Sa10: YES), the controller 11 activates the interrupt handler corresponding to this interrupt signal, and the image processing executed in the target 20 A predetermined process corresponding to the above is executed (step Sa11). The processing executed at this time is hereinafter referred to as “interrupt handling processing”.

  Here, the interrupt handling process will be described. In the interrupt handling process, the controller 11 first refers to the status register of the target 20. The subsequent processing differs depending on the image processing executed by the target 20 and the processing result. For example, if the referenced status register is “2”, that is, if the process ends abnormally, the controller 11 causes the target 20 to execute the same process again. In addition, when the referred status register is “1”, that is, when the processing ends normally, the controller 11 receives data representing the processing result of the target 20 and further performs arithmetic processing on the data. Sometimes. Depending on the type of image processing, there is a case where no processing is required after referring to the status register.

  Subsequently, a procedure in which the controller 11 refers to the status register will be described. When receiving an interrupt signal from the target 20, the controller 11 can determine that some event requiring an interrupt has occurred in the target 20. Of the signal lines connecting the host 10 and the target 20, the number of signal lines allocated for interrupt signals is usually one. Therefore, in such a configuration, the controller 11 can only determine that some event has occurred in the target 20 simply by receiving an interrupt signal, and specifically, what kind of image processing has been executed. It cannot be judged. Therefore, the controller 11 refers to the status register of the processor 21 and identifies which internal processor has executed the arithmetic processing, thereby identifying the image processing that triggered the interrupt signal. Since an internal processor necessary for executing predetermined image processing is determined in advance, the controller 11 may refer to a status register corresponding to the internal processor.

  When the processor 21 has a hierarchical structure as shown in FIG. 2, the controller 11 sequentially refers to the status register of the upper layer and specifies the value of the target status register of the lower layer. For example, in the configuration illustrated in FIG. 2, consider a case where the arithmetic processing is normally executed in the internal processor P11 and the controller 11 tries to determine the state. In this case, it is assumed that none of the internal processors P2, ..., Pn operate. In such a case, in the status register R0, only the value of the register corresponding to the internal processor P1 is “1 (normal end)”, and the values of the registers corresponding to the other internal processors P2,. Are all “0 (idle state)”. In the status register R1, the value of the register corresponding to the internal processor P11 is “1”.

  In order to identify the image processing corresponding to the interrupt signal, the controller 11 first refers to the status register corresponding to the upper layer internal processor, that is, the status register R0, and identifies the register whose value is “1”. To do. Subsequently, the controller 11 refers to the status register of the internal processor corresponding to the lower layer side of the internal processor corresponding to the register whose value is “1”. In the case described above, since the value of the register corresponding to the internal processor P1 is “1”, the controller 11 next refers to the status register R1.

  Returning to the description of FIG. The controller 11 refers to the status register as described above and executes an interrupt handling process. When this interrupt handling process is completed, the controller 11 reads out the data related to the saved process from the memory 12, and resumes the process (step Sa12).

  By operating in this way, the image processing apparatus 100 starts the interrupt handling process without delay not only when the target 20 finishes image processing as predicted, but also when more time is required than predicted. can do. Therefore, even if an unexpected delay occurs in the target 20, the image processing apparatus 100 can immediately respond to an interrupt signal from the target 20 and efficiently execute a series of processes. When the image processing apparatus 100 is operated as in this operation example, the controller 11 evacuates the processing being executed before receiving the interrupt signal from the target 20. As compared with the configuration in which the saving is performed from the beginning, it is possible to perform the interrupt handling process more quickly. Further, when the image processing apparatus 100 is operated as in the present operation example, even if an unexpected delay occurs in the target 20, the controller 11 waits without doing anything, so the controller 11 is useless. Generation of processing (polling or the like) can be suppressed.

(2) Operation example 2
Subsequently, a second operation example of the image processing apparatus 100 of the present embodiment will be described with reference to the flowchart of FIG. This operation example is an operation example particularly suitable when a plurality of image processing execution requests are continuously transmitted to the target 20. In this operation example, as shown in FIG. 4, there is a step for performing the same processing as in the operation example 1 described above. Hereinafter, description of such steps will be omitted as appropriate.

  The processing of steps Sb1 to Sb10 and Sb15 in this operation example is substantially the same as the processing of steps Sa1 to Sa10 and Sa13 in operation example 1. However, in this operation example, it is assumed that process type information indicating two image processes executed by different internal processors is acquired in step Sb2. That is, in this operation example, the controller 11 calculates a required time for each image processing (step Sb4), and makes a request for execution of the processing (step Sb6). In the following description, the two image processes specified by the process type information are referred to as “first image process” and “second image process”, respectively. For convenience of explanation, it is assumed that the time required for the second image processing is longer than the time required for the first image processing.

  When the controller 11 receives the interrupt signal in step Sb10, the controller 11 specifies the image processing that triggered the interrupt signal (step Sb11). At this time, the controller 11 specifies the image processing that triggered the interrupt signal based on the timing at which the interrupt signal is received and the required time calculated in step Sb4. For example, the controller 11 determines the time from the time when image processing is requested to the target 20 at step Sb6 to the time when the interrupt signal is received at step Sb10 as the time required for the first and second image processing calculated at step Sb4. Compared with each, the image processing with the smaller difference from the required time is specified as the image processing triggered by the interrupt signal. As described above, here, since the time required for the second image processing is longer than the time required for the first image processing, the first image processing is specified first.

  When the image processing that triggered the interrupt signal is specified in this way, the controller 11 executes an interrupt handling process (step Sb12). The interrupt handling process of this operation example is different from the interrupt handling process of the operation example 1 described above. In this operation example, the controller 11 specifies a status register to be referred to based on the image processing specified in step Sb11. Since the controller 11 has already specified the image processing that triggered the interrupt signal, the controller 11 can specify the internal processor used for executing this image processing. Therefore, the controller 11 can specify the status register to be referred to without referring to the status register in a hierarchical order, and therefore directly refers to the status register. And the controller 11 performs a subsequent process similarly to the operation example 1 mentioned above as needed.

  When the interrupt handling process is completed, the controller 11 determines whether or not the image processing requested for the target 20 has been completed (step Sb13). In other words, this determination is made as to whether or not both the interrupt signal transmitted at the end of the first image processing and the interrupt signal transmitted at the end of the second image processing have been received. be equivalent to. When all of the image processing requested for the target 20 is completed (step Sb13: YES), that is, when an interrupt signal transmitted upon completion of the second image processing is received, the controller 11 saves. Data relating to the processed processing is read from the memory 12, and the processing is resumed (step Sb14). On the other hand, when the image processing requested to the target 20 has not ended (step Sb13: NO), that is, when the interrupt signal transmitted upon the end of the second image processing has not yet been received, The controller 11 executes the processing after step Sb7 again, and performs processing according to the received interrupt signal.

  By operating in this way, the image processing apparatus 100 can specify the image processing executed on the target 20 without sequentially referring to the status register. As a result, the image processing apparatus 100 can directly refer to the status of the internal processor that executed the image processing triggered by the interrupt signal. For example, in the configuration illustrated in FIG. 2, when the arithmetic processing is executed in the internal processor P11 and the controller 11 tries to determine the state, in the operation example 1, the status register R1 is referred to after referring to the status register R0. Although necessary, in this operation example, the status register R1 can be referred to without referring to the status register R0. As a result, the controller 11 can reduce the time (number of clock cycles) required for the interrupt handling process, and can execute subsequent processes earlier. Accordingly, the controller 11 can request the execution of the next process earlier when the request is continuously transmitted to the target 20, thereby reducing the time for the target 20 to be in the idle state. It becomes possible to do. That is, according to this operation example, the image processing apparatus 100 can improve the processing efficiency as a whole.

[Modification]
In the above, the present invention has been described by exemplifying one preferred embodiment and its operation example. However, the present invention is not limited to the above-described embodiment, and may be implemented in various other modes. Is also possible. In the present invention, for example, the following modifications can be applied to the above-described embodiment.

  In the operation example 2 described above, the controller 11 can specify the image processing that triggered the interrupt signal without referring to the status register, so that the processing that the controller 11 should execute after the end of the image processing is displayed. You can know before referring to the register. For this reason, in the processing shown in the operation example 2, it is possible to omit reference to the status register in the interrupt handling processing. Even in such a case, there is no particular problem as long as the image processing on the target 20 is normally completed.

  However, not referring to the status register means that it is not determined whether the image processing at the target 20 has ended normally or abnormally, so that a problem naturally occurs when the image processing at the target 20 ends abnormally. Therefore, even if the reference of the status register is omitted in the interrupt handling process, it can be said that it is desirable to refer to the status register at any later timing. The timing for referring to the status register is preferably, for example, any period after the end of the interrupt handling process according to a certain interrupt signal and during which the target 20 is executing the image process. Specifically, for example, in the flowchart shown in FIG. 4, when the determination in step Sb13 is negative, after the determination and before executing the process of step Sb7 (resumption of the process being saved) Refer to the status register. If it is determined that the corresponding process has ended abnormally as a result of referring to the status register, the same process may be executed again. In this way, it is possible to recover at the time of abnormality while maintaining efficient processing.

  In the above-described embodiment, a configuration in which one target 20 is connected to one host 10 is shown, but a configuration in which a plurality of targets 20 are connected to one host 10 is described. Also good. In the case of such a configuration, the processing result of a certain target may be delivered to another target, but such processing may be included in the above-described interrupt handling processing. In the above-described embodiment, the image processing apparatus 100 including the host 10 and the target 20 is shown. However, the present invention is not limited to the image processing apparatus. In other words, in the above-described embodiment, the target 20 has been described as executing image processing, but may execute arithmetic processing other than image processing.

It is the block diagram which illustrated the composition of the image processing device of the present invention. It is the figure which illustrated the internal structure of the processor. It is a flowchart which shows the 1st operation example of an image processing apparatus. It is a flowchart which shows the 2nd operation example of an image processing apparatus.

Explanation of symbols

DESCRIPTION OF SYMBOLS 100 ... Image processing apparatus, 11 ... Controller, 12, 22 ... Memory, 13 ... Target IF, 14 ... Input / output IF, 21 ... Processor, 23 ... Host IF, P1, P11, P12, P1m, P2, P3, Pn ... Internal processor, R0, R1, R11, R12, R1m, R2, R3, Rn ... Status register

Claims (5)

An arithmetic processing device capable of executing a predetermined process, and a connection means for connecting to an arithmetic processing device that transmits an interrupt signal when the processing ends.
An acquisition means for acquiring process type information for specifying the content of a process executed in the own apparatus or the arithmetic processing apparatus;
When the process specified by the process type information acquired by the acquisition means is the predetermined process executed in the arithmetic processing apparatus, the arithmetic processing apparatus is caused to execute the process via the connection means. Processing request means to request;
Calculating means for calculating a time required for the arithmetic processing unit to start after the predetermined processing requested by the processing requesting means is completed;
Based on the interrupt signal received from the arithmetic processing device via the connection means or the processing type information acquired by the acquisition means, a process execution means for executing a process to be executed in the own device,
The process execution means includes
When the processing requesting unit requests the arithmetic processing unit to execute the predetermined process and the processing requesting unit requests the execution of the predetermined process when the processing is being performed in the own device. When the processing being executed is interrupted until the required time calculated by the calculating means elapses and then an interrupt signal is received via the connecting means, the predetermined processing executed by the arithmetic processing unit is performed. A control device that performs processing according to processing. The arithmetic processing unit is capable of executing a plurality of the predetermined processes, and indicates a plurality of internal processors executing a plurality of arithmetic processes constituting each of the predetermined processes, and states of the plurality of internal processors In the case of providing a status register for storing information in a storage area corresponding to each internal processor,
The process execution means includes
When the interrupt signal is received through the connection means, the predetermined process that triggered the interrupt signal is specified based on the required time calculated for the process by the calculation means. Item 2. The control device according to Item 1. The process execution means includes
The storage area of the status register is specified and referred to by specifying a storage area in which information indicating the state of the internal processor used when executing the specified processing is specified. Item 3. The control device according to Item 2. The process execution means includes
Process type information indicating the first process and the second process, which are the predetermined processes, is acquired by the acquisition unit, and the first process is specified as a process triggered by the interrupt signal. In this case, the internal processor used when executing the first process in the storage area of the status register during the period after the identification and the arithmetic processing unit is executing the second process. The control device according to claim 2, wherein a storage area in which information indicating the state is stored is referred to. An arithmetic processing unit capable of executing a predetermined process, and a computer connected to the arithmetic processing unit that transmits an interrupt signal upon completion of the process,
An acquisition function that acquires process type information that identifies the content of the process to be executed;
When the process specified by the process type information acquired by the acquisition function is the predetermined process, the calculation processing apparatus is requested to execute the process via a connection unit connected to the calculation processing apparatus. Processing request function;
A calculation function for calculating a time required for the arithmetic processing unit to start from the predetermined process requested by the process request function;
A process execution function for executing a process to be executed in the own apparatus based on an interrupt signal received from the arithmetic processing apparatus via the connection means or a process type information acquired by the acquisition function, When the request function requests the arithmetic processing device to execute the predetermined process, and the processing is being executed in the own device, the calculation is performed after the processing request function requests the execution of the predetermined process. When the processing being executed is interrupted until the required time calculated by the function elapses and then an interrupt signal is received via the connection means, the predetermined processing executed by the arithmetic processing unit is performed. A program that implements a process execution function that executes the corresponding process.

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