JP2010191682A - Apparatus, method and program for processing information controlling computing system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To avoid a processing load increase, when executing hardware computation processings. <P>SOLUTION: An apparatus includes an HW calculating portion 120 for executing operations by a synchronous system or asynchronous system; a delay time calculating portion 105 for calculating a delay time to the completion of a requested operation requested for execution in the HW calculating portion 120; a computing system decision part 102 for comparing the sum of processing and delay times in the execution of a queued operation requested for the next execution in the HW calculating portion 120, with a asynchronization time indicating the processing time of processing, executed in conjunction with the asynchronous system. If the sum is larger than the asynchronization time, decision to execute the queued calculation by the asynchronous system, and a calculation control part 103 for requesting the HW calculating portion 120 for executing the queued calculation by the decided execution system. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to an apparatus, a method, and a program for processing information by controlling hardware arithmetic processing using an asynchronous method and a synchronous method capable of reducing a load on a processor unit.

  In recent years, broadband networks have become widespread in government agencies, companies, educational institutions, homes, etc., and interest in network security for preventing information leakage and data tampering has increased. Communication data transferred via the communication path uses encryption technology and message authentication (digest authentication, hash authentication, HMAC (Keyed / Hashing for Message Authentication code) authentication) technology to prevent eavesdropping and tampering, and security Can be improved.

  As representative communication protocols for improving the security of communication data, IPsec, TLS (Transport Layer Security), and IEEE (The Institute of Electrical Engineering) specified by IETF (Internet Engineering Task Force). .)) And WEP (Wired Equivalent Privacy) defined by. Encryption technology is also used to prevent unauthorized duplication of copyrighted works and to prevent unauthorized disclosure of personal information, confidential business information, and confidential information related to national defense.

  In recent years, digital broadcasting and digital music distribution characterized by high definition and high sound quality have become widespread. Various digital data such as digital audio data, image data, and video data can be reduced in data amount to be stored and data transfer capacity per unit time of a communication path by using a data compression technique. In particular, since the amount of data is increasing due to high definition of image data and video data, the compression technique is an indispensable technique.

  Typical compression techniques for digital image data and digital video data include JPEG (Joint Photographic Experts Group) and MPEG (Moving Picture Experts Group) (registered trademark). Typical compression techniques for digital audio data include AAC (Advanced Audio Coding) (registered trademark), MP3 (MPEG-1 for Audio Layer-3), and ATRAC (Adaptive Transform Acoustic Coding) (registered trademark). .

  Arithmetic processing such as encryption and data compression processing as described above is realized by executing an instruction sequence (program) for calculation on a general-purpose PU (Processing Unit) provided in a general-purpose computer device. There are many cases. However, with this method, the amount of data to be processed per unit time increases as the amount of data and the communication data rate increase, and the processing load on the general-purpose PU increases.

  To solve this problem, a device for performing specific arithmetic processing (hereinafter referred to as an HW arithmetic device) separately from the general-purpose PU is installed in the general-purpose computer device, so that the arithmetic processing load by the PU is reduced. Can be reduced. The execution of arithmetic processing by the HW arithmetic device in this way is often referred to as hardware offloading processing or hardware arithmetic processing.

  With regard to hardware arithmetic processing, in Patent Document 1 and Patent Document 2, software arithmetic processing is performed in order to execute arithmetic processing such as encryption processing or data compression processing in the faster one of the HW arithmetic device or the PU. And a technique for switching between hardware arithmetic processing.

  On the other hand, the method of controlling the HW arithmetic device from a program operating on a general-purpose PU can be classified into two types: a synchronous method and an asynchronous method. The synchronous method is a method of performing processing for waiting for the end of processing by the HW arithmetic device (hereinafter referred to as HW arithmetic end waiting processing) when a calculation process is requested from the program operating on the general-purpose PU to the HW arithmetic device. . The synchronization method is often used in programs that perform arithmetic processing with an HW arithmetic device.

  In addition, the asynchronous method means that processing up to hardware arithmetic processing (hereinafter referred to as pre-processing) and processing after hardware arithmetic processing (hereinafter referred to as post-processing) without waiting for completion of processing by the HW arithmetic device. Is a method that is executed in a divided manner. In the asynchronous method, processing is divided and executed before and after hardware operation processing, so the data held by the preprocessing (eg, parameters related to hardware operation processing, data subject to hardware operation processing) Processing (hereinafter referred to as desynchronization processing) is required to communicate to the processing. As an example of desynchronization processing, all or part of the data held by the preprocessing is passed to the postprocessing, or the memory address of all or part of the data held by the preprocessing is updated The work of passing to processing is mentioned.

  As a specific example of the asynchronous system, Non-Patent Document 1 describes a program for controlling an HW arithmetic unit that performs encryption / decryption in an asynchronous system. However, at present, there are few examples that adopt the asynchronous method compared to the synchronous method.

  Further, as a method similar to the asynchronous method, Patent Document 3 describes a method in which when a waiting time event occurs due to memory access contention or the like, the priority of a thread is changed to switch to another thread. However, an increase in processing time (corresponding to “asynchronization time” representing the time required for desynchronization processing in the asynchronous method) due to execution of switching is not considered.

JP 2006-7638 A JP 2004-180253 A Japanese Patent No. 3714598

A. D. Keromytis et al. , “The Design of the OpenBSD Cryptographic Framework”, 2003 USENIX Annual Technical Conference, USENIX Association, 2003

  However, depending on the type of arithmetic processing, control of the HW arithmetic device by an asynchronous method may not be suitable. For example, if the time during which the asynchronous processing in the asynchronous method is executed in the PU is longer than the time in which the processing for waiting for the completion of the HW calculation in the synchronous method is executed in the PU, it is better to control the HW arithmetic device in the synchronous method. The load on will be reduced.

  As yet another example, when a delay time occurs until the execution of the HW calculation is started and the delay time is longer than the time when the desynchronization process is executed, it is more likely that the HW calculation device is controlled in a synchronous manner. The load on will be reduced.

  That is, there is a problem that even if the device is designed to control the HW arithmetic device in an asynchronous manner in order to reduce the load on the PU, the load on the PU may be increased.

  The present invention has been made in view of the above, and an object of the present invention is to provide an apparatus, a method, and a program that can avoid an increase in processing load when executing hardware arithmetic processing.

  In order to solve the above-described problems and achieve the object, the present invention provides a synchronization method in which a process that requests a predetermined operation is executed in synchronization with the end of the operation, and the process An operation circuit that executes the operation in any one of the execution methods of asynchronous and asynchronous execution, and a time until the requested operation that represents the operation that is requested to be executed by the operation circuit is completed A delay time calculation unit that calculates a delay time that represents the sum of a processing time and a delay time when the arithmetic circuit executes a request waiting operation that represents the operation that is requested to be executed next to the requested operation And, when executing the request wait operation in the asynchronous method, the desynchronization time representing the processing time of the process executed accompanying the request wait operation is compared, and the sum is greater than the desynchronization time A determination unit that determines to execute the request waiting operation in the asynchronous method, and a control unit that requests the arithmetic circuit to execute the request waiting operation in accordance with the determined execution method. It is characterized by that.

  The present invention also relates to a method and a program that can be executed by the above apparatus.

  According to the present invention, it is possible to avoid an increase in processing load when executing hardware arithmetic processing.

FIG. 1 is a network configuration diagram of a communication system including a communication apparatus according to the first embodiment. FIG. 2 is a block diagram illustrating a configuration of the communication apparatus according to the first embodiment. FIG. 3 is a timeline diagram when the hardware offloading process is executed in a synchronous manner and an asynchronous manner. FIG. 4 is a diagram illustrating an example of a test sheet for measuring a processing time in the first embodiment. FIG. 5 is a flowchart illustrating an overall flow of the desynchronization time calculation process according to the first embodiment. FIG. 6 is a diagram showing the relationship of times recorded in the desynchronization time calculation process shown in FIG. FIG. 7 is a diagram illustrating an example of a test sheet for measuring a processing time in the first embodiment. FIG. 8 is a diagram illustrating an example of a graph in which Tsync and Tasync obtained from the results measured using the test sheet of FIG. 7 are plotted for each data size. FIG. 9 is a flowchart showing an overall flow of communication processing in the first embodiment. FIG. 10 is a flowchart showing the overall flow of the calculation method determination process in the first embodiment. FIG. 11 is a diagram illustrating a determination result of the calculation method determination unit in the first embodiment. FIG. 12 is a block diagram illustrating a configuration of a communication apparatus according to the second embodiment. FIG. 13 is a flowchart illustrating an overall flow of communication processing according to the second embodiment. FIG. 14 is a diagram showing the relationship between the time for rewriting the value of the flag area and the processing time of the calculation. FIG. 15 is a flowchart illustrating an overall flow of the calculation method determination process according to the second embodiment.

  Exemplary embodiments of an apparatus, a method, and a program for processing information according to the present invention will be explained below in detail with reference to the accompanying drawings.

(First embodiment)
When the information processing apparatus according to the first embodiment executes encryption processing by hardware, the attribute of the data to be encrypted (data size) and the calculation processing being executed or waiting for execution are completed. Either the synchronous method or the asynchronous method is adopted according to the delay time.

  In the first embodiment, an example using a communication device that performs communication processing according to the IPsec protocol will be described as an example of the information processing device. However, applicable devices are not limited to communication devices that execute such communication processing, and devices that have a function of executing specific operations such as encryption processing and data compression processing by hardware, Applicable to any device.

  FIG. 1 is a network configuration diagram of a communication system including a communication device 100 according to the first embodiment. As shown in FIG. 1, the communication system according to the first embodiment has a configuration in which a communication device 100 and a communication device 200 that is a communication partner are connected via an IP network 300. Communication device 100 and communication device 200 are connected to terminal device 400 and terminal device 500, respectively.

  The communication device 100 is a device that performs packet processing and data processing related to the IPsec protocol, and has a function of executing encryption processing and the like by hardware. As shown in the figure, the communication device 100 is connected to the IP network 300 and the terminal device 400 via a network interface 130 and a network interface 131, respectively.

  The communication device 200 is a device that communicates with the communication device 100 using the IPsec protocol. The terminal device 400 and the terminal device 500 are devices that transmit and receive data via the communication device 100 and the communication device 200, respectively.

  Next, a detailed configuration of the communication apparatus 100 will be described with reference to FIG. FIG. 2 is a block diagram illustrating a configuration of the communication apparatus 100 according to the first embodiment. As shown in the figure, the communication apparatus 100 includes a PU 110, an HW calculation unit 120, a memory 140, a network interface 130, and a network interface 131 as main hardware configurations.

  All of these are connected to the shared bus 111, and data is transferred to each other via the shared bus 111. Note that the network interfaces 130 and 131 are described to show an example of the first embodiment, and may not be installed when communication is not necessary. Further, the number of network interfaces is not limited to two, and one or three or more network interfaces may be mounted according to the processing contents.

  The HW operation unit 120 is an operation circuit that processes specific operations such as encryption / decryption and data compression / expansion by hardware. For example, the HW calculation unit 120 stores a device such as a DSP (Digital Signal Processor) or ASIC (Application Specific Integrated Circuit) dedicated to perform a specific calculation process, or a command sequence of a specific calculation process. It can be configured by a programmable device or the like that configures a circuit by loading from the above.

  The memory 140 is a storage device such as a RAM (Random Access Memory) that stores instruction sequences related to data processing and data to be processed when the PU 110 performs data processing. Note that the memory 140 is not limited to the RAM, and can be configured by any commonly used storage medium such as a memory card, an optical disk, and an HDD (Hard Disk Drive).

  The network interfaces 130 and 131 are devices for the communication apparatus 100 to transmit / receive data to / from an external apparatus. The network interfaces 130 and 131 are interfaces for wired communication such as Ethernet (registered trademark), ISDN (Integrated Services Digital Network) (registered trademark), and FAX Modem, or WiFi (Wireless Fidelity) (registered trademark) (wireless LAN) and It can be configured by any commonly used interface such as a wireless communication interface such as a cellular phone.

  The shared bus 111 is a communication path for electromagnetically or optically transmitting / receiving data between devices such as the PU 110 and the memory 140.

  The PU 110 is a device for executing each task related to the processing time calculation unit 101, the calculation method determination unit 102, the calculation control unit 103, the network processing unit 104, and the delay time calculation unit 105, which are main software configurations.

  The processing time calculation unit 101 calculates the desynchronization time, which is information used as a criterion for determining whether the calculation method determination unit 102 selects the synchronous method or the asynchronous method in the processing of the HW calculation unit 120, as actual data Calculate in advance before processing. The desynchronization time refers to a processing time of a process that is executed in association with the arithmetic process when the arithmetic process is executed by the asynchronous method. In other words, the desynchronization time corresponds to the overhead required for executing the desynchronization process as described above.

  The desynchronization time calculation process that calculates the desynchronization time includes the processing time measurement when the synchronous method is selected, the processing time measurement when the asynchronous method is selected, and the desynchronization time calculation step using the measurement results of the synchronous method and the asynchronous method. Consists of. Details of the processing flow of the desynchronization time calculation process will be described later.

  The calculation method determination unit 102 determines a calculation execution method (hereinafter referred to as a calculation method) by the HW calculation unit 120 based on a determination criterion (asynchronization time) calculated by the processing time calculation unit 101, a synchronous method and an asynchronous method. Decide on one of the methods. Details of the determination method will be described later.

  The arithmetic control unit 103 controls execution of specific arithmetic processing such as encryption / decryption and data compression / decompression by the HW arithmetic unit 120. Specifically, the calculation control unit 103 receives parameters related to calculation from the network processing unit 104, and instructs the HW calculation unit 120 to perform processing according to the received parameters. The arithmetic control unit 103 receives, for example, a processing algorithm, a memory storage area of processing target data, a processing target data size, and the like as parameters.

  The network processing unit 104 is a main part that executes application and system processing, and causes the HW calculation unit 120 to execute part or all of the processing using the calculation control unit 103. Since the first embodiment is an example of communication processing, the network processing unit 104 performs various processes for transmitting and receiving data between the communication device 100 and an external device. For example, the network processing unit 104 analyzes the header portion of data (packet) received from the network interface 130, performs communication protocol processing, creates the header portion of data (packet) to be transmitted from the network interfaces 130 and 131, and creates a communication protocol. Process.

  The delay time calculation unit 105 calculates a delay time representing the time from the current time to the time when the requested calculation ends in response to a request from the calculation method determination unit 102.

  Note that the communication apparatus 100 may be configured to mount any two or more of the PU 110, the memory 140, and the HW calculation unit 120 on a semiconductor device such as a System on chip (SoC).

  Next, with reference to FIG. 3, the concept of the desynchronization time and the desynchronization effect representing the effect of executing the operation in the desynchronization method will be described. FIG. 3 is a timeline diagram when the hardware offloading process is executed in a synchronous manner and an asynchronous manner.

  The pre-processing 301 is a process for calling a calculation process executed by the HW calculation unit 120 from a software process executed by the PU 110. For example, when the software process is a packet process in the IPsec tunnel mode, this corresponds to a process including receiving an IPsec packet and analyzing the packet.

  The post-processing 305 is a process for receiving the result of the arithmetic processing executed by the HW arithmetic unit 120. For example, when the software process is a packet process in the IPsec tunnel mode, this corresponds to a process including encapsulating the data subjected to the calculation process into an IPsec packet and outputting the packet from a predetermined network interface.

  In the Tdelay 302, the request wait calculation is started to be executed on the HW calculation unit 120 from the time when the pre-processing 301 requests the HW calculation unit 120 to start the next calculation process (request waiting calculation). This is the time (delay time) to the point in time. As an example of the case where Tdelay 302 takes a value other than 0, the time when the requested computation process (requested computation) is already executed on the HW computation unit 120 and the time when the pre-processing 301 requests the start of a request waiting computation It can be considered that they overlap.

  Thw 303 indicates the time required for the HW calculation unit 120 to execute the request wait calculation that the pre-processing 301 requests to start.

  The polling process 304 is a process for waiting until the requested calculation is completed after the preprocessing 301 requests the HW calculation unit 120 to start the request waiting calculation. In the polling process 304, a process for determining whether or not the operation process being executed has been completed is repeatedly executed. This process is necessary only for the synchronous method, and this process is not executed in the asynchronous method.

  The desynchronization process 311 refers to a process necessary to eliminate the need to execute the polling process 304 as in the synchronous system when executing the hardware offloading process in an asynchronous system. As a specific example, a process of recording the variable at a predetermined address on the memory 140 so that the temporarily necessary variable held in the pre-processing 301 can be used in the post-processing 305 is given as an example.

The desynchronization effect 312 shows the difference between the processing time of processing executed on the PU 110 in the case of the synchronous method and the processing time of processing executed on the PU 110 in the case of the asynchronous method. If the desynchronization effect 312 is G, G is expressed by the following equation (1). In the formula (1), the desynchronization time is expressed as Toh.
G = Tdelay + Thw-Toh (1)

  In the present embodiment, the calculation method determination unit 102 determines whether to execute in the synchronous method or the asynchronous method depending on whether the desynchronization effect 312 is a positive value or a negative value. Therefore, it is necessary to know the delay time Tdelay, the hardware processing time Thw that is the processing time by the HW calculation unit 120, and the desynchronization time Toh.

  Note that the delay time can be obtained from the hardware processing time, the start time, and the current time of the arithmetic processing being executed (details will be described later). In the following, a method for obtaining the hardware processing time and the desynchronization time will be described.

  First, a processing flow in which the processing time calculation unit 101 calculates the desynchronization time (Toh) will be described with reference to FIGS.

  The processing time calculation unit 101 measures the desynchronization time using a test sheet in which test data and conditions are predetermined as shown in FIG. FIG. 4 is a diagram illustrating an example of a test sheet for measuring a processing time in the first embodiment.

  As shown in FIG. 4, the test sheet includes identification information (No.), processing contents indicating the contents of arithmetic processing, data size of test data used for measurement, arithmetic method (synchronous or asynchronous), data A read address and a data write address are included. The processing content “AES-CBC (encryption)” means that encryption processing is performed in an AES (Advanced Encryption Standard) CBC (Cipher Block Chaining) mode.

  In the example of FIG. 4, only AES-CBC (encryption) is mentioned, but other algorithms and decryption processing may be included. Further, when the HW calculation unit 120 performs calculations such as data compression or decompression algorithm other than encryption / decryption, the contents of those calculations may be set as the processing contents.

  Next, the flow of the desynchronization time calculation process will be described with reference to FIG. FIG. 5 is a flowchart illustrating an overall flow of the desynchronization time calculation process according to the first embodiment.

  First, the processing time calculation unit 101 records the current time in the memory 140 or the like (step S701). For convenience of explanation, the time recorded in this step is referred to as time Tsync1 in the case of the synchronous method and time Tasync1 in the case of the asynchronous method.

  The processing time calculation unit 101 instructs the arithmetic control unit 103 to perform a test (step S702). At this time, the processing time calculation unit 101 instructs execution of a test using any one of the test sheets as shown in FIG.

  Receiving the instruction, the calculation control unit 103 determines whether the calculation method of the test sheet is synchronous or asynchronous (step S703). For example, the test sheet No. of FIG. = If execution of C101 is instructed, the operation control unit 103 determines that the operation method is “synchronous”. Further, for example, the test sheet No. of FIG. When execution of C102 is instructed, the operation control unit 103 determines that the operation method is “asynchronous”.

  When the calculation method is synchronous (step S703: YES), the calculation control unit 103 operates the HW calculation unit 120 so as to start calculation based on the processing content of the test sheet (step S708). Then, the calculation control unit 103 waits until the processing by the HW calculation unit 120 is completed (step S709).

  Upon receiving a calculation processing end notification from the HW calculation unit 120, the calculation control unit 103 notifies the processing time calculation unit 101 of the end of the processing by the synchronization method (step S710) and ends the processing.

  If it is determined in step S703 that the calculation method is asynchronous (step S703: NO), the calculation control unit 103 executes preprocessing for desynchronization such as processing for saving the processing state (step S711). Next, the calculation control unit 103 operates the HW calculation unit 120 so as to start calculation based on the processing content of the test sheet (step S712). Since the method is asynchronous, the arithmetic control unit 103 notifies the processing time calculation unit 101 that the asynchronous method HW arithmetic processing has started, and ends the processing (step S713).

  Thereafter, upon receiving a calculation processing end notification from the HW calculation unit 120, the calculation control unit 103 notifies the processing time calculation unit 101 of the end of the asynchronous HW calculation processing (step S714). Next, the arithmetic control unit 103 executes a post-synchronization process such as a process for calling the stored processing state (step S715). When the post-processing is completed, the arithmetic control unit 103 notifies the processing time calculation unit 101 of the end of the asynchronous processing (step S716), and ends the processing.

  In Step S708 or Step S712, the HW calculation unit 120 that has received a calculation start operation from the calculation control unit 103 executes calculation processing of the instructed processing content (Step S717). For example, the test sheet No. of FIG. = When execution of C101 or C102 is instructed, the HW calculation unit 120 performs CBC mode encryption with an algorithm of AES on the data for 64 bytes from the address A01 on the memory 140, and the processing result data Write to an area of 64 bytes from address A02 on the memory 140.

  When the calculation process is completed, the HW calculation unit 120 notifies the calculation control unit 103 of the end of the calculation process (step S718) and ends the process.

  After instructing the test in step S702, the processing time calculation unit 101 determines whether the arithmetic method of the instructed test is synchronous or asynchronous (step S704). In the case of asynchronous (step S704: NO), the processing time calculation unit 101 records the time Tasync2 when the start notification of the HW calculation process is received from the calculation control unit 103 (step S705). Further, the processing time calculation unit 101 records the time Tasync3 at the time when the completion notification of the HW calculation process is received from the calculation control unit 103 (step S707).

  After recording the time Tasync3, the processing time calculation unit 101 records the time when the processing end notification is received from the arithmetic control unit 103 (step S719). For convenience of explanation, the time recorded in this step is referred to as time Tsync2 in the case of the synchronous method and time Tasync4 in the case of the asynchronous method.

  FIG. 6 is a diagram showing the relationship between the times recorded in this way. FIG. 6 shows Tsync1, Tsync2, Tasync1, Tasync2, Tasync3, and Tasync4, which are the respective times, in the same timeline diagram as FIG.

  Returning to FIG. 5, the processing time calculation unit 101 determines whether all the data of the test sheet has been processed (step S720). If all the data has not been processed (step S720: NO), the next The processing is repeated for the data (step S701).

  In this way, the processing time calculation unit 101 can record the time for calculating the processing time of the arithmetic processing by each arithmetic method for each data having a different data size. Each time is recorded in association with each “No.” of the test sheet.

  When all the data has been processed (step S720: YES), the processing time calculation unit 101 calculates the desynchronization time based on each recorded time (step S721).

Here, the details of the procedure for obtaining the desynchronization time from the measured time in step S721 will be described. First, the processing time calculation unit 101 calculates a processing time for each calculation method from the recorded time. The processing time calculation unit 101 calculates the processing time Tsync of the synchronous method and the processing time Tasync of the asynchronous method by the following equations (2) and (3), respectively.
Tsync = Tsync2-Tsync1 (2)
Tasync = (Tasync2-Tasync1) + (Tasync4-Tasync3) (3)

  Then, the processing time calculation unit 101 calculates the desynchronization time (Toh) from the calculated Tsync and Tasync. Several methods for calculating the desynchronization time (Toh) are conceivable. As one of the simplest methods, a method in which the difference between Tsync and Tasync is Toh can be used. In the test sheet example of FIG. 4, since the data size is the same at 64 bytes regardless of whether the processing method is synchronous or asynchronous, the difference between Tsync and Tasync obtained from the measured value is Toh. In addition, although the value calculated | required from one measurement may be used for Tsync or Tasync, you may obtain | require the average value calculated | required from multiple measurements.

  As another calculation method example, the desynchronization time can be calculated using a test sheet as shown in FIG. 7 instead of FIG. The test sheet in FIG. 7 is obtained by adding data size variations (C103 to C112) to the test sheet in FIG.

  FIG. 8 shows an example of the measurement result. FIG. 8 is an example of a graph in which the Tsync and Tasync obtained from the measurement results are plotted for each data size by performing the desynchronization time calculation process of FIG. 5 using the test sheet of FIG. In this example, the magnitude relationship between the values of Tsync and Tasync is switched between 512 bytes and 768 bytes.

  This indicates that the magnitude relationship between Thw 303, which is the time required for the arithmetic processing shown in FIG. 6, and the processing time of the desynchronization process 311 is switched between 512 bytes and 768 bytes. For example, since Tasync (512 bytes)> Tsync (512 bytes) in the case of 512 bytes, Toh> Thw (512 bytes), and in the case of 768 bytes, Tasync (768 bytes) <Tsync (768 bytes), soh (Ty68). It means that.

  When calculating the desynchronization time using the test sheet of FIG. 7, a linear function is fitted to each of Tasync and Tsync, and Tasync (Tasync (0 byte)) and Tsync when the linear function and the axis of data size 0 intersect. The difference from (Tsync (0byte)) may be the desynchronization time. That is, Toh = Tasync (0 byte) −Tsync (0 byte) may be obtained. In FIG. 8, the desynchronization time 801 represents the desynchronization time obtained in this way.

  Further, the desynchronization time is based on the processing time of the data size (Size) that becomes a threshold at which the magnitude relationship between the desynchronization time (Toh) and the time (Thw) required for the arithmetic processing is switched (that is, the two values are the same). You may ask for. Specifically, the difference between the processing time at the data size serving as the threshold and the Tsync (0) may be used as the desynchronization time. In FIG. 8, the desynchronization time 802 represents the desynchronization time obtained in this way.

  Although common to both FIG. 4 and FIG. 7, the same read address or write address may be used in all trials, or different addresses may be used. The table format of the example of the test sheet shown here can be arbitrarily changed and is a design matter.

  In FIG. 7, the data size is divided into 64 to 256 bytes. However, data divided more finely or data divided more coarsely may be used. However, when the data is roughly divided, there is a high possibility that the accuracy of the required data size threshold will be low.

  The processing time calculation unit 101 executes the desynchronization time calculation process for all or part of the processing contents that can be processed by the HW calculation unit 120 by the method described above, and calculates the calculated value (Toh) as the calculation method determination unit. It is stored in the memory 140 or the like so that it can be shared with 102. The data size threshold calculated by the processing time calculation unit 101 may be notified to the calculation method determination unit 102 and stored in the calculation method determination unit 102.

  As described above, in this embodiment, the desynchronization time that is a criterion for selecting the calculation method can be calculated and stored in advance. As a result, even if the hardware configuration is different, an optimum data size threshold corresponding to the configuration can be obtained.

  Here, as a modification of the processing flow of FIG. 5, the operation control unit 103 may record the time, and the recorded information may be passed to the processing time calculation unit 101 to execute the desynchronization time calculation process. . Furthermore, as another modification of FIG. 5, the calculation control unit 103 may be configured to record the time, and the calculation control unit 103 may measure only the desynchronization time.

  Next, a method for obtaining the hardware processing time Thw will be described. As described above, in order to implement the present embodiment, the time (hardware processing time Thw) required for specific calculation processing executed by the HW calculation unit 120 needs to be known. Specifically, in this embodiment, when the calculation control unit 103 requests the HW calculation unit 120 to perform calculation processing (request waiting calculation), the type and size of data that is the target of the request waiting calculation processing, and the processing content Therefore, it is necessary that the time required for the HW calculation unit 120 to execute the request waiting calculation can be calculated.

  For example, when the encryption process is executed in the AES CBC mode as the calculation process, the time (hardware processing time) required for the encryption process executed by the HW calculation unit 120 is proportional to the size of the data to be processed. To do. For this reason, the correspondence between the data size and the hardware processing time may be measured in advance for a plurality of data sizes.

  Specifically, for each arithmetic processing that can be executed by the HW arithmetic unit 120, the time required for the arithmetic processing (hardware processing time) for a plurality of data sizes is measured. In order to express the hardware processing time with a linear function with the data size as a variable, the hardware processing time is fitted with a linear function, and the slope value of this linear function is held in any processing unit or storage device. You can do it.

  The method for knowing the time required for the arithmetic processing is not limited to this, and any conventionally used method can be applied. The arithmetic processing need not be limited to the arithmetic processing shown in this example, and can be similarly performed in the case of other arithmetic processing including other encryption algorithms and compression / decompression.

  Next, a processing flow when the communication apparatus 100 according to the first embodiment performs communication processing will be described with reference to FIG. The communication process means a process of transmitting / receiving data to / from the communication apparatus 200 via the IP network 300 in FIG. FIG. 9 is a flowchart showing an overall flow of communication processing in the first embodiment.

  Here, as an example of the communication process, a process when an AES-CBC (encryption) process is performed as an IPsec protocol process on the payload of a packet received by the communication apparatus 100 will be described.

  It is assumed that SA (Security Association) and SP (Security Policy) based on the IPsec protocol have already been set between the communication device 100 and the communication device 200.

  First, the network interface 131 of the communication device 100 receives an IP packet transmitted from the terminal device 400 to the communication device 100 and notifies the network processing unit 104 that the packet has been received. The network processing unit 104 performs network processing such as header analysis of the received packet and IPsec protocol processing (step S801).

  Next, the network processing unit 104 gives an instruction regarding the HW calculation process to the calculation control unit 103 (step S802). In this example, the network processing unit 104 instructs the HW calculation unit 120 to execute encryption processing by AES-CBC of the payload of the received packet. Receiving this instruction, the calculation control unit 103 calls the calculation method determination unit 102 (step S803).

  Should the calculation method determination unit 102 select the synchronization method from the data size of the data to be processed (payload of the received packet), information on the process being executed by the HW calculation unit 120, and the desynchronization time described above? A calculation method determining process for determining whether the asynchronous method should be selected is executed (step S804). A specific processing flow of the calculation method determination processing will be described later with reference to FIG.

  The calculation method determination unit 102 notifies the calculation control unit 103 of the determined calculation method (step S805). Receiving the notification, the calculation control unit 103 determines whether the determined calculation method is a synchronous method or an asynchronous method (step S806).

  In the case of the synchronous method (step S806: YES), the operation control unit 103 instructs the HW operation unit 120 about the processing content and starts the encryption process (step S807). Thereafter, the calculation control unit 103 waits until the processing by the HW calculation unit 120 is completed (step S808).

  Upon receiving a calculation processing end notification from the HW calculation unit 120, the calculation control unit 103 notifies the network processing unit 104 of the end of the processing by the synchronization method (step S809), and ends the processing.

  On the other hand, when it is determined in step S806 that the calculation method is an asynchronous method (step S806: NO), the calculation control unit 103 executes preprocessing for desynchronization such as processing for saving the processing state (step S810). . Next, the calculation control unit 103 operates the HW calculation unit 120 so as to start calculation based on the instructed processing content (step S811). Because of the asynchronous method, the operation control unit 103 notifies the network processing unit 104 that the asynchronous method HW operation processing has started, and ends the processing (step S812).

  Thereafter, upon receiving a calculation processing end notification from the HW calculation unit 120, the calculation control unit 103 executes asynchronous post-processing such as processing for calling the stored processing state (step S813). When the post-processing is completed, the arithmetic control unit 103 notifies the network processing unit 104 of the end of the asynchronous process (step S814), and ends the process.

  In Step S807 or Step S811, the HW calculation unit 120 that has received a calculation start operation from the calculation control unit 103 performs calculation processing of the instructed processing content (Step S815). For example, the HW calculation unit 120 executes CBC mode encryption processing with an algorithm of AES on the received data address data (packet payload).

  When the calculation process is completed, the HW calculation unit 120 notifies the calculation control unit 103 of the end of the calculation process (step S816) and ends the process.

  After instructing the arithmetic control unit 103 to perform arithmetic operation, the network processing unit 104 determines whether or not the start notification of the asynchronous HW arithmetic processing is received from the arithmetic control unit 103 (step S817).

  When the notification of the start of the HW calculation process by the asynchronous method is received (step S817: YES), the network processing unit 104 ends the process. When the notification has not been received (step S817: NO), it can be determined that the calculation is being performed by the synchronization method, and thus the network processing unit 104 continues the process in order to receive an end notification of the calculation by the synchronization process.

  After receiving the computation processing end notification transmitted from the computation control unit 103 in step S809 or step S814, the network processing unit 104 executes network processing such as IPsec protocol or IP protocol processing necessary after the encryption processing ( Step S818). Then, the network processing unit 104 instructs the network interface 131 to transmit a packet (step S819).

  As described above, according to the method of the present embodiment, by comparing the data size to be processed and the data size threshold value, data processing is performed by selecting one of the appropriate arithmetic method from the synchronous method and the asynchronous method. It can be carried out.

  Here, the processing flow in the case where the communication apparatus 100 performs the encoding (encryption) processing is shown, but the decoding (decryption) processing can also be realized by the same processing flow with the same configuration. Although an example in which the network processing unit 104 of the communication apparatus 100 performs network processing including encryption is shown here, the network processing unit 104 uses the HW calculation unit 120 to perform calculation processing other than encryption (for example, data (Compression / decompression processing) can also be realized with the same configuration and processing flow.

  Next, details of processing for calculating the time when the processing being executed by the HW calculation unit 120 is completed in the processing (step S807 and step S811) in which the calculation control unit 103 operates the HW calculation unit 120 will be described. When requesting a process to the HW calculation unit 120, the calculation control unit 103 stores information (hereinafter referred to as reference information) necessary for predicting the time at which the process ends among the information related to the requested process. .

  As reference information, the contents of calculation processing, the size of data to be subjected to calculation processing, and the time at which calculation processing is started are given as representative examples. As a specific example, an encryption algorithm (AES CBC mode 128-bit key length encryption process) is used as the operation processing content, and a size of data to be encrypted (IP packet size input from the network interface 130 in the IPsec tunnel mode) is used as the size. As the time, the time when the arithmetic control unit 103 changes the register value of the HW arithmetic unit 120 and starts the processing of the HW arithmetic unit 120 may be stored.

  Further, there are cases where the HW calculation unit 120 cannot immediately start the calculation process, such as when the calculation control unit 103 further requests a calculation process from the HW calculation unit 120 while the HW calculation unit 120 performs some calculation process. In such a case, it is desirable to prepare a queue that waits for the start of the arithmetic processing of the HW arithmetic unit 120, and to appropriately execute the arithmetic processing in the HW arithmetic unit 120. In this case, the operation being executed and the operation included in the queue correspond to the requested operation.

  In this case, it is necessary to consider not only the process being executed by the HW calculation unit 120 but also information about the calculation process included in the queue. In this case, what is necessary is just to add the time concerning each calculation process contained in a queue. The time required for each calculation process can be calculated by a method similar to the method for calculating the remaining time of the process being executed by the HW calculation unit 120. That is, if the contents of the calculation process and the size of the data to be subjected to the calculation process are known, the time required for the calculation process in the HW calculation unit 120 can be predicted.

  Next, details of the calculation method determination processing in step S804 will be described with reference to FIG. FIG. 10 is a flowchart showing the overall flow of the calculation method determination process in the first embodiment.

Note that the calculation control unit 103 notifies the calculation method determination unit 102 of the reference information of the requested calculation when the calculation method determination unit 102 is activated in step S803 in FIG. The calculation method determination unit 102 acquires reference information (step S1001), and requests the delay time calculation unit 105 to calculate the delay time. The delay time calculation unit 105 calculates a calculation being executed on the HW calculation unit 120 and a calculation waiting for execution (requested calculation) included in the queue from the current time and the reference information notified from the calculation method determination unit 102. From the processing time, a delay time that is a time until the arithmetic processing is completed is calculated (step S1002). The following equation (4) may be used to calculate the delay time.
Tdelay = Thw- (Tnow-Tstart) (4)

  Tnow is the current time, and Tstart is the time when the process being executed on the HW calculation unit 120 included in the reference information is started. If Tdelay is negative in equation (4), Tdelay is set to zero. As described above, the hardware processing time Thw can be calculated from the type, data size, and processing content of the data to be processed in the request waiting calculation. In the following description, a variable necessary for calculating Thw such as data size and processing content may be expressed as x, and a hardware processing time calculated according to x may be expressed as Thw (x).

Next, the calculation method determination unit 102 calculates the desynchronization effect G (x, Tdelay) by substituting the calculated Tdelay into the following equation (5) (step S1003).
G (x, Tdelay) = Thw (x) + Tdelay−Toh (5)

  Then, the calculation method determination unit 102 determines whether or not the calculated desynchronization effect G is 0 or more (step S1004). In the case of 0 or more (step S1004: YES), the calculation method determination unit 102 determines the calculation method of the request waiting calculation to be an asynchronous method (step S1005). If the value is smaller than 0 (step S1004: NO), the calculation method determination unit 102 determines the calculation method of the request waiting calculation as a synchronous method (step S1006). The desynchronization effect G corresponds to the desynchronization effect 312 shown in FIG.

  In the figure, when the desynchronization effect G is 0, the calculation method is determined to be an asynchronous method, but the calculation method determination method when the desynchronization effect is 0 is not limited to this. For example, the calculation method determination unit 102 may be configured to determine the synchronization method as the calculation method when the desynchronization effect becomes zero. In such a case, the calculation method determination unit 102 may be configured to determine the calculation method according to a dynamic rule such as alternately adopting a synchronous method and an asynchronous method.

  FIG. 11 is a diagram illustrating a determination result of the calculation method determination unit 102 according to the first embodiment. The horizontal axis represents the time (Thw) required to execute the arithmetic processing in the HW arithmetic unit 120, and the vertical axis represents the delay time (Tdelay) until the arithmetic processing is started. As shown in the figure, in the region where Thw + Tdelay-Toh> 0, the execution time on the PU 110 is shorter when the asynchronous method is selected.

  In the method of simply comparing the hardware processing time (Thw) and the desynchronization time (Toh), the synchronization method is selected in all the areas on the left side of the boundary line where Thw = Toh in FIG. On the other hand, according to the present embodiment, in order to consider the delay time (Tdelay), the synchronization method is selected only in the area 1101.

  Note that in the area 1102, since Thw + Tdelay> Toh, the processing time required for the arithmetic processing is shorter in the asynchronous method. That is, the CPU load is reduced. However, since Thw <Toh, the processing time required for the arithmetic processing itself is larger in the asynchronous method. In the area 1103, since Tdelay> Toh, the processing time required for the arithmetic processing is shorter in the asynchronous method. That is, the CPU load is reduced.

(Modification 1)
In the above desynchronization time calculation process, the processing time is directly measured in the processing flow. On the other hand, the data size threshold may be calculated by a method of estimating the processing time using a method called profiling.

  Profiling is a technique for estimating the execution time of each process by recording the processes being executed on the PU 110 at regular time intervals (hereinafter referred to as sampling). An OProfile implemented in Linux (registered trademark) is a typical implementation example. The ratio of the number of samples for each process obtained by sampling represents the ratio of the execution times of processes executed on the PU 110. For this reason, the ratio of the execution time for each process can be compared by comparing the number of samples for each process.

  When using the profiling method to determine the threshold, profiling is performed for the processing that excludes the processing related to time measurement from the desynchronization time calculation processing as shown in FIG. 5, and the number of samples is converted into real time in the synchronous method and the asynchronous method, Tasync and Tsync are obtained from the actual time, and the desynchronization time can be calculated by any of the methods described above.

  With such a configuration, there is an advantage that the processing time calculation unit 101 and the calculation control unit 103 do not need to have a function of measuring time, and mounting is relatively easy.

(Modification 2)
In the above-described embodiment, the processing time calculation unit 101 executes the desynchronization time calculation process to calculate the data size threshold value and stores it in the memory 140 or the like. In contrast, the desynchronization time calculated in advance by an external device or the like may be stored in the memory 140 or the like without performing the desynchronization time calculation process. In this case, the processing time calculation unit 101 is not necessary. In addition, you may comprise so that desynchronization time can be changed into arbitrary values.

  As described above, in the information processing apparatus according to the first embodiment, when the encryption process is executed by hardware, the data size of the data to be encrypted and the calculation process being executed or waiting for execution are completed. Either a synchronous method or an asynchronous method can be adopted depending on the delay time until. Thereby, an increase in processing load on the PU can be avoided.

(Second Embodiment)
The information processing apparatus according to the second embodiment stores availability information (flag) indicating whether or not an already requested computation process (requested computation) can be executed in an asynchronous manner, and the value of this flag is asynchronous. When it is shown that the method can be executed, the calculation method of the next requested calculation process (request waiting calculation) is determined to be an asynchronous method. This flag is updated to a value indicating that it cannot be executed in the asynchronous manner when the time calculated in advance as the time that can be executed in the asynchronous manner has elapsed.

  FIG. 12 is a block diagram illustrating a configuration of a communication device 1200 according to the second embodiment. As shown in the figure, the communication device 1200 includes a PU 210, an HW calculation unit 120, a memory 240, a network interface 130, a network interface 131, and a time measuring unit 250 as main hardware configurations. Yes.

  In the second embodiment, the flag area 241 in the memory 240, the flag update unit 206 in the PU 210, and the time measuring unit 250 are added, and the calculation method determination unit 202 and the calculation control unit in the PU 210. The function 203 is different from that of the first embodiment. Other configurations and functions are the same as those in FIG. 2, which is a block diagram showing the configuration of the communication apparatus 100 according to the first embodiment, and thus are denoted by the same reference numerals and description thereof is omitted here.

  The flag area 241 indicates a partial area of the storage area of the memory 240. The flag area 241 may be an area where the calculation control unit 203, the calculation method determination unit 202, and the flag update unit 206 described later can read and write at least two types of values. For example, an area having a capacity of 1 byte is secured as a flag area 241 at a certain address on the storage area of the memory 240. The flag area 241 may be configured to read and write “0x00” (hexadecimal notation) as the first value and “0x01” as the second value. In the following, as an example, the first value represents that the request waiting operation can be executed in an asynchronous manner, and the second value represents that the request waiting operation cannot be executed in an asynchronous manner. Note that the physical position on the memory 240 and the value to be read and written are arbitrary.

  The flag update unit 206 rewrites the value in the flag area 241. Specifically, the flag update unit 206 updates the value of the flag area 241 to the first value when the last requested request (final calculation) is requested. In addition, the flag update unit 206 sets the value of the flag area 241 to the second value when the period calculated by the calculation control unit 203 has passed as the period until the final calculation ends after the final calculation is requested. Update.

  The timer unit 250 causes the PU 110 to execute a predetermined process at the set time. For example, the time measuring unit 250 interrupts the PU 110 when the set time is reached. The PU 110 executes processing related to the interrupt. In the present embodiment, the timing unit 250 interrupts the flag updating unit 206 to execute processing for updating the flag area 241 to the second value when the period calculated by the flag updating unit 206 has elapsed. .

  The calculation method determination unit 202 refers to the value of the flag area 241. If this value is the first value, the calculation method of the request wait calculation to be requested next without calculating the desynchronization effect G Is determined to be asynchronous.

  The arithmetic control unit 203 includes the following functions in addition to the functions of the arithmetic control unit 103 of the first embodiment. That is, the calculation control unit 203 requests the flag update unit 206 to update the flag area 241 to the first value before requesting the HW calculation unit 120 to execute the calculation process. In addition, when the hardware arithmetic processing is executed in an asynchronous manner, the arithmetic control unit 203 calculates a time when the flag update unit 206 rewrites the flag area 241 to the second value (details will be described later), and measures the time at that time. The unit 250 instructs the timing unit 250 to interrupt.

  Next, a processing flow when the communication apparatus 1200 according to the second embodiment performs communication processing will be described with reference to FIG. Here, as in the first embodiment, as an example of the communication process, a process when an AES-CBC (encryption) process is performed as an IPsec protocol process on the payload of a packet received by the communication apparatus 1200 will be described. To do. FIG. 13 is a flowchart illustrating an overall flow of communication processing according to the second embodiment.

  In the second embodiment, the calculation control unit 203 requests the flag update unit 206 to update the flag area 241 before requesting the HW calculation unit 120 to perform calculation processing (step S806-1, step S810-). 2) and the step (step S810-1) of setting the time for rewriting the flag area 241 to the second value in the timer unit 250 (step S810-1) are added to the communication processing of the first embodiment shown in FIG. . The other steps are the same as those in FIG.

If it is determined in step S806 that the determination result by the calculation method determination unit 202 is an asynchronous method (step S806: NO), the calculation control unit 203 calculates the time at which the flag update unit 206 rewrites the value of the flag area 241. The timer unit 250 is set to interrupt the flag update at the calculated time (step S810-1). The arithmetic control unit 203 calculates a time T at which the value of the flag area 241 is rewritten by the following equation (6).
T = Tnow + (Tdelay + Thw) −Toh (6)

  Tdelay represents the delay time calculated by the above-described equation (4) with respect to the requested computation that has already been requested. Thw represents the hardware processing time calculated for the requested computation.

  After the setting of the time T is completed, the arithmetic control unit 203 requests the flag update unit 206 to rewrite the value of the flag area 241 to the first value (step S810-2). Also, when it is determined in step S806 that the determination result by the calculation method determination unit 202 is the synchronous method (step S806: YES), the calculation control unit 203 rewrites the value of the flag area 241 to the first value. Is requested to the flag update unit 206 (step S806-1). If the first value is already stored in the flag area 241, there is no need to rewrite it.

  Moreover, although the example which performs the process which rewrites the value of the flag area | region 241 with the function (flag update part 206) performed by PU110 was shown in this Embodiment, it is not necessary to limit to this. For example, you may comprise so that the HW calculating part 120 and the time measuring part 250 may be provided with the function to rewrite the value of the flag area | region 241. FIG.

  In the present embodiment, an example in which a part of the storage area of the memory 240 is used as the flag area 241 is shown. However, the present invention is not limited to this. For example, the PU 110 or the HW arithmetic unit 120 stores storage means (not shown). A part of the storage means may be used as the flag area 241.

  Here, with reference to FIG. 14, the time calculated by the above equation (6) will be described. FIG. 14 is a diagram showing the relationship between the time for rewriting the value of the flag area 241 and the processing time of the calculation. In FIG. 14, T1411 corresponds to time T when the value of the flag area 241 is rewritten.

  Note that the first calculation process in the figure corresponds to the requested calculation. The second calculation process corresponds to a calculation process (request waiting calculation) requested next to the requested calculation. This figure shows an example in which the second arithmetic processing is executed after the preprocessing 301 of the first arithmetic processing and the desynchronization processing 311 are executed. Note that pre-processing 321, desynchronization processing 331, Tdelay 322, and Thw 323 represent each processing included in the second arithmetic processing or processing time of the processing.

As shown in the figure, when viewed from the time point when the calculation method determination unit 202 is executed in the second calculation process (pre-process 321 in the figure), T1411 is the desynchronization time (Toh) 332 from the time when the Tdelay 322 ends. Corresponds to the time obtained by subtracting. If the time point at which the calculation method determination unit 202 is executed is before T1411, considering that Thw> 0, the following equation (7) holds.
Thw + Tdelay-Toh> 0 (7)

  In equation (7), Tdelay represents the delay time calculated by equation (4) above for the request wait calculation. Thw represents the hardware processing time calculated for the request wait calculation.

  For this reason, it is not necessary to calculate the desynchronization effect G (x) for the request waiting operation to be requested next, and the operation method of the request waiting operation may be determined as the asynchronous method. Therefore, the calculation method determination unit 202 of this embodiment determines the calculation method in the processing flow of FIG. FIG. 15 is a flowchart illustrating an overall flow of the calculation method determination process according to the second embodiment.

  The calculation method determination unit 202 determines whether or not the flag area 241 has the first value (step S1501). When the flag area 241 is the first value (step S1501: YES), the calculation method determination unit 202 determines the calculation method to be an asynchronous method (step S1506).

  If the flag area 241 is not the first value, that is, if it is the second value (step S1501: NO), the calculation method determination unit 202 uses the same method as in the first embodiment to change the calculation method. Determine (steps S1502 to S1507). Steps S1502 to S1507 are the same as steps S1001 to S1006 in FIG. 10 in the first embodiment, and thus the description thereof is omitted.

  The determination result of the calculation method determination unit 202 in the second embodiment is the same as FIG. 11 which is the determination result of the calculation method determination unit 102 in the first embodiment.

  As described above, the information processing apparatus according to the second embodiment stores a flag indicating that the requested calculation can be executed in an asynchronous manner, and indicates that the value of the flag indicates that the calculation can be executed in an asynchronous manner. Thus, the calculation method of the request waiting calculation can be determined as an asynchronous method. For this reason, it is possible to reduce the processing time of the calculation method determination processing and further reduce the processing load on the PU as compared with the first embodiment.

  An information processing program executed by the information processing apparatus according to the first or second embodiment is a file in an installable format or an executable format, and is a CD-ROM (Compact Disk Read Only Memory) or a flexible disk (FD). ), A CD-R (Compact Disk Recordable), a DVD (Digital Versatile Disk), and the like.

  Further, the information processing program executed by the information processing apparatus according to the first or second embodiment is stored on a computer connected to a network such as the Internet and provided by being downloaded via the network. It may be configured. The information processing program executed by the information processing apparatus according to the first or second embodiment may be provided or distributed via a network such as the Internet.

  The information processing program according to the first or second embodiment may be provided by being incorporated in advance in a ROM or the like.

  The information processing program executed by the information processing apparatus according to the first or second embodiment includes the above-described units (processing time calculation unit, calculation method determination unit, calculation control unit, network processing unit, delay time calculation unit). As the actual hardware, the PU 110 (processor) reads the information processing program from the storage medium and executes it to load the respective units onto the main storage device. It is generated on a storage device.

  It should be noted that the present invention is not limited to the above-described embodiment as it is, and can be embodied by modifying the constituent elements without departing from the scope of the invention in the implementation stage. In addition, various inventions can be formed by appropriately combining a plurality of constituent elements disclosed in the above embodiments. For example, some components may be deleted from all the components shown in the embodiment. Furthermore, constituent elements over different embodiments may be appropriately combined.

100, 200, 1200 Communication device 101 Processing time calculation unit 102, 202 Calculation method determination unit 103, 203 Calculation control unit 104 Network processing unit 105 Delay time calculation unit 111 Shared bus 120 HW calculation unit 130, 131 Network interface 140, 240 Memory 206 Flag Update Unit 241 Flag Area 250 Timekeeping Unit 300 IP Network 400, 500 Terminal Device

Claims (10)

The execution method is one of a synchronous method in which a process that requests a predetermined operation is executed in synchronization with the end of the operation, and an asynchronous method in which the process is executed asynchronously with the end of the operation. An arithmetic circuit for performing an operation;
A delay time calculation unit that calculates a delay time that represents a time until the requested calculation that represents the calculation requested to be executed by the calculation circuit is completed;
Execution of the request wait operation in the asynchronous manner, and the sum of the processing time and the delay time when the operation circuit executes the request wait operation representing the operation requested to be executed next to the requested operation When the sum is greater than the desynchronization time, the request wait operation is executed in the asynchronous manner when the desynchronization time representing the processing time of the process executed in association with the request wait operation is compared. A decision unit that decides,
A control unit that requests the arithmetic circuit to execute the request waiting operation according to the determined execution method;
An information processing apparatus comprising: The determining unit determines to execute the request waiting operation in the synchronization method when the sum is smaller than the desynchronization time;
The information processing apparatus according to claim 1. A storage unit that stores availability information indicating whether the operation can be performed in the asynchronous manner;
When a final operation representing the requested operation that is requested last among the requested operations is requested, the availability information is updated to a value indicating that the asynchronous operation can be performed, and the final operation is requested. When the time corresponding to the sum of the processing time when the final operation is executed by the arithmetic circuit and the delay time has elapsed, the availability information is updated to a value indicating that the asynchronous method cannot be executed. An update unit,
The determination unit further determines to execute the request waiting operation in the asynchronous method when the availability information is a value indicating that the information can be executed in the asynchronous method;
The information processing apparatus according to claim 1. The determining unit compares the sum and the desynchronization time when the availability information is a value that is not a value indicating that the information can be executed in the asynchronous manner, and when the sum is larger than the desynchronization time, Determining to perform the request wait operation in an asynchronous manner;
The information processing apparatus according to claim 3. A storage unit for storing the predetermined desynchronization time;
The determination unit compares the sum and the desynchronization time stored in the storage unit, and when the sum is greater than the desynchronization time, determines to execute the request waiting operation in the asynchronous method. To do,
The information processing apparatus according to claim 1. A storage unit capable of storing the desynchronization time;
The processing time when the calculation is executed by the asynchronous method with respect to predetermined test data is compared with the processing time when the calculation is executed by the synchronous method with respect to the test data, and the comparison result Further comprising a processing time calculation unit that calculates the desynchronization time based on the data and stores the calculated desynchronization time in the storage unit;
The information processing apparatus according to claim 1. The processing time calculation unit calculates a difference between a processing time when the calculation is performed on the test data by the asynchronous method and a processing time when the calculation is performed on the test data by the synchronous method. Calculating as the desynchronization time, and storing the calculated desynchronization time in the storage unit;
The information processing apparatus according to claim 6. The determination unit calculates a processing time when the request wait calculation is executed in the arithmetic circuit based on a data size of data to be processed by the calculation, and sums the calculated processing time and the delay time. Comparing the desynchronization times and determining to execute the request wait operation in the asynchronous manner if the sum is greater than the desynchronization time;
The information processing apparatus according to claim 1. The execution method is one of a synchronous method in which a process that requests a predetermined operation is executed in synchronization with the end of the operation, and an asynchronous method in which the process is executed asynchronously with the end of the operation. An information processing method executed by an information processing apparatus including an arithmetic circuit for performing an arithmetic operation,
A delay time calculating step in which a delay time calculating unit calculates a delay time representing a time until a requested operation representing the operation requested to be executed by the arithmetic circuit is completed;
The determination unit includes a sum of a processing time and the delay time when the calculation circuit executes a request waiting calculation representing the calculation requested to be executed next to the requested calculation, and the request in the asynchronous manner. When performing the wait operation, the desynchronization time representing the processing time of the process executed in association with the request wait operation is compared, and when the sum is larger than the desynchronization time, the request wait is performed in the asynchronous method. A decision step for deciding to perform the operation;
A control step for requesting the arithmetic circuit to execute the request waiting operation according to the determined execution method;
An information processing method comprising: The execution method is one of a synchronous method in which a process that requests a predetermined operation is executed in synchronization with the end of the operation, and an asynchronous method in which the process is executed asynchronously with the end of the operation. A computer equipped with an arithmetic circuit for performing an operation
A delay time calculation unit that calculates a delay time that represents a time until the requested calculation that represents the calculation requested to be executed by the calculation circuit is completed;
Execution of the request wait operation in the asynchronous manner, and the sum of the processing time and the delay time when the operation circuit executes the request wait operation representing the operation requested to be executed next to the requested operation When the sum is greater than the desynchronization time, the request waiting operation is executed in the asynchronous manner when the desynchronization time representing the processing time of the processing executed in association with the request waiting operation is compared. A decision unit that decides,
An information processing program for causing a function to function as a control unit that requests the arithmetic circuit to execute the request waiting operation according to the determined execution method.

Images