JP2008104053A - Inverter circuit, and delay circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an inverter circuit that reduces a circuit scale, prevents a through-current from flowing, and reduces power consumption when applied to a delay circuit or the like. <P>SOLUTION: The inverter circuit is provided with a MOS transistor P11 turned on/off by an input signal IN1, an N-type MOS transistor N11 turned on/off by an input signal IN2, and two MOS transistors P12, N12 connected in series while being connected with a gate and a drain. The MOS transistor P11, the MOS transistors P12, N12, and the MOS transistor N11 are serially connected between a first power supply VDD and a second power supply VSS. An output signal OUT1 is extracted from a common coupling joint between the MOS transistors P11, P12. An output signal OUT2 is extracted from a common coupling joint between the MOS transistors N11, N12. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

The present invention relates to an inverter circuit and a delay circuit including the inverter circuit.

Conventionally, a circuit as shown in FIG. 5 is known as an example of a delay circuit using a gate array.
This delay circuit is formed by cascading a plurality (six in this example) of inverter circuits 1 to 6. When an input signal IN is input from the input terminal 7, the delay circuit is delayed from the output terminal 8 by a predetermined delay time. An output signal OUT is obtained.

The inverter circuits 1, 5, and 6 are each composed of a general CMOS inverter circuit in which P-type and N-type MOS transistors are combined. The inverter circuits 2 to 4 are basically CMOS inverter circuits. However, the inverter circuits 1, 5, and 6 are different in that P-type MOS transistors are stacked and N-type MOS transistors are stacked. Its configuration is different.

The delay circuit having such a configuration has the following problems.
First, since the inverter circuits 2 to 4 have a structure in which a plurality of P-type and N-type MOS transistors are stacked one by one, the circuit scale of the inverter circuit increases. For this reason, the circuit scale of the delay circuit inevitably increases.
Second, in the inverter circuits 2 to 4 having a structure in which MOS transistors are stacked, the rise and fall of the output are delayed. For this reason, an unnecessary through current flows in the inverter circuit 5 in the output stage.

On the other hand, a conventional delay circuit shown in FIG. 6 is known (see Patent Document 1).
This delay circuit includes a first inverter circuit 11 and a second inverter circuit 12.
The first inverter circuit 11 includes P-type MOS transistors P0 and P1 and an N-type MOS transistor.
It consists of transistors N1 and N0. The MOS transistors P0 and N0 have normal channel lengths, and the MOS transistors P1 and N1 have longer channel lengths than usual.

The second inverter circuit 12 includes P-type MOS transistors P2 and P3 and an N-type MOS transistor.
It consists of transistors N3 and N2. These MOS transistors P2, P3,
N3 and N2 are normal channel lengths.
In the delay circuit having such a configuration, the delay can be increased by using the MOS transistors P1 and N1 whose channel length is longer than usual in the first inverter circuit 11.

However, when an inverter circuit is configured in a gate array, it is necessary to use MOS transistors that constitute cells, and the channel lengths of the MOS transistors are generally the same. For this reason, the MOS transistor P1 whose channel length is longer than usual.
, N1 has a problem that it is difficult to realize on the gate array.
JP 2000-261295 A

Accordingly, an object of the present invention is to provide an inverter circuit that can reduce the circuit scale, prevent a through current, and reduce power consumption when applied to a delay circuit or the like in view of the above points. .
Another object of the present invention is to provide a delay circuit that can reduce the circuit scale, prevent a through current, and reduce power consumption.

In order to solve the above problems and achieve the object of the present invention, each invention has the following configuration.
According to a first aspect of the present invention, there is provided a first transistor of a second conductivity type that is turned on / off by a first input, a second transistor of a first conductivity type that is turned on / off by a second input, and a semiconductor element for voltage drop. The first transistor, the semiconductor element, and the second transistor are connected in series between a first power source and a second power source, and the first transistor and the semiconductor element are connected through a common connection portion. An output of 1 is taken out, and a second output is taken out from a common connection portion between the second transistor and the semiconductor element.

According to a second invention, in the first invention, the semiconductor element comprises at least one of a first conductivity type transistor and a second conductivity type transistor, the gate and drain of which are connected to each other. Yes.
According to a third invention, in the first invention, the semiconductor element comprises a third transistor of the second conductivity type and a fourth transistor of the first conductivity type, both of which are connected in series and each gate And the drain are connected.

In a fourth aspect based on the first aspect, the semiconductor element comprises at least one of a first conductivity type transistor and a second conductivity type transistor, and a predetermined potential is applied to a gate of the one transistor. It has come to be.
In a fifth aspect based on the first aspect, the semiconductor element comprises a third transistor of the second conductivity type and a fourth transistor of the first conductivity type, both of which are connected in series, The gate is connected to the first power source and the second power source.

According to a sixth invention, in the third or fifth invention, the first to fourth transistors use basic cells in a gate array.
A seventh invention is a delay circuit in which a plurality of inverter circuits are connected in cascade, and includes the inverter circuit according to any one of the first to sixth inventions as the plurality of inverter circuits. did.

According to the inverter circuit of the present invention having such a configuration, when applied to a delay circuit or the like, the circuit scale can be reduced, through current can be prevented, and power consumption can be reduced.
Further, according to the delay circuit of the present invention, the circuit scale can be reduced, the through current can be prevented, and the power consumption can be reduced.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
(First embodiment of inverter circuit)
The configuration of the first embodiment of the inverter circuit of the present invention will be described with reference to FIG.
As shown in FIG. 1, the first embodiment of this inverter circuit is a P-type M which is a second conductivity type.
An OS transistor P11, an N-type MOS transistor N11 which is a first conductivity type, a semiconductor element 21, two input terminals 22 and 23, and two output terminals 24 and 25 are provided.

The MOS transistor P11, the semiconductor element 21, and the MOS transistor N11 are connected in series between the first power supply VDD on the high potential side and the second power supply VSS on the low potential side.
The MOS transistor P11 is turned on / off by the input signal IN1. For this reason, the gate of the MOS transistor P11 is connected to the input terminal 22 to which the input signal IN1 is supplied.

The MOS transistor N11 is turned on / off by the input signal IN2. For this reason, the gate of the MOS transistor N11 is connected to the input terminal 23 to which the input signal IN2 is supplied.
The semiconductor element 21 is an element that is interposed between the MOS transistor P11 and the MOS transistor N11 to generate a desired voltage drop or adjust the on / off timing of both the MOS transistors P11 and N11. Specifically, this comprises a P-type MOS transistor P12 which is the second conductivity type and an N-type MOS transistor N12 which is the first conductivity type.

The MOS transistors P12 and N12 are connected in series. The series circuit is provided so as to be inserted between the MOS transistor P11 and the MOS transistor N11. The gates and drains of the MOS transistor P12 and the MOS transistor N12 are connected to each other.
A common connection between the MOS transistor P11 and the semiconductor element 21 is connected to the output terminal 24. That is, the drain of the MOS transistor P11 and the source of the MOS transistor P12 are connected in common, and this common connection is connected to the output terminal 24. The output signal OUT1 is taken out from the output terminal 24.

A common connection between the MOS transistor N11 and the semiconductor element 21 is connected to the output terminal 25. That is, the drain of the MOS transistor N11 and the source of the MOS transistor N12 are connected in common, and this common connection is connected to the output terminal 25. The output signal OUT2 is taken out from the output terminal 25.
The semiconductor element 21 is composed of two MOS transistors P12 and N12. However, at least one of them may be configured. In this case, the gate and the drain of the MOS transistor according to the configuration are connected.

Further, the semiconductor element 21 need not be a MOS transistor as long as it can realize the above function. This also applies to the semiconductor element 21a described later.
Here, in the first embodiment, the MOS transistors P11, P12, N11, N12
Are composed of transistors of the same size. Therefore, the first embodiment can be realized by using a gate array, and in this case, basic cells having the same transistor size can be used.

According to the first embodiment of the inverter circuit having such a configuration, when applied to a delay circuit as described later, the delay circuit is realized with a smaller circuit scale while reducing power consumption per delay time. it can.
In particular, in a design in which the size of each of the P-type and N-type MOS transistors is limited to one type, such as a gate array, the scale of the delay circuit can be reduced.
The first embodiment of the inverter circuit is applied to a delay circuit as will be described later, and the operation will be described in the description of the delay circuit.

(Second embodiment of the inverter circuit)
The configuration of the second embodiment of the inverter circuit of the present invention will be described with reference to FIG.
As shown in FIG. 2, the second embodiment of this inverter circuit is a P-type M which is a second conductivity type.
An OS transistor P11, an N-type MOS transistor N11 which is a first conductivity type, a semiconductor element 22a, two input terminals 22 and 23, and two output terminals 24 and 25 are provided.

In the second embodiment, the semiconductor element 22 of the first embodiment shown in FIG.
It is a replacement. Therefore, in the following description, the same components are denoted by the same reference numerals, and the description thereof is omitted as much as possible.
MOS transistor P11, semiconductor element 21a, and MOS transistor N11
The first power supply VDD on the high potential side and the second power supply VSS on the low potential side are connected in series.

The semiconductor element 21a is interposed between the MOS transistor P11 and the MOS transistor N11 to generate a desired voltage drop, or both the MOS transistors P11, N11.
This is an element for adjusting the on / off timing. Specifically, this is because the second conductivity type P-type MOS transistor P22 and the first conductivity type N-type MOS transistor N22.
It consists of.

The MOS transistors P22 and N22 are connected in series. The series circuit is provided so as to be inserted between the MOS transistor P11 and the MOS transistor N11. A predetermined bias potential is applied to each gate of the MOS transistor P22 and the MOS transistor N22. That is, the MOS transistor P22
A low potential (zero potential) of the second power supply VSS is applied to the gate of the second transistor VSS, and the MOS transistor N2
The high potential of the first power supply VDD is applied to the gate 2.

A common connection between the MOS transistor P11 and the semiconductor element 21a is connected to the output terminal 24. That is, the drain of the MOS transistor P11 and the MOS transistor P22
Are connected in common, and the common connection is connected to the output terminal 24. A common connection between the MOS transistor N11 and the semiconductor element 21a is connected to the output terminal 25.
That is, the drain of the MOS transistor N11 and the source of the MOS transistor N22 are connected in common, and this common connection is connected to the output terminal 25.

The semiconductor element 21a is composed of two MOS transistors P22 and N22. However, it may be configured from at least one of them. In this case, a predetermined voltage is applied to the gate of the MOS transistor according to the configuration.
Here, in the second embodiment, the MOS transistors P11, P22, N11, N22
Are composed of transistors of the same size. For this reason, the second embodiment can be realized by using a gate array, and in this case, a basic cell having the same transistor size can be used.
According to the second embodiment of the inverter circuit having such a configuration, the same effect as that of the first embodiment can be realized when applied to a delay circuit as described later.

(Embodiment of delay circuit)
The configuration of the embodiment of the delay circuit of the present invention will be described with reference to FIG.
In this embodiment of the delay circuit, as shown in FIG. 3, a plurality (six in this example) of inverter circuits 31 to 36 are connected in cascade, and when an input signal IN is inputted from an input terminal 37, an output is obtained. An output signal OUT delayed from the terminal 38 by a predetermined time is obtained.
The inverter circuit 31 is composed of a CMOS inverter circuit in which P-type and N-type MOS transistors P31 and N31 are combined. The inverter circuits 32 to 35 are formed of the inverter circuit shown in FIG. The inverter circuit 36 includes P-type and N-type MOS transistors P32 and N32.
Consists of.

One output signal of the inverter circuit 31 is supplied from the MOS transistor P of the inverter circuit 32.
11 and N11, respectively. Inverter circuit 3
The two output signals 2 to 34 are supplied from the MOS transistors P11 of the inverter circuits 33 to 35, respectively.
Each is input to the gate of N11. Further, the two output signals of the inverter circuit 35 are input to the gates of the MOS transistors P32 and N32 of the inverter circuit 36, respectively.

Next, an operation example of the embodiment of the delay circuit having such a configuration will be described with reference to FIG.
Since this delay circuit is characterized by including the inverter circuits 32 to 35 according to the present invention as inverter circuits, their operations will be mainly described.
Now, a case where the input signal A of the inverter circuit 32 rises from the L level to the H level as shown in FIG. 4A will be described.

Since the MOS transistor N11 of the inverter circuit 32 is turned on at the rising edge of the input signal A, the output signal (output voltage) X2 of the inverter circuit 32 becomes H as shown in FIG.
It changes from level to L level.
Then, after the output signal X2 changes to the L level, the output signal (output voltage) X1 of the inverter circuit 32 is delayed as shown in FIG. 4C through the MOS transistors P12 and N12 whose drain and gate are connected. Is changed from the H level to the intermediate level.

The output signals X1 and X2 output from the inverter circuit 32 in this way are input to the MOS transistors P11 and N11 of the subsequent inverter circuit 33. Output signal X2 is
Since the output signal X1 falls late after the MOS transistor N11 of the circuit 33 is turned off by changing to the L level and the MOS transistor P11 of the circuit 33 is turned on, the M of the circuit 33 is turned on.
A through current flowing from the OS transistor P11 to the MOS transistor N11 can be prevented.
When the output signal X1 of the inverter circuit 32 falls (see FIG. 4B), the MOS transistor P11 of the inverter circuit 33 is turned on. Thus, the inverter circuit 33
Output signal X3 changes to H level as shown in FIG.

When the output signal X3 changes to the H level, the output signal X4 of the inverter circuit 33 passes through the MOS transistors P12 and N12 whose drains and gates are connected, from the L level to the intermediate level with a delay as shown in FIG. To change. Therefore, the output signal X of the circuit 33
4 rises later than the output signal X3. The output signal X3 changes to H level and the circuit 34
After the MOS transistor P11 is turned off, the output signal X4 rises with a delay, and the circuit 34
Since the MOS transistor N11 is turned on, a through current flowing from the MOS transistor P11 of the circuit 34 to the MOS transistor N11 can be prevented. The voltage value at the rising time is lower than the power supply voltage VDD by the MOS transistors P12 and N12.

By such an operation, the inverter circuit 33 causes the MOS transistor P11 to the MOS transistor.
A through current flowing through the transistor N11 can be prevented. Further, because of the body effect of the MOS transistor, the H level of the output signal X4 becomes lower by the threshold voltage of the MOS transistors P12 and N12, so that the delay amount increases and the power consumption can be reduced.
Such an effect in the inverter circuit 33 is also obtained in the inverter circuits 34 and 35 in the subsequent stage.

Next, the case where the input signal A of the inverter circuit 32 falls from the H level to the L level as shown in FIG. 4A will be described.
Since the MOS transistor P11 of the inverter circuit 32 is turned on at the fall of the input signal A, the output signal X1 of the inverter circuit 32 is changed from the intermediate level to the H level as shown in FIG.
Get up to level.

Then, after the output signal X1 changes to H level, the output signal X2 of the inverter circuit 32
Through MOS transistors P12 and N12 whose drains and gates are connected to each other as shown in FIG.
As shown in C), the signal rises from the L level to the intermediate level with a delay. Output signal X1 is H
Since the output signal X2 rises with a delay after the MOS transistor P11 of the circuit 33 is turned off by changing to the level and the MOS transistor N11 of the circuit 33 is turned on, the MO of the circuit 33 is turned on.
A through current flowing from the S transistor P11 to the MOS transistor N11 can be prevented.

As described above, when the input signal A of the inverter circuit 32 changes from the H level to the L level, the inverter circuit 33 is configured to prevent the through current, as in the case where the input signal A changes from the L level to the H level. An effect is obtained.
The operation of the inverter circuit 33 is also performed in the subsequent inverter circuits 34 and 35, and a desired output signal is obtained from the output terminal 38 connected to the inverter circuit 36.
As described above, according to the embodiment of the delay circuit, the delay circuit can be realized with a smaller circuit scale while reducing the power consumption per delay time.
In particular, in a design in which the size of each of the P-type and N-type MOS transistors is limited to one type, such as a gate array, the scale of the delay circuit can be reduced.

(Another embodiment of the delay circuit)
In the embodiment of the delay circuit shown in FIG. 3, the inverter circuits 32 to 35 are configured by the inverter circuit shown in FIG. 1.
However, as another embodiment of the delay circuit, the inverter circuits 32-35 shown in FIG.
You may make it replace with the inverter circuit shown in FIG.
Furthermore, as another embodiment of the delay circuit, the inverter circuits 32 to 35 shown in FIG. 3 may be configured by combining both of the inverter circuits shown in FIG. 1 and FIG.

1 is a circuit diagram showing a configuration of a first embodiment of an inverter circuit of the present invention. It is a circuit diagram which shows the structure of 2nd Embodiment of the inverter circuit of this invention. It is a circuit diagram which shows the structure of embodiment of the delay circuit of this invention. It is a wave form diagram of each part at the time of operation | movement of the delay circuit. It is a circuit diagram which shows the structure of the conventional delay circuit. It is a circuit diagram which shows the structure of the other conventional delay circuit.

Explanation of symbols

N11, N12... First conductivity type MOS transistor, P11, P12... Second conductivity type MOS transistor, 21... Semiconductor element, 22, 23.
25 ... Output terminal, 31-36 ... Inverter circuit

Claims (7)

A first transistor of a second conductivity type that is turned on and off by a first input;
A second transistor of the first conductivity type that is turned on and off by a second input;
A semiconductor element for voltage drop,
Connecting the first transistor, the semiconductor element, and the second transistor in series between a first power source and a second power source;
In addition, the first output is taken out from a common connection portion between the first transistor and the semiconductor element, and the second output is taken out from a common connection portion between the second transistor and the semiconductor element. A characteristic inverter circuit. 2. The semiconductor device according to claim 1, wherein the semiconductor element includes at least one of a first conductivity type transistor and a second conductivity type transistor, and one of the transistors is connected to a gate and a drain. Inverter circuit. The semiconductor element includes a third transistor of the second conductivity type and a fourth transistor of the first conductivity type, both of which are connected in series and have a gate and a drain connected to each other. The inverter circuit according to claim 1. The semiconductor element includes at least one of a first conductivity type transistor and a second conductivity type transistor, and a predetermined potential is applied to a gate of one of the transistors. The inverter circuit according to claim 1. The semiconductor element includes a third transistor of the second conductivity type and a fourth transistor of the first conductivity type. Both transistors are connected in series, and their gates are connected to the first power source and the second power source. The inverter circuit according to claim 1, wherein the inverter circuit is connected. 6. The inverter circuit according to claim 3, wherein the first to fourth transistors use basic cells in a gate array. A delay circuit in which a plurality of inverter circuits are connected in cascade,
A delay circuit comprising the inverter circuit according to any one of claims 1 to 6 as the plurality of inverter circuits.

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