JP2008098817A - Overcurrent protection circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an overcurrent protection circuit of a semiconductor integrated circuit for preventing an overcurrent generated at abnormal time such as the case that an output terminal is erroneously short-circuited to the GND and preventing the heat generation and destruction of a semiconductor element in an output drive circuit. <P>SOLUTION: By the overcurrent protection circuit comprising a current detection circuit 111 for detecting the current of a PchMOS transistor Q1 for output drive and a control circuit 121 for interrupting the operation of the output drive circuit 101 when a value detected in the current detection circuit 111 exceeds a prescribed threshold, the overcurrent of the PchMOS transistor Q1 for the output drive is prevented. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention prevents the semiconductor element of a semiconductor integrated circuit from being heated and destroyed due to an overcurrent that occurs when an output terminal is short-circuited in an output drive circuit of an information communication device equipped with a speaker or the like. The present invention relates to an overcurrent protection circuit.

  FIG. 6 is shown in Patent Document 1 and shows an example of a conventional overcurrent protection circuit. Hereinafter, a conventional overcurrent protection circuit will be described with reference to FIG.

  The output drive circuit 101 includes an output drive PchMOS transistor Q1, an amplifier 4, a current source I1, and switch circuits 6 and 7. The output drive circuit 101 outputs a signal input from the input terminal 1 to the output terminal 2, and outputs an output load 3. To drive. The current detection circuit 115 is connected to the output drive circuit 101, and a current detection PchMOS transistor Q2 having a gate-source common to the PchMOS transistor Q1 and forming a current mirror, and a current connected between the drain of the PchMOS transistor Q2 and GND. It is comprised with resistance R1 for a detection. When the potential difference generated in the current detection resistor R1 exceeds a predetermined threshold value, the control circuit 121 controls the switch circuits 6 and 7 of the output drive circuit 101 to turn off the operation of the PchMOS transistor Q1 and to the amplifier 4. The operation of the output drive circuit 101 is cut off by cutting off the current supply. The current detection circuit 115 and the control circuit 121 constitute an overcurrent protection circuit.

  The operation of the overcurrent protection circuit configured as described above will be described below.

In FIG. 6, the output driving PchMOS transistor Q1 and the current detecting PchMOS transistor Q2 have a common gate-source connection, so that a current proportional to the size of the PchMOS transistor Q1 and the PchMOS transistor Q2 is used for current detection. Is detected by the PchMOS transistor Q2. The detected current flows to the GND through the current detection resistor R1, and a potential difference is generated between both ends of the resistor R1. When the output terminal 2 is short-circuited to GND or the like, the current of the output driving PchMOS transistor Q1 increases, and when the potential difference of the resistor R1 exceeds a predetermined threshold value of the control circuit 121, the control circuit 121 The operation of the drive circuit 101 is cut off and overcurrent is prevented. In this way, overcurrent protection operates.
JP-A-8-154022

  However, such a conventional configuration has a problem that the current ratio between the Pch MOS transistors Q1 and Q2 is not constant because the drain voltage of the output driving PchMOS transistor Q1 is different from the drain voltage of the current detecting PchMOS transistor Q2. .

  FIG. 9 shows a timing chart of the drain voltage and drain current of the Pch MOS transistors Q1 and Q2. As shown in the figure, the output driving PchMOS transistor Q1 operates in the saturation region when the output voltage of the output terminal 2 is low, and operates in the non-saturation region when the output voltage is high. The current detecting PchMOS transistor Q2 operates in the saturation region regardless of the magnitude of the output voltage at the output terminal 2. For this reason, the current ratio between the PchMOS transistors Q1 and Q2 is not constant during the time from t1 to t2 when the PchMOS transistor Q1 operates in the non-saturated region, and the current detection PchMOS transistor Q2 with respect to the current of the output driving PchMOS transistor Q1. Current ratio increases. Here, for example, it is assumed that the value of the potential difference generated in the current detection resistor R1 is set as the threshold value of the control circuit 121 when the output drive PchMOS transistor Q1 operates in the saturation region and a current of 1A flows. At this time, if the PchMOS transistor Q1 operates in the saturation region, the overcurrent protection operates when a current of 1 A or more flows. However, if the PchMOS transistor Q1 operates in the nonsaturation region, Since the current ratio to the PchMOS transistor Q2 increases, the potential difference generated in the current detection resistor R1 exceeds the threshold value of the control circuit 121 even though a current of 1 A or more does not flow through the PchMOS transistor Q1. Protection will work. As described above, since the current ratio between the output drive PchMOS transistor Q1 and the current detection PchMOS transistor Q2 is not constant, the current flowing through the output drive PchMOS transistor Q1 is equal to or less than the set value of the overcurrent. Is operating normally, the overcurrent protection is activated, and the operation of the output drive circuit 101 may be interrupted.

  As described above, since the current ratio between the output driving transistor and the current detection transistor is not determined depending on the state of the output voltage at the output terminal 2, overcurrent protection is erroneously performed when the output driving circuit 101 is operating normally. Problems occur. Also, if the overcurrent set value is increased so that overcurrent protection does not operate during normal operation, the output drive transistor will generate heat or be destroyed before the overcurrent protection operates.

  Next, another example of a conventional overcurrent protection circuit is shown in FIG. In the figure, the output drive circuit 105 is configured by adding a current detection resistor R3 between the source of the output drive PchMOS transistor Q1 and VCC from the configuration of the output drive circuit 101. The current is detected as a potential difference across the resistor R3. When this potential difference exceeds a predetermined threshold value of the control circuit 121, the switch circuits 6 and 7 of the output drive circuit 105 are controlled, and the operation of the output drive circuit 105 is shut off. In this way, overcurrent protection operates. However, in this circuit, since the current of the output drive PchMOS transistor Q1 is detected by the resistor R3, the current detection ratio is constant, but the same current as that supplied to the output load is the current detection resistor R3. Also flows. For this reason, there arises a problem that the output voltage range corresponding to the voltage generated at both ends of the current detection resistor R3 is narrowed.

  The present invention has been made in view of such a conventional problem, and prevents an overcurrent that occurs at the time of an abnormality such as a short circuit of an output terminal in an output drive circuit of an information communication device including a speaker or the like. Another object of the present invention is to provide an overcurrent protection circuit for a semiconductor integrated circuit that prevents heat generation and destruction of a semiconductor element.

  In order to achieve the above object, according to the first aspect of the present invention, there is provided a first output drive circuit including a first PchMOS transistor having a source connected to VCC and driving an output with an outflow current. A first current detection circuit including a second PchMOS transistor having a gate and a source connected in common to the PchMOS transistor and detecting a current of the first PchMOS transistor; and a current detection value of the first current detection circuit is An overcurrent protection circuit comprising a first control circuit that cuts off the operation of the first output drive circuit when a predetermined value is exceeded, wherein the drain of the second PchMOS transistor is connected to the first control circuit. It is characterized by having substantially the same potential as the drain of the Pch MOS transistor.

  According to a second aspect of the present invention, in the overcurrent protection circuit according to the first aspect, the first current detection circuit has a base connected to the drain of the first PchMOS transistor and a constant current source at the emitter. A first NPN transistor to be connected, a base is connected to an emitter of the first NPN transistor, and an emitter is connected to a drain of the second PchMOS transistor.

  According to a third aspect of the present invention, there is provided a second output drive circuit including a first NchMOS transistor having a source connected to GND and driving an output with an inflow current. A second current detection circuit including a second NchMOS transistor connected in common and detecting a current of the first NchMOS transistor; and a current detection value of the second current detection circuit exceeding a predetermined value; An overcurrent protection circuit having a second control circuit configured to cut off the operation of the second output drive circuit, wherein the drain of the second NchMOS transistor has substantially the same potential as the drain of the first NchMOS transistor. It is characterized by.

  According to a fourth aspect of the present invention, there is provided a third output driving circuit including a second PNP transistor having an emitter connected to VCC and driving an output with an outflow current, wherein the second PNP transistor, the base and the emitter are connected to each other. A third current detection circuit including a third PNP transistor connected in common and detecting a current of the second PNP transistor; and when a current detection value of the third current detection circuit exceeds a predetermined value, An overcurrent protection circuit comprising a third control circuit that cuts off the operation of the third output drive circuit, wherein the collector of the third PNP transistor has substantially the same potential as the collector of the second PNP transistor. It is characterized by.

  According to a fifth aspect of the present invention, in the overcurrent protection circuit according to the first aspect, the first control circuit holds a state in which the operation of the first output drive circuit is cut off for a predetermined time, It has a function of returning from the holding state after a predetermined time has elapsed.

  The invention according to claim 6 includes the first PchMOS transistor and the first NchMOS transistor, and the first output terminal is determined by the outflow current of the first PchMOS transistor and the inflow current of the second NchMOS transistor. , A first PchMOS transistor and a first NchMOS transistor, and a second output current of the first PchMOS transistor and an inflow current of the first NchMOS transistor. A fifth output drive circuit for driving the output terminals of the first output terminal, a load connected between the first output terminal and the second output terminal, and a fourth output drive circuit and a fifth output drive. In the BTL output circuit in which the circuit drives the load by flowing current in and out, the first PchMOS transistor and And a current detection value of the first current detection circuit and the first current detection circuit each having a second PchMOS transistor for detecting a current of the first PchMOS transistor having a gate and a source connected in common. An overcurrent protection circuit comprising a fourth control circuit that cuts off the operation of both the fourth output drive circuit and the fifth output drive circuit when the value exceeds the value, wherein the second PchMOS A first overcurrent protection circuit, wherein the drain of the transistor is set to substantially the same potential as the drain of the first PchMOS transistor; and the first NchMOS transistor has a gate and a source commonly connected to the first overcurrent protection circuit. The second current detection circuit including the second NchMOS transistor for detecting the current of the NchMOS transistor and the second current detection circuit An overcurrent protection circuit comprising a fifth control circuit that cuts off the operations of both the fourth output drive circuit and the fifth output drive circuit when the current detection value of the detection circuit exceeds a predetermined value. A second overcurrent protection circuit, characterized in that the drain of the second NchMOS transistor has substantially the same potential as the drain of the first NchMOS transistor, and the fourth output drive circuit, An overcurrent protection circuit configured to be provided in both of the fifth output drive circuits, wherein the fourth output is generated in accordance with respective overcurrents of the fourth output drive circuit and the fifth output drive circuit. The operation of both the drive circuit and the fifth output drive circuit is cut off.

  According to the overcurrent protection circuit of the present invention, in the output drive circuit, the output voltage range is not limited, and the output drive transistor current is supplied at a constant current ratio regardless of the output voltage. Since it can be detected, malfunction of overcurrent protection during normal operation can be prevented, and an effect of preventing the semiconductor element from generating heat and being destroyed by the overcurrent can be obtained.

(First embodiment)
Hereinafter, an overcurrent protection circuit according to a first embodiment of the present invention will be described with reference to the drawings. FIG. 1 shows an example of an overcurrent protection circuit to which the first embodiment of the present invention is applied.

  In this embodiment, the output drive circuit 101 includes an amplifier 4, an output drive PchMOS transistor Q 1, a current source I 1, and switch circuits 6 and 7, and a signal input from the input terminal 1 is output to the output terminal 2. Output to. The current detection circuit 111 is connected to the output drive circuit 101, and the output drive PchMOS transistor Q1 and the gate-source have a common current mirror, and the base is connected to the drain of the PchMOS transistor Q1. NPN transistor Q3 connected with a current source connected to the emitter, a base connected to the emitter of NPN transistor Q3, and an emitter connected to the drain of PchMOS transistor Q2 between the collector of PNP transistor Q4 and PNP transistor Q4 and GND The drain voltage of the PchMOS transistor Q1 is supplied to the drain of the PchMOS transistor Q2 via the NPN transistor Q3 and the PNP transistor Q4. Drain voltage of the output driving PchMOS transistor Q1 and the current detection PchMOS transistor Q2 is maintained at substantially the same potential. When the voltage generated across the current detection resistor R1 of the current detection circuit 111 exceeds a predetermined threshold, the control circuit 121 controls the switch circuits 6 and 7 of the output drive circuit 101 to operate the PchMOS transistor Q1. Is turned off and the current supply to the amplifier 4 is cut off, whereby the operation of the output drive circuit 101 is cut off. The current detection circuit 111 and the control circuit 121 constitute an overcurrent protection circuit.

  The operation of the overcurrent protection circuit configured as described above will be described below.

  In FIG. 1, an output driving PchMOS transistor Q1 and a current detecting PchMOS transistor Q2 have their gates and sources connected in common, and a current proportional to the size of the PchMOS transistor Q1 and the PchMOS transistor Q2 is a current detecting PchMOS. Detected by transistor Q2. Here, since the drain voltages of the Pch MOS transistor Q1 and the Pch MOS transistor Q2 are substantially the same potential, the proportional relationship of the detected current is maintained regardless of the voltage of the output terminal 2. Further, the current detected by the current detection PchMOS transistor Q2 flows to the current detection resistor R1 via the PNP transistor Q4, and a potential difference is generated between both ends of the resistor R1. When the output terminal 2 is short-circuited to GND or the like, the current of the output driving PchMOS transistor Q1 increases, and when the potential difference of the resistor R1 exceeds a predetermined threshold value of the control circuit 121, the control circuit 121 The operation of the drive circuit 101 is cut off and overcurrent is prevented. In this way, overcurrent protection operates.

  Next, FIG. 10 shows a timing chart of the drain voltage and drain current of the Pch MOS transistors Q1 and Q2, and the collector voltage and collector current of the PNP transistor Q4. As shown in the figure, since the drain voltage of the output driving PchMOS transistor Q1 and the drain voltage of the current detecting PchMOS transistor Q2 are substantially the same potential, when the PchMOS transistor Q1 operates in the non-saturated region, the PchMOS transistor Q2 similarly operates in the non-saturated region. Accordingly, the current ratio between the output drive PchMOS transistor Q1 and the current detection PchMOS transistor Q2 is constant regardless of the operating region of the PchMOS transistor Q1. For this reason, for example, when a current of 1 A flows through the output driving PchMOS transistor Q1, the value of the potential difference generated in the current detection resistor R1 is set as the threshold value of the control circuit 121. Even in such a state, the overcurrent protection operates only when a current of 1 A or more flows through the output driving PchMOS transistor Q1. As described above, the overcurrent protection operates when an overcurrent of a predetermined current value or more flows through the output driving PchMOS transistor Q1, and therefore it is possible to prevent the overcurrent protection from being erroneously operated during the normal operation. Further, as shown in FIG. 7, since a resistance between the output driving transistor and VCC is not required, there is no problem that the output voltage range is limited.

(Second Embodiment)
Hereinafter, an overcurrent protection circuit according to a second embodiment of the present invention will be described with reference to the drawings. FIG. 2 shows an example of an overcurrent protection circuit to which the second embodiment of the present invention is applied. 2, the same parts as those in FIG. 1 are denoted by the same reference numerals, and detailed description thereof is omitted.

  In this embodiment, the output drive circuit 102 is configured in the same manner as the output drive circuit 101 using an NchMOS transistor Q5 as an output drive transistor, outputs a signal input from the input terminal 1 to the output terminal 2, and supplies the VCC and output terminal. The output load 3 connected between the two is driven. The current detection circuit 112 is connected to the output drive circuit 102, and the output drive NchMOS transistor Q5 and the current-detection NchMOS transistor Q6 that form a current mirror in common with the NchMOS transistor Q5 and the base are connected to the drain of the NchMOS transistor Q5. PNP transistor Q7 connected with current source I3 connected to the emitter, and the base connected to the emitter of PNP transistor Q7, and the emitter connected to the drain of NchMOS transistor Q6 between the collector of NPN transistor Q8 and NPN transistor Q8 and VCC The drain voltage of the NchMOS transistor Q5 is supplied to the drain of the NchMOS transistor Q6 via the PNP transistor Q7 and the NPN transistor Q8. Ri, the drain voltage of the output driving NchMOS transistor Q5 and the current detection NchMOS transistor Q6 is kept substantially the same potential. The current detection circuit 112 and the control circuit 121 constitute an overcurrent protection circuit.

  Next, the operation of this embodiment will be described. Since the operation of the overcurrent protection circuit is the same as that of the first embodiment, detailed description thereof is omitted.

  In FIG. 2, since the drain voltage of the output driving NchMOS transistor Q5 and the drain voltage of the current detecting NchMOS transistor Q6 are substantially the same potential, when the NchMOS transistor Q5 operates in the non-saturated region, the same applies to the NchMOS transistor Q6. Operates in the non-saturated region. Therefore, the current ratio between the output drive NchMOS transistor Q5 and the current detection NchMOS transistor Q6 is constant regardless of the operation region. For this reason, since the overcurrent protection operates only when an overcurrent of a predetermined current value or more flows through the output driving NchMOS transistor Q5, it is possible to prevent the overcurrent protection from being erroneously operated during the normal operation. . Further, the problem that the output voltage range is limited does not occur.

(Third embodiment)
Hereinafter, an overcurrent protection circuit according to a third embodiment of the present invention will be described with reference to the drawings. FIG. 3 shows an example of an overcurrent protection circuit to which the third embodiment of the present invention is applied. 3, the same parts as those in FIG. 1 are denoted by the same reference numerals, and detailed description thereof is omitted.

  In this embodiment, the output drive circuit 103 is configured in the same manner as the output drive circuit 101, with the output drive transistor being a PNP transistor Q9. The current detection circuit 113 is configured in the same manner as the current detection circuit 111 with the current detection transistor being a PNP transistor Q10, and the collector voltage of the PNP transistor Q9 is supplied to the collector of the PNP transistor Q10 via the NPN transistor Q3 and the PNP transistor Q4. Thus, the collector voltages of the PNP transistor Q9 for driving the output and the PNP transistor Q10 for detecting the current are maintained at substantially the same potential. The current detection circuit 113 and the control circuit 121 constitute an overcurrent protection circuit.

  Next, the operation of this embodiment will be described. Note that detailed description of the operation of the overcurrent protection circuit similar to that of the first embodiment is omitted.

  In FIG. 3, the collector voltage of the PNP transistor Q9 for driving the output and the collector voltage of the PNP transistor Q10 for detecting the current are substantially the same. Therefore, when the PNP transistor Q9 operates in the non-saturated region, the PNP transistor Q10 is also the same. Operates in the non-saturated region. Therefore, the current ratio between the output driving PNP transistor Q9 and the current detection PNP transistor Q10 is constant regardless of the operating region. For this reason, the overcurrent protection operates only when an overcurrent of a predetermined current value or more flows through the PNP transistor Q9 for driving the output, so that it is possible to prevent the overcurrent protection from being erroneously operated during the normal operation. . Further, the problem that the output voltage range is limited does not occur.

  In the third embodiment, the output driving PNP transistor Q9 can be configured as an NPN transistor to form a similar overcurrent protection circuit, and the same effect can be obtained.

(Fourth embodiment)
Hereinafter, an overcurrent protection circuit according to a fourth embodiment of the present invention will be described with reference to the drawings. FIG. 4 shows an example of an overcurrent protection circuit to which the fourth embodiment of the present invention is applied. 4, the same parts as those in FIG. 1 are denoted by the same reference numerals, and detailed description thereof is omitted.

  In this embodiment, the current detection circuit 111, the control circuit 121, and the state holding circuit 131 constitute an overcurrent protection circuit. An example of the state holding circuit 131 is shown in FIG. This circuit is composed of NPN transistors Q31 to 34, resistors R31 to 33, and a capacitor C31, and outputs a HIGH voltage when a HIGH voltage is input to the input, and outputs a LOW voltage when a LOW voltage is input. Since the NPN transistor Q32 and the capacitor C31 constitute a filter that controls the ON time of the NPN transistor Q32, the output is held at the HIGH voltage for a certain time after the input is switched from the HIGH voltage to the LOW voltage. , Has a state holding function for switching to the LOW voltage. The holding time is determined by the discharge time of the capacitor C31 due to the base current of the NPN transistor Q32.

  Next, the operation of this embodiment will be described. Note that detailed description of the operation of the overcurrent protection circuit similar to that of the first embodiment is omitted.

  In FIG. 4, when an overcurrent is generated in the output driving PchMOS transistor Q1, the potential difference between both ends of the current detection resistor R1 exceeds a predetermined threshold value of the control circuit 121, and the operation of the output driving circuit 101 is shut off. At this time, the operation holding state of the output drive circuit 101 is held for a certain time by the state holding circuit 131. Thereafter, the operation of the output drive circuit 101 is restored. However, if the state in which an overcurrent is generated in the PchMOS transistor Q1 continues, the operation of the output drive circuit 101 is interrupted again and the state is maintained. Thereafter, the same operation is repeated, and the average current of the output drive circuit 101 hardly increases even if an abnormal state in which an overcurrent occurs continues. For this reason, the semiconductor element does not generate heat at all.

  As described above, according to the fourth embodiment, it is possible to prevent the overcurrent protection from being erroneously operated during the normal operation as in the first embodiment, and to filter the state of the overcurrent of the output driving transistor with the filter. Since it is held and prevented, the semiconductor element of the output drive circuit and the package of the semiconductor integrated circuit do not generate heat at all, and the destruction of the semiconductor element can be prevented.

(Fifth embodiment)
Hereinafter, an overcurrent protection circuit according to a fifth embodiment of the present invention will be described with reference to the drawings. FIG. 5 shows an example of an overcurrent protection circuit to which the fifth embodiment of the present invention is applied. 5, the same parts as those in FIGS. 1 to 4 are denoted by the same reference numerals, and detailed description thereof is omitted.

  In this embodiment, the output drive circuit 104 includes amplifiers 4 and 5, an output drive PchMOS transistor Q1, an NchMOS transistor Q5, a current source I1, and switch circuits 6 to 8, and the output stage is a PchMOS transistor Q1. The signal input from the input terminal 1 is output to the output terminal 2 with the configuration of rail-to-rail output that drives the output by the current flowing out of the NchMOS transistor Q5 and the inflow current of the NchMOS transistor Q5. The output drive circuit 204 is configured similarly to the output drive circuit 104, and outputs a signal input from the input terminal 1 via the inverting amplifier 21 to the output terminal 22. The output load 3 is connected between the output terminal 2 and the output terminal 22, and the output drive circuit 104 and the output drive circuit 204 output signals whose phases are inverted with each other, and the output load 3 is driven. As described above, the output drive circuits 104 and 204 constitute a BTL output circuit. The current detection circuit 114 includes a Pch MOS transistor Q2, an Nch MOS transistor Q6, NPN transistors Q3 and Q8, PNP transistors Q4 and Q7, current detection resistors R1 and R2, and current sources I2 and I3. The drain voltages of the transistor Q1, the current detecting PchMOS transistor Q2, the output driving NchMOS transistor Q5, and the current detecting NchMOS transistor Q6 are maintained at substantially the same potential. The current detection circuit 214 is configured in the same manner as the current detection circuit 114. The control circuit 122 is composed of PNP transistors Q13 to 16 and NPN transistors Q11 to Q12. When any of the transistors Q11 to Q14 is turned on, the control circuit 122 outputs a HIGH voltage and operates both the output drive circuits 104 and 204. Shut off. The current detection circuits 114 and 214, the control circuit 122, and the state holding circuit 131 constitute an overcurrent protection circuit.

  Next, the operation of this embodiment will be described. The detailed description of the operation of the overcurrent protection circuit similar to those in the first to fourth embodiments is omitted.

  In FIG. 5, when the output terminal 2 and the output terminal 22 are accidentally shorted, for example, when a positive half wave of a sine wave signal is input from the input terminal 1, a positive half wave of a sine wave is output from the output terminal 2. The negative half wave of the sine wave is output from the output terminal 22, and the VCC is connected to the PchMOS transistor Q 1 of the output drive circuit 104, between the shorted output terminal 2 and the output terminal 22, and further to the NchMOS of the output drive circuit 204. Overcurrent that flows to GND via transistor Q25 is generated. For this reason, the current flowing through the current detecting PchMOS transistor Q2 and the NchMOS transistor Q26 increases, and the potential difference generated in the voltage detecting resistors R1 and R22 increases. When this potential difference exceeds one of the threshold values set by each Vbe in the NPN transistor Q11 and the PNP transistor Q14 of the control circuit 122, either the NPN transistor Q11 or the PNP transistor Q14 is turned on, and the control circuit 122 Is switched from the LOW voltage to the HIGH voltage, the operations of both the output drive circuits 104 and 204 are cut off. At this time, since this state is held for a certain period of time by the state holding circuit 131, the average current of both the output drive circuits 104 and 204 does not increase. Thus, overcurrent generated in the output drive circuits 104 and 204 can be prevented. Even when a negative half wave of a sine wave signal is input from the input terminal 1, a negative half wave of a sine wave is output from the output terminal 2, and a positive half wave of a sine wave is output from the output terminal 22, overcurrent protection is provided. The operation of is the same.

  When the output terminal 2 or the output terminal 22 is short-circuited to GND or when an overcurrent is generated in the output drive circuits 104 and 204, such as when short-circuited to VCC, the output terminal 2 and the output terminal 22 are connected to each other. The operation of both the output drive circuits 104 and 204 is shut off by the same overcurrent protection operation as when a short circuit occurs, and overcurrent can be prevented in any output terminal abnormal state.

  As described above, according to the fifth embodiment, since the overcurrent protection function is added to each of the four output driving transistors in the BTL output circuit, overcurrent is prevented in any output terminal abnormal state. Heat generation and destruction of the semiconductor element can be prevented. Moreover, since overcurrent protection does not operate unless an overcurrent of a certain current value or more flows in any state of the output voltage, malfunction of overcurrent protection is prevented during normal operation. Furthermore, the output voltage range is not limited. Therefore, it is particularly useful in a BTL output circuit in which the output stage has a rail-to-rail output configuration in order to widen the output voltage range to almost the same as the power supply voltage.

  In the fifth embodiment, the same overcurrent protection circuit can be configured even if the output driving transistor is a bipolar transistor, and the same effect can be obtained. In the first to fifth embodiments, the same effect can be obtained when the output load 3 is another speaker, coil, or the like.

  As described above, according to the present invention, in an output drive circuit of an information communication device equipped with a speaker or the like, a semiconductor element generates heat and breaks down due to an overcurrent that occurs when an output terminal is short-circuited. This is useful for an overcurrent protection circuit that prevents this.

1 is a configuration diagram of an overcurrent protection circuit according to a first embodiment of the present invention. The block diagram of the overcurrent protection circuit in the 2nd Embodiment of this invention Configuration diagram of an overcurrent protection circuit according to a third embodiment of the present invention The block diagram of the overcurrent protection circuit in the 4th Embodiment of this invention The block diagram of the overcurrent protection circuit in the 5th Embodiment of this invention Configuration diagram of the overcurrent protection circuit in the conventional example Configuration diagram of another overcurrent protection circuit in the conventional example Configuration diagram showing an example of the state holding circuit 131 of FIGS. Timing chart of the overcurrent protection circuit in the conventional example of FIG. Timing chart of overcurrent protection circuit in first embodiment of the present invention

Explanation of symbols

DESCRIPTION OF SYMBOLS 1, 31 Input terminal 2, 22, 32 Output terminal 3 Output load 4, 5 Amplifier 6-8 Switch circuit 21 Inverting amplifier Q1-2, Q21-22 PchMOS transistor Q5-6, Q25-26 NchMOS transistor Q3, Q8, Q11 Q12, Q23, Q28, Q31-34 NPN transistors Q4, Q7, Q13-16 PNP transistors R1-3, R11, R21-22, R31-33 Resistor C1 Capacitors I1-3, I21-23 Current sources 101-105, 204 Output drive circuit 111-114, 214 Current detection circuit 121-122 Control circuit 131 State holding circuit

Claims (6)

In the first output driving circuit including a first PchMOS transistor having a source connected to VCC and driving an output with an outflow current, the first PchMOS is connected in common to the first PchMOS transistor and the gate and the source. A first current detection circuit including a second PchMOS transistor for detecting a current of the transistor, and an operation of the first output drive circuit when a current detection value of the first current detection circuit exceeds a predetermined value; An overcurrent protection circuit having a first control circuit that cuts off the current, wherein the drain of the second PchMOS transistor has substantially the same potential as the drain of the first PchMOS transistor. Protection circuit. The first current detection circuit includes a first NPN transistor having a base connected to a drain of the first PchMOS transistor and a constant current source connected to an emitter, and a base connected to an emitter of the first NPN transistor. 2. The overcurrent protection circuit according to claim 1, further comprising a first PNP transistor connected and having an emitter connected to a drain of the second PchMOS transistor. In a second output drive circuit having a first NchMOS transistor having a source connected to GND and driving an output with an inflow current, the first NchMOS is connected in common to the first NchMOS transistor and the first NchMOS. A second current detection circuit including a second NchMOS transistor for detecting a current of the transistor; and an operation of the second output drive circuit when a current detection value of the second current detection circuit exceeds a predetermined value. An overcurrent protection circuit configured to include a second control circuit that shuts off the overcurrent, wherein the drain of the second NchMOS transistor has substantially the same potential as the drain of the first NchMOS transistor. Protection circuit. In a third output drive circuit comprising a second PNP transistor whose emitter is connected to VCC and drives an output with an outflow current, the second PNP transistor, the base and the emitter are connected in common, and the second PNP transistor A third current detection circuit including a third PNP transistor for detecting a current of the transistor; and an operation of the third output drive circuit when a current detection value of the third current detection circuit exceeds a predetermined value. An overcurrent protection circuit comprising a third control circuit for shutting off the overcurrent, wherein the collector of the third PNP transistor has substantially the same potential as the collector of the second PNP transistor. Protection circuit. The first control circuit has a function of holding a state where the operation of the first output driving circuit is cut off for a predetermined time, and returning from the holding state after a predetermined time has elapsed. The overcurrent protection circuit according to claim 1. A fourth output drive circuit including the first PchMOS transistor and the first NchMOS transistor, and driving a first output terminal by an outflow current of the first PchMOS transistor and an inflow current of the second NchMOS transistor; And a first PchMOS transistor and a first NchMOS transistor, and a second output terminal is driven by the outflow current of the first PchMOS transistor and the inflow current of the first NchMOS transistor. An output drive circuit, a load is connected between the first output terminal and the second output terminal, and the fourth output drive circuit and the fifth output drive circuit flow current in and out. In the BTL output circuit for driving the load, the gate and the source are shared with the first PchMOS transistor. When the current detection value of the first current detection circuit and the first current detection circuit including the second PchMOS transistor connected to detect the current of the first PchMOS transistor exceeds a predetermined value, An overcurrent protection circuit having a fourth control circuit configured to block operations of both the fourth output drive circuit and the fifth output drive circuit, wherein the drain of the second PchMOS transistor is connected to the first control circuit. A first overcurrent protection circuit characterized by having substantially the same potential as the drain of the PchMOS transistor, and the current of the first NchMOS transistor is detected by connecting the gate and source in common with the first NchMOS transistor Current detection values of the second current detection circuit including the second NchMOS transistor and the second current detection circuit are An overcurrent protection circuit having a fifth control circuit configured to cut off the operation of both the fourth output drive circuit and the fifth output drive circuit when a predetermined value is exceeded, A second overcurrent protection circuit characterized in that the drain of the NchMOS transistor has substantially the same potential as the drain of the first NchMOS transistor, the fourth output drive circuit and the fifth output drive circuit Both of the fourth output drive circuit and the fifth output drive circuit in accordance with respective overcurrents of the fourth output drive circuit and the fifth output drive circuit. An overcurrent protection circuit characterized by shutting off both operations of the output drive circuit.

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