JP4887180B2 - Semiconductor device with short-circuit protection function - Google Patents

Description

  The present invention relates to a semiconductor device, and more particularly to a semiconductor device in which reliability is improved by protecting a circuit against a short circuit of an output stage.

Conventionally, for example, as an output circuit for amplifying and outputting a signal such as a video signal, for example, a circuit as shown in FIG. 6 is well known.
Hereinafter, the conventional circuit will be described with reference to FIG. 1. This conventional circuit is a semiconductor device for performing signal amplification and the like, and its output stage performs buffer amplification or power amplification of the signal. The amplifier circuit 2A is configured to have a push-pull operation and output transistors Q1 and Q2 that output signals from the amplifier circuit 2A to the outside.
As an output circuit of a similar semiconductor device, for example, there is one disclosed in Patent Document 1 or the like.
JP 2000-49586 A (page 2-5, FIG. 1 and FIG. 2)

By the way, in such a conventional circuit, when the output terminal which is the connection point between the output transistors Q1 and Q2 is short-circuited to a certain potential such as ground for some reason, a large current continuously flows in the output transistors Q1 and Q2. There is a fear.
However, since the above-described conventional circuit is not provided with a short-circuit protection circuit that can cope with such a case, in the worst case, there is a possibility of destruction of the output transistors Q1 and Q2 and further destruction of the semiconductor device. It was.

  The present invention has been made in view of the above circumstances, and even when a large current flows through the output transistor due to a short circuit of the output end, the state is quickly eliminated, circuit protection is achieved, and normal operation is promptly performed without external control. A highly reliable semiconductor device capable of returning to an operating state is provided.

In order to achieve the object of the present invention, a semiconductor device with a short-circuit protection function according to the present invention is provided so that two output transistors perform a push-pull operation between a power supply and a ground, and the two output transistors are interposed therebetween. In the semiconductor device configured to be able to output a signal from a preceding circuit that operates by receiving a current supply from a current source, a signal level at each control terminal of the two output transistors is not less than a predetermined level. A monitor circuit for detecting, and an oscillation circuit for performing an oscillation operation while the signal level at the control terminal is detected by the monitor circuit to be greater than or equal to a predetermined level, and the current source is an output of the oscillation circuit The ON / OFF operation is configured according to the current, and when a current exceeding a predetermined value flows through the two output transistors, the power And allowed stopping current supply operation of the source is made as a possible stoppage of the operation of the two output transistors.
In such a configuration, the two output transistors are bipolar transistors, and the monitor circuit is configured to be able to detect that the base current has exceeded a predetermined value for each of the two output transistors. Is preferred.
Further, in the above configuration, the two output transistors are MOS transistors, and the monitor circuit can detect that the gate-source voltage has become a predetermined value or more for each of the two output transistors. It is suitable also as what is comprised.

  According to the present invention, when a large current flows through the output transistor, the operation of the current source that supplies current to the circuit in the previous stage can be stopped, so even if a large current starts flowing through the output transistor due to a short circuit or the like, Since the application of the signal from the previous stage circuit to the output transistor is cut off due to the operation stop of the current source, the large current in the output transistor is quickly eliminated, and it is reliably avoided that the circuit is damaged. It is possible to provide a highly reliable semiconductor device that can quickly return to a normal operation state without control.

Embodiments of the present invention will be described below with reference to FIGS. 1 to 5.
The members and arrangements described below do not limit the present invention and can be variously modified within the scope of the gist of the present invention.
First, a configuration example of a semiconductor device with a short circuit protection function in an embodiment of the present invention will be described with reference to FIG.
The semiconductor device 1 with a short-circuit protection function in the embodiment of the present invention is configured such that its output stage performs a push-pull operation with an amplifier circuit 2 that performs buffer amplification and power amplification of a signal. The first and second output transistors (indicated as “Q1” and “Q2” in FIG. 1) 11 and 12 output to the outside, respectively, and a circuit for short circuit protection as will be described later Is configured.

Here, the amplifier circuit 2 uses, for example, an operational amplifier configured to be able to output two differential output signals, and receives a signal (for example, a video signal) from a preceding circuit (not shown) for amplification. It is output.
In the embodiment of the present invention, a pnp transistor is used as the first output transistor 11 and an npn transistor is used as the second output transistor 12. The collector of the first output transistor 11 and the collector of the second output transistor 12 are connected to each other as an output terminal, and are connected to the output terminal 13. On the other hand, the power supply voltage V + is applied to the emitter of the first output transistor 11, while the emitter of the second output transistor 12 is connected to the ground.

  Then, the semiconductor device 1 with a short circuit protection function in the embodiment of the present invention has a current monitor circuit (in FIG. 1, “monitors”) the base current of each of the first and second output transistors 11 and 12. I-MONI ”3, an oscillation circuit (indicated as“ OSC ”in FIG. 1) 4 that operates according to the monitoring result of the current monitor circuit 3, and an output stage according to the output of the oscillation circuit 4 In particular, a current source (indicated as “I-SOURCE” in FIG. 1) 5 for performing a current supply operation to the amplifier circuit 2 is provided.

Next, the operation in this configuration will be described with reference to FIG.
For example, if the output terminal 13 is short-circuited to the ground for some reason and a large current flows through the first and second output transistors 11 and 12, the respective base currents increase accordingly (FIG. 2A). And FIG. 2 (B)).
When the base current of either the first or second output transistor 11 or 12 exceeds a predetermined current (limit current) value, the current monitor circuit 3 outputs a voltage signal at a level corresponding to the logical value High during that time. It is configured to do. Therefore, when the increased base current exceeds the limit value as described above, a voltage signal corresponding to the logical value High is output from the current monitor circuit 3 (FIGS. 2B and 2C). reference).

  Further, the current monitor circuit 3 is configured to hold the signal for an appropriate time when outputting a signal of the logical value High, and even if the base current falls below the limit value, the output of the current monitor circuit 3 is The state does not immediately change to the logical value Low, and the state of the logical value High is maintained (see FIG. 2C).

  The oscillation circuit 4 is configured to output a rectangular wave pulse signal at a predetermined repetition period while the output of the current monitor circuit 3 is a logical value High. That is, the oscillation circuit 4 in the embodiment of the present invention has a switch element (not shown) that can switch its operation between an operation state and a non-operation state by an external signal. When the output of the current monitor circuit 3 becomes a level corresponding to the logical value High, the oscillation circuit 4 is put into an operating state, while when the output of the current monitor circuit 3 becomes a level corresponding to the logical value Low, the oscillation circuit 4 is not operated. It is intended to act as a state.

  Further, similarly to the oscillation circuit 4, the current source 5 is also assumed to have a switching element (not shown) whose operation can be switched between an operating state and a non-operating state by an external signal. Yes. Then, when a signal having a level corresponding to the logical value High is applied from the oscillation circuit 4, the switching element makes the current source 5 inoperative, while a signal having a level corresponding to the logical value Low is output from the oscillation circuit 4. When applied, it acts to bring the current source 5 into an operating state.

Therefore, when the base current of either the first or second output transistor 11 or 12 exceeds the limit value, the output of the current monitor circuit 3 becomes a logical value High, and the oscillation circuit 4 outputs a pulse signal, thereby The current supply operation of the current source 5 is stopped. As a result, a large current does not flow through the first and second output transistors 11 and 12, and a base current also does not flow (see FIGS. 2B to 2E).
When the output of the oscillation circuit 4 becomes the logic value Low, the current supply operation by the current source 5 is resumed, so that a large current flows through the first and second output transistors 11 and 12, and the base current is limited again. When the value is exceeded, the output of the current monitor circuit 3 that has been gradually decreased until then becomes the logical value High again, so that the above-described operation is repeated (see FIGS. 2B to 2E). ).

  Such an operation is continued until the short-circuit state of the output terminal 13 is resolved. That is, since the short-circuit state of the output terminal 13 is eliminated and the base currents of the first and second output transistors 11 and 12 become normal values, the output of the current monitor circuit 3 becomes the logical value Low. 4 is stopped, the current supply operation by the power source 5 is continued, and the semiconductor device 1 returns to the normal operation state.

Next, a first specific circuit example of the current monitor circuit 3 will be described with reference to FIG. The same components as those shown in FIG. 1 are denoted by the same reference numerals, detailed description thereof will be omitted, and different points will be mainly described below.
This configuration example is suitable when the first and second output transistors 11 and 12 are bipolar transistors. In FIG. 3, a pnp type first transistor is used from the viewpoint of simplifying the drawing and facilitating understanding. A portion for monitoring the base current of one output transistor 11 is shown, and a circuit portion for monitoring the base current of the second output transistor 12 having basically the same configuration is not shown. Yes.

  A current monitor circuit 3 shown in FIG. 3 includes a pnp-type third transistor (denoted as “Q3” in FIG. 3) having an emitter connected to the base (control terminal) of the first output transistor 11. Two current mirror circuits 31, 32, an npn-type fourth transistor 14 through which a current from the second current mirror circuit 32 flows, and a constant current source (indicated as "IA" in FIG. 3) 33 Is the main component.

First, the constant current source 33 is connected to the emitter of the third transistor 13 and the base of the first output transistor 11 is connected, while the collector is an npn that constitutes the first current mirror circuit 31. It is connected to the collector of the sixth transistor 6 of the type. The constant current source 33 is applied with a power supply voltage V + and outputs a constant current I1.
The base of the third transistor 13 is connected to a driver circuit 34 that amplifies a signal from a preceding circuit (not shown) that amplifies the input signal.

The sixth transistor 16 has its collector and base connected to the base of the npn-type seventh transistor 17 and each emitter connected to the ground to constitute the first current mirror circuit 31. It has become.
The collector of the seventh transistor 17 is connected to the collector of the pnp-type eighth transistor 18 constituting the second current mirror circuit 32.

The collector and base of the eighth transistor 18 are connected to the base of the pnP-type ninth transistor 19, while the power supply voltage V + is applied to each emitter. The current mirror circuit 32 is configured.
The collector of the ninth transistor 19 is connected to the collector of the npn-type fourth transistor 14 via the first resistor 35 (denoted as “R1” in FIG. 3). .

The fourth transistor 14 has an emitter connected to the ground, and a base connected to the collector of the npn-type tenth transistor 20.
A first capacitor (indicated as “C1” in FIG. 3) 36 is connected between the collector of the ninth transistor 19 and the connection point of the first resistor 35 and the ground. .

  Between the current monitor circuit 3 configured as described above, the oscillation circuit 4 and the current source 5, the output of the current monitor circuit 3 is supplied to the oscillation circuit 4, and power is supplied by the current source 5 according to the output of the oscillation circuit 4. Are connected to the fifth transistor (indicated as “Q5” in FIG. 3) 15 and the tenth to thirteenth transistors (in FIG. 3, “Q10”, “Q11”, “Q12”, respectively). ”And“ Q13 ”) 20 to 23 as main components.

  That is, the power supply voltage V + is applied to the collector of the tenth transistor 20 via a second resistor (indicated as “R2” in FIG. 3) 42, while the emitter is connected to the ground. Has been. The base of the tenth transistor 20 is connected to the output stage of the oscillation circuit 4 and to the current source 5. Here, the connection location of the current source 5 to which the output stage of the oscillation circuit 4 is connected is suitable for intermittent current supply operation according to the output signal of the oscillation circuit 4 as described in the operation of FIG. (Switching element not shown).

On the other hand, the npn-type fifth transistor 15 has a base connected to the connection point of the ninth transistor 19 of the current monitor circuit 3 and the first resistor 35, while the collector has a third resistor 15. A power supply voltage V + is applied via a device 43 (denoted as “R3” in FIG. 3), and the base of an npn-type eleventh transistor 21 is connected.
The eleventh transistor 21 has an emitter connected to the ground, and a collector to which the power supply voltage V + is applied via a fourth resistor (indicated as “R4” in FIG. 3) 44 and npn The base of the twelfth transistor 22 of the type and a predetermined location where the operation of the oscillation circuit 4 can be controlled are connected.
Here, the predetermined portion where the operation of the oscillation circuit 4 can be controlled is not shown in FIG. 1 provided so as to be able to control the operation of the oscillation circuit 4 in accordance with a signal from the outside. It is a switch element.

  The power supply voltage V + is applied to the collector of the twelfth transistor 22 via a fifth resistor 45 (denoted as “R5” in FIG. 3) 45, and the thirteenth npn-type transistor is also applied. While connected to the base of the transistor 23, the emitter is connected to the ground.

  The power supply voltage V + is applied to the collector of the thirteenth transistor 23 via a sixth resistor 46 (denoted as “R6” in FIG. 3) 46 and connected to the current source 5. ing. The connection point to the current source 5 is the same as the point where the output terminal of the oscillation circuit 4 described above is connected. The emitter of the thirteenth transistor 23 is connected to the ground.

Next, the operation in the above configuration will be described.
The base current ib 1 of the first output transistor 11 flows into the emitter of the third transistor 13 in the current monitor circuit 3. Since the constant current source 33 is connected to the collector of the third transistor 13, the constant current I1 supplied from the constant current source 33 and the first output are connected to the emitter of the third transistor 13. The sum (I1 + ib1) of the base current ib1 of the transistor 11 flows, and almost the same current flows to the collector of the third transistor 13.

Then, the collector current (I1 + ib1) of the third transistor 13 is mirrored by the first current mirror circuit 31 to the second current mirror circuit 32 and flows into the collector of the fourth transistor 14.
As a result, the output voltage VA of the current monitor circuit 3, which is the voltage at the connection point between the collector of the ninth transistor 19 and the first resistor 35, is VA = R1 × (I1 + ib1) + Vce4. Here, R 1 is the resistance value of the first resistor 35, and Vce 4 is the collector-emitter voltage of the fourth transistor 14.

Since the output voltage VA is applied to the base of the fifth transistor 15, the base current ib <b> 1 of the first output transistor 11 is increased, and the output voltage VA is equal to that of the fifth transistor 15. When the base-emitter voltage Vbe5 is exceeded, the voltage is held in the first capacitor 36, and the fifth transistor 15 is turned on.
As the fifth transistor 15 is turned on, the eleventh transistor 21 is turned off, and the switch element in the oscillation circuit 4 that controls the operation of the oscillation circuit 4 described above has a level corresponding to the logical value High. And the voltage is applied to the base of the twelfth transistor 22.

Therefore, the oscillation circuit 4 is in an operating state.
In addition, the twelfth transistor 22 becomes conductive, whereby the thirteenth transistor 23 becomes nonconductive, and the collector potential thereof is substantially the power supply voltage V +.

As a result, a predetermined repetitive pulse signal is applied to the current source 5 from the oscillation circuit 4 as described above.
In this state, the current source 5 stops operating while the pulse signal is output from the oscillation circuit 4, while the output of the pulse signal stops, and the output of the oscillation circuit 4 has a level corresponding to the logic value Low. Then, a current supply operation is performed (see FIGS. 2C to 2E).

When a large current does not flow through the first and second output transistors 11 and 12 and the respective base currents become normal, the output voltage VA of the current monitor circuit 3 is the base-emitter of the fifth transistor 15. The level exceeding the inter-voltage Vbe5 is not reached, and the output of the current monitor circuit 3 is in a state corresponding to the logic value Low (see FIG. 2C).
Therefore, while the fifth transistor 15 is turned off, the eleventh transistor 21 is turned on, and a voltage of a level corresponding to the logical value Low is applied to the oscillation circuit 4. The oscillation operation is stopped.

  Further, since the eleventh transistor 21 is turned on, the twelfth transistor 22 is turned off, and the thirteenth transistor 23 is turned on. Therefore, the eleventh transistor 21 is provided in the current source 5 described above. Since a voltage of a level corresponding to the logical value Low is applied to a switch element (not shown) for operation control, the current source 5 returns to a normal current supply operation (FIG. 2 ( C) to FIG. 2 (E)).

Next, a configuration example in the case of using a MOS transistor will be described with reference to FIG. The same components as those shown in FIG. 1 are denoted by the same reference numerals, detailed description thereof is omitted, and different points will be mainly described below.
In this configuration example, the first and second output transistors (represented as “M1” and “M2” in FIG. 4) 11A and 12A are MOS transistors, respectively. Except for the point that the voltage monitor circuit 6 (indicated as “V-MONI” in FIG. 4) 6 is provided, it has basically the same configuration as the configuration example shown in FIG.
In the embodiment of the present invention, the first output transistor 11A is an N-channel MOS transistor, and the second output transistor 12A is a P-channel MOS transistor.

Next, a preferred specific circuit example of the voltage monitor circuit 6 suitable for the first and second output transistors 11A and 12A using MOS transistors will be described with reference to FIG. The same constituent elements as those shown in FIG. 3 or FIG. 4 are denoted by the same reference numerals, detailed description thereof will be omitted, and different points will be mainly described below.
FIG. 5 shows a portion for monitoring the voltage between the gate and source of the first output transistor 11A from the viewpoint of simplifying the drawing and facilitating understanding, and basically has the same configuration. The circuit portion for monitoring the gate current of the second output transistor 12A is not shown.

First, the power supply voltage V + is applied to the source of the first output transistor 11A, while the drain is connected to the drain of the second output transistor 12A, and the second output transistor 12A. The source of is connected to ground.
The gate (control terminal) of the first output transistor 11A is applied with a signal to be output to the outside through the first output transistor 11A from a subsequent circuit (not shown). Thus, connection to the voltage monitor circuit 6 is made.

That is, a constant current source 33, an N-channel third MOS transistor (indicated as “M3” in FIG. 5) 13A, and a second constant current source 51 between a power source and a ground (not shown) from the power source side. Are connected in series, and the gate of the first output transistor 11A is connected to the connection point between the constant current source 33 and the third MOS transistor 13A.
The gate (control terminal) of the second output transistor 12A is connected to the connection point between the third MOS transistor 13A and the second constant current source 51.

  The third MOS transistor 13A includes a P-channel fourth MOS transistor (indicated as “M4” in FIG. 5) 24 and an N-channel sixth MOS transistor (in FIG. 5, “M6”). 26) are connected in parallel.

The gate of the fourth MOS transistor 24 is connected to the gate of a fifth MOS transistor (indicated as “M5” in FIG. 5) 25 provided in the voltage monitor circuit 6 described later.
The gate of the sixth MOS transistor 26 is connected to the gate of the third MOS transistor 13A, and a predetermined reference voltage is applied. Here, the predetermined reference voltage is a voltage that is selected so that a so-called idling current when the first and second output transistors 11 and 12 are not in a signal has a predetermined magnitude.

On the other hand, the voltage monitor circuit 6 is configured around a current mirror circuit 32A composed of the eighth and ninth transistors 18 and 19.
That is, the eighth and ninth transistors 18 and 19 have the collector and base of the eighth transistor 18 connected to the drain of the P-channel fifth MOS transistor 25, and the source of the fifth MOS transistor 25. Is connected to the connection point between the third MOS transistor 13A and the second constant current source 51 described above.
A predetermined reference voltage similar to that of the sixth MOS transistor 26 is applied to the gate of the fifth MOS transistor 25.

  On the other hand, the first resistor 35, the fourth transistor 14, and the first capacitor 36 are provided on the collector side of the ninth transistor 19, similarly to the current monitor circuit 3 described with reference to FIG. Yes. Since the connection is the same as that described with reference to FIG. 3, the description thereof is omitted here.

Next, the operation in such a configuration will be described. First, for example, when the output terminal 13 is short-circuited to the ground for some reason and a large current flows through the first output transistor 11A, the gate-source voltage Vth1 is While increasing, the gate-source voltage Vth2 of the second output transistor 12A decreases.
Along with this, the current flowing through the third MOS transistor 13A decreases, and the current I1 of the constant current source 33 flowing into the third MOS transistor 13A gradually flows into the fourth MOS transistor 24. The current of the fourth MOS transistor 24 gradually approaches the current I1.

Since the current of the fourth MOS transistor 24 is mirrored to the fifth MOS transistor 25 of the voltage monitor circuit 6, the current IB of the fifth MOS transistor 25 is gradually changed to the current I1 as well. It will be asymptotic.
Then, the current IB of the fifth MOS transistor 25 is mirrored to the collector of the ninth transistor 19 by the ninth and eighth transistors 18 and 19 and flows.

As a result, the output voltage VA of the voltage monitor circuit 6 exceeds the base-emitter voltage Vbe5 of the fifth transistor 15 in the same way as described in the current monitor circuit 3 of FIG. It will be conducted.
As a result, as described in the configuration example in FIG. The current supply operation of the current source 5 is controlled. Note that the details of the operation are basically the same as those described above with reference to FIGS. 1 to 3, and thus detailed description thereof is omitted here.

It is a block diagram which shows the 1st structural example of the semiconductor device with a short circuit protection function in embodiment of this invention. FIG. 2A is a waveform diagram of a main part for explaining the operation of the semiconductor device with a short-circuit protection function in the embodiment of the present invention, and FIG. 2A is a waveform diagram showing changes in the output of the semiconductor device, and FIG. FIG. 2C is a waveform diagram showing changes in the base current of the first and second output transistors, FIG. 2C is a waveform diagram showing changes in the output of the current monitor circuit, and FIG. 2D is an output of the oscillation circuit. FIG. 2E is a waveform diagram showing changes in the output of the current source. It is a circuit diagram which shows the specific circuit example of the current monitor circuit provided in the semiconductor device with a short circuit protection function in embodiment of this invention. It is a block diagram which shows the 2nd structural example of the semiconductor device with a short circuit protection function in embodiment of this invention. FIG. 6 is a circuit diagram showing a specific circuit example of a voltage monitor circuit in the second configuration example shown in FIG. 5. It is a circuit diagram which shows the example of a circuit of the output stage of the conventional semiconductor device.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Semiconductor device 2 ... Amplifier circuit 3 ... Current monitor circuit 4 ... Oscillator circuit 5 ... Current source 6 ... Voltage monitor circuit

Claims (3)

Two output transistors are provided between the power supply and the ground so as to perform a push-pull operation, and a signal from a previous circuit that operates by receiving a current supply from a current source can be output via the two output transistors. In the configured semiconductor device,
A monitor circuit for detecting that a signal level at each control terminal of the two output transistors is equal to or higher than a predetermined value;
An oscillation circuit that performs an oscillation operation while the monitor circuit detects that the signal level at the control terminal is equal to or higher than a predetermined level,
The current source is configured to be capable of ON / OFF operation according to the output of the oscillation circuit,
A semiconductor device with a short-circuit protection function, wherein when a current of a predetermined value or more flows through the two output transistors, the current supply operation of the current source is stopped so that the operation of the two output transistors can be stopped. . The two output transistors are bipolar transistors,
2. The semiconductor device with a short circuit protection function according to claim 1, wherein the monitor circuit is configured to be able to detect that the base current has become a predetermined value or more for each of the two output transistors. The two output transistors are MOS transistors,
2. The semiconductor with a short circuit protection function according to claim 1, wherein the monitor circuit is configured to be able to detect that a gate-source voltage is a predetermined value or more for each of the two output transistors. apparatus.

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