JP2007158084A - Ld driver circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To surely turn a current outputted, when LED drive is off, to be 100 μA or lower. <P>SOLUTION: A first transistor for interruption is serially connected to a differential circuit and to a constant-current source transistor, the first transistor for the interruption is interrupted, when the LD drive is off, and an operating current supplied from the constant-current source transistor is interrupted. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to an LD driver circuit that differentially drives a laser diode (hereinafter referred to as LD).

  A conventional LD driver circuit is shown in FIG. 3 (see, for example, Non-Patent Document 1). This LD driver includes npn transistors Q1 and Q2 constituting a differential circuit, an npn transistor Q3 as a constant current source, load resistors RLP and RLN, a constant current source stabilization resistor RSS, switching differential input terminals ISP and ISN, a difference It has dynamic output terminals OSP and OSN, a high potential power supply terminal VCC, a low potential power supply terminal VEE, and a constant current source control terminal VCS.

  The input terminal ISN is connected to the base of the transistor Q1, the input terminal ISP is connected to the base of the transistor Q2, the output terminal OSP is connected to the common connection point of the collector of the transistor Q1 and the load resistor RLP, and the output terminal The OSN is connected to the common connection point of the collector of the transistor Q2 and the load resistor RLN, the other end of the load resistors RLP and RLN is connected to the high potential power supply terminal VCC, and the emitters of the transistors Q1 and Q2 are commonly connected to the collector of the transistor Q3. The constant current source control terminal VCS is connected to the base of the transistor Q3, and the emitter of the transistor Q3 is connected to the low potential power supply terminal VEE via the current source stabilization resistor RSS.

When this LD driver circuit is used by inputting a burst signal to the differential input terminals ISP and ISN, it is necessary to reduce the current flowing through the output terminal OSP or OSN to 100 μA or less when the LD driving is off to realize a good off characteristic. is there.
S.Morley, "Conventional Laser Diode Driver (LDD)", ISSCC 2005 VISUALS SUPPLEMENT, p.170

  However, it was confirmed by simulation that this condition cannot be satisfied depending on the characteristics of the LD device. Therefore, it has been required to ensure that the current is 100 μA or less when the LD drive is off.

  An object of the present invention is to provide an LD driver circuit capable of reliably reducing the output current when the LD drive is off to 100 μA or less.

In order to achieve the above object, an invention according to claim 1 includes a differential circuit composed of first and second transistors, a pair of load resistors connected to an output side of the differential circuit, and the differential circuit. An output current based on a differential voltage generated in the pair of load resistors by a differential LD drive signal input to the first and second transistors. In the LD driver circuit, a first cutoff transistor is connected in series with the differential circuit and the constant current source transistor, and the output current is cut off by blocking the first cutoff transistor. And
According to a second aspect of the present invention, there is provided a differential circuit comprising the first and second transistors, a pair of load resistors connected to the output side of the differential circuit, and a constant current for supplying an operating current to the differential circuit. In the LD driver circuit comprising a current source transistor and supplying an output current to the LD based on a differential voltage generated in the pair of load resistors by a differential LD drive signal input to the first and second transistors. A second blocking transistor is connected between the base or gate of the current source transistor and the power supply terminal, and a third blocking transistor is connected between the base or gate of the constant current source transistor and the constant current source control terminal; Shutting off the constant current source transistor by turning on the second blocking transistor and blocking the third blocking transistor; Wherein thereby cut off the serial output current.

  According to the LD driver circuit of the present invention, when the LD drive is turned off, the operating current supplied by the constant current source transistor is cut off, so that the LD driver output current can be reliably reduced to 100 μA or less, Good off characteristics can be realized, which is suitable when a burst signal is used as a differential input signal.

  FIG. 1 is a circuit diagram showing a configuration of an LD driver circuit according to a first embodiment of the present invention. This LD driver includes npn transistors Q1 and Q2 constituting a differential circuit, an npn transistor Q3 as a constant current source, an NMOS transistor MN1 (first cutoff transistor) as a cutoff, load resistors RLP and RLN, a constant current It has a source stabilization resistor RSS, switching differential input terminals ISP and ISN, differential output terminals OSP and OSN, a high potential power supply terminal VCC, a low potential power supply terminal VEE, a constant current source control terminal VCS, and a gate terminal ISH.

  The input terminal ISN is connected to the base of the transistor Q1, the input terminal ISP is connected to the base of the transistor Q2, the output terminal OSP is connected to the common connection point of the collector of the transistor Q1 and the load resistor RLP, and the output terminal OSN is connected to the common connection point of the collector of the transistor Q2 and the load resistor RLN, and the other ends of the load resistors RLP and RLN are connected to the high potential power supply terminal VCC. The emitters of the transistors Q1 and Q2 are commonly connected to the drain of the transistor MN1, the source of the transistor MN1 is connected to the collector of the transistor Q3, the gate of the transistor MN1 is connected to the gate terminal ISH, and the constant current source control terminal VCS is Connected to the base of the transistor Q3, the emitter of the transistor Q3 is connected to the low potential power supply terminal VEE via the constant current source stabilization resistor RSS.

  When a low level which is the same voltage as the low potential power supply terminal VEE is input to the gate terminal ISH of the transistor MN1, the constant current source transistor MN1 is completely turned off, so that no current flows therethrough. As a result, the LD driver The circuit output current stops flowing. That is, the current output when the LD drive is off is reliably 100 μA or less.

  The transistor MN1 may be connected between the low current source transistor Q3 and the resistor RSS, or between the resistor RSS and the low potential power supply terminal VEE.

  FIG. 2 is a circuit diagram showing a configuration of an LD driver circuit according to a second embodiment of the present invention. This LD driver includes npn transistors Q1 and Q2 constituting a differential circuit, an npn transistor Q3 as a constant current source, NMOS transistors MN2 and MN3 (second and third cutoff transistors) as cutoffs, and a load resistance RLP. , RLN, constant current source stabilization resistor RSS, switching differential input terminals ISP, ISN, differential output terminals OSP, OSN, high potential power supply terminal VCC, low potential power supply terminal VEE, constant current source control terminal VCS, gate terminal Has ISHP and ISHN.

  The input terminal ISN is connected to the base of the transistor Q1, the input terminal ISP is connected to the base of the transistor Q2, the output terminal OSP is connected to the common connection point of the collector of the transistor Q1 and the load resistor RLP, and the output terminal OSN is connected to the common connection point of the collector of the transistor Q2 and the load resistor RLN, and the other ends of the load resistors RLP and RLN are connected to the high potential power supply terminal VCC. The emitters of the transistors Q1 and Q2 are commonly connected to the collector of the transistor Q3, and the emitter of the transistor Q3 is connected to the low potential power supply terminal VEE via the constant current source stabilization resistor RSS. The base of the transistor Q3 is connected to the drain of the transistor MN2 and the source of the MN3, the source of the transistor MN2 is connected to the power supply terminal VEE, the gate is connected to the gate terminal ISHN, and the drain of the transistor MN3 is controlled by a constant current source. The gate is connected to the terminal VCS and the gate is connected to the gate terminal ISHP.

  When a low level which is the same voltage as the low potential power supply terminal VEE is input to the gate terminal ISHP and an appropriate high level (for example, 2.5 V or 3.3 V) is input to the gate terminal ISHN, the transistor MN2 is turned on. Since MN3 is turned off, the transistor Q3 is turned off with the base potential VEE, and no current flows through the transistor Q3, which is a constant current source. As a result, the output current of the LD driver circuit does not flow. That is, the current output when the LD drive is off is reliably 100 μA or less.

  In each of the embodiments described above, the transistors Q1, Q2, and Q3 have been described as nail transistors of a bipolar, but the same effect can be obtained with an NMOS transistor. Further, the same effect can be obtained by forming the transistors Q1, Q2, Q3, MN, MN2, and MN3 with compound semiconductor transistors.

1 is a circuit diagram of an LD driver circuit according to a first embodiment of the present invention. It is a circuit diagram of the LD driver circuit of the 2nd Example of this invention. It is a circuit diagram of the LD driver circuit of the conventional Example.

Explanation of symbols

Q1, Q2, Q3: Bipolar transistors MN1, MN2, MN3: NMOS transistors RLP, RLN: Load resistance RSS: Constant current source stabilization resistance ISN, ISP: Switching differential input terminal OSN, OSP: Differential output terminal ISH, ISHP , ISHN: gate terminal VCS: constant current source control terminal VCC: high potential power supply terminal VEE: low potential power supply terminal

Claims (2)

A differential circuit composed of first and second transistors, a pair of load resistors connected to the output side of the differential circuit, and a constant current source transistor for supplying an operating current to the differential circuit, In an LD driver circuit for supplying an output current to the LD based on a differential voltage generated in the pair of load resistors by a differential LD drive signal input to the first and second transistors,
An LD driver circuit, wherein a first cutoff transistor is connected in series to the differential circuit and the constant current source transistor, and the output current is cut off by blocking the first cutoff transistor. A differential circuit composed of first and second transistors, a pair of load resistors connected to the output side of the differential circuit, and a constant current source transistor for supplying an operating current to the differential circuit, In an LD driver circuit for supplying an output current to the LD based on a differential voltage generated in the pair of load resistors by a differential LD drive signal input to the first and second transistors,
A second cutoff transistor is connected between the base or gate of the constant current source transistor and the power supply terminal, and a third cutoff transistor is connected between the base or gate of the constant current source transistor and the constant current source control terminal. An LD driver circuit, wherein the constant current source transistor is cut off and the output current is cut off by turning on the second cut-off transistor and turning off the third cut-off transistor.

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