JP4807117B2 - Multiplexer circuit - Google Patents

Description

  The present invention relates to a multiplexer circuit that selects and outputs one input signal among a plurality of input signals, and more particularly to a multiplexer circuit that can reduce a power supply voltage necessary for operation.

  Prior art documents related to conventional multiplexer circuits include the following.

Japanese Unexamined Patent Publication No. 64-049313 JP 2000-236244 A JP 2002-152022 A JP 2004-241797 A

  FIG. 3 is a circuit diagram showing an example of a conventional multiplexer circuit. In FIG. 3, 1, 2, 10, 15 and 16 are resistors, 3, 4, 5, 6, 7, 8, 9, 11, 12, 13 and 14 are transistors, 100 and 101, and 102 and 103 are respectively Differential input signals, 104 and 105 are differential selection signals, 106 is a bias voltage signal, and 107 and 108 are differential output signals.

  The input signal 101 is an inverted signal of the input signal 100, the input signal 103 is an inverted signal of the input signal 102, the selection signal 105 is an inverted signal of the selection signal 104, and the output signal 108 is an inverted signal of the output signal 107.

  Input signals 100 and 101 are applied to the bases of transistors 3 and 4, respectively, and input signals 102 and 103 are applied to the bases of transistors 5 and 6, respectively. The selection signals 104 and 105 are applied to the bases of the transistors 7 and 8, respectively.

  The collector of the transistor 3 is connected to one end of the resistor 1, the collector of the transistor 5 and the base of the transistor 12, respectively. The collector of the transistor 4 is connected to one end of the resistor 2, the collector of the transistor 6 and the base of the transistor 11.

  The emitter of transistor 3 is connected to the emitter of transistor 4 and the collector of transistor 7, and the emitter of transistor 5 is connected to the emitter of transistor 6 and the collector of transistor 8.

  The emitter of the transistor 7 is connected to the emitter of the transistor 8 and the collector of the transistor 9, and the emitter of the transistor 9 is connected to one end of the resistor 10.

  On the other hand, the output signal 107 is output from the emitter of the transistor 11, the emitter of the transistor 11 is connected to the collector of the transistor 13, and the emitter of the transistor 13 is connected to one end of the resistor 15.

  The output signal 108 is output from the emitter of the transistor 12, the emitter of the transistor 12 is connected to the collector of the transistor 14, and the emitter of the transistor 14 is connected to one end of the resistor 16.

  Finally, the bias voltage signal 106 is applied to the bases of the transistors 9, 13 and 14 and the positive voltage source “VCC” is applied to the other ends of the resistors 1 and 2 and to the collectors of the transistors 11 and 12, respectively. VEE "is applied to the other ends of the resistors 10, 15 and 16, respectively.

  Here, the operation of the conventional example shown in FIG. 3 will be described. The transistor 9 and the resistor 10 operate as a constant current source that outputs a current uniquely determined by the bias voltage applied to the base of the transistor 9 and the resistance value of the resistor 10.

That is, when the bias voltage is “Vbias”, the base-emitter voltage of the transistor 9 is “Vbe9”, and the resistance value of the resistor 10 is “R10”, the constant current “I1” is
I1 = (Vbias−Vbe9−VEE) / R10 (1)
It becomes.

  On the other hand, since the transistors 7 and 8 constitute a differential circuit, they operate so as to switch the above-described constant current “I1” according to the signal levels of the differential selection signals 104 and 105 inputted.

  If the selection signal 104 is at a high level and the selection signal 105 is at a low level, the constant current “I1” is supplied to the differential circuit side constituted by the transistors 3 and 4.

  Here, when the input signal 100 is at a high level and the input signal 102 is at a low level, the transistor 3 is “ON” and the transistor 4 is “OFF”.

  Therefore, if the resistance value of the resistor 1 is “R1”, the voltage of the collector of the transistor 3 becomes “VCC−R1 · I1” due to the current “I1” flowing through the resistor 1.

Since this voltage is output as an output signal 108 (inverted signal) through an emitter follower circuit composed of transistors 12 and 14 and a resistor 16, the voltage value is "V108" and the base-emitter voltage of the transistor 12 is If it is “Vbe12”,
V108 = VCC-R1 · I1-Vbe12 (2)
It becomes. Further, the voltage value of the expression (2) is at a low level.

  On the other hand, the voltage at the collector of the transistor 4 remains “VCC” because no current flows through the resistor 2.

Since this voltage is output as an output signal 107 (non-inverted signal) through an emitter follower circuit composed of transistors 11 and 13 and a resistor 15, the voltage value is “V107”, and the base-emitter voltage of the transistor 11. Is "Vbe11",
V107 = VCC-Vbe11 (3)
It becomes. Further, the voltage value of the expression (3) becomes a high level.

  That is, if the selection signal 104 is at a high level and the selection signal 105 is at a low level, the signal level (high level) of the differential input signal 100 is output as the differential output signal 107, and the differential input signal The signal level (low level) 101 is output as the differential output signal 108.

  Similarly, if the selection signal 104 is at a low level and the selection signal 105 is at a high level, the signal level of the differential input signal 102 is output as the differential output signal 107 and the signal of the differential input signal 103 is output. The level is output as a differential output signal 108.

  As a result, by switching and supplying a constant current based on the selection signals 104 and 105 to two differential circuits to which two differential input signals are applied, one input signal among a plurality of input signals is supplied. Can be selected and output.

However, in the conventional example as shown in FIG. 3, the input signal has a signal level as shown in Equation (2) and Equation (3) and does not saturate all the transistors, in other words, between the base and collector of all the transistors. In order for the voltage to be positive, if the input signal voltage is “Vin” and the base-emitter voltages of the transistors 3 and 7 are “Vbe3” and “Vbe7”,
Vin-Vbe3-Vbe7-Vbe9-R10 · I1> VEE (4)
There is a need to be.

If the input signal voltage “Vin” is high level and the base-emitter voltage of each transistor is equal to “Vbe”,
VCC-Vbe-Vbe-Vbe-Vbe-R10 · I1> VEE
VCC-VEE> 4 · Vbe + R10 · I1 (5)
Thus, when “Vbe = 0.8 V”, there is a problem that a power supply voltage of “3.2 V” or more is required at least.
Therefore, the problem to be solved by the present invention is to realize a multiplexer circuit capable of reducing the power supply voltage required for operation.

In order to achieve such a problem, the invention according to claim 1 of the present invention is:
In a multiplexer circuit that selects and outputs one input signal among a plurality of input signals,
A differential circuit that receives a differential input signal and outputs a differential output voltage, first and second load resistors having one end connected to the differential output of the differential circuit, and the first and second A common mode resistor connected in common to the other end of the load resistor, and when the common mode current flows through the common mode resistor, the common mode current is higher than the low level output voltage. The first and second buffer circuits to which the first and second differential input signals are applied, the output voltage of which is reduced , and the common mode resistor in the first buffer circuit by the differential selection signal control a first common mode control circuit for controlling whether or not to pass the common mode currents, whether or not to pass the common mode current to the common mode resistor in said second buffer circuit by the differential selection signal A second common mode control circuit and an output for outputting, as a differential output signal, an output voltage of the buffer circuit having a larger output voltage out of the output voltage of the first buffer circuit or the output voltage of the second buffer circuit By providing the stage circuit, the number of vertically stacked transistors can be reduced by one, so that the power supply voltage necessary for the operation can be lowered.

The invention according to claim 2
In a multiplexer circuit that selects and outputs one input signal among a plurality of input signals,
A differential circuit that receives a differential input signal and outputs a differential output; first and second load resistors having one end connected to the differential output of the differential circuit; and the first and second It is composed of a common mode resistor connected in common to the other end of the load resistor, and when the common mode current flows through the common mode resistor, the output is higher than the low level output voltage when the common mode current does not flow A plurality of buffer circuits to which a plurality of differential input signals are respectively applied with a reduced voltage, and whether or not the common mode current is allowed to flow through the common mode resistors in the plurality of buffer circuits are controlled by the differential selection signal. The same number of common mode control circuits as the buffer circuit, and an output stage that outputs the output voltage of the buffer circuit having a large output voltage among the output voltages of the plurality of buffer circuits as a differential output signal By providing a road, vertically stacked stages of the transistors it is possible to lower the power supply voltage required for the operation because it reduces one stage.

The invention described in claim 3
In a multiplexer circuit that selects and outputs one input signal among a plurality of input signals,
A differential circuit that receives a differential input signal and outputs a differential output; first and second load resistors having one end connected to the differential output of the differential circuit; and the first and second It is composed of a common mode resistor connected in common to the other end of the load resistor, and when the common mode current flows through the common mode resistor, the output is higher than the low level output voltage when the common mode current does not flow The first and second buffer circuits to which the first and second differential input signals are applied, the voltage of which decreases , and the common mode resistor or the first buffer circuit in the first buffer circuit by the differential selection signal a common mode control circuit of the control to pass the common mode current to one of the common mode resistance in the second buffer circuit, the output voltage or the second back of the first buffer circuit Since the output stage circuit for outputting the output voltage of the buffer circuit having a large output voltage as the differential output signal among the output voltages of the transistor circuit is provided, the number of vertically stacked transistors can be reduced by one stage, which is necessary for the operation. The power supply voltage can be lowered.

The invention according to claim 4
In the multiplexer circuit according to claim 1 or claim 2,
The common mode control circuit is
Since the differential circuit is configured to control whether the common mode current flows through the common mode resistor in the buffer circuit by the differential selection signal, the number of vertically stacked transistors can be reduced by one. The required power supply voltage can be lowered.

The invention according to claim 5
In the multiplexer circuit according to claim 3,
The common mode control circuit is
The differential selection signal includes a differential circuit that controls the common mode current to flow through either the first buffer circuit or the common mode resistor in the second buffer circuit . Since the number of vertically stacked stages can be reduced by 1, the power supply voltage necessary for the operation can be lowered.

The invention described in claim 6
In the multiplexer circuit according to any one of claims 1 to 5,
The transistors constituting each circuit are
By using NPN transistors, N-type MOS transistors, or a mixture of NPN transistors and N-type MOS transistors, the number of vertically stacked transistors can be reduced by one, so the power supply voltage required for operation can be lowered. become.

The invention described in claim 7
In the multiplexer circuit according to any one of claims 1 to 5,
The transistors constituting each circuit are
Since PNP transistors, P-type MOS transistors, or a mixture of PNP transistors and P-type MOS transistors can reduce the number of vertically stacked transistors, the power supply voltage required for operation can be lowered. become.

The present invention has the following effects.
According to the inventions of claims 1, 2, 3, 4, 5, 6, and 7 , the common mode control circuit controls the common mode current flowing in the buffer circuit by the selection signal, and the common mode current does not flow. By outputting the output of the buffer circuit as an output signal, the number of vertically stacked transistors can be reduced by one, so that the power supply voltage necessary for the operation can be lowered.

  Hereinafter, the present invention will be described in detail with reference to the drawings. FIG. 1 is a circuit diagram showing an embodiment of a multiplexer circuit according to the present invention.

  In FIG. 1, 17, 18, 19, 23, 27, 28, 29, 30, 34, 38, 42 and 46 are resistors, 20, 21, 22, 24, 25, 26, 31, 32, 33, 35, 36, 37, 39, 40, 41, 43, 44 and 45 are transistors, 109 and 110, and 111 and 112 are differential input signals, respectively 113 and 114, and 115 and 116 are differential selections, respectively. Signal 117 is a bias voltage signal, and 118 and 119 are differential output signals.

  17, 18, 19, 20, 21, 22, and 23 are the buffer circuit 80, 24, 25, 26, and 27 are the common mode control circuit 81, and 28, 29, 30, 31, 32, 33, and 34 are The buffer circuit 82, 35, 36, 37 and 38 constitute a common mode control circuit 83, and 39, 40, 41, 42, 43, 44, 45 and 46 constitute an output stage circuit 84, respectively.

  The buffer circuit 80 includes a differential circuit composed of 20, 21, 22, and 23, a load resistance composed of 18 and 19, and a common mode resistance composed of 17. Similarly, the buffer circuit 82 includes a differential circuit composed of 31, 32, 33 and 34, a load resistance composed of 29 and 30, and a common mode resistance composed of 28.

  The common mode control circuit 81 is composed of a differential circuit composed of 24, 25, 26 and 27, and the common mode control circuit 83 is composed of a differential circuit composed of 35, 36, 37 and 38.

  Further, the input signal 110 is an inverted signal of the input signal 109, the input signal 112 is an inverted signal of the input signal 111, the selection signal 114 is an inverted signal of the selection signal 113, the selection signal 116 is an inverted signal of the selection signal 115, and the output signal 119 is This is an inverted signal of the output signal 118.

  As a combination of signal levels that the selection signal 113 and the selection signal 115 can take, the selection signal 113 is at a high level and the selection signal 115 is at a low level, or the selection signal 113 is at a low level and the selection signal 115 is at a high level. Only other combinations are not considered.

  Input signals 109 and 110 are applied to the bases of transistors 20 and 21, respectively, and input signals 111 and 112 are applied to the bases of transistors 31 and 32, respectively.

  The selection signals 113 and 114 are applied to the bases of the transistors 25 and 24, respectively, and the selection signals 115 and 116 are applied to the bases of the transistors 36 and 35, respectively.

  The collector of the transistor 20 is connected to one end of the resistor 18 and the base of the transistor 43, and the collector of the transistor 21 is connected to one end of the resistor 19 and the base of the transistor 39, respectively.

  The emitter of the transistor 20 is connected to the emitter of the transistor 21 and the collector of the transistor 22, and the emitter of the transistor 22 is connected to one end of the resistor 23.

  The collector of the transistor 24 is connected to the other ends of the resistors 18 and 19 and one end of the resistor 17, the emitter of the transistor 24 is connected to the emitter of the transistor 25 and the collector of the transistor 26, and the emitter of the transistor 26 is one end of the resistor 27. Connected to.

  The collector of the transistor 31 is connected to one end of the resistor 29 and the base of the transistor 44, and the collector of the transistor 32 is connected to one end of the resistor 30 and the base of the transistor 40, respectively.

  The emitter of the transistor 31 is connected to the emitter of the transistor 32 and the collector of the transistor 33, and the emitter of the transistor 33 is connected to one end of the resistor 34.

  The collector of the transistor 35 is connected to the other ends of the resistors 29 and 30 and one end of the resistor 28, the emitter of the transistor 35 is connected to the emitter of the transistor 36 and the collector of the transistor 37, and the emitter of the transistor 37 is one end of the resistor 38. Connected to.

  On the other hand, an output signal 118 is output from the emitter of the transistor 39, the emitter of the transistor 39 is connected to the emitter of the transistor 40 and the collector of the transistor 41, and the emitter of the transistor 41 is connected to one end of the resistor 42.

  An output signal 119 is output from the emitter of the transistor 43, the emitter of the transistor 43 is connected to the emitter of the transistor 44 and the collector of the transistor 45, and the emitter of the transistor 45 is connected to one end of the resistor 46.

  Finally, the bias voltage signal 117 is applied to the bases of the transistors 22, 26, 33, 37, 41 and 45, and the positive voltage source “VCC” is connected to the other ends of the resistors 17 and 28, and the transistors 39, 40, 43 and 44. A negative voltage source “VEE” is applied to the collectors, respectively, and is applied to the other ends of the resistors 23, 27, 34, 38, 42 and 46.

  Here, the operation of the embodiment shown in FIG. 1 will be described. The resistance values of the resistors 17, 18, 19, 28, 29, and 30 are “R17”, “R18”, “R19”, “R28”, “R29”, and “R30”, respectively.

  The output current of the constant current source composed of the transistor 22 and the resistor 23 is referred to as “I2”, and the output current of the constant current source composed of the transistor 26 and the resistor 27 is referred to as “I3” (hereinafter referred to as a common mode current). ), The output current of the constant current source including the transistor 33 and the resistor 34 is “I4”, and the output current of the constant current source including the transistor 37 and the resistor 38 is referred to as “I5” (hereinafter referred to as a common mode current). ).

And these values are
R17 = R28 = Ra (6)
R18 = R19 = R29 = R30 = Rb (7)
I2 = I4 = Id (8)
I3 = I5 = Ic (9)
Meet, and
Ra · Ic> Rb · Id (10)
It is assumed that the circuit element parameters are set so that

  If the selection signal 113 is at a high level (the inverted signal selection signal 114 is at a low level), the common mode current “I3” is supplied from the positive voltage source “VCC” by the transistor 25 without passing through the buffer circuit 80. It will flow directly.

  In other words, if the selection signal 113 is at a high level (the inverted signal selection signal 114 is at a low level), the common mode control circuit 81 causes the common mode current “I3” to flow without passing through the buffer circuit 80. Become.

For this reason, if the input signals 109 and 110 are at a high level and a low level, respectively, the signal levels of the two outputs of the buffer circuit 80 are at a high level.
VCC-R17 · I2 = VCC-Ra · Id
And the low level is
VCC− (R17 + R18) · I2 = VCC− (Ra + Rb) · Id
It becomes.

  On the other hand, if the selection signal 115 is at a low level (the inverted signal selection signal 116 is at a high level), the common mode current “I5” is generated by the transistor 35 from the positive voltage source “VCC” to the resistor 28 (which forms the buffer circuit 82). It flows through the common mode resistor.

  In other words, if the selection signal 115 is at a low level (the inverted signal selection signal 116 is at a high level), the common mode control circuit 83 causes the common mode current “I5” to be generated by the resistor 28 (common mode resistance) constituting the buffer circuit 82. ) Will flow through.

For this reason, if the input signals 111 and 112 are set to a high level and a low level, respectively, the signal levels of the two outputs of the buffer circuit 82 are high levels.
VCC−R28 · (I4 + I5) = VCC−Ra · (Ic + Id)
And the low level is
VCC- (R28 + R29) ・ I4-R28 ・ I5
= VCC- (Ra + Rb) .Id-Ra.Ic
It becomes.

Here, when the difference “ΔV” between the low level of the buffer circuit 80 and the high level of the buffer circuit 82 is calculated,
ΔV = {VCC− (Ra + Rb) · Id} − {VCC−Ra · (Ic + Id)}
= Ra · Ic-Rb · Id (11)
It becomes.

  However, since there is a relationship shown in Expression (10), Expression (11) is always positive. In other words, the output voltage of the buffer circuit 80 is always higher than the output voltage of the buffer circuit 82 regardless of whether the output voltage of the buffer circuit 82 is high level or low level.

  That is, when the common mode current flows through the buffer circuit, the output voltage becomes lower than the low level output voltage when the common mode current does not flow.

  On the other hand, in the transistors 39 and 40 and the transistors 43 and 44 constituting the output stage circuit 84, the transistor having the larger input voltage to the base of each transistor is turned “ON” and the other is turned “OFF”.

  Therefore, when the selection signal 113 is high level (the inverted signal selection signal 114 is low level) and the selection signal 115 is low level (the inverted signal selection signal 116 is high level), the output voltage of the buffer circuit 82 is Regardless of the high level or the low level, the output voltage 118 is the high level output voltage of the buffer circuit 80, and the output voltage 119 is the low level output voltage of the buffer circuit 80. It will be.

  Similarly, when the selection signal 113 is low level (the inverted signal selection signal 114 is high level) and the selection signal 115 is high level (the inverted signal selection signal 116 is low level), the output voltage of the buffer circuit 80 is Regardless of the high level or the low level, the differential output voltage of the buffer circuit 82 is output as the output voltages 118 and 119.

  Incidentally, the differential circuit (transistors 7 and 8) to which the selection signal required in the conventional example shown in FIG. 3 is applied can be reduced, and the number of vertically stacked transistors is reduced by one, so that the power supply voltage necessary for the operation is reduced. Can be improved by "0.8V".

  As a result, the common mode control circuit controls the common mode current flowing in the buffer circuit by the selection signal, and the output of the buffer circuit in which the common mode current does not flow is output as an output signal, so that the number of vertically stacked transistors is one stage. Since it can be reduced, the power supply voltage necessary for the operation can be lowered.

  FIG. 2 is a circuit diagram showing another embodiment of the multiplexer circuit according to the present invention. In FIG. 2, 17, 18, 19, 20, 21, 22, 23, 28, 29, 30, 31, 32, 33, 34, 39, 40, 41, 42, 43, 44, 45, 46, 80, 82 and 84 are assigned the same reference numerals as in FIG.

  47, 48 and 49 are transistors, 50 is a resistor, 120 and 121, and 122 and 123 are differential input signals, 124 and 125 are differential selection signals, 126 is a bias voltage signal, 127 and 128, respectively. Is a differential output signal. Reference numerals 47, 48, 49, and 50 constitute a common mode control circuit 85.

  The common mode control circuit 85 is composed of a differential circuit composed of 47, 48, 49 and 50.

  Further, the input signal 121 is an inverted signal of the input signal 120, the input signal 123 is an inverted signal of the input signal 122, the selection signal 125 is an inverted signal of the selection signal 124, and the output signal 128 is an inverted signal of the output signal 127.

  Input signals 120 and 121 are applied to the bases of transistors 20 and 21, respectively, and input signals 122 and 123 are applied to the bases of transistors 31 and 32, respectively.

  Selection signals 124 and 125 are applied to the bases of transistors 48 and 47, respectively.

  The collector of the transistor 20 is connected to one end of the resistor 18 and the base of the transistor 43, and the collector of the transistor 21 is connected to one end of the resistor 19 and the base of the transistor 39, respectively.

  The emitter of the transistor 20 is connected to the emitter of the transistor 21 and the collector of the transistor 22, and the emitter of the transistor 22 is connected to one end of the resistor 23.

  The collector of the transistor 47 is connected to the other ends of the resistors 18 and 19 and one end of the resistor 17, the emitter of the transistor 47 is connected to the emitter of the transistor 48 and the collector of the transistor 49, and the emitter of the transistor 49 is one end of the resistor 50. Connected to.

  The collector of the transistor 31 is connected to one end of the resistor 29 and the base of the transistor 44, and the collector of the transistor 32 is connected to one end of the resistor 30 and the base of the transistor 40, respectively.

  The emitter of the transistor 31 is connected to the emitter of the transistor 32 and the collector of the transistor 33, and the emitter of the transistor 33 is connected to one end of the resistor 34.

  The collector of the transistor 48 is connected to the other ends of the resistors 29 and 30 and one end of the resistor 28.

  On the other hand, an output signal 127 is output from the emitter of the transistor 39, the emitter of the transistor 39 is connected to the emitter of the transistor 40 and the collector of the transistor 41, and the emitter of the transistor 41 is connected to one end of the resistor 42.

  The output signal 128 is output from the emitter of the transistor 43, the emitter of the transistor 43 is connected to the emitter of the transistor 44 and the collector of the transistor 45, and the emitter of the transistor 45 is connected to one end of the resistor 46.

  Finally, the bias voltage signal 1267 is applied to the bases of the transistors 22, 33, 41, 45 and 49, and the positive voltage source “VCC” is applied to the other ends of the resistors 17 and 28 and to the collectors of the transistors 39, 40, 43 and 44. A negative voltage source “VEE” is applied to the other ends of the resistors 23, 34, 42, 46 and 50, respectively.

  Here, the operation of the embodiment shown in FIG. 2 will be described. However, the description of the same operation as that of the embodiment shown in FIG. 1 is omitted.

Further, the constant current source “I6” (hereinafter referred to as a common mode current) composed of the transistor 49 and the resistor 50 is used. Formulas (6) to (8) and (10) are the same as described above,
I6 = Ic (12)
Meet.

  If the selection signal 124 is at a high level and the selection signal 125 is at a low level, the common mode current “I6” is generated by the transistor 48 from the positive voltage source “VCC” to the resistor 28 (common mode resistance). Will flow through.

  In other words, if the selection signal 124 is high level and the selection signal 125 is low level, the common mode control circuit 85 causes the common mode current “I6” to pass through the resistor 28 (common mode resistance) constituting the buffer circuit 82. It will flow.

  If the selection signal 124 is at a low level and the selection signal 125 is at a high level, the common mode current “I6” is generated by the transistor 47 from the positive voltage source “VCC” to the resistor 17 (common mode resistance). Will flow through.

  In other words, if the selection signal 124 is at a low level and the selection signal 125 is at a high level, the common mode control circuit 85 causes the common mode current “I6” to pass through the resistor 17 (common mode resistor) constituting the buffer circuit 80. It will flow.

  That is, in the embodiment shown in FIG. 1, the buffer circuit and the common mode control circuit are configured as a pair, but in the embodiment shown in FIG. 2, one common mode control circuit 85 is formed by two buffer circuits 80 and 82. The configuration is shared.

  Therefore, when the selection signal 124 is high level and the selection signal 125 is low level, the output voltages 127 and 128 are buffered regardless of whether the output voltage of the buffer circuit 82 is high level or low level. The differential output voltage of the circuit 80 is output.

  Similarly, when the selection signal 124 is low level and the selection signal 125 is high level, the output voltages 127 and 128 are buffered regardless of whether the output voltage of the buffer circuit 80 is high level or low level. The differential output voltage of the circuit 82 is output.

  Incidentally, in the embodiment shown in FIG. 2, the differential circuit (transistors 7 and 8) to which the selection signal required in the conventional example shown in FIG. 3 is applied can be reduced, and the number of vertically stacked transistors is reduced by one. Thus, the power supply voltage necessary for the operation can be improved by “0.8 V”.

  As a result, the common common mode control circuit controls the common mode current flowing in the buffer circuit by the selection signal, and the output of the buffer circuit in which the common mode current does not flow is output as an output signal, so that the number of transistors stacked vertically can be increased. Since one stage can be reduced, the power supply voltage necessary for the operation can be lowered.

  In the embodiment shown in FIG. 1, two pairs of buffer circuits and common mode control circuits are used. In the embodiment shown in FIG. 2, the buffer circuit and the common mode control circuit are shared. ing.

  That is, a so-called “2 to 1” multiplexer circuit that selects one of two differential input signals and outputs it as one output signal is illustrated. Of course, three or more buffer circuits and a common mode are used. You may apply to the multiplexer circuit of "n to 1 (n is an integer)" using a pair with a control circuit.

  As an output stage circuit, a constant current source (for example, a constant current source composed of a transistor 41 and a resistor 42 or a transistor is used by sharing the emitters of a plurality of transistors connected to the base of the output of each buffer circuit. 45 and a constant current source composed of a resistor 46).

  In this case, the plurality of common mode control circuits are controlled by the selection signal so that the common mode current flows through the plurality of buffer circuits other than the one buffer circuit to be selected.

  For this reason, only the output voltage of the selected buffer circuit in which the common mode current did not flow is increased, only the transistor to which the differential output voltage of the selected buffer circuit is applied is turned “ON”, and the other plural These transistors are turned off, and the differential of the buffer circuit to which the turned on transistors are connected regardless of whether the output voltages of the other buffer circuits are at high level or low level. Only the output voltage is output.

  It is also possible to form a D-type flip-flop by combining two multiplexer circuits shown in FIGS.

  1 and 2 exemplify a multiplexer circuit using an NPN transistor. Of course, only an N-type MOS (Metal Oxide Semiconductor) transistor, or an NPN transistor and an N-type MOS transistor are used. A multiplexer circuit may be configured by mixing them.

  A multiplexer circuit may be configured by mixing a PNP transistor, a P-type MOS transistor, or a PNP transistor and a P-type MOS transistor.

  In this case, the NPN transistor in FIG. 1 or the like is replaced with a PNP transistor, and the positive voltage source “VCC” and the negative voltage source “VEE” are replaced.

It is a circuit diagram which shows one Example of the multiplexer circuit based on this invention. It is a circuit diagram which shows the other Example of the multiplexer circuit based on this invention. It is a circuit diagram which shows an example of the conventional multiplexer circuit.

Explanation of symbols

1, 2, 10, 15, 16, 17, 18, 19, 23, 27, 28, 29, 30, 34, 38, 42, 46, 50 Resistors 3, 4, 5, 6, 7, 8, 9, 11, 12, 13, 14, 20, 21, 22, 24, 25, 26, 31, 32, 33, 35, 36, 37, 39, 40, 41, 43, 44, 45, 47, 48, 49 Transistors 80, 82 Buffer circuit 81, 83, 85 Common mode control circuit 84 Output stage circuit 100, 101, 102, 103, 109, 110, 111, 112, 120, 121, 122, 123 Input signal 104, 105, 113, 114 115, 116, 124, 125 Select signal 106, 117, 126 Bias voltage signal 107, 108, 118, 119, 127, 128 Output signal

Claims (7)

In a multiplexer circuit that selects and outputs one input signal among a plurality of input signals,
A differential circuit that receives a differential input signal and outputs a differential output voltage, first and second load resistors having one end connected to the differential output of the differential circuit, and the first and second A common mode resistor connected in common to the other end of the load resistor, and when the common mode current flows through the common mode resistor, the common mode current is higher than the low level output voltage. First and second buffer circuits to which the first and second differential input signals are applied, respectively, in which the output voltage is reduced;
A first common mode control circuit that controls whether or not to flow the common mode current to the common mode resistor in the first buffer circuit by a differential selection signal;
A second common mode control circuit for controlling whether or not to allow the common mode current to flow through the common mode resistor in the second buffer circuit by a differential selection signal;
An output stage circuit for outputting, as a differential output signal, an output voltage of the buffer circuit having a larger output voltage out of the output voltage of the first buffer circuit or the output voltage of the second buffer circuit; Multiplexer circuit. In a multiplexer circuit that selects and outputs one input signal among a plurality of input signals,
A differential circuit that receives a differential input signal and outputs a differential output; first and second load resistors having one end connected to the differential output of the differential circuit; and the first and second It is composed of a common mode resistor connected in common to the other end of the load resistor, and when the common mode current flows through the common mode resistor, the output is higher than the low level output voltage when the common mode current does not flow A plurality of buffer circuits to which a plurality of differential input signals are respectively applied, the voltage of which is reduced;
The same number of common mode control circuits as the buffer circuit for controlling whether or not to flow the common mode current to the common mode resistors in the plurality of buffer circuits by a differential selection signal;
A multiplexer circuit comprising: an output stage circuit that outputs an output voltage of a buffer circuit having a large output voltage among the output voltages of the plurality of buffer circuits as a differential output signal. In a multiplexer circuit that selects and outputs one input signal among a plurality of input signals,
A differential circuit that receives a differential input signal and outputs a differential output; first and second load resistors having one end connected to the differential output of the differential circuit; and the first and second It is composed of a common mode resistor connected in common to the other end of the load resistor, and when the common mode current flows through the common mode resistor, the output is higher than the low level output voltage when the common mode current does not flow A first buffer circuit and a second buffer circuit to which a first differential input signal and a second differential input signal are applied, respectively .
A common mode control circuit for controlling the common mode current to flow through either the common mode resistor in the first buffer circuit or the common mode resistor in the second buffer circuit by a differential selection signal;
An output stage circuit for outputting, as a differential output signal, an output voltage of the buffer circuit having a larger output voltage out of the output voltage of the first buffer circuit or the output voltage of the second buffer circuit; Multiplexer circuit. The common mode control circuit is
3. The multiplexer circuit according to claim 1, further comprising: a differential circuit that controls whether or not the common mode current is caused to flow through a common mode resistor in the buffer circuit according to the differential selection signal. . The common mode control circuit is
The differential selection signal is configured to include a differential circuit that controls the common mode current to flow through either the first buffer circuit or the common mode resistor in the second buffer circuit . 4. The multiplexer circuit according to claim 3. The transistors constituting each circuit are
NPN transistor, N-type MOS transistors, or a multiplexer circuit according to any one of claims 1 to 5, characterized in that a mixture of the NPN transistor and the N-type MOS transistor. The transistors constituting each circuit are
PNP transistor, P-type MOS transistors, or a multiplexer circuit according to any one of claims 1 to 5, characterized in that a mixture of the PNP transistor and the P-type MOS transistor.

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