JP2008098211A - Pattern shape of printed circuit board, and insulation deterioration test method of printed circuit board - Google Patents
Pattern shape of printed circuit board, and insulation deterioration test method of printed circuit board Download PDFInfo
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- JP2008098211A JP2008098211A JP2006274605A JP2006274605A JP2008098211A JP 2008098211 A JP2008098211 A JP 2008098211A JP 2006274605 A JP2006274605 A JP 2006274605A JP 2006274605 A JP2006274605 A JP 2006274605A JP 2008098211 A JP2008098211 A JP 2008098211A
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本発明は、プリント配線板の絶縁劣化試験方法及びプリント配線板のパターン形状に関する。 The present invention relates to a method for testing insulation deterioration of a printed wiring board and a pattern shape of the printed wiring board.
従来の絶縁劣化試験において短絡が発生した場合の解析手順例を、図4、図5、図6にて説明する。図4は、従来の技術による絶縁劣化試験用プリント配線板の一水平断面形状を示し、スルーホール1、導体パターン5、クリアランス7から構成される。所定の絶縁劣化試験を実施したプリント配線板は電気的に絶縁劣化したスルーホールを絞り込み解析しやすい大きさにプリント配線版を切断する。次に表裏層どちらから1層づつ水平研磨で削り込み、図5のようにスルーホール1と導体パターン5の間に絶縁劣化6を確認するまで削り込む。削り込みの過程では、実体顕微鏡や金属顕微鏡で観察し、絶縁劣化の有無を確認しながら研磨を実施することが必要となる。更に絶縁劣化箇所に対し、垂直方向に研磨した図を図6に示す。導体パターン5とスルーホール1間に絶縁劣化箇所6を示している。
An example of an analysis procedure when a short circuit occurs in a conventional insulation deterioration test will be described with reference to FIGS. 4, 5, and 6. FIG. 4 shows a horizontal cross-sectional shape of a printed wiring board for an insulation deterioration test according to the prior art, which is composed of a
また近年では、プリント配線板材料の樹脂成分にフィラーや着色剤が入っている材料が多く実体顕微鏡や金属顕微鏡で観察しにくいため、絶縁劣化現象を手前で捉えることが困難になっている。この結果、水平研磨段階で削りすぎにより絶縁劣化現象が消滅するケースが多くなってきているため、研磨での削りこみ前に電気的に絶縁劣化方向が確認出来る手段が求められている。 In recent years, since many materials containing fillers and colorants are contained in the resin component of the printed wiring board material, it is difficult to observe the insulation deterioration phenomenon in the foreground because it is difficult to observe with a stereo microscope or a metal microscope. As a result, there are many cases in which the insulation deterioration phenomenon disappears due to excessive shaving in the horizontal polishing stage. Therefore, there is a demand for means for electrically confirming the direction of insulation deterioration before shaving in polishing.
上記従来技術による絶縁劣化の解析では、水平研磨を行わないと絶縁劣化方向が特定できない場合がある。また、水平研磨の弊害として過研磨による絶縁劣化現象の消滅というリスクが発生するおそれがある。 In the analysis of insulation deterioration according to the above-described prior art, the direction of insulation deterioration may not be specified unless horizontal polishing is performed. Moreover, there is a risk that the risk of disappearance of the insulation deterioration phenomenon due to overpolishing may occur as an adverse effect of horizontal polishing.
本発明の目的は、電気的な確認だけで絶縁劣化箇所が推定できるプリント配線板の絶縁劣化試験方法を提供することにある。 An object of the present invention is to provide an insulation deterioration test method for a printed wiring board that can estimate an insulation deterioration location only by electrical confirmation.
上記目的を達成するために本発明は、プリント配線板の設計段階で導体とスルーホールの距離が一定となるようにスルーホールを取り囲む導体パターンを放射状にn分割することを特徴とする。また、n分割された導体パターンを等電位とし導体パターンとスルーホールに電圧を印加して所定の絶縁劣化試験を実施した後、n分割された導体パターンとスルーホール間の絶縁抵抗を個別に測定することを特徴とする。 In order to achieve the above object, the present invention is characterized in that the conductor pattern surrounding the through hole is radially divided into n so that the distance between the conductor and the through hole is constant at the design stage of the printed wiring board. In addition, after conducting a predetermined insulation deterioration test by applying a voltage to the conductor pattern and the through-hole with the conductor pattern divided into n equal potentials, the insulation resistance between the n-divided conductor pattern and the through-hole is individually measured. It is characterized by doing.
導体パターンのスルーホールを取り囲む内層パターンを個別化することで、電気的な確認だけで絶縁劣化箇所が推定できる利点がある。 By individualizing the inner layer pattern that surrounds the through hole of the conductor pattern, there is an advantage that the location of insulation deterioration can be estimated only by electrical confirmation.
図1は、本発明の一実施形態である絶縁劣化試験用プリント配線板の導体パターン3.1から3.8を用いた基板の平面図を示す。 FIG. 1 is a plan view of a substrate using conductor patterns 3.1 to 3.8 of an insulating deterioration test printed wiring board according to an embodiment of the present invention.
絶縁劣化試験用プリント配線板の構造は板厚1.6mmで層数10層である。層数10層の内、表裏層を除く内層8層は導体パターン3.1から3.8とスルーホール1の距離が一定となるようにクリアランス2を挟みスルーホール1を取り囲み導体パターン3.1から3.8を放射状に8分割して形成する。この8分割された導体パターン3.1から3.8は電気的に繋がらない構造にしてプリント配線板を作成した。
The structure of the printed wiring board for insulation deterioration test has a plate thickness of 1.6 mm and 10 layers. Among the 10 layers, the inner layer 8 layers excluding the front and back layers surround the through
絶縁劣化試験条件は、高温高湿槽を用い、設定条件を温度85℃、湿度85%とし、印加電圧を100Vに設定した。試験前に電圧印加するための線材をスルーホール1に1本、8分割された導体パターン3に1本づつ計9本配線した。電圧印加については、スルーホール1を陰極として8分割された導体パターン3.1から3.8を8本1つに束ねて陽極とした。試験前に陰極と陽極がショートしていないか回路テスターで確認し試験槽にプリント配線板を設置した。試験中の絶縁劣化状態はハイブリットレコーダーにて電圧モニターすることで確認した。絶縁劣化が発生した後、試験を停止し、サンプルを取り出し1つに束ねた陽極を離し8分割にして回路テスターで陰極と陽極の抵抗を測定してショートしているポイントが4層目の導体パターン3.7(図2)であることを特定した。
The insulation deterioration test conditions were a high-temperature and high-humidity tank, the setting conditions were a temperature of 85 ° C. and a humidity of 85%, and the applied voltage was set to 100V. Before the test, a total of nine wires were applied, one for the through
次に不良解析を実施するにあたり、電気的に確認できた絶縁劣化方向があっているか従来の不良解析手順に添って解析することにした。電気的に確認できた絶縁劣化箇所を含む領域より若干大きく基板を切断し、水平研磨を1づつ、実体顕微鏡及び金属顕微鏡と回路テスターで抵抗を確認しながら研磨した。4層目の手前で絶縁劣化している導体パターン3.7(図2)と絶縁劣化箇所4を確認した。更に絶縁劣化している箇所と平行に垂直方向へ研磨をして実体顕微鏡及び金属顕微鏡を用い研磨をし、図3に示す導体パターン3.7とスルーホール1の間に絶縁劣化箇所4がガラスクロスに添って炭化した絶縁劣化現象を確認できた。
Next, when carrying out the failure analysis, it was decided to analyze according to the conventional failure analysis procedure whether there was an electrically confirmed direction of insulation deterioration. The substrate was cut slightly larger than the region including the insulation degradation point that could be electrically confirmed, and polished one by one with horizontal polishing, while confirming the resistance with a stereomicroscope, metal microscope and circuit tester. The conductor pattern 3.7 (FIG. 2) and the
以上の解析により、電気的に確認出来た絶縁劣化方向と水平研磨及び垂直研磨で確認出来た絶縁劣化方向が一致したことにより本発明による導体パターン3.1から3.8を使用することにより検証することができた。この結果から、近年使用されているフィラー入り等の材料でも絶縁劣化方向が電気的に確認できることで従来行っていた水平研磨での絶縁劣化方向を特定することを省け、解析時間の短縮と不良解析での絶縁劣化現象が容易に確認出来るようになった。 Based on the above analysis, the insulation deterioration direction confirmed electrically can be verified by using the conductor patterns 3.1 to 3.8 according to the present invention because the insulation deterioration directions confirmed by horizontal polishing and vertical polishing are the same. We were able to. From this result, it is possible to electrically identify the direction of insulation deterioration even in materials that have been used in recent years, such as filler-filled materials, thereby eliminating the need to specify the direction of insulation deterioration in horizontal polishing, which has been performed in the past, and shortening analysis time and failure analysis Insulation deterioration phenomenon can be easily confirmed.
1:スルーホール
2:クリアランス
3.1〜3.8:導体パターン
4:絶縁劣化箇所
5:導体パターン
6:絶縁劣化箇所
7:クリアランス
1: Through hole 2: Clearance 3.1 to 3.8: Conductor pattern 4: Insulation deterioration place 5: Conductor pattern 6: Insulation deterioration place 7: Clearance
Claims (2)
In the printed circuit board for insulation deterioration test using the conductor pattern according to claim 1, after conducting a predetermined insulation deterioration test by applying a voltage to the conductor pattern and the through hole with the conductor pattern divided into n equal potentials. An insulation deterioration test method for a printed wiring board, wherein the insulation resistance between the n-divided conductor pattern and the through hole is individually measured.
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Cited By (1)
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JP2012037314A (en) * | 2010-08-05 | 2012-02-23 | Fujitsu Ltd | Evaluation substrate and substrate evaluation method |
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Cited By (1)
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JP2012037314A (en) * | 2010-08-05 | 2012-02-23 | Fujitsu Ltd | Evaluation substrate and substrate evaluation method |
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