JP2008097507A - Sequence control circuit, pattern generating device, and semiconductor testing device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a sequence control circuit that can perform a higher speed operation as compared with the conventional practice and to provide a pattern generating device capable of generating a high speed pattern by providing the sequence control circuit to it, and a semiconductor testing device provided with the pattern generating device. <P>SOLUTION: The sequence control circuit 1 includes: an instruction memory 11 for storing a sequence control instruction for generating a program counter signal PC; a first program counter part 12 for generating a program counter signal PC1 according to the sequence control instruction stored in the instruction memory 11; a second program counter part 13 for generating a program counter signal PC2 following the program counter signal PC1 by using the sequence control instruction stored in the instruction memory 11; and a multiplexing circuit 16 for multiplexing the generated program counter signals PC1 and PC2 to be a program counter signal PC. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a sequence control circuit that controls a generation sequence of a predetermined pattern, a pattern generation apparatus including the circuit, and a semiconductor test apparatus including the apparatus.

  A semiconductor test apparatus generally applies a test pattern to a device under test (hereinafter referred to as DUT (Device Under Test)), compares a signal output from the DUT with a predetermined expected value, and passes the test pattern. / Fail data indicating failure is obtained, and the DUT is tested for good or bad based on the fail data. The semiconductor test apparatus includes a pattern generator that generates a test pattern to be applied to the DUT. The pattern generator is provided with a sequence control circuit that controls a test pattern generation sequence.

  FIG. 8 is a block diagram showing a schematic configuration of the semiconductor test apparatus. As shown in FIG. 8, the semiconductor test apparatus 100 includes a clock generation circuit 101, a pattern generation apparatus 102, and a comparative note 103, and tests the DUT 200 by applying a test pattern P <b> 1 to the DUT 200. The clock generation circuit 101 generates a reference clock CLK that defines the operation of the semiconductor test apparatus 100. The reference clock CLK is input to the pattern generator 102 and the comparison note 103.

  The pattern generation device 102 includes a sequence control circuit 111, an instruction memory 112, and a pattern generation circuit 113, and generates a test pattern P1 and an expected value E1 to be applied to the DUT 200. The sequence control circuit 111 outputs a program counter signal PC that controls the generation sequence of the test pattern P1 and the expected value E1 in accordance with a sequence control command described in a test program created by the user.

  The instruction memory 112 stores the pattern generation command described in the test program, reads the pattern generation command stored at the address indicated by the program counter signal PC output from the sequence control circuit 111, and reads the pattern generation command signal PG. Output as. The pattern generation circuit 113 performs a predetermined calculation according to the pattern generation command signal PG output from the instruction memory 112, and outputs a test pattern P1 and an expected value E1. The comparative note 103 compares the signal D1 obtained by applying the test pattern P1 to the DUT 200 and the expected value E1 to generate fail data, and determines whether the DUT 200 is good or bad.

  FIG. 9 is a diagram illustrating an example of a test program created by the user. As shown in FIG. 9, the test program describes a sequence control instruction and a pattern generation instruction in association with each line. The sequence control instruction “NOOP” in FIG. 9 is an instruction for incrementing the program counter. The sequence control instruction “LOOP” is an instruction for jumping the program counter until the designated number of times from the designated line to the line describing the sequence control instruction is executed.

  In the example shown in FIG. 9, “AA: LOOP 4 AA” is described, but the character string “AA:” described on the left side of the sequence control instruction “LOOP” is a label, and the sequence control instruction “ The number “4” described on the right side of “LOOP” is the number of times, and the character string “AA” is the row. That is, in this example, the line in which the label “AA:” is described by the character string “AA” described on the right side of the sequence control instruction “LOOP”, that is, the line in which the sequence control instruction “LOOP” is described is designated. Therefore, this line is executed four times.

  Next, the operation of the semiconductor test apparatus 100 shown in FIG. 8 will be described. FIG. 10 is a timing chart of signals output from each part of the semiconductor test apparatus 100. When the test is started, the test program shown in FIG. 9 is read into the pattern generation unit 102 and the pattern generation instruction described in the test program is stored in the instruction memory 112. Specifically, the pattern generation instruction “X = 0” is stored at address 0 of the instruction memory 112, the pattern generation instruction “X = X + 1” is stored at address 1, and the pattern generation instruction “X” is stored at address 3. = 0 ”is stored, and the pattern generation instruction“ X = X + 1 ”is stored at addresses 4 and 5.

  When the above processing is completed, the sequence control circuit 111 executes the sequence control instruction described in the test program shown in FIG. 9 in synchronization with the reference clock CLK and outputs the program counter signal PC. Specifically, as shown in FIG. 10, a program counter signal PC whose value changes as “0, 1, 1, 1, 1, 2, 3, 4,. The instruction memory 112 reads the pattern generation command stored at the address indicated by the program counter signal PC output from the sequence control circuit 111 in synchronization with the reference clock CLK, and outputs it as a pattern generation command signal PG. Specifically, as shown in FIG. 10, after the pattern generation instruction “X = 0” stored at address 0 is read, the pattern generation instruction “X = X + 1” stored at address 1 is read four times. Next, the pattern generation instruction “X = 0” stored at the address 2, the pattern generation instruction “X = + 1” stored at the address 3, and the pattern generation instruction “X = X + 1” stored at the address 4 Are sequentially read and output as a pattern generation command signal PG.

  The pattern generation circuit 113 performs a predetermined calculation according to the pattern generation command signal PG output from the instruction memory 112, and outputs a test pattern P1 and an expected value E1. Specifically, as shown in FIG. 10, a test pattern P1 and an expected value E1 whose values change as “0, 1, 2, 3, 4, 0, 1, 2,. The test pattern P1 output from the pattern generation circuit 113 is applied to the DUT 200, and the DUT 200 outputs a signal D1 corresponding to the applied test pattern P1. The comparison note 103 compares the signal D1 from the DUT 200 with the expected value E1 output from the pattern generation circuit 113 to generate fail data, and determines whether the DUT 200 is good or bad.

  Next, the sequence control circuit 111 will be described. FIG. 11 is a block diagram showing a configuration of the sequence control circuit 111. As shown in FIG. 11, the sequence control circuit 111 includes an instruction memory 121, a program counter control unit 122, and a register 123. The instruction memory 121 stores the sequence control instruction described in the test program, reads the sequence control instruction stored at the address indicated by the program counter signal PC output from the register 123, and outputs it as the sequence control instruction S101. .

  The program counter control unit 122 decodes the sequence control instruction SC output from the instruction memory 121 and then outputs a program counter signal S102 to be output as the program counter signal SC. The register 123 temporarily holds the program counter signal S102 output from the program counter control unit 122, and outputs it as the program counter signal PC in synchronization with the reference clock CLK.

  Next, the operation of the sequence control circuit 111 shown in FIG. 11 will be described. FIG. 12 is a timing chart of signals output from each unit of the sequence control circuit 111. When the operation is started, a sequence control instruction described in the test program shown in FIG. 9 is stored in the instruction memory 121. Specifically, the sequence control command “NOOP” is stored at address 0 of the instruction memory 121, the sequence control command “LOOP” is stored at address 1, and the sequence control command “NOOP” is stored at addresses 2-4. Remembered. The initial value of the register 123 is set to “0”.

  When the reference clock CLK is input to the register 123 after the above processing ends, the initial value “0” stored in the register 123 is output as the program counter signal PC. The program counter signal PC is input to the instruction memory 121, and the sequence control instruction “NOOP” stored at address 0 of the instruction memory 121 is read out and output as the sequence control instruction S101. The program counter control unit 122 decodes the sequence control instruction SC output from the instruction memory 121, and then outputs a program counter signal S102 to be output as the program counter signal SC. Specifically, as shown in FIG. 12, the input sequence control instruction “NOOP” is decoded and a value obtained by incrementing the program counter (that is, the value “1”) is output as the program counter signal S102.

The program counter signal S102 is stored in the register 123, and is output as the program counter signal PC at the timing when the reference clock CLK is input next. By repeating the above operation, the sequence control circuit 111 generates a program counter signal PC whose value changes as “0, 1, 1, 1, 1, 1, 2, 3, 4,...” As shown in FIG. Output in synchronization with the reference clock CLK. Another conventional sequence control circuit is disclosed in, for example, Patent Document 1 below.
JP 2001-282324 A

  Incidentally, in recent years, the operation speed of the DUT 200 has been improved, and it is necessary to generate the test pattern P1 at a higher speed. Since the generation speed of the test pattern P1 is defined by the operation speed of the sequence control circuit 111, it can be considered that the test pattern P1 can be generated at high speed by increasing the speed of the sequence control circuit 111. Here, if the reference clock CLK is set to a higher frequency, the sequence control circuit 111 can be speeded up and the test pattern P1 can be generated at a higher speed.

  However, the above-described conventional sequence control circuit 111 reads the sequence control command from the instruction memory 121 during one cycle of the reference clock CLK, and obtains the program counter signal S102 to be output next by the program counter control unit 122. Yes. For this reason, one cycle of the reference clock CLK cannot be made equal to or less than the total time of the access time of the instruction memory 121 and the processing time of the program counter control unit 122, and the maximum operation speed of the sequence control circuit 111 is improved. There was a problem with limitations.

  The present invention has been made in view of the above circumstances, and provides a sequence control circuit capable of operating at a higher speed than before, and a pattern generator capable of generating a pattern at a high speed by including the sequence control circuit, and An object of the present invention is to provide a semiconductor test apparatus including the pattern generation apparatus.

In order to solve the above-described problems, a sequence control circuit according to the present invention is a sequence control circuit that generates a control signal in a sequence control circuit (1) that outputs a control signal (PC) for controlling a generation sequence of a predetermined pattern. A storage unit (11) for storing a command, a first control unit (12) for generating a first control signal (PC1) according to the sequence control command stored in the storage unit, and the storage unit stored in the storage unit A second control unit (13) that generates a second control signal (PC2) following the first control signal using a sequence control command, the first control signal generated by the first control unit, and the second control signal And a multiplexing unit (16) that multiplexes the second control signal generated by the control unit and outputs the second control signal as the control signal.
According to the present invention, the first control signal is generated by the first control unit in accordance with the sequence control command stored in the storage unit, and the first control signal is generated by the second control unit using the sequence control command stored in the storage unit. A subsequent second control signal is generated, and the first control signal generated by the first control unit and the second control signal generated by the second control unit are multiplexed by the multiplexing unit and output as a control signal. .
In the sequence control circuit of the present invention, the storage unit includes a first sequence control instruction for generating the first control signal, a second sequence control instruction for generating the second control signal, When the first sequence control instruction is a jump instruction, a third sequence control instruction that is a jump destination sequence control instruction is stored in association with each address.
In the sequence control circuit of the present invention, the storage unit includes a first storage area (R1) for storing the first sequence control instruction, and a second storage area (R2) for storing the second sequence control instruction. And a third storage area (R3) for storing the third sequence control instruction.
In the sequence control circuit of the present invention, the storage unit stores the first sequence control instruction stored in association with an address specified by the second control signal generated by the second control unit, The second sequence control command and the third sequence control command are read out.
Furthermore. In the sequence control circuit of the present invention, the first control unit generates the first control signal according to the first sequence control command read from the storage unit, and the second control unit receives from the storage unit. The second control signal is generated according to a combination of the read first sequence control instruction, the second sequence control instruction, and the third sequence control instruction.
The pattern generator of the present invention is a pattern generator for generating a predetermined pattern, stores the sequence control circuit according to any one of the above, and a pattern generation command for generating the predetermined pattern, from the sequence control circuit An instruction memory (112) that reads out the pattern generation instruction stored in the address specified by the output control signal, and performs a predetermined operation according to the pattern generation instruction read out from the instruction memory. And a pattern generation circuit (113) for generating the predetermined pattern.
The semiconductor test apparatus of the present invention is the above-described pattern that generates the predetermined pattern as the test pattern in a semiconductor test apparatus that tests the device under test by applying the test pattern (P1) to the device under test (200). A generation device is provided.

  According to the present invention, the first control unit generates the first control signal according to the sequence control command stored in the storage unit, and the second control unit uses the sequence control command stored in the storage unit to generate the first control signal. Since the second control signal following is generated, the first control signal generated by the first control unit and the second control signal generated by the second control unit are multiplexed by the multiplexing unit and output as a control signal. There is an effect that it is possible to operate at a higher speed than in the prior art. Further, by providing the pattern generation device with the sequence control circuit of the present invention, there is an effect that a pattern generation device capable of generating a higher speed pattern can be realized. Furthermore, by providing a pattern generation apparatus including the sequence control circuit of the present invention in a semiconductor test apparatus, it is possible to test a device under test that operates at high speed.

  Hereinafter, a sequence control circuit, a pattern generator, and a semiconductor test apparatus according to an embodiment of the present invention will be described in detail with reference to the drawings. FIG. 1 is a block diagram showing a configuration of a sequence control circuit according to an embodiment of the present invention. As shown in FIG. 1, the sequence control circuit 1 according to the present embodiment includes an instruction memory 11 (storage unit), a first program counter control unit 12 (first control unit), and a second program counter control unit 13 (second control unit). ), Registers 14 and 15, a multiplexer circuit 16 (multiplexer), a frequency divider circuit 17, and a loop counter 18, and outputs a program counter signal PC (control signal). The program counter signal PC output from the sequence control circuit 1 is used to control the generation sequence of a predetermined pattern.

  The instruction memory 11 stores a sequence control instruction described in the test program, reads out the sequence control instruction stored at the address indicated by the program counter signal PC12 output from the register 15, and outputs them as sequence control instructions S11 to S13. Output. Hereinafter, in order to simplify the description, it is assumed that a sequence control instruction described in the test program shown in FIG. 9 is stored in the instruction memory 11.

  Here, the instruction memory 11 has a sequence control instruction (first sequence control instruction) for generating the program counter signal PC1 and a sequence control instruction (second sequence) for generating the program counter signal PC2 following the program counter signal PC1. A sequence control instruction) and a jump destination sequence control instruction (third sequence control instruction) when the first sequence control instruction is a jump instruction such as “LOOP” are stored in association with each address. The instruction memory 11 includes a first sequence control instruction storage area R1 (first storage area) for storing the first sequence control instruction and a second sequence control instruction storage area R2 (first storage) for storing the second sequence control instruction. 2 storage areas) and a third sequence control instruction storage area R3 (third storage area) for storing the above-described third sequence control instructions.

  FIG. 2 is a diagram illustrating an example of a sequence control instruction stored in the instruction memory 11. As shown in FIG. 2, the address of the instruction memory 11 is common to the first sequence control instruction storage area R1, the second sequence control instruction storage area R2, and the third sequence control instruction storage area R3. In the first sequence control instruction storage area R1, the sequence control instructions shown in FIG. 9 are stored as they are in order from the address 0. On the other hand, the sequence control instructions described in the second and subsequent lines of the test program shown in FIG. 9 are stored in order from address 0 in the second sequence control instruction storage area R1. As a result, the sequence control instruction described in a line of the test program is associated with the sequence control instruction described in the next line of the line, and the first sequence control instruction storage area R1 and the second sequence control instruction are associated with each other. They are stored in the storage area R2.

  The third sequence control instruction storage area R3 stores a jump destination sequence control instruction when the sequence control instruction described in the test program shown in FIG. 9 is a jump instruction such as “LOOP”. Note that in the case of a sequence control instruction such as a sequence control instruction “NOOP” which is not a jump instruction, there is no jump destination, so nothing is stored and “undefined data” is obtained. Here, referring to the test program shown in FIG. 9, a sequence control instruction “LOOP 4 AA” which is a kind of jump instruction is described in the second line, and the jump destination of this sequence control instruction is labeled “AA”. : ”, That is, the same line as the line in which the sequence control instruction“ LOOP 4 AA ”is described.

  Therefore, at the address 1 in the third sequence control instruction storage area R3 of the instruction memory 11, the same sequence control instruction “LOOP 4 as the sequence control instruction stored at the address 1 of the first sequence control instruction storage area R1. AA "is stored. In the example shown in FIG. 2, the sequence control instruction stored at addresses 0 and 2 to 4 in the first sequence control instruction storage area R1 is “NOOP” and is not a jump instruction. The addresses 0 and 2 to 4 in the instruction storage area R3 are “indefinite data”. Thus, the jump destination sequence control instruction is stored in the third sequence control instruction storage area R3 in association with the sequence control instructions stored in the first sequence control instruction storage area R1 and the second sequence control instruction storage area R2. Is done.

  When the program counter signal PC12 is output from the register 15, the instruction memory 11 stores the sequence instruction stored in association with the address indicated by the program counter signal PC12 in the first sequence control instruction storage area R1, the second Read from each of the sequence control instruction storage area R2 and the third sequence control instruction storage area R3, and output as sequence control instructions S11 to S13, respectively.

  The first program counter control unit 12 receives a sequence control instruction S11 output from the instruction memory 11, a program counter signal PC12 output from the register 15, and a count signal CE output from the loop counter 18. The program counter signal PC1 (first control signal) is generated according to the sequence control command S11 and the count signal CE. The second program counter control unit 13 receives the sequence control instructions S11 to S13 output from the instruction memory 11, the program counter signal PC12 output from the register 15, and the count signal CE output from the loop counter 18. A program counter signal PC2 (second control signal) following the program counter signal PC1 is generated in accordance with the combination of the sequence control commands S11 to S13 and the count signal CE that are input. Details of the first program counter control unit 12 and the second program counter control unit 13 will be described later.

  The register 14 temporarily holds the program counter signal PC1 output from the first program counter controller 12, and outputs it as the program counter signal PC11 in synchronization with the clock signal CLK1. The register 15 temporarily holds the program counter signal PC2 output from the second program counter control unit 13, and outputs it as the program counter signal PC12 in synchronization with the clock signal CLK1. The multiplexing circuit 16 multiplexes the program counter signal PC11 output from the register 14 and the program counter signal PC12 output from the register 15, and outputs the result as a program counter signal PC in synchronization with the reference clock CLK.

  The frequency dividing circuit 17 divides the input reference clock CLK by 2 and outputs the divided reference clock CLK to the registers 14 and 15 as the clock signal CLK1. The initial value of the loop counter 18 is set by the first program counter control unit 12 or the second program counter control unit 13, and the control signal C 1 output from the first program counter control unit 12 or the second program counter control unit 13 When the output control signal C2 is input, it counts down and outputs a count signal CE indicating the count state to the first program counter control unit 12 and the second program counter control unit 13. When the initial value of the loop counter 18 is set to N (N is an integer equal to or greater than 3), the count ends when (N-2) counts down.

  Next, details of the first program counter control unit 12 and the second program counter control unit 13 will be described in order.

[First Program Counter Control Unit 12]
FIG. 3 is a block diagram showing a configuration of the first program counter control unit 12. As shown in FIG. 3, the first program counter control unit 12 includes an adder 21, a jump control circuit 22, and a selector 23. The program counter signal PC12 output from the register 15 is input to the adder 21, and the sequence control instruction S11 output from the instruction memory 11 is input to the jump control circuit 22. When the sequence control command S11 input to the first program counter control unit 12 is a jump command such as “LOOP”, the jump destination address included in the sequence control command S11 is input to the selector 23 as a signal S22. Is done.

  The adder 21 adds (increments) the value “1” to the value of the program counter signal PC12 and outputs the result to the selector 23 as a signal S21. The jump control circuit 22 outputs a selection signal L1 for selecting one of the signal S21 and the signal S22 input to the selector 23 based on the sequence control command S11 and the count signal CE output from the loop counter 18. . FIG. 4 is a chart showing signal selection conditions of the jump control circuit 22 provided in the first program counter control unit 12. As shown in FIG. 4, the jump control circuit 22 selects the signal S22 when the input sequence control instruction S11 is a jump instruction such as “LOOP” and the count signal CE indicates that counting is in progress. In other cases, the selection signal L1 for selecting the signal S21 output from the adder 21 is output.

  The jump control circuit 22 is a control signal for causing the loop counter 18 to count down when the input sequence control command S11 is the sequence control command “LOOP” and the count signal CE indicates that counting is in progress. C1 is output. When the sequence control instruction S11 is the sequence control instruction “LOOP” and the count signal CE does not indicate that counting is in progress, the loop count included in the sequence control instruction S11 is set as the initial value of the loop counter 18. . The selector 23 selects one of the input signal S21 and the signal S22 based on the selection signal L1 output from the jump control circuit 22, and outputs it as the program counter signal PC1.

[Second Program Counter Control Unit 13]
FIG. 5 is a block diagram showing a configuration of the second program counter control unit 13. As shown in FIG. 5, the second program counter control unit 13 includes adders 31 and 32, a jump control circuit 33, and a selector 34. The program counter signal PC12 output from the register 15 is input to the adder 31, and the sequence control instructions S11 to S13 output from the instruction memory 11 are input to the jump control circuit 33.

  When the sequence control command S11 input to the second program counter control unit 13 is a jump command such as “LOOP”, the jump destination address included in the sequence control command S11 is sent to the adder 32 as a signal S41. Entered. When the sequence control instructions S12 and S13 input to the second program counter control unit 13 are jump instructions such as “LOOP”, the jump destination address included in the sequence control instructions S12 and S13 is the signal S33, The data is input to the selector 34 as S34.

  The adder 31 adds the value “2” to the value of the program counter signal PC12 and outputs it to the selector 34 as a signal S31. The adder 32 adds (increments) the value “1” to the value of the input signal S41 and outputs the result to the selector 34 as the signal S32. The jump control circuit 33 is a selection signal for selecting any one of the signals S31 to S34 input to the selector 34 based on the combination of the sequence control instructions S11 to S13 and the count signal CE output from the loop counter 18. L2 is output.

  FIG. 6 is a chart showing signal selection conditions of the jump control circuit 33 provided in the second program counter control unit 13. As shown in FIG. 6, the jump control circuit 33 selects the signal S31 output from the adder 31 when, for example, the input sequence control instructions S11 and S12 are both sequence control instructions “NOOP”. L2 is output. On the other hand, when the sequence control command S11 is a sequence control command “NOOP” and the sequence control command S12 is a jump command such as “LOOP”, the signal to be selected changes according to the count signal CE. That is, the signal S31 output from the adder 31 is selected when the count signal CE indicates the end of counting, and the signal S33 indicating the jump destination address included in the sequence control instruction S12 when indicating the counting in progress. Select.

  The jump control circuit 33 counts down the loop counter 18 when the input sequence control instructions S11 and S13 are both sequence control instructions “LOOP” and the count signal CE indicates that counting is in progress. The control signal C2 to be output is output. When the sequence control command S11 is the sequence control command “NOOP”, the sequence control command S12 is the sequence control command “LOOP”, and the count signal CE does not indicate that the counting is being performed, the sequence control command S12 is changed to the sequence control command S12. The included loop count is set as the initial value of the loop counter 18. The selector 34 selects any one of the input signals S31 to S34 based on the selection signal L2 output from the jump control circuit 33 and outputs the selected signal as the program counter signal PC2.

  Next, the operation of the sequence control circuit 1 of the present embodiment will be described. FIG. 7 is a timing chart of signals output from each part of the sequence control circuit 1 according to the embodiment of the present invention. When the operation is started, a sequence control instruction described in the test program shown in FIG. 9 is stored in the instruction memory 11. Specifically, as shown in FIG. 2, in the first sequence control instruction storage area R1 of the instruction memory 11, the sequence control instruction “NOOP” is stored at the address 0, and the sequence control instruction “LOOP 4” is stored at the address 1. AA "is stored, and the sequence control instruction" NOOP "is stored at addresses 2-4.

  In the second sequence control instruction storage area R2 of the instruction memory 11, the sequence control instruction “LOOP 4 AA” is stored at address 0, and the sequence control instruction “NOOP” is stored at addresses 1 to 3. In the third sequence control instruction storage area R3 of the instruction memory 11, the sequence control instruction “LOOP 4 AA” is stored at the address 1 and the addresses 0, 2 to 4 are “indefinite data”. The initial value of the register 15 is set to “0”.

  When the reference clock CLK is input to the sequence control circuit 1 after the above processing ends, the reference clock CLK is input to the frequency divider 17 and the multiplexer 16 respectively. The reference clock CLK input to the frequency dividing circuit 17 is divided by two and input to the registers 14 and 15 as the clock signal CLK1. When the clock signal CLK1 is input to the register 15, the initial value “0” stored in the register 15 is output as the program counter signal PC12 (program counter signal PC12 in the period T1 in FIG. 7).

  The program counter signal PC12 is input to the instruction memory 11, the first program counter control unit 12, and the second program counter control unit 13, respectively. When the program counter signal PC12 is input to the instruction memory 11, the sequence control instruction stored at the address 0 of the instruction memory 11 is read out.

  Specifically, the sequence control instruction “NOOP” stored at address 0 of the first sequence control instruction storage area R1, and the sequence control instruction “NOOP” stored at address 0 of the second sequence control instruction storage area R2. “LOOP 4 AA” and “undefined data” stored at address 0 of the third sequence control instruction storage area R3 are read out and output as sequence control instructions S11 to S13, respectively (period T1 in FIG. 7). Sequence control instructions S11 to S13). The sequence control command S11 is input to the first program counter control unit 12 and the second program counter control unit 13, and the sequence control commands S12 and S13 are input to the second program counter control unit 13.

  When the program counter signal PC12 is input to the first program counter control unit 12, the value is incremented by the adder 21 to become the value “1”, and is output to the selector 23 as the signal S21. When the sequence control command S11 is input to the first program counter control unit 12, the jump control circuit 22 outputs a selection signal L1 for selecting the signal S21 output from the adder 21. This is because the sequence control command “NOOP” is input as the sequence control command S11, and the count signal CE does not indicate that counting is in progress (see FIG. 4). The selector 23 selects the signal S21 based on the selection signal L1 and outputs it as the program counter signal PC1 (program counter signal PC1 in the period T1 in FIG. 7). The program counter signal PC1 output from the first program counter control unit 12 is temporarily stored in the register 14.

  On the other hand, when the program counter signal PC12 is input to the second program counter control unit 13, the value "2" is added by the adder 32 and is output to the selector 34 as the signal S31. When the sequence control instructions S11 to S13 are input to the second program counter control unit 13, the jump control circuit 33 first sets the loop count “4” included in the sequence control instruction S12 as the initial value of the loop counter 18. To do. This is because the sequence control command “NOOP” is input as the sequence control command S11, the sequence control command “NOOP 4 AA” is input as the sequence control command S12, and “undefined data” is input as the sequence control command S13. This is because the signal CE does not indicate that counting is in progress. With the above initial value setting, the count signal CE indicates that counting is in progress.

  Next, based on the combination of the sequence control instructions S11 to S13 and the count signal CE, the second program counter control unit 13 selects the selection signal L2 that selects the signal S33 indicating the jump destination address included in the sequence control instruction S12. Output (see FIG. 6). The selector 34 selects the signal S33 based on the selection signal L2 and outputs it as the program counter signal PC2 (program counter signal PC2 in the period T1 in FIG. 7). Here, the jump destination of the sequence control instruction “LOOP 4 AA” described in the second line of the test program shown in FIG. 9 is the same second line in which the label “AA:” is described. Since this sequence control instruction “LOOP 4 AA” is stored at address 1 of the first sequence control instruction storage area R1 of the instruction memory 11, the jump destination address is “1”. Therefore, the address indicated by the signal S33 is “1”, and the value of the program counter signal PC2 is also “1”. The program counter signal PC2 output from the second program counter control unit 13 is temporarily stored in the register 15.

  When the next clock signal CLK1 is output from the frequency divider circuit 17, it is input to the registers 14 and 15, and the program counter signals PC11 and PC12 are output (program counter signals PC11 and PC12 in the period T2 in FIG. 7), respectively. Input to the multiplexing circuit 16. Further, the reference clock signal PC12 is input to the instruction memory 11, the first program counter control unit 12, and the second program counter control unit 13, respectively. When the program counter signal PC12 is input to the instruction memory 11, the sequence control instruction stored in the address 1 of the instruction memory 11 is read.

  Specifically, the sequence control instruction “LOOP 4 AA” stored at the address 1 of the first sequence control instruction storage area R1 and the sequence control stored at the address 1 of the second sequence control instruction storage area R2 The instruction “NOOP” and “LOOP 4 AA” stored at address 1 of the third sequence control instruction storage area R3 are read out and output as sequence control instructions S11 to S13, respectively (period in FIG. 7) Sequence control instructions S11 to S13 at T2. The sequence control command S11 is input to the first program counter control unit 12 and the second program counter control unit 13, and the sequence control commands S12 and S13 are input to the second program counter control unit 13.

  When the program counter signal PC12 is input to the first program counter control unit 12, the value is incremented by the adder 21 to become the value “2”, and is output to the selector 23 as the signal S21. When the sequence control command S11 is input to the first program counter control unit 12, the jump control circuit 22 outputs a selection signal L1 for selecting the signal S22 indicating the jump destination address included in the sequence control command S11. . This is because the sequence control command “LOOP” is input as the sequence control command S11 and the count signal CE indicates that counting is in progress (see FIG. 4).

  The selector 23 selects the signal S22 based on the selection signal L1 and outputs it as the program counter signal PC1 (program counter signal PC1 in the period T2 in FIG. 7). Referring to FIG. 7, the value of the program counter signal PC1 in the period T2 is “1”. This is because the jump destination address of the sequence control instruction “LOOP 4 AA” input as the sequence control instruction S11 is This is because “1”. The program counter signal PC1 output from the first program counter control unit 12 is temporarily stored in the register 14. The jump control circuit 22 outputs a control signal C1 that causes the loop counter 18 to count down. This is because the input sequence control command S11 is the sequence control command “LOOP” and the count signal CE indicates that counting is in progress.

  On the other hand, when the program counter signal PC12 is input to the second program counter control unit 13, the value “2” is added by the adder 32 to become the value “3”, which is output to the selector 34 as the signal S31. When the sequence control instructions S11 to S13 are input to the second program counter control unit 13, the jump control circuit 33 is included in the sequence control instruction S13 based on the combination of the sequence control instructions S11 to S13 and the count signal CE. The selection signal L2 for selecting the signal S34 indicating the jump destination address is output (see FIG. 6). The selector 34 selects the signal S34 based on the selection signal L2 and outputs it as the program counter signal PC2 (program counter signal PC2 in the period T2 in FIG. 7). Referring to FIG. 7, the value of the program counter signal PC2 in the period T2 is “1”. This is because the jump destination address of the sequence control instruction “LOOP 4 AA” input as the sequence control instruction S13 is This is because “1”. The program counter signal PC2 output from the second program counter control unit 13 is temporarily stored in the register 15.

  The jump control circuit 33 outputs a control signal C2 that causes the loop counter 18 to count down. This is because the input sequence control instructions S11 and S13 are both the sequence control instruction “LOOP” and the count signal CE indicates that counting is in progress. As a result, the control signals C1 and C2 are input to the loop counter 18 twice in total, and the count value becomes “2” when the loop counter 18 counts down twice. Therefore, a count signal CE indicating the end of counting is output from the loop counter 18 to the first program counter control unit 12 and the second program counter control unit 13.

  Further, when the next clock signal CLK1 is output from the frequency divider circuit 17, it is input to the registers 14 and 15 and the program counter signals PC11 and PC12 are output respectively (program counter signals PC11 and PC12 in the period T3 in FIG. 7). , Input to the multiplexing circuit 16. Further, the reference clock signal PC12 is input to the instruction memory 11, the first program counter control unit 12, and the second program counter control unit 13, respectively.

  When the program counter signal PC12 is input to the instruction memory 11, the sequence control instruction stored in the address 1 of the instruction memory 11 is read. Specifically, as in the period T2 in FIG. 7, the sequence control instruction “LOOP 4 AA” stored in the address 1 of the first sequence control instruction storage area R1 and the second sequence control instruction storage area R2 The sequence control instruction “NOOP” stored at the address 1 and the “LOOP 4 AA” stored at the address 1 of the third sequence control instruction storage area R3 are read out as sequence control instructions S11 to S13, respectively. These are output (sequence control instructions S11 to S13 in period T3 in FIG. 7). The sequence control command S11 is input to the first program counter control unit 12 and the second program counter control unit 13, and the sequence control commands S12 and S13 are input to the second program counter control unit 13.

  When the program counter signal PC12 is input to the first program counter control unit 12, the value is incremented by the adder 21 to become the value “2”, and is output to the selector 23 as the signal S21. When the sequence control command S11 is input to the first program counter control unit 12, the jump control circuit 22 outputs a selection signal L1 for selecting the signal S21 output from the adder 21. This is because the input sequence control command S11 is the sequence control command “LOOP” and the count signal CE indicates the end of counting (see FIG. 4). The selector 23 selects the signal S21 based on the selection signal L1 and outputs it as the program counter signal PC1 (program counter signal PC1 in the period T3 in FIG. 7). The program counter signal PC1 output from the first program counter control unit 12 is temporarily stored in the register 14.

  On the other hand, when the program counter signal PC12 is input to the second program counter control unit 13, the value “2” is added by the adder 32 to become the value “3”, which is output to the selector 34 as the signal S31. The jump control circuit 33 of the second program counter control unit 13 outputs a selection signal L2 for selecting the signal S31 output from the adder 31. This is because the input sequence control command S11 is the sequence control command “LOOP”, the sequence control command S12 is the sequence control command “NOOP”, and the count signal CE indicates the count end (FIG. 6). reference). The selector 34 selects the signal S31 based on the selection signal L2 and outputs it as the program counter signal PC2 (program counter signal PC2 in the period T3 in FIG. 7). The program counter signal PC2 output from the second program counter control unit 13 is temporarily stored in the register 15.

  Further, when the next clock signal CLK1 is output from the frequency dividing circuit 17, it is input to the registers 14 and 15 and the program counter signals PC11 and PC12 are output (the program counter signals PC11 and PC12 in the period T4 in FIG. 7). ) And input to the multiplexing circuit 16. Further, the reference clock signal PC12 is input to the instruction memory 11, the first program counter control unit 12, and the second program counter control unit 13, respectively.

  When the program counter signal PC12 is input to the instruction memory 11, the sequence control instruction stored at address 3 of the instruction memory 11 is read. Specifically, the sequence control instruction “NOOP” stored at address 3 in the first sequence control instruction storage area R1 and the sequence control instruction “NOOP” stored in address 3 in the second sequence control instruction storage area R2 NOOP ”and“ undefined data ”stored at address 3 of the third sequence control instruction storage area R3 are read out and output as sequence control instructions S11 to S13, respectively (sequence in period T4 in FIG. 7) Control instructions S11-S13). The sequence control command S11 is input to the first program counter control unit 12 and the second program counter control unit 13, and the sequence control commands S12 and S13 are input to the second program counter control unit 13.

  When the program counter signal PC12 is input to the first program counter control unit 12, the value is incremented by the adder 21 to become the value “4” and is output to the selector 23 as the signal S21. When the sequence control command S11 is input to the first program counter control unit 12, the jump control circuit 22 outputs a selection signal L1 for selecting the signal S21 output from the adder 21 (see FIG. 4). The selector 23 selects the signal S21 based on the selection signal L1 and outputs it as the program counter signal PC1 (program counter signal PC1 in the period T4 in FIG. 7). The program counter signal PC1 output from the first program counter control unit 12 is temporarily stored in the register 14.

  On the other hand, when the program counter signal PC12 is input to the second program counter control unit 13, the value “2” is added by the adder 32 to become the value “5”, which is output to the selector 34 as the signal S31. When the sequence control instructions S11 to S13 are input to the second program counter control unit 13, the jump control circuit 33 is output from the adder 32 based on the combination of the sequence control instructions S11 to S13 and the count signal CE. The selection signal L2 for selecting the signal S31 is output (see FIG. 6). The selector 34 selects the signal S34 based on the selection signal L2 and outputs it as the program counter signal PC2 (program counter signal PC2 in the period T4 in FIG. 7). The program counter signal PC2 output from the second program counter control unit 13 is temporarily stored in the register 15.

  Thereafter, the same operation is sequentially repeated, and the program counter signals PC1 and PC2 sequentially output from the first program counter control unit 12 and the second program counter control unit 13 are temporarily stored in the registers 14 and 15, respectively. After that, the program counter signals PC11 and PC12 are sequentially input to the multiplexing circuit 16. Then, in the multiplexing circuit 16, the program counter signal PC11 and the program counter signal PC12 are multiplexed so as to be temporally aligned in this order and output as the program counter signal PC. By repeating the above operation, the sequence control circuit 1 generates a program counter signal PC whose value changes as “0, 1, 1, 1, 1, 1, 2, 3, 4,...” As shown in FIG. Output in synchronization with the reference clock CLK.

  The sequence control circuit 1 according to the present embodiment described above generates the program counter signals PC1 and PC2 by operating the first program counter control unit 12 and the second program counter control unit 13 with a period obtained by dividing the reference clock by two. The program counter signal PC obtained by multiplexing the program counter signals PC1 and PC2 is output in synchronization with the reference clock. For this reason, the reference clock CLK can be set to a higher frequency, and the program counter signal PC can be output at a higher speed than before.

  The semiconductor test apparatus according to the embodiment of the present invention has been described above, but the present invention is not limited to the above-described embodiment, and can be freely changed within the scope of the present invention. For example, in the above embodiment, the configuration includes two program counter control units (the first program counter control unit 12 and the second program counter control unit 13), but the number of program counter control units is three or more. You can also

  Further, by using the sequence control circuit 1 described in the above embodiment instead of the sequence control circuit 111 provided in the pattern generation apparatus 102 shown in FIG. 8, a pattern generation apparatus capable of generating a higher speed pattern is realized. be able to. Furthermore, a DUT that operates at high speed can be tested by providing such a pattern generator having the sequence control circuit 1 of this embodiment in the semiconductor test apparatus 100 shown in FIG.

It is a block diagram which shows the structure of the sequence control circuit by one Embodiment of this invention. It is a figure which shows an example of the sequence control command memorize | stored in the instruction memory. 4 is a block diagram showing a configuration of a first program counter control unit 12. FIG. 6 is a chart showing signal selection conditions of a jump control circuit 22 provided in the first program counter control unit 12. 3 is a block diagram showing a configuration of a second program counter control unit 13. FIG. 6 is a chart showing signal selection conditions of a jump control circuit 33 provided in the second program counter control unit 13. It is a timing chart of the signal output from each part of the sequence control circuit 1 by one Embodiment of this invention. It is a block diagram which shows schematic structure of a semiconductor test apparatus. It is a figure which shows an example of the test program produced by the user. 4 is a timing chart of signals output from each unit of the semiconductor test apparatus 100. 2 is a block diagram showing a configuration of a sequence control circuit 111. FIG. 4 is a timing chart of signals output from each unit of the sequence control circuit 111.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Sequence control circuit 11 Instruction memory 12 1st program counter control part 13 2nd program counter control part 16 Multiplex circuit 112 Instruction memory 113 Pattern generation circuit 200 DUT
P1 Test pattern PC Program counter signal PC
PC1 Program counter signal PC
PC2 Program counter signal PC
R1 First sequence control instruction storage area R2 Second sequence control instruction storage area R3 Third sequence control instruction storage area

Claims (7)

In a sequence control circuit that outputs a control signal for controlling a generation sequence of a predetermined pattern,
A storage unit for storing a sequence control command for generating the control signal;
A first control unit that generates a first control signal according to the sequence control instruction stored in the storage unit;
A second control unit that generates a second control signal following the first control signal using the sequence control command stored in the storage unit;
A multiplexing unit that multiplexes the first control signal generated by the first control unit and the second control signal generated by the second control unit and outputs the multiplexed signal as the control signal. Sequence control circuit to perform. The storage unit includes a first sequence control instruction for generating the first control signal;
A second sequence control command for generating the second control signal;
2. The sequence control according to claim 1, wherein when the first sequence control instruction is a jump instruction, a third sequence control instruction that is a jump destination sequence control instruction is stored in association with each address. circuit. The storage unit includes a first storage area that stores the first sequence control instruction;
A second storage area for storing the second sequence control instruction;
The sequence control circuit according to claim 2, further comprising: a third storage area that stores the third sequence control instruction.   The storage unit stores the first sequence control command, the second sequence control command, and the third sequence stored in association with an address specified by the second control signal generated by the second control unit. 4. The sequence control circuit according to claim 2, wherein a sequence control instruction is read out. The first control unit generates the first control signal according to the first sequence control command read from the storage unit,
The second control unit generates the second control signal according to a combination of the first sequence control command, the second sequence control command, and the third sequence control command read from the storage unit. The sequence control circuit according to claim 4. In a pattern generator for generating a predetermined pattern,
The sequence control circuit according to any one of claims 1 to 5,
An instruction memory for storing a pattern generation instruction for generating the predetermined pattern, and reading the pattern generation instruction stored in an address specified by the control signal output from the sequence control circuit;
A pattern generation apparatus comprising: a pattern generation circuit configured to perform a predetermined operation according to the pattern generation instruction read from the instruction memory and generate the predetermined pattern. In a semiconductor test apparatus that applies a test pattern to a device under test to test the device under test,
A semiconductor test apparatus comprising the pattern generation apparatus according to claim 6, wherein the predetermined pattern is generated as the test pattern.

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