JP5126090B2 - Memory test equipment - Google Patents

Description

  The present invention relates to a memory test apparatus for testing a semiconductor memory, and more particularly to a memory test apparatus for testing a semiconductor memory such as an SDRAM (Synchronous Dynamic Random Access Memory) having a burst function capable of continuous access. The present invention relates to a technique suitable for application.

  In a memory test apparatus (memory tester) for testing a semiconductor memory, a write / read test is performed on each memory cell of a memory to be tested (memory to be measured) to determine whether the memory cell is good or bad. The memory under test includes an SDRAM having a burst function (burst mode) that reads and writes data continuously while automatically generating a subsequent address when a certain address is given from the outside.

  FIG. 1 shows a general configuration of a memory tester for testing an SDRAM. The memory tester of FIG. 1 controls a sequence of programs such as jumps and loops and outputs a program counter signal (PC value), and an instruction memory 12 that outputs an instruction code (instruction) specified by the PC value. The address generation circuit 13 generates address signals of the memory under test 20 and the failure analysis memory 30 according to the instruction code read from the memory, and the generated address signals are in a desired order according to the cell arrangement in the memory under measurement. The address scramble circuit 14 converts the address signal into an address signal for reading / writing to the cell, and the address conversion circuit 15 converts the address signal output from the address generation circuit 13 into an address signal that facilitates failure analysis such as cumulative storage of fail data. Is provided.

  The memory tester also includes a data generation circuit 16 that generates data (test pattern) for testing the memory under test in accordance with the instruction code read from the instruction memory 12, a chip selection signal for the memory under test 20, read / write A control signal generating circuit 17 that generates a control signal, a waveform shaping circuit 18 that shapes a signal input to the memory under measurement 20 at a predetermined timing, a data signal read from the memory under measurement 20 and an expected value. An expected value judging circuit 19 for comparing and judging is provided. When the mismatch between the read data and the expected value is detected by the expected value judging circuit 19, it is determined which address of the memory 20 to be measured has failed. 30.

  FIG. 3 shows a general configuration of the address generation circuit 13 in the conventional memory tester. As shown in FIG. 3, the conventional address generation circuit includes an address generation circuit MAG to be measured, a counter CNT operated by a clock CK having a predetermined frequency, and an m generated by the address generation circuit MAG to be measured. It comprises an arithmetic logic circuit ALU that performs a logical operation such as addition or exclusive OR of a part of the bit address (lower n bits) and the count value of the counter CNT. In addition, as invention regarding a memory tester, there exist some which are described in patent document 1, for example.

JP 2004-133960 A

  When generating an address corresponding to the burst mode of the SDRAM, an address generation circuit in a conventional memory tester calculates the lower-order bits of the address and the value of the address counter, and uses the calculated value as an address for a failure analysis memory. Was configured to generate as.

  When testing a packaged memory, there is no problem with such an address generation method, but the manufacturer of the memory also conducts a memory test in the wafer state, and the wafer test does not limit continuous addresses to lower bits. You may perform your own test. In the conventional address generation circuit having the configuration shown in FIG. 3, the address of the failure analysis memory corresponding to the test in which the continuous address is not limited to the lower bits, which is performed in the memory test in the wafer state. There was a problem that it could not be generated.

  The present invention has been made paying attention to the above-mentioned problems, and its purpose is an address that can also generate an address of a failure analysis memory corresponding to a burst mode test in which a continuous address is not limited to lower bits. An object of the present invention is to provide a memory test apparatus including a generation circuit.

In order to achieve the above object, the invention described in claim 1
A memory test apparatus comprising an address generation circuit for generating an address for storing information on a defective bit in an address for testing a memory under test having a burst function and a defect analysis memory,
The address generation circuit includes:
A start address generation circuit capable of generating a start address for a test in a burst mode of the memory under measurement;
For a failure analysis memory for generating an address for accessing the failure analysis memory by changing any of a plurality of bits of the address for testing the memory under test generated by the head address generation circuit in accordance with the burst mode An address generation circuit ,
The defect analysis memory address generation circuit includes:
A first selection circuit for extracting a plurality of arbitrary bits from an address for testing the memory under measurement generated by the head address generation circuit;
An arithmetic circuit that performs predetermined arithmetic processing on the plurality of bits extracted by the first selection circuit;
A second bit in which a plurality of bits resulting from the arithmetic processing by the arithmetic circuit are replaced with a plurality of bits extracted by the first selection circuit among the addresses for testing the memory under test generated by the head address generation circuit; And a selection circuit .

  According to the above-described configuration, the failure analysis memory address corresponding to the burst mode test in which the continuous address is not limited to the lower bits can be generated, so that the test executed only in the wafer state is also possible.

According to a second aspect of the present invention, in the first aspect of the present invention, the failure analysis memory address generation circuit includes a counter that performs a count operation according to a clock signal, and the arithmetic circuit is covered by the first selection circuit. A plurality of bits taken out from the address for testing the measurement memory and the value of the counter are calculated and output.

According to a third aspect of the present invention, in the first or second aspect of the present invention, the failure analysis memory address generation circuit extracts from the test memory address generated by the head address generation circuit. A register capable of setting information designating an arbitrary plurality of bits is provided. Accordingly, it is possible to easily perform setting for generating an address corresponding to a different burst mode test of a memory under measurement having a different cell arrangement.

According to a fourth aspect of the present invention, in the third aspect of the invention, the number of bits of any of the plurality of bits to be taken out from the address for testing the memory under test is variable. Thereby, an address corresponding to a burst mode test having a different burst length can be generated.

  According to the present invention, it is possible to generate a failure analysis memory address corresponding to a burst mode test in which a continuous address is not limited to the lower bits, thereby enabling an address generation that enables a test executed only in a wafer state. There is an effect that a memory test device including a circuit can be realized.

1 is a block diagram showing a configuration example of a memory tester for testing a suitable SDRAM to which the present invention is applied. FIG. 3 is a block diagram illustrating a specific configuration example of an address generation circuit in the memory tester of the embodiment. FIG. It is a block diagram which shows the specific structural example of the address generation circuit in the conventional memory tester.

  DESCRIPTION OF EXEMPLARY EMBODIMENTS Hereinafter, preferred embodiments of the invention will be described with reference to the drawings.

  FIG. 1 shows a configuration example of a memory tester for testing a suitable SDRAM to which the present invention is applied.

  As shown in FIG. 1, the memory tester of this embodiment is designated by a sequence control circuit 11 that outputs a program counter signal (PC value) by controlling a program sequence such as a jump or loop, and is designated by a PC value. An instruction memory 12 that outputs an instruction code (instruction), an address generation circuit 13 that generates an address signal of the memory 20 to be measured and a failure analysis memory 30 according to the instruction code read from the memory, and a measurement of the generated address signal An address scramble circuit 14 that converts an address signal corresponding to the cell arrangement in the memory, and an address conversion circuit that converts the address signal output from the address generation circuit 13 into an address signal that facilitates failure analysis, such as cumulative storage of fail data. 15.

  In addition, the memory tester of the present embodiment includes a data generation circuit 16 that generates data (test pattern) for testing the memory under test in accordance with the instruction code read from the instruction memory 12, and a chip selection signal for the memory under test 20 From the control signal generation circuit 17 that generates a read / write control signal, the waveform shaping circuit 18 that shapes the signal input to the memory under measurement 20 so as to change at the timing specified by the program, and the memory under measurement 20 An expected value determination circuit 19 for comparing and determining the read data signal and the expected value is provided. When the expected value determination circuit 19 detects a mismatch between the read data and the expected value, any of the memories 20 to be measured 20 Whether or not a failure has occurred at the address is stored in the failure analysis memory 30.

  The memory tester according to the present embodiment is configured to be able to test the SDRAM as the memory under test 20. One of the features of the SDRAM is the burst mode access in which data is continuously read / written while an address following the address is automatically generated when a leading address is given from the outside. In this burst mode, data called a burst length that specifies the number of data that are continuously input and output is given together with the head address. The SDRAM includes an internal counter, and when a head address is given, the internal counter is incremented to generate continuous addresses.

  The burst length is variable. When “2” is designated as the burst length, one address following the head address is generated inside the SDRAM, and two data corresponding to the two addresses are read or written. When “4” is designated as the burst length, three addresses following the head address are generated inside the SDRAM, and four data corresponding to the four addresses are read or written, and “8” is designated as the burst length. Is designated, seven addresses following the head address are generated in the SDRAM, and eight data corresponding to the eight addresses are read or written. Further, when “16” is designated as the burst length, 15 addresses following the head address are generated inside the SDRAM, and 16 data corresponding to the 16 addresses are read or written. When the burst length is “16” at the maximum, the code specifying the burst length is 4 bits.

  There are two types of burst modes, a sequential type and an interleave type. In the sequential type, the start address and the counter value are added to generate a continuous address, and in the interleave type, the start address and the counter value are exclusive ORed to generate a continuous address.

  In order to cope with the access in the burst mode in the SDRAM as described above, the address generation circuit 13 of the memory tester in FIG. 1 generates a head address for the SDRAM and is generated in the memory 20 to be measured. An address similar to the address is generated for the defect analysis memory 30. The memory under test 20 operates using the address converted by the address scramble circuit 14 as the head address, but the failure analysis memory 30 uses the address before the address scramble without being aware of the cell arrangement of the memory under test as the head address. The address converted at 15 is used as the head address.

  FIG. 2 shows a specific configuration example of the address generation circuit 13 in the memory tester of the present embodiment.

  As shown in FIG. 2, the address generation circuit 13 of the present embodiment is generated by a memory under test address generation circuit MAG, a counter CNT operated by a clock CK having a predetermined frequency, and a memory under test address generation circuit MAG. 1st selector SEL1 that selects an arbitrary n bit from the m-bit address and selects “0” as the other bit and transmits it to the arithmetic circuit ALU, and addition or exclusion of the count value of the counter CNT An arithmetic logic circuit ALU that performs logical operations such as logical OR is provided. The arithmetic logic circuit ALU is designated which operation is to be performed by the instruction code read from the instruction memory 12. The counter CNT is reset before the start of address generation and is counted up in synchronization with the clock CK.

  Further, the address generation circuit 13 outputs n bits selected by the first selector SEL1 out of the m bits address generated by the memory generation address generation circuit MAG to be n bits output from the arithmetic logic circuit ALU. A second selector SEL2 for transmitting m-bit data replaced with data as a failure analysis memory address, and a register REG for storing setting information for designating selection bits in the first selector SEL1 and the second selector SEL2 are provided. .

  For example, the first selector SEL1 selectively transmits / blocks m unit selectors having two inputs and one output, a shift register capable of shifting the data taken in parallel in the lower bit direction, and the lower n bits of the shift register. And possible transmission gates. The second selector SEL2 includes, for example, a transmission gate capable of selectively transmitting and blocking the n-bit output of the arithmetic logic circuit ALU, a shift register capable of shifting the data taken in parallel in the upper bit direction, and two inputs and one output M unit selectors. The bits selected by the first selector SEL1 and the second selector SEL2 are arbitrary n bits in the m-bit address, but these bits are consecutive bits.

  Next, in the circuit of FIG. 2, for example, out of the m-bit memory addresses A0 to Am-1, the bits A0 to A9 and A13 to Am-1 use the bits of the memory address to be measured as they are, The case where address bits corresponding to the burst mode are generated for bits A10 to A12 will be specifically described.

  In this case, the register REG selects bits A10 to A12 of the memory address to be measured as bits 0 to 2 of the output of the selector SEL1, and sets bits 3 to (n-1) to select "0". . On the other hand, the selector SEL2 selects the bits A0 to A9 and A13 to Am-1 of the memory address to be measured for the output bits 0 to 9 and 13 to (m-1), and the bits 10 to 12 are for the arithmetic circuit ALU. Set to select bits 0-2 of output.

  As a result, the arithmetic circuit ALU calculates the bits A10 to A12 of the memory address to be measured selected by the selector SEL1 and the count value from the counter CNT, and among the memory addresses to be measured A0 to Am-1 by the selector SEL2. It is possible to generate and output a failure analysis memory address corresponding to the burst mode in which bits A10 to A12 are replaced with counter values. As a result, it becomes possible to generate a failure analysis memory address corresponding to a burst mode test in which the continuous address is not limited to the lower bits.

  Although the invention made by the present inventor has been specifically described based on the embodiment, the present invention is not limited to the above embodiment. For example, the sequence control circuit 11 can be configured to determine an instruction code to be read next from the instruction memory 12 by feeding back a part of the instruction code read from the instruction memory 12. In addition, the counter CNT may be omitted by providing the arithmetic circuit ALU in the circuit of FIG. 2 with a counter function.

  In the above description, the invention made by the present inventor has been described as being applied to a memory tester capable of testing SDRAM, which is the field of use behind the invention. However, the present invention is not limited to this and is not limited thereto. It can be widely used in a memory test apparatus that wants to test a semiconductor memory having a function.

DESCRIPTION OF SYMBOLS 11 Sequence control circuit 12 Instruction memory 13 Address generation circuit 14 Address scramble circuit 15 Address conversion circuit 16 Data generation circuit 17 Control signal generation circuit 18 Waveform shaping circuit 19 Expected value determination circuit 20 Memory to be measured 30 Defect analysis memory

Claims (4)

A memory test apparatus comprising an address generation circuit for generating an address for storing information on a defective bit in an address for testing a memory under test having a burst function and a defect analysis memory,
The address generation circuit includes:
A start address generation circuit capable of generating a start address for a test in a burst mode of the memory under measurement;
For a failure analysis memory for generating an address for accessing the failure analysis memory by changing any of a plurality of bits of the address for testing the memory under test generated by the head address generation circuit in accordance with the burst mode An address generation circuit ,
The defect analysis memory address generation circuit includes:
A first selection circuit for extracting a plurality of arbitrary bits from an address for testing the memory under measurement generated by the head address generation circuit;
An arithmetic circuit that performs predetermined arithmetic processing on the plurality of bits extracted by the first selection circuit;
A second bit in which a plurality of bits resulting from the arithmetic processing by the arithmetic circuit are replaced with a plurality of bits extracted by the first selection circuit among the addresses for testing the memory under test generated by the head address generation circuit; A selection circuit;
A memory test apparatus comprising: The defect analysis memory address generation circuit includes a counter that performs a count operation according to a clock signal, and the arithmetic circuit includes a plurality of bits extracted from an address for testing the memory under measurement by the first selection circuit and the counter The memory test apparatus according to claim 1 , wherein the value is calculated and output. The address generation circuit for the failure analysis memory includes a register capable of setting information specifying any of a plurality of bits to be extracted from an address for testing the memory under measurement generated by the head address generation circuit. The memory test apparatus according to claim 1 or 2 . 4. The memory test apparatus according to claim 3 , wherein the number of bits of any of a plurality of bits to be taken out from an address for testing the memory under test is variable.

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