JP2008091702A - Solid-state imaging device and manufacturing method thereof, and electronic information apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a solid-state imaging element which has a high-density impurity layer formed by ion injection at an element separation region end so that the element separation region does not come into contact with a depletion layer, pixel portions being downscaled. <P>SOLUTION: When solid-state imaging devices 10, 10A, or 10B having pixel portions separated by an element area region 13 is manufactured, a part to become an active region is patterned and ion injection using the active pattern as a mask 19 is performed on a semiconductor substrate 11 to form a part or the whole of the ion injection region as the element separation region 13. Unlike conventional techniques wherein ion injection is performed using a resist mask provided at a predetermined distance d from an element separation region end, the resist mask is not misaligned and the distance d from the end of the element separation region 13 is made stable to stably form a p-type impurity region 133. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  INDUSTRIAL APPLICABILITY The present invention is used for a MOS type sensor or a CMOS type sensor that can image light from a subject by photoelectric conversion so that a depletion layer does not directly contact an element isolation region in which each pixel portion is separated. In addition, a solid-state imaging device manufacturing method in which a high-concentration impurity layer is formed at the end of the element isolation region by ion implantation, a solid-state imaging device manufactured thereby, and the solid-state imaging device used as an image input device in an imaging unit, for example The present invention relates to electronic information devices such as digital cameras such as digital video cameras and digital still cameras, image input cameras, scanners, facsimiles, and camera-equipped mobile phone devices.

  2. Description of the Related Art In recent years, CMOS type sensors that are advantageous for achieving high-speed operation and low power consumption have been drawing attention in place of CCD (Charge Coupled Device) type sensors as solid-state imaging devices. One of the factors that determine the image quality of this CMOS type sensor is dark current, and this dark current particularly affects sensitivity at low luminance and display roughness.

  This dark current is caused by the interface state generated at the interface between the semiconductor substrate and the oxide film, and in particular, it has been found that the interface state in the element isolation region that separates the pixel portions is a big problem. Therefore, many proposals have been made to solve this problem.

  For example, Patent Document 1 and Patent Document 2 propose a solid-state imaging device in which a high-concentration impurity layer is formed at the end of an element isolation region by ion implantation so that a depletion layer does not contact the element isolation region.

As another method, for example, Patent Document 3 proposes a solid-state imaging device in which a protective gate electrode is formed in an element isolation region so that a depletion layer is not in contact therewith. For example, Patent Document 4 proposes a solid-state imaging device in which a gate electrode is embedded in an element isolation region and a voltage is applied to the gate electrode to suppress the depletion layer from extending. Further, for example, Patent Document 5 proposes a solid-state imaging device in which a drain region for discharging generated current is provided next to an element isolation region.
These conventional solid-state imaging devices proposed in Patent Documents 3 to 5 are not practical because the manufacturing conditions are complicated and they are not suitable for pixel miniaturization.

  Therefore, here, as a method that can be most easily manufactured and expected to have a dark current reduction effect, a conventional method for manufacturing a solid-state imaging device disclosed in Patent Document 1 will be described with reference to FIGS. This will be described in detail with reference to (b).

  FIG. 8A and FIG. 8B are main part longitudinal sectional views showing one pixel in each manufacturing process for explaining a conventional method of manufacturing a solid-state imaging device.

First, as shown in FIG. 8A, an insulating film 102 made of, for example, SiO ₂ is formed on the surface of the n-type semiconductor substrate 101, and trench isolation ( A pixel separation groove 103 is formed.
Next, a resist mask 104 is formed in the pixel region of the active region separated by the groove 103 so as to be separated from the end of the trench separation groove 103 toward the active region by a predetermined distance d1. A p-type impurity 105 is ion-implanted from above the resist mask 104, and a second p-type semiconductor well region 106 is formed on the semiconductor substrate 101 so that a part of the p-type impurity 105 protrudes from the trench 103 to the pixel region side (resist mask 104 side). (P-well2) is formed.
At this time, the second p-type semiconductor well region 106 is formed with a sufficient width and depth over the side and bottom of the groove 103, and the insulating film embedded in the active region and the groove 103 at the side and bottom of the groove 103. It is formed so as to surround all of the interface.

Further, as shown in FIG. 8B, for example, a SiO ₂ film material is buried in the trench 103 as the buried insulating film 107 by, for example, a CVD (chemical vapor deposition) method, and the surface thereof is flattened to obtain the trench 103. Then, a trench element isolation layer 108 made of the buried insulating film 107 is formed.
After that, a resist mask 109 is formed so that the termination exists on the trench element isolation layer 108 except for the pixel region, and a p-type impurity and an n-type are selectively selectively formed in the depth direction from the resist mask 109 on the pixel region side. Impurities are ion-implanted to form a first p-type semiconductor well region 110 connected to the second p-type semiconductor well region 106 at a deep position in the semiconductor substrate 101, and charge accumulation on the surface side of the semiconductor substrate 101. An n-type semiconductor region 111 to be a region is formed, and a high-concentration p-type semiconductor region 112 connected to the second p-type impurity well region 106 is further formed at the interface between the n-type semiconductor region 111 and the semiconductor insulating film 102. To do. At this time, the semiconductor substrate portion between the n-type semiconductor region 111 on the surface side and the first p-type semiconductor well region 110 is an n-type impurity region 113 having a lower concentration than the n-type semiconductor region 111.

  Here, the ion implantation process of the first p-type semiconductor well region 110, the n-type semiconductor region 111, and the high-concentration p-type semiconductor region 112 is shown in one figure, but this is performed in the same process. However, it may be a separate process for the purpose of forming other sites.

In this way, a sensor part (photodiode part) as a target photoelectric conversion part is formed. This sensor unit includes a so-called HAD (Hole Accumulation Diode) by a high-concentration p-type semiconductor region 112, an n-type semiconductor region 111, a low-concentration n-type impurity region 113, and a first p-type semiconductor well region 110. It is configured as a sensor unit.
JP 2000-299453 A JP 2004-207455 A JP 2003-218337 A JP 2005-101864 A JP 2005-175104 A

  However, the conventional method for manufacturing a solid-state imaging device has the following problems.

  Since the second p-type semiconductor well region 106 is formed using the resist mask 104, the end of the second p-type semiconductor well region 106 and the end of the trench element isolation layer 108 are shown in FIG. At the distance d1, dimensional variations due to misalignment of the resist mask 104 always occur. Therefore, in order to prevent the depletion layer from the n-type semiconductor region 111 and the n-type impurity region 113 constituting the sensor part (photodiode) from directly contacting the end of the trench element isolation layer 108, the second Considering the variation in the formation position of the p-type semiconductor well region 106 with respect to the trench element isolation layer 108, it is necessary to increase the distance d1. However, if the distance d1 is increased, it becomes impossible to form further fine pixels as required in the future.

  The present invention solves the above-described conventional problems, and forms a high-concentration impurity layer at the edge of the element isolation region by ion implantation so that the depletion layer does not directly contact the element isolation region. In a solid-state imaging device of the present invention, a manufacturing method of a solid-state imaging device capable of simplifying the manufacturing conditions without being complicated as in the prior art and miniaturizing pixels, a solid-state imaging device manufactured thereby, and An object of the present invention is to provide an electronic information device using the solid-state imaging device as an image input device in an imaging unit.

  The solid-state imaging device manufacturing method of the present invention is a solid-state imaging device manufacturing method for manufacturing a solid-state imaging device in which each active region is element-isolated by an element isolation region. A mask forming process for forming a mask patterned on the semiconductor substrate so as to open around the active region, an ion implantation process for performing ion implantation on the semiconductor substrate from the mask, and the ion using the mask An element isolation region forming step for forming the element isolation region before, after, or after implantation, thereby achieving the above object.

  Preferably, a mask in the method for manufacturing a solid-state imaging device of the present invention is used for the ion implantation and for forming an element isolation groove in the element isolation region.

  Further preferably, the active region in the method for manufacturing a solid-state imaging device of the present invention includes a pixel unit, a signal detection unit that detects a signal from the pixel unit, and a gate region between the pixel unit and the signal detection unit. Have

  Further preferably, the direction of ion implantation in the method for manufacturing a solid-state imaging device of the present invention is inclined at least toward the active region side.

  Further preferably, the method further includes a heat treatment step of diffusing and activating the implanted ions by heat treatment after the ion implantation in the method of manufacturing the solid-state imaging device of the present invention.

  Still preferably, in a solid-state imaging device manufacturing method according to the present invention, the element isolation region forming step includes a groove forming step of forming a groove by etching the semiconductor substrate using the mask after the heat treatment step.

  Still preferably, in a solid-state imaging device manufacturing method according to the present invention, the element isolation region forming step includes a groove forming step of forming a groove by etching the semiconductor substrate using the mask after the ion implantation.

  Further preferably, the element isolation region forming step in the method for manufacturing a solid-state imaging device of the present invention includes a groove forming step of forming a groove by etching the semiconductor substrate using the mask before the ion implantation.

  Further preferably, ion implantation is performed while rotating the semiconductor substrate in the method of manufacturing the solid-state imaging device of the present invention.

  Further preferably, the ion implantation direction in the method of manufacturing a solid-state imaging device of the present invention is such that the implantation angle from the perpendicular to the main surface of the semiconductor substrate is in the range of 0 to 7 degrees or 10 to 30 degrees. Set.

  Further preferably, ion implantation in the method for manufacturing a solid-state imaging device of the present invention is performed in a state where the mask is retracted by a predetermined amount toward the active region.

  Further preferably, the element isolation region forming step in the method of manufacturing a solid-state imaging device of the present invention includes a sidewall forming step of forming a sidewall on at least the side wall of the active region of the mask, the mask and the sidewall Forming a groove by etching the semiconductor substrate by using the method.

  Further preferably, the element isolation region forming step in the method of manufacturing a solid-state imaging device of the present invention further includes an insulating region forming step of forming an insulating region by embedding an insulating film in the groove.

  Further preferably, ion implantation in the method for manufacturing a solid-state imaging device of the present invention is performed at an acceleration energy of 500 KeV or more and 800 KeV or less.

  Further preferably, ion implantation is performed a plurality of times in the method for manufacturing a solid-state imaging device of the present invention.

Further preferably, ion implantation in the method for manufacturing a solid-state imaging device of the present invention is performed at an acceleration energy of 500 KeV to 800 KeV and a concentration of 1E11 / cm ^{2 to} 1E12 / cm ² and an acceleration energy of 200 KeV to 300 KeV and a concentration of 1E11 / cm ^2. performed for each condition of a concentration 1E12 / cm ² or more 1E13 / cm ² or less below 100 KeV 1E12 / cm ² or less and an acceleration energy 40KeV or more.

Further preferably, the ion implantation in the method for manufacturing a solid-state imaging device of the present invention is performed as a first ion implantation under the condition of an acceleration energy of 20 KeV to 60 KeV and a concentration of 1E12 / cm ^{2 to} 1E13 / cm ^2. After the separation groove is formed, second ion implantation is performed using the mask.

Further preferably, the second ion implantation in the method for manufacturing a solid-state imaging device of the present invention is performed under the conditions of an acceleration energy of 20 KeV to 40 KeV and a concentration of 1E12 / cm ^{2 to} 1E13 / cm ² .

Further preferably, ion implantation in the manufacturing method of the solid-state imaging device of the present invention is performed under the condition that the acceleration energy is 20 KeV or more and 40 KeV or less and the concentration is 1E12 / cm ² or more and 1E13 / cm ² or less after forming the groove for element isolation. Do.

  Further preferably, boron ions are implanted by ion implantation in the method for manufacturing a solid-state imaging device of the present invention to form a p-type impurity region.

  Further preferably, the depth of the groove in the method for manufacturing a solid-state imaging device of the present invention is set to 200 nm or more and 400 nm or less.

  Further preferably, the width of the groove in the method for manufacturing a solid-state imaging device of the present invention is set to 0.1 μm or more and 1.0 μm or less.

  Further preferably, the width of the groove in the method for manufacturing a solid-state imaging device of the present invention is set to 0.2 μm or more and 0.3 μm or less.

  Further preferably, in the method for manufacturing a solid-state imaging device of the present invention, the distance from the end of the groove to the end of the active region is set within a range of 0.01 μm or more and 0.5 μm or less, and from the end of the groove An ion implantation region by the ion implantation is formed up to the end of the active region.

  Further preferably, in the method of manufacturing a solid-state imaging device according to the present invention, a distance from the end of the groove to the end of the active region is set within a range of 0.03 μm or more and 0.1 μm or less, and An ion implantation region by the ion implantation is formed up to the end of the active region.

  Further preferably, in the method for manufacturing a solid-state imaging device according to the present invention, the distance from the end of the element isolation region to the end of the active region is set to the acceleration energy and the implantation concentration by the ion implantation, and the implantation after the ion implantation. The temperature is adjusted by at least one of the temperature and time of the thermal diffusion treatment of ions.

  Further preferably, the mask in the method for manufacturing a solid-state imaging device of the present invention is composed of a composite film of an oxide film, a nitride film and a resist film.

  Further preferably, the thickness of the resist film in the method for manufacturing a solid-state imaging device of the present invention is set within a range of 500 nm to 1500 nm.

  Further preferably, in the method of manufacturing a solid-state imaging device according to the present invention, the ion implantation is performed in a state where the resist film of the mask is retracted by a predetermined amount toward the active region.

  Furthermore, it is preferable that the method further includes a photodiode forming step in which a photodiode for photoelectrically converting light to obtain a signal charge is formed as a pixel portion in the active region in the method for manufacturing a solid-state imaging device of the present invention.

  Further preferably, in the method for manufacturing a solid-state imaging device according to the present invention, a p-type impurity region is formed as an ion implantation region by the ion implantation so as to have a higher concentration than a p-type well region constituting the photodiode. .

  The solid-state imaging device of the present invention is a solid-state imaging device manufactured by the method for manufacturing a solid-state imaging device of the present invention, wherein the element isolation region is provided between the active regions, the element isolation region and the active region An ion implantation region is provided between the regions, and thereby the above-described object is achieved.

  The electronic information device of the present invention is such that the solid-state imaging device of the present invention is provided in an imaging unit, thereby achieving the above object.

  The operation of the present invention will be described below with the above configuration.

  In the present invention, when manufacturing a solid-state imaging device in which pixel portions are separated by an element isolation region, a mask patterned so as to open the periphery of the active region between the active regions, leaving a portion to be an active region, is used as a semiconductor. It is formed on the substrate, and ion implantation is performed on the semiconductor substrate from above the mask, and an element isolation region is formed before and after or after this ion implantation using the mask. In this way, ion implantation and formation of an element isolation region (formation of an element isolation trench) are performed using the same mask. As a result, the edge of the insulating region constituting the element isolation region does not occur without mask misalignment as in the prior art in which ion implantation is performed using a mask provided to be separated from the edge of the element isolation region by a predetermined distance d. Thus, it is possible to stably form the distance d from, for example, the end of the p-type impurity region by ion implantation. The p-type impurity region is provided as a depletion layer stopper so that the depletion layer from the photodiode does not contact the element isolation region, and the interface between the oxide film and the semiconductor in the element isolation portion is provided by the p-type impurity region. It is possible to prevent dark current from being generated due to the interface state generated in.

  A trench for element isolation is formed by etching the semiconductor substrate using a mask after ion implantation, and an insulating film is embedded in the trench, so that a part of the ion implantation region around the pixel portion between each pixel portion or this It is possible to make the whole including the element isolation region. In the case where the implanted ions are diffused and activated by heat treatment after the ion implantation, the semiconductor substrate is etched using the mask after this heat treatment step to form a groove (Embodiment 1). By embedding an insulating film in this trench, it is possible to make part of the ion implantation region around the pixel portion between the pixel portions or all including the ion implantation region as an element isolation region. Further, ion implantation is performed in a state where the mask is retracted by a predetermined amount toward the active region side, a sidewall is formed at least on the side wall on the active region side of the mask, and the semiconductor substrate is etched using the mask and the sidewall. A groove is formed (Embodiment 3). By embedding an insulating film in this trench, it is possible to make part of the ion implantation region around the pixel portion between the pixel portions or all including the ion implantation region as an element isolation region.

  In this case, for example, the p-type impurity region in the ion-implanted region functions not only as a depletion layer stopper from the photodiode, but at the same time, element isolation between the pixel portions is effectively performed by the p-type impurity region at a deep position where ions are implanted at the same time. Can be performed. This makes it possible to form a fine element isolation region having a high element isolation capability and to stably form, for example, a p-type impurity region of an ion implantation region at least at the end of the element isolation region on the active region side.

  Further, by etching the semiconductor substrate using a mask before ion implantation, an element isolation trench is formed, and after ion implantation is performed from above the trench, an insulating film is buried in the trench so that each pixel portion is A part of the ion implantation region around the pixel portion or the entire region including the ion implantation region can be used as an element isolation region. Also in this case, for example, the p-type impurity region in the ion implantation region functions not only as a depletion layer stopper from the photodiode, but also the element isolation between the pixels is effective by the p-type impurity region in the deep position where ions are implanted at the same time. (Embodiment 2). As a result, ion implantation can be performed under low energy conditions with little damage, and an element isolation region that is fine and has high element isolation capability is formed, and at the end of the element isolation region on the active region side, for example, a p-type impurity region Can be formed stably.

  Furthermore, by performing ion implantation by retracting at least a part of the mask to the active region side, it is possible to cope with the case where a finer element isolation region is formed.

  Furthermore, by setting the acceleration energy to 500 KeV or more at the time of ion implantation, it becomes possible to implant impurities effectively even when the width of the element isolation region is quite narrow.

  As described above, according to the present invention, when manufacturing a solid-state imaging device in which the active regions are separated from each other by the element isolation region, the periphery of the active regions between the active regions is opened except for the portion that becomes the active region. Using the mask thus patterned, ion implantation and formation of element isolation regions (of which element isolation trenches are formed) can be simplified without complicating the manufacturing conditions as in the prior art. The ion implantation region can be stably formed at the end of the element isolation region. By this ion implantation region, the depletion layer can be prevented from being in direct contact with the element isolation region, and a solid-state imaging device with good image quality with reduced dark current can be obtained, and the pixel can be miniaturized. it can.

  A trench is formed by etching the semiconductor substrate using a mask after ion implantation, and an insulating film is embedded in the trench, and a region including a part of the ion implantation region around the active region or the entire region including this is separated into an element isolation region. As a result, it is possible to form a fine element isolation region having a high isolation capability, and to stably form, for example, a p-type impurity region of an ion implantation region at the end of the element isolation region. In this case, when the implanted ions are diffused and activated by heat treatment after ion implantation, the semiconductor substrate can be etched using the mask after this heat treatment step to form a groove. Also, ion implantation is performed with the mask set back by a predetermined amount toward the active region, a sidewall is formed on at least the sidewall of the active region, and the semiconductor substrate is etched using the mask and the sidewall. Grooves can also be formed.

  In addition, a groove is formed by etching the semiconductor substrate using a mask before ion implantation, and after the ion implantation, an insulating film is embedded in the groove to include a part of the ion implantation region around the active region. By forming the region or the entire region including this as an element isolation region, ion implantation is performed under a low energy condition with little damage to form a fine and high element isolation region, and an ion implantation region on the element isolation region side. For example, a p-type impurity region can be stably formed.

  Furthermore, it is possible to cope with the case where a finer element isolation region is formed by performing ion implantation by retracting at least a part of the mask toward the active region. Further, by setting the acceleration energy to 500 KeV or more at the time of ion implantation, impurities can be effectively implanted even when the width of the element isolation region is quite narrow.

Embodiments 1 to 3 of the method for manufacturing a solid-state imaging device of the present invention will be described in detail below with reference to the drawings.
(Embodiment 1)
In the first embodiment, when ion implantation with high acceleration energy and formation of an element isolation region (formation of an element isolation groove) are performed using a mask, the implanted ions are diffused and activated by heat treatment after ion implantation. A case where an element isolation region is formed by forming a trench by etching a semiconductor substrate using this mask and forming an insulating region by embedding an insulating film in the trench will be described later with reference to FIGS. To do.

  FIG. 1 is a longitudinal sectional view of a main part showing one pixel of a basic unit of a solid-state imaging device according to Embodiment 1 of the present invention. Here, although one pixel is shown as a basic unit, a plurality of pixels are actually provided in a planar shape.

  In FIG. 1, the solid-state imaging device 10 according to the first embodiment is used as each pixel unit for obtaining signal charges by receiving light in an active region that is a pixel region of an n-type semiconductor substrate 11 and performing photoelectric conversion. A photodiode 12 is provided, and the periphery of the pixel portion between adjacent pixel portions is isolated from each other by the element isolation region 13.

  The photodiode 12 is a Pin type photodiode in which a low-concentration p-type impurity layer 121, an n-type charge storage layer 122, and a high-concentration p-type impurity layer 123 are stacked in this order from the n-type semiconductor substrate 11 side to the surface side.

  In the element isolation region 13, the inside of the groove 131 is filled with an insulating oxide film 132 as an insulating film. It is configured. A p-type impurity region 133 is reliably interposed between the trench 131 and the photodiode 12 using a mask 19 to be described later, so as to suppress dark current and improve image quality. The depletion layer is not in direct contact with the film 132).

  FIG. 2 is a plan view showing one pixel of the solid-state imaging device of FIG. 1 is a vertical cross section taken along the line A-A ′ of FIG. 2.

  In FIG. 2, the solid-state imaging device 10 of Embodiment 1 includes a photodiode 12 surrounded on one side by an element isolation region 13 in a plan view, and provided on the other side with a transfer gate 14. Further, a floating diffusion portion 15 is provided as a signal detection portion that detects a signal charge transferred from the photodiode 12 through the transfer gate 14 with the transfer gate 14 interposed therebetween.

  Ion implantation In1 is performed on the n-type semiconductor substrate 11 using the active region pattern as a mask, and a region including a part of the ion implantation region 133 around the pixel portion or the entire region including this is defined as an element isolation region 13.

  Below, the manufacturing method of the solid-state imaging device 10 of this Embodiment 1 is demonstrated in detail using Fig.3 (a)-FIG.3 (e).

  FIG. 3A to FIG. 3E are main part longitudinal cross-sectional views showing one pixel in each manufacturing process for explaining the manufacturing method of the solid-state imaging device 10 of FIG. 1.

  First, as shown in the mask formation step (part 1) in FIG. 3A, a silicon oxide film 16 is formed on the n-type semiconductor substrate 11 with a thickness of 10 nm to 20 nm, and a silicon nitride film 17 is formed thereon with a thickness of 100 nm. A positive resist film 18 as a resist film is formed thereon to a thickness of 500 nm or more.

  Next, as shown in the mask formation step (No. 2) in FIG. 3B, the portion that becomes the active region (pixel portion region) is left, and the area around the pixel portion (element isolation region 13) between the pixel portions is opened. Thus, a mask 19 made of the silicon oxide film 16, the silicon nitride film 17, and the positive resist film 18 is formed by patterning into a predetermined shape. In FIG. 3B, α is the width of the opening that becomes the element isolation region 13. The positive resist film 18 is used for adjusting the film thickness of the mask 19.

Further, as shown by an arrow in the ion implantation process of FIG. 3C, impurity ions are implanted into the n-type semiconductor substrate 11 using the mask 19. In the first embodiment, boron ions are used as p-type impurity ions at an acceleration energy of 500 KeV to 800 KeV and a concentration of 1E11 / cm ^{2 to} 1E12 / cm ² , and an acceleration energy of 200 KeV to 300 KeV and a concentration of 1E11 / cm ^{2 to} 1E12 / cm. ² below, and were sequentially ion-implanted under the conditions of an acceleration energy 40KeV least 100KeV less at a concentration 1E12 / cm ² or more 1E13 / cm ² or less. Here, by performing ion implantation with acceleration energy of 500 KeV or more and 800 KeV or less, ion implantation is also performed on the n-type semiconductor substrate 11 below the edge of the mask 19 due to refraction in the mask 19, and impurity ions are activated. Introduced also to the region side, it is possible to effectively form an ion implantation region 133a having a high impurity concentration.

  Thereafter, in the heat treatment step, heat treatment is performed at a temperature of 850 ° C. or more and 950 ° C. or less for a predetermined time to activate the ion-implanted p-type impurity region 133a and further diffuse the impurities, so that under the edge of the mask 19 A p-type impurity region 133 extending in the lateral direction is also formed on the n-type semiconductor substrate 11.

  Further, in the groove forming step, the n-type semiconductor substrate 11 is etched from the mask 19 to a depth of 200 nm or more and 400 nm or less from the mask 19 by using a known RIE method to form a trench 131 (pixel separation) groove 131 (semiconductor substrate 11). Etching region). Thereafter, in the insulating region forming step, after the mask 19 is removed, an insulating oxide film 132 is deposited to a thickness of 400 nm to 700 nm to fill the trench 131 to form an insulating region, and the insulating oxide film is formed by CMP. The surface of 132 is flattened. FIG. 3D shows a state in which the insulating oxide film 132 remains in the trench 131 after the planarization. A p-type impurity region 133 after the impurity diffusion step (after heat treatment) is formed around the insulating oxide film 132 in the trench 131. The trench isolation step and the insulating region formation step constitute an element isolation region formation step, and the element isolation region 13 is formed after ion implantation using the mask 19.

Thereafter, as a photodiode forming step, ion implantation for forming the photodiode 12 is performed. In the first embodiment, boron ions are ion-implanted under conditions of an acceleration energy of 1 MeV to 2 MeV and a concentration of 1E11 / cm ^{2 to} 1E12 / cm ² , an acceleration energy of 300 KeV to 900 KeV, and a concentration of 1E11 / cm ^{2 to} 1E12 / cm ^2. and, the arsenic ion acceleration energy ion implantation and with the proviso that the concentration of 1E11 / cm ² or more 1E12 / cm ² or less at 200KeV least 300KeV less, the concentration of boron ions in the following acceleration energy 5KeV least 10 KeV 1E12 / cm ² or more 1E13 / cm ² By performing ion implantation under the following conditions, as shown in FIG. 3E, the Pin type photodiode 12 having the low concentration p-type impurity layer 121, the n-type charge storage layer 122, and the high concentration p-type impurity layer 123 is formed. Form. Here, phosphorus ions may be used instead of arsenic ions.

  At the time of ion implantation for forming the photodiode, the low-concentration p-type impurity layer 121 is ion-implanted over the entire surface of the substrate, and the n-type charge storage layer 122 and the high-concentration p-type impurity layer 123 are formed in the groove including the photodiode portion. Ion implantation is performed using another mask having openings up to half of the region.

  In the actual manufacturing process, each process such as gate formation and wiring formation is performed thereafter, but since it is not a main part of the present invention, description thereof is omitted here.

  As described above, according to the first embodiment, the mask 19 is used to form the p-type impurity region 133 in the ion implantation region and the device isolation trench 131 by high acceleration energy, and therefore, from the end of the device isolation region. As in the prior art in which ion implantation is performed using a mask provided at a distance d, the photodiode 12 is formed from the end of the insulating oxide film 132 constituting the element isolation region 13 without causing mask misalignment. Distance d (this distance d is determined by the diffusion width of the p-type impurity region 133 toward the active region, but acceleration energy, implantation concentration, heat treatment temperature (for example, 800 to 900 degrees Celsius) and time (for example, Can be adjusted in 15 minutes to 1 hour), and a p-type impurity region 133 is reliably formed at least at the end of the element isolation region 13 on the active region side. It can be.

For example, the distance d shown in FIG.
Conventionally, it has been necessary to satisfy the requirement of distance d> misalignment + depletion layer width from the photodiode 12, but in the first embodiment, this misalignment does not occur. Therefore, although depending on the accuracy of the exposure apparatus, the distance d can be reduced within a range of 0.03 μm to 0.1 μm. This reduced value is an effective value for forming a fine photodiode 12. For example, when the pixel size is about 1.5 μm or more and 3.0 μm or less on a side, the size of the photodiode region is about 1.0 μm or more and 2.5 or less μm, so that the influence is about 6% or more.

  Further, after ion implantation with high acceleration energy and after a predetermined heat treatment, the implanted ions are sufficiently diffused, and then the n-type semiconductor substrate 11 is etched to form a groove 131. Since the element isolation region 13 is formed by embedding the oxide film 132, the p-type impurity region 133 not only functions as a depletion layer stopper from the photodiode 12, but at the same time, the p-type impurity region 133 is deeply implanted with ions. Element isolation between the pixel portions can be effectively performed. Therefore, it is possible to form the element isolation region 13 that is fine and has high isolation capability, and to stably form the p-type impurity region 133 at least on the end side of the element isolation region 13 on the active region side. For example, in the first embodiment, the element isolation width (groove width) can be set to about 0.2 μm or more and 0.3 μm or less.

  Further, even when the width of the element isolation region 13 (the width of the p-type impurity region 133) is considerably narrow by setting the acceleration energy to 500 KeV or more and 800 KeV or less during ion implantation for forming the p-type impurity region 133. Impurities can be effectively ion-implanted.

In the first embodiment, the ion implantation process with high acceleration energy and the subsequent heat treatment process are performed together. However, the present invention is not limited to this, and any one of the ion implantation process with high acceleration energy and the subsequent heat treatment process is used. Also good.
(Embodiment 2)
In the second embodiment, when performing ion implantation and formation of the element isolation region 13 (formation of the element isolation trench 131) using the mask 19, the n-type semiconductor substrate 11 is etched using the mask 19 before ion implantation. Then, the groove 131 is formed, the first ion implantation In2 is performed at a predetermined implantation angle (for example, 0 to 7 degrees) with respect to the groove 131, and the n-type semiconductor substrate 11 is rotated as the second ion implantation In3. Then, the ion implantation is performed while tilting the implantation angle (for example, 10 degrees or more and 30 degrees or less), and after the second ion implantation, an insulating region 132 is formed by embedding an insulating oxide film 132 in the trench 131. The case where the region is formed will be described in detail with reference to FIGS.

  FIG. 4 is a longitudinal sectional view of a main part showing one pixel of the basic unit of the solid-state imaging device according to the second embodiment of the present invention.

  In FIG. 4, in the solid-state imaging device 10 </ b> A according to the second embodiment, a photodiode 12 is provided in an active region that is a pixel region of an n-type semiconductor substrate 11, and element periphery is separated between adjacent pixel portions. Elements are isolated from each other by the region 13.

  The photodiode 12 is a Pin type photodiode in which a low-concentration p-type impurity layer 121, an n-type charge storage layer 122, and a high-concentration p-type impurity layer 123 are stacked in this order from the n-type semiconductor substrate 11 side to the surface side.

  In the element isolation region 13, the trench 131 is embedded with an insulating oxide film 132, and the side surface and the bottom surface of the trench 131 that is the end of the element isolation region 13 are surrounded by the p-type impurity region 133. By using the mask 19 to reliably interpose the p-type impurity region 133 between the trench 131 and the photodiode 12, an element isolation region (insulating oxide film 132) is provided in order to suppress dark current and improve image quality. ) So that the depletion layer does not come into direct contact.

  Note that the second embodiment is configured in the same manner as in FIG. 2, and the ion implantations In 2 and 3 are sequentially performed on the n-type semiconductor substrate 11 using the active region pattern as a mask 19, so that pixels between the pixel units are formed. A region including a part of the ion implantation region 133 around the part or the entire region including this is defined as an element isolation region 13.

  Below, the manufacturing method of 10 A of solid-state imaging devices of this Embodiment 2 is demonstrated in detail using Fig.5 (a)-FIG.5 (f).

  FIG. 5A to FIG. 5F are main part longitudinal cross-sectional views showing one pixel in each manufacturing process for explaining the manufacturing method of the solid-state imaging device 10A of FIG.

  First, as shown in the mask formation step (part 1) in FIG. 5A, a silicon oxide film 16 is formed on the n-type semiconductor substrate 11 to a thickness of 10 nm to 20 nm, and a silicon nitride film 17 is formed thereon to a thickness of 100 nm. The positive resist film 18 is formed to a thickness of 500 nm or more.

  Next, as shown in the mask formation step (No. 2) in FIG. 5B, the silicon oxide film 16 and the silicon nitride film are patterned so that only the element isolation region 13 is opened by patterning a portion to be an active region. A mask 19 composed of the film 17 and the positive resist film 18 is formed. In FIG. 5B, α is the width of the opening that becomes the element isolation region 13. The steps up to here are the same as those in the method of manufacturing the solid-state imaging device 10 of the first embodiment.

  Further, as shown in the groove forming step of FIG. 5C, the semiconductor substrate 11 is etched by a depth of 200 nm to 400 nm through the opening of the mask 19 by using a known RIE method for trench isolation (pixel isolation). ) Groove 131 is formed.

Thereafter, as shown by an arrow in the ion implantation step (No. 1; In2) of FIG. 5C, the first ion implantation In2 from above is performed using the mask 19. In the second embodiment, boron ions are ion-implanted as first p-type ions under the conditions of an acceleration energy of 20 KeV to 60 KeV and a concentration of 1E12 / cm ^{2 to} 1E13 / cm ² . Here, if necessary, ion implantation with high acceleration energy of acceleration energy of 500 KeV or more may be added. By performing ion implantation with a high acceleration energy of acceleration energy of 500 KeV or more, impurities implanted into the vicinity of the opening end of the mask 19 are also introduced into the active region side due to refraction in the mask 19 and the like. In addition, the impurity concentration can be increased. In FIG. 5C, the p-type impurity region 133b on the lower bottom side of the trench 131 is a region ion-implanted by the first ion implantation In2.

Further, as shown by an arrow in the ion implantation step (No. 2; In3) in FIG. 5D, the second ion implantation In3 is performed using the same mask 19. In the second embodiment, boron ions are used as the second p-type ions in the range of an implantation angle of 10 degrees or more and 30 degrees or less under the condition of an acceleration energy of 20 KeV or more and 40 KeV or less and a concentration of 1E12 / cm ² or more and 1E13 / cm ² or less. Ions were implanted while rotating the semiconductor substrate 11. In FIG. 5D, the p-type impurity region 133c on the side wall side of the trench 131 is a region where ions are implanted. Here, when the element isolation width is finer, the second ion implantation In3 may be easily performed by retracting a part of the mask 19 (resist film) by O ₂ plasma treatment.

  Further, after the mask 19 is removed, an insulating oxide film 132 is deposited to a thickness of 400 nm to 700 nm, and the surface is planarized by CMP. FIG. 5E shows an insulating region forming step in which the insulating oxide film 132 remains only in the groove 131 after the planarization. A p-type impurity region 133 after the ion implantation In3 is formed around the insulating oxide film 132 in the trench 131. The trench isolation step and the insulating region formation step constitute an element isolation region formation step, and the element isolation region 13 is formed before and after ion implantation using the mask 19.

Thereafter, ion implantation for forming the photodiode 121 is performed as shown in the photodiode formation step of FIG. In the second embodiment, boron ions are ion-implanted under the conditions of an acceleration energy of 1 MeV to 2 MeV and a concentration of 1E11 / cm ^{2 to} 1E12 / cm ² , an acceleration energy of 300 KeV to 900 KeV, and a concentration of 1E11 / cm ^{2 to} 1E12 / cm ^2. and, the arsenic ion acceleration energy ion implantation and with the proviso that the concentration of 1E11 / cm ² or more 1E12 / cm ² or less at 200KeV least 300KeV less, the concentration of boron ions in the following acceleration energy 5KeV least 10 KeV 1E12 / cm ² or more 1E13 / cm ² By performing ion implantation under the following conditions, as shown in FIG. 5F, the Pin photodiode 12 having the low-concentration p-type impurity layer 121, the n-type charge storage layer 122, and the high-concentration p-type impurity layer 123 is formed. Form. Here, phosphorus ions may be used instead of arsenic ions.

  In the actual manufacturing process, each process such as gate formation and wiring formation is performed thereafter, but since it is not a main part of the present invention, description thereof is omitted here.

  As described above, according to the second embodiment, the first ion implantation In2 in the vertical direction and the second ion implantation In3 in the oblique direction are performed on the n-type semiconductor substrate 11 using the active region pattern as the mask 17 to form the bottom. In order to obtain the p-type impurity region 133b of the portion and the p-type impurity region 133c of the side wall portion, and to set the opening portion α of the mask 17 to the width of the element isolation region 13, it is provided apart from the end of the element isolation region by a predetermined distance d. The distance d from the end of the insulating film 132 constituting the element isolation region 13 to the photodiode 12 is stabilized without causing misalignment of the resist mask as in the prior art in which ion implantation is performed using the resist mask formed. Thus, the p-type impurity region 133 can be stably formed at the end of the element isolation region 13.

  Further, the trench 131 is formed by etching the semiconductor substrate 11 before ion implantation, and the element isolation region 13 is formed by embedding the insulating oxide film 132 in the trench 131 after ion implantation. Ion implantation can be performed under low energy conditions, and the element isolation region 13 that is fine and has high isolation capability can be formed, and the p-type impurity region 133 can be stably formed at the end of the element isolation region 13. .

  Further, by performing the second ion implantation by retreating the resist of the mask 17, it is possible to cope with the case where the finer element isolation region 13 is formed.

  Although not particularly described in Embodiment 2, only the second ion implantation In3 in the oblique direction may be performed without performing the first ion implantation In2 as follows.

6A, a mask 19 made of an active pattern (SiO / SiN / SiO) is formed so as to cover the active region on the semiconductor substrate 11 in the mask formation step of FIG. 6A, and the p-type stopper of FIG. In the forming step, a groove forming step of forming a groove 131 by etching in the opening portion of the mask 19 and an ion implantation In3 only while rotating the n-type semiconductor substrate 11 in the oblique implantation direction from above the mask 19 and under the end of the mask 19 Also, an ion implantation step for forming an ion implantation region (p-type impurity region 133) is performed. Further, the mask 19 is removed in FIG. 6C, and the trench 131 is filled with the insulating oxide film 132 and then flattened. As shown in FIG. 6D, the insulating oxide in the trench 131 is oxidized. The periphery of the film 132 can be covered with the p-type impurity region 133.
(Embodiment 3)
In the third embodiment, when ion implantation In4 is performed using a mask 19B which is recessed by a predetermined amount from the mask 19 toward the active region, a sidewall 131 is provided if necessary, and the groove 131 is formed by etching. It is. This case will be described in detail below.

  FIG. 7A to FIG. 7D are vertical cross-sectional views of main parts showing one pixel in each manufacturing process for explaining a method for manufacturing a solid-state imaging device according to Embodiment 3 of the present invention.

  First, as shown in FIG. 7A, in a mask formation step, a mask 19B made of an active pattern (SiO / SiN / SiO) is formed so as to cover an active region on the semiconductor substrate 11. The mask 19B is a mask that is reduced by reducing its end by a predetermined distance (for example, the distance d) on both sides of the mask 19.

  Next, as shown in the ion implantation step of FIG. 7B, the ion implantation In4 from the vertical direction through the opening of the mask 19B which is retracted by a predetermined distance (for example, the distance d) from the mask 19 to the active region side. To form an ion implantation region.

  Further, as shown in a groove forming step (No. 1; side wall forming step) in FIG. 7C, a side wall 171 having a thickness of the predetermined distance (for example, the distance d) is provided on the side wall of the mask 19B. Then, etching is performed using the mask 19B and the sidewall 171 to form the groove 131 at a predetermined depth with a width between the sidewalls 171 on the side wall of the opening.

  Thereafter, as shown in the groove forming step (No. 2) in FIG. 7D, the mask 19B and the sidewall 171 are removed, and the groove 131 is filled with the insulating oxide film 132 and then flattened. The periphery of the insulating oxide film 132 can be covered with the p-type impurity region 133.

  In the actual manufacturing process, each process such as gate formation and wiring formation is performed thereafter, but since it is not a main part of the present invention, description thereof is omitted here.

  In this way, the solid-state imaging device 10B in which the pixel portions are separated by the element isolation region 13 is manufactured.

  As described above, according to the first to third embodiments, when manufacturing the solid-state imaging device 10, 10 </ b> A, or 10 </ b> B in which the pixel portions are separated by the element isolation region 13, the portion that becomes the active region is patterned. By performing ion implantation on the semiconductor substrate 11 using the active pattern as a mask 19, a part or the whole of the ion implantation region is used as the element isolation region 13. The distance d from the end of the element isolation region 13 does not cause misalignment of the resist mask as in the prior art in which ion implantation is performed using a resist mask provided to be separated from the end of the element isolation region by a predetermined distance d. The p-type impurity region 133 can be stabilized and formed. As a result, a high-concentration impurity layer can be formed at the end of the element isolation region 13 by ion implantation so that the depletion layer does not directly contact the element isolation region 13, which can sufficiently cope with further miniaturization of the pixel portion. be able to.

  Although not particularly described in the first to third embodiments, in short, a solid-state imaging device manufacturing method for manufacturing a solid-state imaging device in which each active region (for example, a pixel unit) is element-isolated by the element isolation region 13. And forming a mask on the semiconductor substrate patterned so as to open the periphery of the active region between the active regions while leaving a portion to be an active region, and ion implantation from the mask to the semiconductor substrate. If there is an ion implantation step to be performed and an element isolation region forming step for forming the element isolation region before, after or after the ion implantation using the mask, the depletion layer is not in direct contact with the element isolation region In this way, a high-concentration impurity layer is formed at the end of the element isolation region by ion implantation, and a solid-state imaging device with good image quality that suppresses the dark current generated at the interface between silicon and silicon oxide. Te, production conditions as in the prior art can be simplified not complicated, it is possible to achieve the object of the present invention can be miniaturized further pixel portion. As described above, since stopper ions are implanted by self-alignment before field formation, a stable stopper ion implantation layer (p-type impurity region 133) can be reliably formed between the end of the trench 131 and the end of the photodiode. Thus, enlargement of the pixel size by securing the misalignment margin for stopper ion implantation and characteristic variation due to misalignment of stopper ion implantation can be eliminated.

  Although not specifically described in the first to third embodiments, the width of the groove 131 can be set in a range of 0.1 μm to 1.0 μm. Further, the distance d from the end of the groove 131 to the end of the active region is set within a range of 0.01 μm or more and 0.5 μm or less, and ion implantation by ion implantation is performed between the end of the groove 131 and the end of the active region. A region (p-type impurity region 133) can be formed. The distance d from the end of the trench 131 to the end of the active region is the width of the p-type impurity region 133.

  Although not specifically described in the first to third embodiments, for example, a digital video camera or a digital still camera using at least one of the solid-state imaging devices 10, 10A, and 10B of the first to third embodiments as an imaging unit. Electronic information equipment with image input devices such as digital cameras, image input cameras, surveillance cameras, door phone cameras, in-vehicle cameras, TV phone cameras, mobile phone cameras, scanners, facsimiles, camera phone devices, etc. Will be described. The electronic information device of the present invention provides a predetermined signal for recording high-quality image data obtained by using at least one of the solid-state imaging devices 10, 10A, and 10B of the first to third embodiments of the present invention as an imaging unit. A memory unit such as a recording medium for recording data after processing, a display means such as a liquid crystal display device for displaying the image data on a display screen such as a liquid crystal display screen after processing a predetermined signal for display, and the image data At least one of communication means such as a transmission / reception device that performs communication processing after performing predetermined signal processing for communication, and image output means for printing (printing) and outputting (printing out) the image data. is doing.

  As mentioned above, although this invention has been illustrated using preferable Embodiment 1-3 of this invention, this invention should not be limited and limited to this Embodiment 1-3. It is understood that the scope of the present invention should be construed only by the claims. It is understood that those skilled in the art can implement an equivalent range based on the description of the present invention and the common general technical knowledge from the description of specific preferred embodiments 1 to 3 of the present invention. Patents, patent applications, and documents cited herein should be incorporated by reference in their entirety, as if the contents themselves were specifically described herein. Understood.

  The present invention is used in a MOS type sensor or a CMOS type sensor that can image an image light from a subject by photoelectric conversion so that a depletion layer does not directly contact an element isolation region in which pixel portions are separated. , Manufacturing method of solid-state imaging device in which high-concentration impurity layer is formed at end of element isolation region by ion implantation, solid-state imaging device manufactured thereby, and digital imaging device using this solid-state imaging device as an image input device, for example, in an imaging unit In the field of digital information cameras such as video cameras and digital still cameras, and electronic information equipment such as image input cameras, scanners, facsimiles, and camera-equipped mobile phone devices, solid-state imaging devices in which active regions are separated from each other by element separation regions When manufacturing the pattern, the pattern is formed so as to open the active area between the active areas, leaving a portion to be the active area. Since the ion implantation and formation of the element isolation region (formation of the element isolation groove) are performed using the masked mask, the manufacturing conditions are not complicated as in the prior art, and the element on the active region side can be simplified. An ion implantation region can be stably formed at the end of the separation region. By this ion implantation region, the depletion layer can be prevented from being in direct contact with the element isolation region, and a solid-state imaging device with good image quality with reduced dark current can be obtained, and the pixel can be miniaturized. it can.

  A trench is formed by etching the semiconductor substrate using a mask after ion implantation, and an insulating film is embedded in the trench, and a region including a part of the ion implantation region around the active region or the entire region including this is separated into an element isolation region. As a result, it is possible to form a fine element isolation region having a high isolation capability, and to stably form, for example, a p-type impurity region of an ion implantation region at the end of the element isolation region. In this case, when the implanted ions are diffused and activated by heat treatment after ion implantation, the semiconductor substrate can be etched using the mask after this heat treatment step to form a groove. Also, ion implantation is performed with the mask set back by a predetermined amount toward the active region, a sidewall is formed on at least the sidewall of the active region, and the semiconductor substrate is etched using the mask and the sidewall. Grooves can also be formed.

  In addition, a groove is formed by etching the semiconductor substrate using a mask before ion implantation, and after the ion implantation, an insulating film is embedded in the groove to include a part of the ion implantation region around the active region. By forming the region or the entire region including this as an element isolation region, ion implantation is performed under a low energy condition with little damage to form a fine and high element isolation region, and an ion implantation region on the element isolation region side. For example, a p-type impurity region can be stably formed.

  Furthermore, it is possible to cope with the case where a finer element isolation region is formed by performing ion implantation by retracting at least a part of the mask toward the active region. Further, by setting the acceleration energy to 500 KeV or more at the time of ion implantation, impurities can be effectively implanted even when the width of the element isolation region is quite narrow.

It is a principal part longitudinal cross-sectional view which shows 1 pixel of the basic unit of the solid-state imaging device which concerns on Embodiment 1 of this invention. FIG. 2 is a plan view showing one pixel of the solid-state imaging device of FIG. 1. (A)-(e) is a principal part longitudinal cross-sectional view which shows 1 pixel in each manufacturing process for demonstrating the manufacturing method of the solid-state imaging device of FIG. It is a principal part longitudinal cross-sectional view which shows 1 pixel of the basic unit of the solid-state imaging device which concerns on Embodiment 2 of this invention. (A)-(f) is a principal part longitudinal cross-sectional view which shows 1 pixel in each manufacturing process for demonstrating the manufacturing method of the solid-state imaging device of FIG. (A)-(d) is a principal part longitudinal cross-sectional view which shows typically 1 pixel in each manufacturing process for demonstrating simply the modification of the manufacturing method of the solid-state imaging device which concerns on Embodiment 2 of this invention. It is. (A)-(d) is a principal part longitudinal cross-sectional view which shows typically 1 pixel in each manufacturing process for demonstrating simply the manufacturing method of the solid-state imaging device which concerns on Embodiment 3 of this invention. (A) And (b) is a principal part longitudinal cross-sectional view which shows one pixel in each manufacturing process for demonstrating the manufacturing method of the conventional solid-state imaging device.

Explanation of symbols

10, 10A, 10B Solid-state imaging device 11 n-type semiconductor substrate (semiconductor substrate)
12 Photodiode (pixel part)
121 low-concentration p-type impurity layer 122 n-type charge storage layer 123 high-concentration p-type impurity layer 13 element isolation region 131 groove (element isolation groove)
132 Insulating oxide film (insulating film)
133 p-type impurity region 133a p-type impurity ion implantation region 133b first p-type impurity ion implantation region 133c second p-type impurity ion implantation region 14 transfer gate (gate region)
15 Floating diffusion part (signal detection part)
16 Silicon oxide film (oxide film)
17 Silicon nitride film (nitride film)
18 Positive resist film (resist film)
19, 19B Mask In1 p-type impurity ion implantation In2 First p-type impurity ion implantation In3 Second p-type impurity ion implantation d Width of p-type impurity region

Claims (33)

In a manufacturing method of a solid-state imaging device for manufacturing a solid-state imaging device in which each active region is separated by an element isolation region
A mask forming step of forming a mask patterned on the semiconductor substrate so as to open the periphery of the active region between the active regions while leaving a portion to be an active region;
An ion implantation step of implanting ions into the semiconductor substrate from above the mask;
A method of manufacturing a solid-state imaging device, comprising: forming an element isolation region before and after or after the ion implantation using the mask.   The method of manufacturing a solid-state imaging device according to claim 1, wherein the mask is used for the ion implantation and used for forming an element isolation groove in the element isolation region.   The method for manufacturing a solid-state imaging device according to claim 1, wherein the active region includes a pixel unit, a signal detection unit that detects a signal from the pixel unit, and a gate region between the pixel unit and the signal detection unit. .   The method of manufacturing a solid-state imaging device according to claim 1, wherein a direction of the ion implantation is inclined at least toward the active region side.   The method of manufacturing a solid-state imaging device according to claim 1, further comprising a heat treatment step of diffusing and activating the implanted ions by heat treatment after the ion implantation.   The solid-state imaging device manufacturing method according to claim 5, wherein the element isolation region forming step includes a groove forming step of forming a groove by etching the semiconductor substrate using the mask after the heat treatment step.   3. The method of manufacturing a solid-state imaging device according to claim 1, wherein the element isolation region forming step includes a groove forming step of forming a groove by etching the semiconductor substrate using the mask after the ion implantation.   The solid-state imaging device manufacturing method according to claim 1, wherein the element isolation region forming step includes a groove forming step of forming a groove by etching the semiconductor substrate using the mask before the ion implantation.   The method for manufacturing a solid-state imaging device according to claim 1, wherein ion implantation is performed while rotating the semiconductor substrate.   10. The solid-state imaging device according to claim 4, wherein the ion implantation direction is set such that an implantation angle from a perpendicular to the main surface of the semiconductor substrate is in a range of 0 ° to 7 ° or 10 ° to 30 °. Production method.   The method of manufacturing a solid-state imaging device according to claim 1, wherein the ion implantation is performed in a state where the mask is retracted by a predetermined amount toward the active region.   The element isolation region forming step includes forming a sidewall by forming a sidewall on at least a side wall of the mask on the active region side, and etching the semiconductor substrate using the mask and the sidewall to form a groove. The method for manufacturing a solid-state imaging device according to claim 11, further comprising a groove forming step.   13. The method for manufacturing a solid-state imaging element according to claim 2, wherein the element isolation region forming step further includes an insulating region forming step of forming an insulating region by embedding an insulating film in the groove.   The method of manufacturing a solid-state imaging device according to claim 1, wherein the ion implantation is performed at an acceleration energy of 500 KeV or more and 800 KeV or less.   The method of manufacturing a solid-state imaging device according to claim 1, wherein the ion implantation is performed a plurality of times. The ion implantation is performed at an acceleration energy of 500 KeV to 800 KeV and a concentration of 1E11 / cm ^{2 to} 1E12 / cm ² , an acceleration energy of 200 KeV to 300 KeV and a concentration of 1E11 / cm ^{2 to} 1E12 / cm ² and an acceleration energy of 40 KeV to 100 KeV. The method for manufacturing a solid-state imaging device according to claim 15, which is performed under each condition of a density of 1E12 / cm ² or more and 1E13 / cm ² or less. The ion implantation is performed as a first ion implantation under conditions of an acceleration energy of 20 KeV to 60 KeV and a concentration of 1E12 / cm ^{2 to} 1E13 / cm ² to form an element isolation groove, and then using the mask The method for manufacturing a solid-state imaging device according to claim 15, wherein the second ion implantation is performed. 18. The method of manufacturing a solid-state imaging device according to claim 17, wherein the second ion implantation is performed under an acceleration energy of 20 KeV to 40 KeV and a concentration of 1E12 / cm ^{2 to} 1E13 / cm ² . The ion implantation, after forming a trench for device isolation, according to any one of claims 1 and 9-11 carried out on condition that a concentration 1E12 / cm ² or more 1E13 / cm ² or less in the following acceleration energy of 20KeV least 40KeV Manufacturing method of solid-state imaging device.   The method for manufacturing a solid-state imaging device according to claim 1, wherein boron ions are implanted by the ion implantation to form a p-type impurity region.   18. The method for manufacturing a solid-state imaging device according to claim 2, wherein the depth of the groove is set to 200 nm or more and 400 nm or less.   The method of manufacturing a solid-state imaging device according to any one of claims 2, 6 to 8, 12, 13, 17 and 21, wherein the width of the groove is set to 0.1 µm or more and 1.0 µm or less.   The method of manufacturing a solid-state imaging device according to any one of claims 2, 6 to 8, 12, 13, 17, and 21, wherein the width of the groove is set to 0.2 µm or more and 0.3 µm or less.   The distance from the end of the groove to the end of the active region is set within a range of 0.01 μm or more and 0.5 μm or less, and the ion implantation region is formed by the ion implantation between the end of the groove and the end of the active region. The method for manufacturing a solid-state imaging device according to claim 2, wherein the solid-state imaging device is formed.   The distance from the end of the groove to the end of the active region is set within a range of 0.03 μm or more and 0.1 μm or less, and the ion implantation region is formed by the ion implantation between the end of the groove and the end of the active region. The method for manufacturing a solid-state imaging device according to claim 2, wherein the solid-state imaging device is formed.   The distance from the edge of the element isolation region to the edge of the active region is adjusted by at least one of acceleration energy and implantation concentration by the ion implantation, and temperature and time of thermal diffusion treatment of implanted ions after the ion implantation The manufacturing method of the solid-state imaging device of Claim 1.   The method of manufacturing a solid-state imaging device according to claim 1, wherein the mask is composed of a composite film of an oxide film, a nitride film, and a resist film.   28. The method of manufacturing a solid-state imaging device according to claim 27, wherein the thickness of the resist film is set within a range of 500 nm to 1500 nm.   29. The method of manufacturing a solid-state imaging device according to claim 9, wherein the ion implantation is performed in a state where a resist film of the mask is retracted by a predetermined amount toward the active region.   2. The method of manufacturing a solid-state imaging device according to claim 1, further comprising a photodiode forming step of forming a photodiode for obtaining a signal charge by photoelectrically converting light in the active region as a pixel portion.   31. The method of manufacturing a solid-state imaging device according to claim 30, wherein a p-type impurity region is formed as an ion implantation region so as to have a higher concentration than the p-type well region constituting the photodiode by the ion implantation.   32. A solid-state imaging device manufactured by the method of manufacturing a solid-state imaging device according to claim 1, wherein the element isolation region is provided between the active regions, and the element isolation region and the active region A solid-state imaging device in which an ion implantation region is provided therebetween.   An electronic information device in which the solid-state imaging device according to claim 32 is provided in an imaging unit.

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