JP5600924B2 - Solid-state imaging device, manufacturing method thereof, and camera - Google Patents

Description

  The present invention relates to a solid-state imaging device, a manufacturing method thereof, and a camera, and more particularly to a solid-state imaging device in which pixels having photodiodes on a light receiving surface are arranged in a matrix, a manufacturing method thereof, and a camera including the solid-state imaging device.

  Usually, the charge storage capacity of a photodiode largely depends on the capacity of a PN junction formed near the substrate surface. However, if the pixel is further miniaturized, the surface area of the photodiode is reduced, thereby reducing the area of the PN junction, thereby reducing the charge storage capacity.

When a large amount of light is incident on the photodiode, electrons photoelectrically converted in the photodiode easily overflow from the photodiode, and the image is overexposed.
Therefore, when the pixel is further miniaturized, the dynamic range of the image sensor is reduced.

  Therefore, in order to increase the charge storage capacity, it is desired to increase the capacity of the PN junction of the photodiode. For this purpose, it is important to increase the junction capacitance by steepening the gradient of the effective impurity concentration in the PN junction.

In order to obtain a steep PN junction, shallow and deep ion implantation must be performed, and then heat treatment must be suppressed so as not to cause thermal diffusion.
However, if the heat treatment is insufficient, implantation defects caused by ion implantation remain in the vicinity of the PN junction without being recovered by sufficient heat treatment.

Defects and impurities are also introduced in the vicinity of the PN junction in etching processes such as reactive ion etching in gate etching and sidewall etch back.
However, since heat treatment must be reduced for the above reasons, heat treatment for sufficient defect recovery cannot be performed.

  Therefore, when an attempt is made to increase the junction capacitance by increasing the steepness of the surface PN junction, the above-described defects are left in the vicinity of the PN junction, and trap assist band-to-band transition occurs. For this reason, many junction leakage currents are induced even when the transition occurs between bands that are governed only by the original electric field strength, which causes an increase in dark current.

  As described above, improving the dynamic range by simply steepening the PN junction causes a decrease in yield such as an increase in dark current.

Patent Document 1 describes that P ⁺ polysilicon is embedded in element isolation and a negative potential is applied to the polysilicon to pin the vicinity of the SiO ₂ / Si interface. P ⁺ polysilicon pinning is limited to device isolation.

  Patent Document 2 describes that a Si active layer is deposited on a glass substrate, and a photogate (Al) is disposed thereon. The photogate is used to form a depletion layer in order to accumulate one charge among carriers generated by photoelectric conversion in the active layer in the active layer.

  Patent Document 3 describes that a transparent electrode is arranged on the back surface and a negative potential is applied. The transparent electrode is for pinning the back surface.

  Patent Document 4 describes a CMOS image sensor that emits light from the back side.

  Patent Documents 5 to 7 describe a configuration in which electrodes are provided on the surface of the light receiving surface.

JP 2005-167588 A JP 2001-189286 A JP 2003-338615 A JP 2003-31785 A JP 2006-173351 A JP 2007-258684 A International Publication No. 2008/139644 Pamphlet

  As described above, there is a problem that it is difficult to suppress a decrease in yield while improving the dynamic range by sharpening the PN junction.

  A solid-state imaging device according to the present invention includes a photodiode having a semiconductor region of a first conductivity type formed by being divided for each pixel arranged in a matrix on a light receiving surface of a semiconductor substrate, and a region adjacent to the photodiode. A transfer gate electrode of a first conductivity type formed on the semiconductor substrate via a gate insulating film and transferring a signal charge generated and accumulated in the photodiode, and a voltage corresponding to the signal charge or the signal charge A signal reading unit to be read and a region that covers part or all of the photodiode is formed on the semiconductor substrate via the gate insulating film, and is made of a conductor or semiconductor having a work function larger than that of the transfer gate electrode. An inversion layer induction electrode, and the inversion layer induction electrode causes the inversion layer induction electrode side surface of the semiconductor region to Formed by accumulating conductive carrier inversion layer is induced.

  In the above-described solid-state imaging device of the present invention, the photodiode having the first conductivity type semiconductor region is formed by being divided into pixels arranged in a matrix on the light receiving surface of the semiconductor substrate. In a region adjacent to the photodiode, a transfer gate electrode of a first conductivity type that transfers signal charges generated and accumulated in the photodiode is formed on the semiconductor substrate via a gate insulating film. A signal reading unit that reads a voltage corresponding to the signal charge or the signal charge is formed. Further, an inversion layer induction electrode made of a conductor or semiconductor having a work function larger than that of the transfer gate electrode is formed on the semiconductor substrate via a gate insulating film in a region covering a part or all of the photodiode. Here, an inversion layer in which carriers of the second conductivity type are accumulated is induced on the surface of the semiconductor region on the inversion layer induction electrode side by the inversion layer induction electrode.

  According to another aspect of the present invention, there is provided a method of manufacturing a solid-state imaging device, comprising: a step of forming a first conductivity type semiconductor region in a photodiode formation region by dividing each pixel arranged in a matrix on a light receiving surface of a semiconductor substrate; Forming a transfer gate electrode of a first conductivity type for transferring a signal charge generated and accumulated in the photodiode via a gate insulating film on the semiconductor substrate in a region adjacent to the formation region; and the signal charge And a step of forming a signal reading unit for reading the voltage or the signal charge according to the above, and the transfer gate via the gate insulating film on the semiconductor substrate in a region covering a part or all of the photodiode formation region Forming an inversion layer-inducing electrode made of a conductor or semiconductor having a work function larger than that of the electrode, As diode, to form a photo diode, wherein the inversion layer induced electrode formed by accumulating a second conductive carrier to the inversion layer induced electrode side surface of the semiconductor region inversion layer is induced.

In the method for manufacturing a solid-state imaging device according to the present invention, the first conductivity type semiconductor region is formed in the photodiode formation region by dividing the pixel into pixels arranged in a matrix on the light receiving surface of the semiconductor substrate. Next, a transfer gate electrode of the first conductivity type that transfers signal charges generated and stored in the photodiode is formed on the semiconductor substrate via a gate insulating film in a region adjacent to the photodiode formation region. In addition, a voltage corresponding to the signal charge or a signal reading unit that reads the signal charge is formed. Further, an inversion layer induction electrode made of a conductor or a semiconductor having a work function larger than that of the transfer gate electrode is formed on the semiconductor substrate through a gate insulating film in a region covering a part or all of the photodiode formation region.
Here, as the photodiode, a photodiode is formed in which an inversion layer is formed by accumulating carriers of the second conductivity type on the surface of the inversion layer induction electrode side of the semiconductor region by the inversion layer induction electrode.

  The camera according to the present invention includes a solid-state imaging device in which a plurality of pixels are integrated on a light-receiving surface, an optical system that guides incident light to an imaging unit of the solid-state imaging device, and signal processing that processes an output signal of the solid-state imaging device The solid-state imaging device includes: a photodiode having a semiconductor region of a first conductivity type formed by dividing each pixel arranged in a matrix on a light-receiving surface of a semiconductor substrate; and the photodiode A transfer gate electrode of a first conductivity type that is formed on the semiconductor substrate via a gate insulating film in an adjacent region and transfers a signal charge generated and accumulated in the photodiode, and a voltage or a voltage corresponding to the signal charge A signal reading unit for reading the signal charge and a region covering a part or all of the photodiode are formed on the semiconductor substrate via the gate insulating film. And an inversion layer inducing electrode made of a conductor or semiconductor having a work function larger than that of the transfer gate electrode, and the inversion layer inducing electrode causes a second conductivity type surface on the inversion layer inducing electrode side surface of the semiconductor region. An inversion layer formed by accumulating carriers is induced.

  The camera according to the present invention includes a solid-state imaging device in which a plurality of pixels are integrated on a light receiving surface, an optical system that guides incident light to an imaging unit of the solid-state imaging device, and signal processing that processes an output signal of the solid-state imaging device. Circuit. Here, the solid-state imaging device is a solid-state imaging device according to the present invention having the above-described configuration.

  In the solid-state imaging device of the present invention, an inversion layer induction electrode is formed in a region covering a part or all of a photodiode, and inversion is performed by accumulating carriers of the second conductivity type on the surface of the semiconductor region on the inversion layer induction electrode side. The layer is induced. Thereby, it is possible to suppress a decrease in yield while improving the dynamic range by sharpening the PN junction.

  In the method for manufacturing a solid-state imaging device of the present invention, an inversion layer induction electrode is formed in a region covering a part or all of a photodiode, and carriers of the second conductivity type are accumulated on the surface of the semiconductor region on the inversion layer induction electrode side. Thus, a solid-state imaging device in which the inversion layer is induced can be manufactured. Thereby, it is possible to suppress a decrease in yield while improving the dynamic range by sharpening the PN junction.

  The camera of the present invention can provide a camera using a solid-state imaging device that can suppress a decrease in yield while improving a dynamic range by sharpening a PN junction.

FIG. 1 is a plan view of the solid-state imaging device according to the first embodiment of the present invention. 2A and 2B are cross-sectional views of the solid-state imaging device according to the first embodiment of the present invention. FIGS. 3A to 3D are energy band diagrams of the photodiode region of the solid-state imaging device according to the first embodiment of the present invention and the solid-state imaging device according to the comparative example. 4A and 4B are cross-sectional views illustrating manufacturing steps of the method for manufacturing the solid-state imaging device according to the first embodiment of the present invention. 5A and 5B are cross-sectional views illustrating manufacturing steps of the method for manufacturing the solid-state imaging device according to the first embodiment of the present invention. 6A and 6B are cross-sectional views illustrating the manufacturing process of the method for manufacturing the solid-state imaging device according to the first embodiment of the present invention. 7A and 7B are cross-sectional views illustrating the manufacturing steps of the method for manufacturing the solid-state imaging device according to the first embodiment of the present invention. FIGS. 8A and 8B are cross-sectional views illustrating manufacturing steps of the method for manufacturing the solid-state imaging device according to the first embodiment of the present invention. FIG. 9 is a timing chart of the applied voltage of the solid-state imaging device according to the first modification of the present invention. FIGS. 10A to 10C are cross-sectional views showing manufacturing steps of a method for manufacturing a solid-state imaging device according to the second modification of the present invention. FIG. 11 is a plan view of a solid-state imaging device according to the second embodiment of the present invention. FIGS. 12A and 12B are cross-sectional views of a solid-state imaging device according to the second embodiment of the present invention. FIGS. 13A to 13C are cross-sectional views illustrating manufacturing steps of a method for manufacturing a solid-state imaging device according to the second embodiment of the present invention. FIGS. 14A and 14B are cross-sectional views illustrating manufacturing steps of a method for manufacturing a solid-state imaging device according to the second embodiment of the present invention. FIGS. 15A and 15B are cross-sectional views illustrating manufacturing steps of a method for manufacturing a solid-state imaging device according to the second embodiment of the present invention. FIGS. 16A and 16B are cross-sectional views illustrating manufacturing steps of a method for manufacturing a solid-state imaging device according to the second embodiment of the present invention. FIGS. 17A and 17B are cross-sectional views illustrating the manufacturing steps of the method of manufacturing the solid-state imaging device according to the second embodiment of the present invention. 18 (a) and 18 (b) are cross-sectional views illustrating manufacturing steps of a method for manufacturing a solid-state imaging device according to the second embodiment of the present invention. FIGS. 19A and 19B are cross-sectional views illustrating manufacturing steps of a method for manufacturing a solid-state imaging device according to the second embodiment of the present invention. 20A and 20B are cross-sectional views illustrating the manufacturing process of the method for manufacturing the solid-state imaging device according to the second embodiment of the present invention. FIG. 21 is a plan view of a solid-state imaging device according to the third embodiment of the present invention. 22A and 22B are cross-sectional views of the solid-state imaging device according to the third embodiment of the present invention. 23A to 23C are cross-sectional views illustrating manufacturing steps of a method for manufacturing a solid-state imaging device according to the third embodiment of the present invention. FIGS. 24A and 24B are cross-sectional views illustrating manufacturing steps of a method for manufacturing a solid-state imaging device according to the third embodiment of the present invention. FIGS. 25A and 25B are cross-sectional views illustrating manufacturing steps of a method for manufacturing a solid-state imaging device according to the third embodiment of the present invention. FIGS. 26A and 26B are cross-sectional views illustrating manufacturing steps of the method of manufacturing the solid-state imaging device according to the third embodiment of the present invention. FIGS. 27A and 27B are cross-sectional views illustrating manufacturing steps of a method for manufacturing a solid-state imaging device according to the third embodiment of the present invention. FIGS. 28A and 28B are cross-sectional views illustrating manufacturing steps of a method for manufacturing a solid-state imaging device according to the third embodiment of the present invention. FIGS. 29A and 29B are cross-sectional views illustrating manufacturing steps of a method for manufacturing a solid-state imaging device according to the third embodiment of the present invention. 30 (a) and 30 (b) are cross-sectional views illustrating manufacturing steps of a method for manufacturing a solid-state imaging device according to the third embodiment of the present invention. FIG. 31 is a schematic configuration diagram of a camera according to the fourth embodiment of the present invention.

  Embodiments of a solid-state imaging device, a manufacturing method thereof, and a camera including the solid-state imaging device according to the present invention will be described below with reference to the drawings.

The description will be given in the following order.
1. First embodiment (basic configuration)
2. First modification (extrusion of signal charge by inversion layer induced electrode applied voltage)
3. Second Modification (Modification of Gate Electrode Processing Step)
4). Second embodiment (configuration having a groove in an element isolation region of a photodiode)
5. Third embodiment (configuration having a groove below the transfer gate)
6). Third modification (configuration in which no groove is provided in the element isolation region of the photodiode in the third embodiment)
7). Fourth Embodiment (Camera Using Solid-State Imaging Device)

<First Embodiment>
[Plan view of solid-state imaging device]
FIG. 1 is a plan view of a CMOS image sensor which is a solid-state imaging device according to the present embodiment.
In the solid-state imaging device according to the present embodiment, for example, the photodiode PD is formed by being divided for each pixel arranged in a matrix on the light receiving surface of the semiconductor substrate.
For example, a transfer gate electrode TG is formed in a region adjacent to the photodiode PD, and a floating diffusion FD is formed in a region adjacent to the transfer gate electrode TG.

For example, in the present embodiment, a set of four photodiodes PD separated from each other in the element isolation region I are arranged in a matrix. A transfer gate electrode TG, a floating diffusion FD, a contact CT, and other transistors are arranged in a region between the photodiode sets.
For example, the floating diffusion FD is connected to four photodiodes PD surrounding the floating diffusion FD through four transfer gate electrodes TG. In other words, one floating diffusion FD is shared by four pixels.

  For example, the photodiode PD accumulates signal charges generated by the photoelectric effect when receiving light. An amplification transistor, a selection transistor, and the like are connected to the floating diffusion FD, and a signal reading unit that reads a voltage corresponding to a signal charge is configured. Further, a reset transistor is connected to the floating diffusion FD, so that signal charges accumulated in the photodiode PD and the floating diffusion FD can be removed.

In the CMOS image sensor of this embodiment, the inversion layer induction electrode PG is formed on the semiconductor substrate via the gate insulating film in a region that covers a part or all of the photodiode PD.
The inversion layer induction electrode PG is made of a conductor or semiconductor having a work function larger than that of the transfer gate electrode TG. An inversion layer in which carriers of the second conductivity type are accumulated is induced on the surface of the first conductivity type semiconductor region constituting the photodiode PD on the inversion layer induction electrode PG side by the inversion layer induction electrode PG. For example, an inversion layer in which holes that are P-type carriers are accumulated is induced on the surface of the N-type semiconductor region constituting the photodiode PD on the inversion layer induction electrode PG side.

  In the CMOS image sensor of this embodiment, as will be described later, in a region (not shown), a CMOS transistor composed of an NMOS transistor and a PMOS transistor forming a logic circuit or the like is formed on the same substrate as a semiconductor substrate having a light receiving surface. Has been.

[Cross-sectional view of solid-state imaging device]
FIG. 2A is a cross-sectional view of the solid-state imaging device according to the present embodiment. For example, corresponding to the photodiode region _{A PD} and the transfer gate region _{A TG} X-X in FIG. 1 'sectional view in the X-X in FIG. 2 (a)' indicated by. The transfer gate region _ATG includes a transfer gate electrode and a floating diffusion region. Further, for example, FIG. 2A also shows an NMOS transistor region A _NMOS and a PMOS transistor region A _PMOS constituting a logic circuit (not shown in FIG. 1).

For example, in the photodiode region _APD divided by the element isolation region 10b, the N-type semiconductor region 17 constituting the photodiode is formed in the semiconductor substrate 10 made of P-type silicon. The semiconductor substrate 10 may be a bulk silicon substrate or an SOI (Silicon on Insulator) substrate.
A P-type semiconductor layer 26 is formed on the surface layer portion of the semiconductor region 17 at the end of the photodiode region _APD .
In the transfer gate region _ATG adjacent to the region of the P-type semiconductor layer 26, a conductive layer 21 a made of N-type polysilicon, which is a transfer gate electrode, is formed on the semiconductor substrate 10 via the gate insulating film 20. Further, an N-type semiconductor layer 30 which is a floating diffusion is formed in a region adjacent to the conductive layer 21a which is a transfer gate electrode.

In the CMOS image sensor of the present embodiment, a conductive layer 21b made of P-type polysilicon that is an inversion layer induction electrode is formed on the semiconductor substrate 10 via the gate insulating film 20 in a region that covers a part or all of the photodiode. Is formed. As shown in FIG. 2A, the conductive layer 21b which is the inversion layer induction electrode is formed integrally with the conductive layer 21b which is the inversion layer induction electrode formed on the adjacent photodiode.
In the above, sidewall insulating films 27 are formed on the side surfaces of the N-type conductive layer 21a and the P-type conductive layer 21b.

In the CMOS image sensor of this embodiment, the NMOS transistor and the PMOS transistor constituting the logic circuit and the like are formed on the semiconductor substrate 10 in the NMOS transistor region A _NMOS and the PMOS transistor region _APMOS . The NMOS transistor and the PMOS transistor constitute a CMOS transistor.
That is, an element isolation insulating film 14 is formed by an STI (Shallow Trench Isolation) method embedded in an element isolation trench 10 a formed in the semiconductor substrate 10. In the NMOS transistor region A _NMOS separated by the element isolation insulating film 14, a conductive layer 21 a made of N-type polysilicon, which is a gate electrode, is formed on the semiconductor substrate 10 via a gate insulating film 20.
In the above, the sidewall insulating film 27 is formed on the side surface of the N-type conductive layer 21a, and the N-type semiconductor layer 29 which is the source / drain region is formed in the semiconductor substrate 10 on both sides thereof. The NMOS transistor is configured as described above.

Further, the segmented PMOS transistor region _{A PMOS} element isolation insulating film 14 by an STI method of the semiconductor substrate 10, N-type well 16 is formed. Further, a conductive layer 21b made of P-type polysilicon which is a gate electrode is formed on the semiconductor substrate 10 with a gate insulating film 20 interposed therebetween.
In the above, the sidewall insulating film 27 is formed on the side surface of the P-type conductive layer 21b, and the P-type semiconductor layer 32 which is the source / drain region is formed in the semiconductor substrate 10 on both sides thereof. A PMOS transistor is configured as described above.

FIG. 2B is a cross-sectional view of the solid-state imaging device according to this embodiment.
Although substantially the same as FIG. 2A, the inversion layer 17a is induced on the surface of the N-type semiconductor region 17 on the side of the conductive layer 21b made of P-type polysilicon which is the inversion layer induction electrode. Show.
For example, the inversion layer inducing electrode is made of a conductor or semiconductor having a work function larger than that of the transfer gate electrode. In this embodiment, the inversion layer induction electrode is made of P-type polysilicon, and the transfer gate electrode is made of N-type polysilicon.
An inversion layer 17a formed by accumulating holes as P-type carriers is induced on the surface of the N-type semiconductor region 17 constituting the photodiode on the inversion layer induction electrode side by the inversion layer induction electrode.
The inversion layer induction electrode has an effect of inducing the inversion layer 17a due to the work function of the inversion layer induction electrode even when no voltage is applied. For example, a higher concentration of holes is accumulated by applying a negative voltage. Thus, the effective carrier concentration in the inversion layer 17a can be increased. The holes on the surface are effective in reducing the leakage current caused by the substrate surface, and the higher the concentration, the more the leakage can be reduced. The reason why the surface inversion layer 17a is induced will be described later.

  It is preferable that the effective concentration of the N-type impurity in the semiconductor region 17 has a smooth concentration gradient that is higher as it is closer to the surface of the semiconductor substrate. In this case, the signal charge generated by the photodiode moves smoothly to the vicinity of the substrate surface. The signal charge is captured by the potential and accumulated in the photodiode PD.

In addition, an insulating film, an upper layer wiring, and the like are formed on the semiconductor substrate so as to cover the photodiode.
When the light incident surface is on the back side of the substrate (direction A in FIG. 2B), a color filter or the like is formed on the back side of the substrate as necessary. Furthermore, an optical waveguide, an on-chip lens, or the like may be provided on the back side of the substrate. In the above configuration, the inversion layer induction electrode formed by covering the photodiode may not be transparent to the incident light. For example, the inversion layer induction electrode can be formed of P-type polysilicon which is the same layer as the gate electrode of the PMOS transistor. In addition, when incident light from the back side of the substrate is transmitted without being absorbed by the photodiode, a metal film such as copper is used as a film reflective to the incident light so that the light is returned to the photodiode region again. Is also possible.
The inversion layer inducing electrode is made of a conductor or semiconductor having a work function larger than that of the transfer gate electrode, for example, P-type silicon, P-type polysilicon, copper, tungsten, NiSi, CoSi, TiN, ITO (indium tin oxide), etc. Can be used.

  Alternatively, when the light incident surface is on the substrate surface side (direction B in FIG. 2B), an optical waveguide is provided in the insulating film on the substrate as necessary, and a color filter, an on-chip lens, or the like is provided on the upper layer. Is formed. In the above configuration, it is important that the inversion layer inducing electrode formed by covering the photodiode is transmissive to incident light. For example, it can be formed of a transparent electrode such as ITO. Alternatively, even polysilicon has a certain degree of light transmittance depending on the film thickness, and can be used if applicable. Since the inversion layer induction electrode such as polysilicon can reduce the interface state on the substrate surface, it has an effect of reducing noise caused by the surface of the photodiode, and can be preferably applied to a device in which reduction of surface noise is important. Depending on device conditions, the inversion layer inducing electrode can be selected from the above materials.

  In FIGS. 2A and 2B, the insulating film, upper layer wiring, optical waveguide, color filter, and on-chip lens are not shown.

[Energy band of photodiodes constituting a solid-state imaging device]
FIGS. 3A to 3D are energy band diagrams of the photodiode region of the CMOS image sensor according to this embodiment and the CMOS image sensor according to the comparative example.
3A and 3B are energy band diagrams of the photodiode region of the CMOS image sensor according to this embodiment. The energy band in the cross section of the conductive layer 21b which is an inversion layer induction electrode, the gate insulating film 20, and the semiconductor region 17 in YY ′ in FIG. Here, FIG. 3A shows a case where the voltage applied to the inversion layer induction electrode is zero, and FIG. 3B shows a case where a predetermined negative voltage is applied.

  3C and 3D are energy band diagrams of the photodiode region of the CMOS image sensor according to the comparative example. In the comparative example, the inversion layer inducing electrode is composed of a conductive layer 21a made of N-type polysilicon, which corresponds to the cross section taken along the line Y-Y 'in FIG. Here, FIG. 3C shows a case where the applied voltage to the inversion layer induction electrode is zero, and FIG. 3D shows a case where a predetermined negative voltage is applied.

  In the CMOS image sensor of the comparative example, when the applied voltage is zero as shown in FIG. 3C, the conductive layer 21a and the semiconductor region 17 have the same potential, and the inversion layer is not induced. When a predetermined negative potential is applied as shown in FIG. 3D, holes h accumulate on the surface of the semiconductor region 17 on the conductive layer 21a side, and the inversion layer 17a is induced.

In the CMOS image sensor of this embodiment, when a material having a sufficiently large work function such as P-type polysilicon is used for the inversion layer induction electrode, even when the applied voltage is zero as shown in FIG. For example, holes h accumulate on the surface of the semiconductor region 17 on the conductive layer 21b side as in the case shown in FIG. 3D, and the inversion layer 17a is induced. This is because the work function of the conductive layer 21b is larger than that of the conductive layer 21a.
Further, as shown in FIG. 3B, when a predetermined negative potential is applied to the conductive layer 21b, holes having a higher concentration can be accumulated to increase the effective carrier concentration in the inversion layer 17a.

In the solid-state imaging device according to the present embodiment, an inversion layer induction electrode is formed in a region covering a part or all of the photodiode, and carriers of the second conductivity type are accumulated on the surface of the semiconductor region on the inversion layer induction electrode side. An inversion layer is induced. As a result, the PN junction can be sharpened to improve the dynamic range.
In addition, as described later, in the method for manufacturing a solid-state imaging device, it is possible to perform a heat treatment for recovering defects introduced by gate etching, sidewall etch back, and the like. In addition, the conductive layer itself, which is the inversion layer induction electrode that covers the photodiode, suppresses the introduction of defects into the photodiode region during the etching process. Thereby, an increase in dark current can be avoided and yield reduction can be suppressed.

[Method for Manufacturing Solid-State Imaging Device]
4 to 8 are cross-sectional views illustrating manufacturing steps of the method for manufacturing the solid-state imaging device according to the present embodiment. With reference to these drawings, a method for manufacturing a CMOS image sensor which is the solid-state imaging device of the present embodiment will be described.
The drawing shows a cross-sectional view corresponding to FIGS. 2A and 2B and shows a photodiode region A _PD , a transfer gate region A _TG , an NMOS transistor region A _NMOS and a PMOS transistor region A _PMOS .

First, as shown in FIG. 4A, for example, in the NMOS transistor region A _NMOS and the PMOS transistor region _APMOS , the element isolation trench 10a is formed in the semiconductor substrate 10 by the STI method, and the element isolation insulating film 14 is formed. To do. For example by ion implantation of N type impurities to form N-type well 16 in the PMOS transistor region _{A PMOS.} For the formation of the N-type well 16, P is formed by a combination of ion implantation with an implantation energy of 0.2 to 1000 keV and a dose of 1 × 10 ¹¹ to 1 × 10 ¹³ / cm ² .
Further, in the photodiode region A _PD and the transfer gate region A _TG performs isolation by P-type isolation region 10b, to form an N-type semiconductor region 17 constituting the photodiode in the photodiode region A _PD. For example, to form the N-type semiconductor region 17, P is formed by a combination of implantation energy of 50 to 3000 keV and ion implantation of a dose amount of 1 × 10 ¹¹ to 1 × 10 ¹³ / cm ² .
Further, other wells, channel impurities and element isolation impurities are ion-implanted as necessary.
The semiconductor substrate 10 may be a bulk silicon substrate or an SOI substrate.

  In the formation of the semiconductor region 17, for the reasons described above, it is preferable to form the semiconductor region 17 so that the effective concentration of the N-type impurity has a smooth concentration gradient as the concentration is closer to the surface of the semiconductor substrate.

Next, as shown in FIG. 4B, for example, a gate insulating film 20 is formed on the surface of the semiconductor substrate 10 in the photodiode region A _PD , the transfer gate region A _TG , the NMOS transistor region A _NMOS, and the PMOS transistor region A _PMOS . To do. The gate insulating film 20 is formed by depositing silicon oxide by, for example, a thermal oxidation method or a CVD (Chemical Vapor Deposition) method. Next, a polysilicon layer 21 is formed to a thickness of 80 to 250 nm on the gate insulating film 20 by, eg, CVD.

Next, as shown in FIG. 5A, for example, a resist film 22 that protects the photodiode region _APD and the PMOS transistor region _APMOS is patterned. Using the resist film 22 as a mask, in the transfer gate region _ATG and the NMOS transistor region A _NMOS , an N-type conductive impurity such as P is introduced into the polysilicon layer 21 to form an N-type conductive layer 21a. For example, the dose is set to 0 to 1 × 10 ¹⁶ / cm ² with an implantation energy of 5 to 30 keV.

Next, as shown in FIG. 5B, for example, a resist film 23 for protecting the transfer gate region _ATG and the NMOS transistor region _ANMOS is patterned. Using the resist film 23 as a mask, in the photodiode region _APD and the PMOS transistor region _APMOS , a P type conductive impurity such as B is introduced into the polysilicon layer 21 to form a P type conductive layer 21b. For example, the dose amount is 0 to 1 × 10 ¹⁶ / cm ² with an implantation energy of 3 to 15 keV.

Next, as shown in FIG. 6A, for example, a resist film 24 is patterned on the conductive layer 21a and the conductive layer 21b.
Resist film 24 has a pattern of the photo diode region inversion layer induced electrodes _{A PD,} transfer gate electrodes of the transfer gate region _{A TG,} NMOS transistor region _{A NMOS} and PMOS transistor regions _{A PMOS} gate electrode.

Next, as shown in FIG. 6B, for example, an etching process is performed using the resist film 24 as a mask. As the etching process, for example, an anisotropic etching process such as RIE (reactive ion etching) using plasma of a mixed gas of Cl ₂ + O ₂ is used.
Thus, the conductive layer 21b as the inversion layer inducing electrode, the conductive layer 21a as the transfer gate electrode, the conductive layer 21a as the gate electrode of the NMOS transistor, and the conductive layer 21b as the gate electrode of the PMOS transistor are pattern-formed. The conductive layer 21b which is the inversion layer induction electrode is formed integrally with the conductive layer 21b which is the inversion layer induction electrode on the photodiode of the adjacent pixel.
In the above etching process, the gate insulating film 20 is also processed into the same pattern as each conductive layer (21a, 21b).

  Here, the width W between the conductive layer 21b that is the inversion layer induction electrode and the conductive layer 21a that is the transfer gate electrode is a distance that allows the P-type conductive layer 21b and the N-type conductive layer 21a to be sufficiently separated. Good. For example, it can be formed with the minimum design rule that can be processed. For example, it is 50 to 300 nm.

Next, as shown in FIG. 7 (a), for example, a resist film 25 for exposing the region adjacent to the transfer gate area A _TG A end portion of the photodiode region A _PD. P-type impurities such as B are ion-implanted using the resist film 25 as a mask, and a part of the PN junction that becomes a photodiode is formed as the semiconductor region 17 in the surface layer portion of the semiconductor region 17 at the end of the photodiode region _APD. A P-type semiconductor layer 26 is formed. For example, the dosage is set to 1 × 10 ^{12 to} 5 × 10 ¹³ cm ² with an implantation energy of 0.2 to 10 keV.

Next, as shown in FIG. 7B, for example, a 5 to 30 nm silicon oxide film and a 30 to 100 nm silicon nitride film are stacked on the entire surface by CVD, and an etch back process is performed on the front surface. Thereby, in the photodiode region A _PD , the transfer gate region A _TG , the NMOS transistor region A _NMOS and the PMOS transistor region A _PMOS , the sidewall insulating film 27 is formed on the side surfaces of the N-type conductive layer 21a and the P-type conductive layer 21b. Form.
For example, the etching back process is an anisotropic etching process such as RIE (reactive ion etching) using plasma of a mixed gas of CF ₄ + O ₂ , for example.
The width W between the conductive layer 21b serving as the inversion layer induction electrode and the conductive layer 21a serving as the transfer gate electrode may be entirely filled with the sidewall insulating film 27.

Next, as shown in FIG. 8A, for example, a resist film 28 that protects the photodiode region _APD and the PMOS transistor region _APMOS is patterned. Next, N-type conductive impurities such as P are introduced using the resist film 28 as a mask. NMOS transistor region A In the _NMOS , an N-type semiconductor layer 29 which is an N-type source / drain region is formed. Further, a semiconductor layer 30 of N-type is a floating diffusion in transfer gate region A _TG. Here, for example, the dosage is set to 1 × 10 ^{15 to} 5 × 10 ¹⁵ / cm ² with an implantation energy of 5 to 20 keV.

Next, as shown in FIG. 8 (b), for example, the transfer gate region _{A TG} and, (region of the semiconductor layer 26) end adjacent to the transfer gate area _{A TG} photodiode region _{A PD} and the NMOS transistor region _{A NMOS} A resist film 31 for protecting the pattern is formed. Next, using the resist film 31 as a mask, a P-type conductive impurity such as B is introduced. PMOS transistor region A In the _PMOS , a P-type semiconductor layer 32 which is a P-type source / drain region is formed. Further, in the photodiode region A _PD increase the P-type impurity concentration in the P-type conductive layer 21b. Here, for example, the dose amount is 1 × 10 ^{15 to} 5 × 10 ¹⁵ / cm ² with an implantation energy of 2 to 8 keV.
After the above ion implantation, an RTA (Rapid Thermal Annealing) process is performed at 1000 to 1100 ° C. for about 0 to 20 seconds to activate impurities and recover defects.

  As the subsequent steps, for example, when the light incident surface is the substrate back side (direction A in FIG. 2B), the substrate back surface is ground to reduce the thickness of the substrate, and further the substrate back side as necessary. A color filter or the like is formed on the substrate. Further, an optical waveguide or an on-chip lens may be provided.

Alternatively, for example, when the light incident surface is on the substrate surface side (the B direction in FIG. 2B), an optical waveguide is provided in the insulating film on the substrate as necessary, and a color filter and on-chip are provided on the upper layer. Form a lens.
Through the above steps, a CMOS image sensor having the configuration shown in FIGS. 2A and 2B can be manufactured.

In the manufacturing method of the solid-state imaging device according to the present embodiment, the inversion layer induction electrode is formed in a region covering part or all of the photodiode, and the second conductivity type carriers are accumulated on the surface of the semiconductor region on the inversion layer induction electrode side. Thus, a solid-state imaging device in which the inversion layer is induced can be manufactured.
In addition, heat treatment for recovering defects introduced by gate etching, sidewall etchback, or the like can be performed. In addition, the conductive layer itself, which is the inversion layer induction electrode that covers the photodiode, suppresses the introduction of defects into the photodiode region during the etching process. Thereby, an increase in dark current can be avoided and yield reduction can be suppressed.

<First Modification>
[Extrusion of signal charge by inversion layer induced electrode applied voltage]
In the first embodiment, the applied voltage to the inversion layer induction electrode may be basically fixed at a predetermined negative voltage, but the applied voltage may be varied at a certain timing as in this modification.
FIG. 9 is a timing chart of the applied voltage of the solid-state imaging device according to this modification. The voltage applied to the inversion layer induced electrode S _PG, applied voltage S _TG to the transfer gate _electrode, the applied voltage S _R to the gate of the reset transistor.
During the charge accumulation period T at a field, a predetermined negative voltage as the voltage applied S _PG to the inversion layer induced electrode (-) is applied to. The applied voltage _STG to the transfer gate electrode is zero and the transfer gate is closed.
At time t1 when the charge accumulation period T ends, the voltage _STG applied to the transfer gate electrode is set to (+), the transfer gate is opened, and the accumulated signal charge is transferred to the floating diffusion. Here, the applied voltage S _PG The greater negative voltage to the inversion layer induced electrode (-) by applying a, can form a sufficient push potential signal charges to the floating diffusion. Thus, the signal charge in the photodiode can be depleted.
At time t2 the transfer of the signal charges is completed, the voltage applied to S _TG to the transfer gate electrode returned to zero, the applied voltage S _PG also predetermined negative voltage to the inversion layer induced electrode - back to ().
At time t3 to start the reset operation, to remove the signal charge voltages applied S _R to the gate of the reset transistor as (+).
From time t4 when the reset operation ends, the charge accumulation period of the next field starts.

<Second Modification>
[Modification of gate electrode processing process]
FIGS. 10A to 10C are cross-sectional views illustrating manufacturing steps of the method for manufacturing the solid-state imaging device according to the second modification.
The steps up to FIG. 5B are the same as in the above embodiment.
Next, as shown in FIG. 10A, for example, a hard mask 40 is patterned on the conductive layer 21a and the conductive layer 21b.
Hard mask 40 has the inversion layer induced electrode of the photo diode region _{A PD,} transfer gate electrodes of the transfer gate region _{A TG,} a pattern of the NMOS transistor region _{A NMOS} and PMOS transistor regions _{A PMOS} gate electrode. This can be obtained, for example, by forming a silicon nitride film and etching the pattern.
Next, as shown in FIG. 10B, sidewalls 41 are formed on the sides of the hard mask 40. This can be formed, for example, by depositing a silicon nitride film on the entire surface and etching back.
Next, as shown in FIG. 10C, the conductive layers (21a, 21b) are etched and patterned using the hard mask 40 and the sidewalls 41 as a mask. The width between the conductive layer 21b serving as the inversion layer induction electrode and the conductive layer 21a serving as the transfer gate electrode can be formed narrower than the minimum processable design rule.
After the above steps, the hard mask 40 and the sidewalls 41 are removed, and the manufacturing can be performed in the same manner as in the first embodiment.

Second Embodiment
[Plan view of solid-state imaging device]
FIG. 11 is a plan view of a CMOS image sensor which is a solid-state imaging device according to the present embodiment. FIG. 12A is a cross-sectional view of the solid-state imaging device according to this embodiment. For example, X-X 'in FIG. 11 cross-sectional view taken along the X-X in FIG. 12 (a)' corresponding to the photodiode region _{A PD} and the transfer gate region _{A TG} shown in.
In the element isolation region I (10b) for dividing the photodiode for each pixel, a recess 10c that exposes the side surface of the semiconductor region 17 is formed on the semiconductor substrate. On the side surface of the semiconductor region 17, a conductive layer 21 b serving as an inversion layer induction electrode is formed via the gate insulating film 20.

FIG. 12B is a cross-sectional view of the solid-state imaging device according to the present embodiment.
Although substantially the same as FIG. 12A, the inversion layer 17a is induced on the surface of the N-type semiconductor region 17 on the side of the conductive layer 21b made of P-type polysilicon which is the inversion layer inducing electrode. Show.
Here, as described above, in the element isolation region I (10b), the recess 10c exposing the side surface of the semiconductor region 17 is formed in the semiconductor substrate, and the conductive layer 21b is formed in the recess 10c via the gate insulating film 20. Has been. For this reason, the inversion layer 17a is induced from the side surface of the semiconductor region.
Except for the above, the configuration is substantially the same as in the first embodiment.

In the solid-state imaging device according to the present embodiment, an inversion layer induction electrode is formed in a region covering a part or all of the photodiode, and carriers of the second conductivity type are accumulated on the surface of the semiconductor region on the inversion layer induction electrode side. An inversion layer is induced. As a result, the PN junction can be sharpened to improve the dynamic range.
In addition, as described later, in the method for manufacturing a solid-state imaging device, it is possible to perform a heat treatment for recovering defects introduced by gate etching, sidewall etch back, and the like. In addition, the conductive layer itself, which is the inversion layer induction electrode that covers the photodiode, suppresses the introduction of defects into the photodiode region during the etching process. Thereby, an increase in dark current can be avoided and yield reduction can be suppressed.

[Method for Manufacturing Solid-State Imaging Device]
13 to 20 are cross-sectional views illustrating manufacturing steps of the method for manufacturing the solid-state imaging device according to the present embodiment. With reference to these drawings, a method for manufacturing a CMOS image sensor which is the solid-state imaging device of the present embodiment will be described.

The drawing shows a cross-sectional view corresponding to FIGS. 12A and 12B and shows a photodiode region A _PD , a transfer gate region A _TG , an NMOS transistor region A _NMOS, and a PMOS transistor region A _PMOS .

First, as shown in FIG. 13A, for example, silicon nitride is deposited on the entire surface of the semiconductor substrate 10 with a film thickness of 100 to 250 nm by the CVD method to form the hard mask 11.
The semiconductor substrate 10 may be a bulk silicon substrate or an SOI substrate.

Next, as shown in FIG. 13B, for example, a resist film 12 that opens the element isolation region in the NMOS transistor region A _NMOS and the PMOS transistor region A _{PMOS and} the element isolation region in the photodiode region _APD is patterned.

Next, as shown in FIG. 13C, for example, the hard mask 11 is pattern-etched using the resist film 12 as a mask. Further, in the NMOS transistor region A _NMOS and the PMOS transistor region A _PMOS , an element isolation groove 10 a is formed in the surface layer of the semiconductor substrate 10. A recess 10c is also formed in the element isolation region 10b of the photodiode region _APD .
The above etching is performed by, for example, RIE of a CF ₄ + O ₂ mixed gas, and the depth of the element isolation trench 10a and the recess 10c is set to 0 to 300 nm.

Next, as shown in FIG. 14A, for example, after the resist film 12 is removed, a resist film 13 opening the NMOS transistor region A _NMOS and the PMOS transistor region A _PMOS is patterned.

Next, as shown in FIG. 14B, for example, the depth of the element isolation trench 10a in the NMOS transistor region A _NMOS and the PMOS transistor region A _PMOS is deeply processed using the resist film 13 as a mask.
The above etching is performed, for example, by RIE of a Cl ₂ + O ₂ mixed gas, and the depth of the element isolation groove 10a and the recess 10c is set to 200 to 500 nm in combination with the previous etching.

Next, as shown in FIG. 15A, silicon oxide is deposited to a thickness of 200 to 800 nm on the entire surface by filling the element isolation trench 10a and the recess 10c by, for example, a CVD method. Next, the silicon oxide deposited outside the element isolation trench 10a and the recess 10c is removed by CMP (Chemical Mechanical Polishing) and planarized.
Thus, the element isolation insulating film 14 embedded in the element isolation trench 10a is formed. A dummy film 15a is formed in the recess 10c.
Further, the silicon nitride hard mask 11 is removed by hot phosphoric acid treatment. The protrusion amount of the element isolation insulating film 14 from the semiconductor substrate 10 is adjusted by dilute hydrofluoric acid treatment after the CMP treatment.

Next, as shown in FIG. 15B, for example, an N-type well 16 is formed by ion implantation of an N-type impurity in the PMOS transistor region _APMOS . For the formation of the N-type well 16, P is formed by a combination of ion implantation with an implantation energy of 0.2 to 1000 keV and a dose of 1 × 10 ¹¹ to 1 × 10 ¹³ / cm ² .
In addition, an N-type semiconductor region 17 constituting the photodiode is formed in the photodiode region _APD . For example, to form the N-type semiconductor region 17, P is formed by a combination of implantation energy of 50 to 3000 keV and ion implantation of a dose amount of 1 × 10 ¹¹ to 1 × 10 ¹³ / cm ² .
Further, other wells, channel impurities and element isolation impurities are ion-implanted as necessary.

  In the formation of the semiconductor region 17, it is preferable to form the semiconductor region 17 so as to have a smooth concentration gradient in which the effective concentration of the N-type impurity becomes higher as it is closer to the surface of the semiconductor substrate.

Next, as shown in FIG. 16A, for example, the NMOS transistor region A _NMOS and the PMOS transistor region A _PMOS are protected, and a resist film 18 that opens the photodiode region _APD and the transfer gate region _ATG is patterned. To do.
Next, for example, wet etching with dilute hydrofluoric acid is performed using the resist film 18 as a mask to remove the silicon oxide dummy film 15a. As a result, a recess 10 c that exposes the side surface of the semiconductor region 17 is formed.

Next, as shown in FIG. 16B, for example, a gate insulating film 20 is formed on the surface of the semiconductor substrate 10 in the photodiode region A _PD , the transfer gate region A _TG , the NMOS transistor region A _NMOS and the PMOS transistor region A _PMOS . To do. The gate insulating film 20 is formed by depositing silicon oxide by, for example, a thermal oxidation method or a CVD method. At this time, the gate insulating film 20 is formed so as to cover the side surface of the semiconductor region 17 in the recess 10c.
Next, a polysilicon layer 21 is formed to a thickness of 80 to 250 nm on the gate insulating film 20 by, eg, CVD. At this time, the polysilicon layer 21 is formed so as to have a buried layer 21c filling the upper layer of the gate insulating film 20 in the recess 10c.

Next, as shown in FIG. 17A, for example, a resist film 22 that protects the photodiode region _APD and the PMOS transistor region _APMOS is patterned. Using the resist film 22 as a mask, in the transfer gate region _ATG and the NMOS transistor region A _NMOS , an N-type conductive impurity such as P is introduced into the polysilicon layer 21 to form an N-type conductive layer 21a. For example, the dose is 1 × 10 ¹⁵ / cm ² with an implantation energy of 5 to 30 keV.

Next, as shown in FIG. 17B, for example, a resist film 23 that protects the transfer gate region _ATG and the NMOS transistor region _ANMOS is patterned. Using the resist film 23 as a mask, in the photodiode region _APD and the PMOS transistor region _APMOS , a P type conductive impurity such as B is introduced into the polysilicon layer 21 to form a P type conductive layer 21b. For example, the dose amount is 0 to 1 × 10 ¹⁶ / cm ² with an implantation energy of 3 to 15 keV.
The drawing shows a state in which P-type conductive impurities are not diffused to the buried layer 21c in the recess 10c.

Next, as shown in FIG. 18A, for example, a resist film 24 is patterned on the conductive layer 21a and the conductive layer 21b.
Resist film 24 has a pattern of the photo diode region inversion layer induced electrodes _{A PD,} transfer gate electrodes of the transfer gate region _{A TG,} NMOS transistor region _{A NMOS} and PMOS transistor regions _{A PMOS} gate electrode.

Next, as shown in FIG. 18B, for example, an etching process is performed using the resist film 24 as a mask. As the etching process, for example, an anisotropic etching process such as RIE (reactive ion etching) using plasma of a mixed gas of Cl ₂ + O ₂ is used.
Thus, the conductive layer 21b as the inversion layer inducing electrode, the conductive layer 21a as the transfer gate electrode, the conductive layer 21a as the gate electrode of the NMOS transistor, and the conductive layer 21b as the gate electrode of the PMOS transistor are pattern-formed. The conductive layer 21b which is the inversion layer induction electrode is formed integrally with the conductive layer 21b which is the inversion layer induction electrode on the photodiode of the adjacent pixel.
In the above etching process, the gate insulating film 20 is also processed into the same pattern as each conductive layer (21a, 21b).

  Here, the width W between the conductive layer 21b that is the inversion layer induction electrode and the conductive layer 21a that is the transfer gate electrode is a distance that allows the P-type conductive layer 21b and the N-type conductive layer 21a to be sufficiently separated. Good. For example, it can be formed with the minimum design rule that can be processed. For example, it is 50 to 300 nm.

Next, as shown in FIG. 19 (a), for example, a resist film 25 for exposing the region adjacent to the transfer gate area A _TG A end portion of the photodiode region A _PD. P-type impurities such as B are ion-implanted using the resist film 25 as a mask, and a part of the PN junction that becomes a photodiode is formed as the semiconductor region 17 in the surface layer portion of the semiconductor region 17 at the end of the photodiode region _APD. A P-type semiconductor layer 26 is formed. For example, the dosage is set to 1 × 10 ¹² to 1 × 10 ¹³ cm ² with an implantation energy of 0.2 to 10 keV.

Next, as shown in FIG. 19B, for example, a 5 to 30 nm silicon oxide film and a 30 to 100 nm silicon nitride film are stacked on the entire surface by CVD, and an etch back process is performed on the front surface. Thereby, in the photodiode region A _PD , the transfer gate region A _TG , the NMOS transistor region A _NMOS and the PMOS transistor region A _PMOS , the sidewall insulating film 27 is formed on the side surfaces of the N-type conductive layer 21a and the P-type conductive layer 21b. Form.
For example, the etching back process is an anisotropic etching process such as RIE (reactive ion etching) using plasma of a mixed gas of CF ₄ + O ₂ , for example.
The width W between the conductive layer 21b serving as the inversion layer induction electrode and the conductive layer 21a serving as the transfer gate electrode may be entirely filled with the sidewall insulating film 27.

Next, as shown in FIG. 20A, for example, a resist film 28 that protects the photodiode region _APD and the PMOS transistor region _APMOS is patterned. Next, N-type conductive impurities such as P are introduced using the resist film 28 as a mask. NMOS transistor region A In the _NMOS , an N-type semiconductor layer 29 which is an N-type source / drain region is formed. Further, a semiconductor layer 30 of N-type is a floating diffusion in transfer gate region A _TG. Here, for example, the dosage is set to 1 × 10 ^{15 to} 5 × 10 ¹⁵ / cm ² with an implantation energy of 5 to 20 keV.

Next, as shown in FIG. 20 (b), for example, the transfer gate region _{A TG} and, (region of the semiconductor layer 26) end adjacent to the transfer gate area _{A TG} photodiode region _{A PD} and the NMOS transistor region _{A NMOS} A resist film 31 for protecting the pattern is formed. Next, using the resist film 31 as a mask, a P-type conductive impurity such as B is introduced. PMOS transistor region A In the _PMOS , a P-type semiconductor layer 32 which is a P-type source / drain region is formed. Further, in the photodiode region A _PD increase the P-type impurity concentration in the P-type conductive layer 21b. Here, for example, the dose amount is 1 × 10 ^{15 to} 5 × 10 ¹⁵ / cm ² with an implantation energy of 2 to 8 keV.
After the above ion implantation, an RTA (Rapid Thermal Annealing) process is performed at 1000 to 1100 ° C. for about 0 to 20 seconds to activate impurities and recover defects.
With the above RTA treatment, the P-type conductive impurity diffuses to the buried layer 21c in the recess 10c.

  As a subsequent process, for example, when the light incident surface is on the back side of the substrate (direction A in FIG. 12B), the back surface of the substrate is ground to reduce the thickness of the substrate. A color filter or the like is formed on the substrate. Further, an optical waveguide or an on-chip lens may be provided.

Alternatively, for example, when the light incident surface is on the substrate surface side (direction B in FIG. 12B), an optical waveguide is provided in the insulating film on the substrate as necessary, and a color filter and an on-chip are provided on the upper layer. Form a lens.
Through the above steps, a CMOS image sensor having the configuration shown in FIGS. 12A and 12B can be manufactured.

In the manufacturing method of the solid-state imaging device according to the present embodiment, the inversion layer induction electrode is formed in a region covering part or all of the photodiode, and the second conductivity type carriers are accumulated on the surface of the semiconductor region on the inversion layer induction electrode side. Thus, a solid-state imaging device in which the inversion layer is induced can be manufactured.
In addition, heat treatment for recovering defects introduced by gate etching, sidewall etchback, or the like can be performed. In addition, the conductive layer itself, which is the inversion layer induction electrode that covers the photodiode, suppresses the introduction of defects into the photodiode region during the etching process. Thereby, an increase in dark current can be avoided and yield reduction can be suppressed.

<Third Embodiment>
[Plan view of solid-state imaging device]
FIG. 21 is a plan view of a CMOS image sensor which is a solid-state imaging device according to this embodiment. The CMOS image sensor of this embodiment has a structure having a groove below the transfer gate.
FIG. 21 is a plan view of a CMOS image sensor which is a solid-state imaging device according to this embodiment. FIG. 22A is a cross-sectional view of the solid-state imaging device according to this embodiment. For example, corresponding to the photodiode region _{A PD} and the transfer gate region _{A TG} X-X in FIG. 21 'sectional view in the X-X in FIG. 22 (a)' indicated by.
In the element isolation region I (10b) for dividing the photodiode for each pixel, a recess 10c that exposes the side surface of the semiconductor region 17 is formed on the semiconductor substrate. On the side surface of the semiconductor region 17, a conductive layer 21 b serving as an inversion layer induction electrode is formed via the gate insulating film 20.

FIG. 22B is a cross-sectional view of the solid-state imaging device according to this embodiment.
Although substantially the same as FIG. 22A, the inversion layer 17a is induced on the surface of the N-type semiconductor region 17 on the side of the conductive layer 21b made of P-type polysilicon which is the inversion layer induction electrode. Show.
Here, as described above, in the element isolation region I (10b), the recess 10c exposing the side surface of the semiconductor region 17 is formed in the semiconductor substrate, and the conductive layer 21b is formed in the recess 10c via the gate insulating film 20. Has been. For this reason, the inversion layer 17a is induced from the side surface of the semiconductor region.

In addition, a recess 10d is formed in the semiconductor substrate 10 below the conductive layer 21a that is a transfer gate electrode, and the conductive layer 21a that is a transfer gate electrode is embedded in the recess 10d through the gate insulating film 20. ing.
The buried layer 21d, which is a conductive layer buried in the recess 10d, functions as a so-called vertical gate, and can smoothly and reliably transfer the signal charge accumulated in the photodiode to the floating diffusion.
Also, as the N-type semiconductor region constituting the photodiode in the photodiode region A _PD, in the present embodiment, it shows a structure in which the effective N-type impurity concentration has a low low density region 17b and the high high-concentration region 17c.
Except for the above, the configuration is substantially the same as in the first embodiment.

In the solid-state imaging device according to the present embodiment, an inversion layer induction electrode is formed in a region covering a part or all of the photodiode, and carriers of the second conductivity type are accumulated on the surface of the semiconductor region on the inversion layer induction electrode side. An inversion layer is induced. As a result, the PN junction can be sharpened to improve the dynamic range.
In addition, as described later, in the method for manufacturing a solid-state imaging device, it is possible to perform a heat treatment for recovering defects introduced by gate etching, sidewall etch back, and the like. In addition, the conductive layer itself, which is the inversion layer induction electrode that covers the photodiode, suppresses the introduction of defects into the photodiode region during the etching process. Thereby, an increase in dark current can be avoided and yield reduction can be suppressed.

[Method for Manufacturing Solid-State Imaging Device]
23 to 30 are cross-sectional views illustrating manufacturing steps of the method for manufacturing the solid-state imaging device according to the present embodiment. With reference to these drawings, a method for manufacturing a CMOS image sensor which is the solid-state imaging device of the present embodiment will be described.

The drawing shows a cross-sectional view corresponding to FIGS. 22A and 22B and shows a photodiode region A _PD , a transfer gate region A _TG , an NMOS transistor region A _NMOS and a PMOS transistor region A _PMOS .

First, as shown in FIG. 23A, for example, silicon nitride is deposited on the entire surface of the semiconductor substrate 10 to a thickness of 100 to 250 nm by the CVD method to form the hard mask 11.
The semiconductor substrate 10 may be a bulk silicon substrate or an SOI substrate.

Next, as shown in FIG. 23B, for example, a resist film 12 is formed on the hard mask 11 by patterning.
The resist film 12 opens an element isolation region in the NMOS transistor region A _NMOS and PMOS transistor region A _PMOS, an element isolation region in the photodiode region _APD , and a region to be a vertical gate below the transfer gate.

Next, as shown in FIG. 23C, for example, the hard mask 11 is pattern-etched using the resist film 12 as a mask. Further, in the NMOS transistor region A _NMOS and the PMOS transistor region A _PMOS , an element isolation groove 10 a is formed in the surface layer of the semiconductor substrate 10. A recess 10c is also formed in the element isolation region 10b of the photodiode region _APD . A recess 10d is formed in a region to be a vertical gate below the transfer gate.
The above etching is performed, for example, by RIE of a CF ₄ + O ₂ mixed gas, and the depth of the element isolation trench 10a, the recess 10c, and the recess 10d is set to 0 to 300 nm.

Next, as shown in FIG. 24A, for example, after removing the resist film 12, the resist film 13 opening the NMOS transistor region A _NMOS and the PMOS transistor region A _PMOS is patterned.

Next, as shown in FIG. 24B, for example, the depth of the element isolation trench 10a in the NMOS transistor region A _NMOS and the PMOS transistor region A _PMOS is deeply processed using the resist film 13 as a mask.
The above etching is performed, for example, by RIE of a Cl ₂ + O ₂ mixed gas, and the depth of the element isolation groove 10a and the recess 10c is set to 200 to 500 nm in combination with the previous etching.

Next, as shown in FIG. 25A, silicon oxide is deposited to a thickness of 200 to 800 nm on the entire surface by filling the element isolation trench 10a and the recess 10c by, for example, a CVD method. Next, the silicon oxide deposited outside the element isolation trench 10a and the recess 10c is removed by CMP (Chemical Mechanical Polishing) and planarized.
Thus, the element isolation insulating film 14 embedded in the element isolation trench 10a is formed. A dummy film 15a is formed in the recess 10c, and a dummy film 15b is formed in the recess 10d.
Further, the silicon nitride hard mask 11 is removed by hot phosphoric acid treatment. The protrusion amount of the element isolation insulating film 14 from the semiconductor substrate 10 is adjusted by dilute hydrofluoric acid treatment after the CMP treatment.

Next, as shown in FIG. 25B, for example, an N-type well 16 is formed by ion implantation of an N-type impurity in the PMOS transistor region _APMOS . For the formation of the N-type well 16, P is formed by a combination of ion implantation with an implantation energy of 0.2 to 1000 keV and a dose of 1 × 10 ¹¹ to 1 × 10 ¹³ / cm ² .
In addition, an N-type semiconductor region constituting the photodiode is formed in the photodiode region _APD . In the present embodiment, a configuration having a low concentration region 17b having a low effective N-type impurity concentration and a high concentration region 17c having a high effective N type impurity concentration is shown.
For example, for the formation of the N-type low concentration region 17b and the high concentration region 17c, P is formed by a combination of ion implantation with an implantation energy of 50 to 3000 keV and a dose amount of 1 × 10 ¹¹ to 1 × 10 ¹³ / cm ^2. To do.
Further, other wells, channel impurities and element isolation impurities are ion-implanted as necessary.

  In the formation of the semiconductor region, for the reasons described above, the low-concentration region 17b and the high-concentration region have a smooth concentration gradient in which the effective concentration of the N-type impurity is close to the surface of the semiconductor substrate. It is preferable to form with the structure etc. which have 17c.

Next, as shown in FIG. 26A, for example, a resist film 18 that protects the NMOS transistor region A _NMOS and the PMOS transistor region A _PMOS and opens the photodiode region _APD and the transfer gate region _ATG is patterned. .
Next, for example, wet etching with dilute hydrofluoric acid is performed using the resist film 18 as a mask to remove the silicon oxide dummy film 15a and the dummy film 15b. As a result, a recess 10 c that exposes the side surface of the semiconductor region 17 is formed. Further, a recess 10d is formed in a region to be a vertical gate below the transfer gate.

Next, as shown in FIG. 26B, for example, a gate insulating film 20 is formed on the surface of the semiconductor substrate 10 in the photodiode region A _PD , the transfer gate region A _TG , the NMOS transistor region A _NMOS, and the PMOS transistor region A _PMOS . To do. The gate insulating film 20 is formed by depositing silicon oxide by, for example, a thermal oxidation method or a CVD method. At this time, the gate insulating film 20 is formed so as to cover the side surface of the semiconductor region 17 in the recess 10c. Moreover, it forms so that an inner wall may be coat | covered in the recessed part 19d.
Next, a polysilicon layer 21 is formed to a thickness of 80 to 250 nm on the gate insulating film 20 by, eg, CVD. At this time, the polysilicon layer 21 is formed so as to have a buried layer 21c filling the upper layer of the gate insulating film 20 in the recess 10c. Further, it is formed so as to have a buried layer 21d that fills the upper layer of the gate insulating film 20 in the recess 10d.

Next, as shown in FIG. 27A, for example, a resist film 22 that protects the photodiode region _APD and the PMOS transistor region _APMOS is patterned. Using the resist film 22 as a mask, in the transfer gate region _ATG and the NMOS transistor region A _NMOS , an N-type conductive impurity such as P is introduced into the polysilicon layer 21 to form an N-type conductive layer 21a. For example, the dose is 1 × 10 ¹⁵ / cm ² with an implantation energy of 5 to 30 keV.

Next, as shown in FIG. 27B, for example, a resist film 23 that protects the transfer gate region _ATG and the NMOS transistor region _ANMOS is patterned. Using the resist film 23 as a mask, in the photodiode region _APD and the PMOS transistor region _APMOS , a P type conductive impurity such as B is introduced into the polysilicon layer 21 to form a P type conductive layer 21b. For example, the dose amount is 0 to 1 × 10 ¹⁶ / cm ² with an implantation energy of 3 to 15 keV.
The drawing shows a state in which P-type conductive impurities are not diffused to the buried layer 21c in the recess 10c and the buried layer 21d in the recess 10d.

Next, as shown in FIG. 28A, for example, a resist film 24 is patterned on the conductive layer 21a and the conductive layer 21b.
Resist film 24 has a pattern of the photo diode region inversion layer induced electrodes _{A PD,} transfer gate electrodes of the transfer gate region _{A TG,} NMOS transistor region _{A NMOS} and PMOS transistor regions _{A PMOS} gate electrode.

Next, as shown in FIG. 28B, for example, an etching process is performed using the resist film 24 as a mask. As the etching process, for example, an anisotropic etching process such as RIE (reactive ion etching) using plasma of a mixed gas of Cl ₂ + O ₂ is used.
Thus, the conductive layer 21b as the inversion layer inducing electrode, the conductive layer 21a as the transfer gate electrode, the conductive layer 21a as the gate electrode of the NMOS transistor, and the conductive layer 21b as the gate electrode of the PMOS transistor are pattern-formed. The conductive layer 21b which is the inversion layer induction electrode is formed integrally with the conductive layer 21b which is the inversion layer induction electrode on the photodiode of the adjacent pixel.
In the above etching process, the gate insulating film 20 is also processed into the same pattern as each conductive layer (21a, 21b).

  Here, the width W between the conductive layer 21b that is the inversion layer induction electrode and the conductive layer 21a that is the transfer gate electrode is a distance that allows the P-type conductive layer 21b and the N-type conductive layer 21a to be sufficiently separated. Good. For example, it can be formed with the minimum design rule that can be processed. For example, it is 50 to 300 nm.

Next, as shown in FIG. 29 (a), for example, a resist film 25 for exposing the region adjacent to the transfer gate area A _TG A end portion of the photodiode region A _PD. P-type impurities such as B are ion-implanted using the resist film 25 as a mask, and a part of the PN junction that becomes a photodiode is formed as the semiconductor region 17 in the surface layer portion of the semiconductor region 17 at the end of the photodiode region _APD. A P-type semiconductor layer 26 is formed. For example, the dosage is set to 1 × 10 ¹² to 1 × 10 ¹³ cm ² with an implantation energy of 0.2 to 10 keV.

Next, as shown in FIG. 29B, for example, a 5 to 30 nm silicon oxide film and a 30 to 100 nm silicon nitride film are stacked on the entire surface by CVD, and an etch back process is performed on the front surface. Thereby, in the photodiode region A _PD , the transfer gate region A _TG , the NMOS transistor region A _NMOS and the PMOS transistor region A _PMOS , the sidewall insulating film 27 is formed on the side surfaces of the N-type conductive layer 21a and the P-type conductive layer 21b. Form.
The etching back process is, for example, an anisotropic etching process such as RIE (reactive ion etching) using plasma of a mixed gas of CF ₄ + O ₂ as the etching process.
The width W between the conductive layer 21b serving as the inversion layer induction electrode and the conductive layer 21a serving as the transfer gate electrode may be entirely filled with the sidewall insulating film 27.

Next, as shown in FIG. 30A, for example, a resist film 28 that protects the photodiode region _APD and the PMOS transistor region _APMOS is patterned. Next, N-type conductive impurities such as P are introduced using the resist film 28 as a mask. NMOS transistor region A In the _NMOS , an N-type semiconductor layer 29 which is an N-type source / drain region is formed. Further, a semiconductor layer 30 of N-type is a floating diffusion in transfer gate region A _TG. Here, for example, the dosage is set to 1 × 10 ^{15 to} 5 × 10 ¹⁵ / cm ² with an implantation energy of 5 to 20 keV.

Next, as shown in FIG. _30B , for example, the transfer gate region _ATG , the end portion (region of the semiconductor layer 26) adjacent to the transfer gate region _ATG of the photodiode region _APD , and the NMOS transistor region _ANMOS A resist film 31 for protecting the pattern is formed. Next, using the resist film 31 as a mask, a P-type conductive impurity such as B is introduced. PMOS transistor region A In the _PMOS , a P-type semiconductor layer 32 which is a P-type source / drain region is formed. Further, in the photodiode region A _PD increase the P-type impurity concentration in the P-type conductive layer 21b. Here, for example, the dose amount is 1 × 10 ^{15 to} 5 × 10 ¹⁵ / cm ² with an implantation energy of 2 to 8 keV.
After the above ion implantation, an RTA (Rapid Thermal Annealing) process is performed at 1000 to 1100 ° C. for about 0 to 20 seconds to activate impurities and recover defects.
With the above RTA process, the P-type conductive impurities are diffused to the buried layer 21c in the recess 10c and the buried layer 21d in the recess 10d.

  As a subsequent process, for example, when the light incident surface is on the back side of the substrate (direction A in FIG. 22B), the back surface of the substrate is thinned by grinding the back surface of the substrate, and further on the back side of the substrate as necessary. A color filter or the like is formed on the substrate. Further, an optical waveguide or an on-chip lens may be provided.

Alternatively, for example, when the light incident surface is on the substrate surface side (B direction in FIG. 22B), an optical waveguide is provided in an insulating film on the substrate as necessary, and a color filter and an on-chip lens are formed thereon. Form etc.
Through the above steps, a CMOS image sensor having the configuration shown in FIGS. 22A and 22B can be manufactured.

In the manufacturing method of the solid-state imaging device according to the present embodiment, the inversion layer induction electrode is formed in a region covering part or all of the photodiode, and the second conductivity type carriers are accumulated on the surface of the semiconductor region on the inversion layer induction electrode side. Thus, a solid-state imaging device in which the inversion layer is induced can be manufactured.
In addition, heat treatment for recovering defects introduced by gate etching, sidewall etchback, or the like can be performed. In addition, the conductive layer itself, which is the inversion layer induction electrode that covers the photodiode, suppresses the introduction of defects into the photodiode region during the etching process. Thereby, an increase in dark current can be avoided and yield reduction can be suppressed.

<Third Modification>
[Configuration in which the trench is not formed in the element isolation region of the photodiode in the third embodiment]
In the third embodiment, the conductive layer 21b which is an inversion layer induction electrode has a buried layer 21c embedded in the recess 10c. Further, the conductive layer 21a as a transfer gate electrode has a buried layer 21d embedded in the recess 10d.
However, the recess 10c is not formed, and the conductive layer 21b as the inversion layer induction electrode may not have the embedded layer 21c embedded in the recess 10c.

<Fourth embodiment>
[Camera using solid-state imaging device]
FIG. 31 is a schematic configuration diagram of a camera according to the present embodiment.
A solid-state imaging device 50 in which a plurality of pixels are integrated, an optical system 51, and a signal processing circuit 53 are provided.
In the present embodiment, the solid-state imaging device 50 includes the solid-state imaging device according to any one of the first to third embodiments.

The optical system 51 forms image light (incident light) from the subject on the imaging surface of the solid-state imaging device 50. Thereby, in the photodiode which comprises each pixel on the imaging surface of the solid-state imaging device 50, it converts into a signal charge according to incident light quantity, and the corresponding signal charge is accumulate | stored for a fixed period.
The accumulated signal charge is taken out as an output signal Vout through, for example, a CCD charge transfer path.
The signal processing circuit 53 performs various signal processing on the output signal Vout of the solid-state imaging device 50 and outputs it as a video signal.

  The camera of the present embodiment can provide a camera using a solid-state imaging device that can suppress a decrease in yield while improving the dynamic range by sharpening the PN junction.

The present invention is not limited to the above description.
For example, in the embodiment, the present invention can be applied to both a CMOS sensor and a CCD element. In the case of a CCD element, the signal reading unit has a configuration in which a charge coupled device (CCD) is connected to a photodiode. The signal charge transferred from each pixel in the CCD is read.
In each embodiment, the first conductivity type and the second conductivity type can be interchanged. In this case, carriers induced in the inversion layer are not holes but electrons.
In the solid-state imaging device according to the first to third embodiments, a film having a negative fixed charge such as hafnium oxide may be formed on the semiconductor substrate in a region between the transfer gate electrode and the inversion layer inducing electrode. Examples of the film having a negative fixed charge include hafnium oxide, aluminum oxide, zirconium oxide, tantalum oxide, and titanium oxide. Alternatively, lanthanum oxide, praseodymium oxide, cerium oxide, neodymium oxide, promethium oxide, samarium oxide, europium oxide, gadolinium oxide, terbium oxide, dysprosium oxide, holmium oxide, erbium oxide, thulium oxide, ytterbium oxide, lutetium oxide, yttrium oxide, etc. Also mentioned.
In addition, various modifications can be made without departing from the scope of the present invention.

  DESCRIPTION OF SYMBOLS 10 ... Semiconductor substrate, 10a ... Element isolation groove, 10b ... Element isolation region, 14 ... Element isolation insulating film, 16 ... N type well, 17 ... N type semiconductor region, 20 ... Gate insulating film, 21a ... N type 21b... P-type conductive layer, 26... P-type semiconductor layer, 27... Sidewall insulating film, 29... N-type semiconductor layer, 30... N-type semiconductor layer, 32. , 50 ... Solid-state imaging device, 51 ... Optical system, 53 ... Signal processing circuit, PD ... Photodiode, PG ... Inversion layer induction electrode, TG ... Transfer gate electrode, FD ... Floating diffusion, CT ... Contact, I ... Element isolation region

Claims (10)

A photodiode having a semiconductor region of a first conductivity type formed separately for each pixel arranged in a matrix on a light receiving surface of a semiconductor substrate;
A transfer gate electrode of a first conductivity type that is formed on the semiconductor substrate via a gate insulating film in a region adjacent to the photodiode, and transfers a signal charge generated and accumulated in the photodiode;
A signal reading unit for reading a voltage corresponding to the signal charge or the signal charge;
The photodiode is formed on the semiconductor substrate through the gate insulating film in the region of the photodiode excluding a portion adjacent to the transfer gate electrode, and having a work function larger than that of the transfer gate electrode. An inversion layer induction electrode made of a conductor or a semiconductor, and
A solid-state imaging device, wherein an inversion layer formed by accumulating carriers of the second conductivity type is induced on the inversion layer induction electrode side surface of the semiconductor region by the inversion layer induction electrode. The solid-state imaging device according to claim 1, wherein the inversion layer induction electrode is made of a second conductivity type semiconductor. The solid-state imaging device according to claim 1 or 2, a negative voltage is applied to the inversion layer induced electrode. A recess for exposing a side surface of the semiconductor region is formed in the semiconductor substrate in an element isolation region for dividing the photodiode for each pixel, and the inversion layer induction electrode is interposed on the side surface through the gate insulating film. is formed, the solid-state imaging device according to any one of aspects of the semiconductor regions of the preceding claims, wherein the inversion layer is induced. Wherein a recess is formed in the semiconductor substrate at the bottom of the transfer gate electrodes, to claim 1, wherein the transfer gate electrodes are formed is embedded through the gate insulating film in the recess The solid-state imaging device described. The solid-state imaging device according to claim 1, wherein the effective concentration of the first conductivity type impurity in the semiconductor region is higher as it is closer to the surface of the semiconductor substrate. Forming a first conductivity type semiconductor region in the photodiode forming region by dividing the pixels arranged in a matrix on the light receiving surface of the semiconductor substrate;
Forming a transfer gate electrode of a first conductivity type for transferring a signal charge generated and accumulated in the photodiode via a gate insulating film on the semiconductor substrate in a region adjacent to the photodiode formation region;
Forming a voltage corresponding to the signal charge or a signal reading unit for reading the signal charge;
A work function larger than that of the transfer gate electrode is provided on the semiconductor substrate via the gate insulating film in the photodiode formation region excluding a portion adjacent to the transfer gate electrode at an end portion of the photodiode formation region . Forming an inversion layer induction electrode made of a conductor or a semiconductor, and
As the photodiode, a photodiode in which an inversion layer formed by accumulating carriers of the second conductivity type is induced on the surface of the semiconductor region on the inversion layer induction electrode side is formed by the inversion layer induction electrode. Production method. The step of forming the transfer gate electrode and the step of forming the inversion layer induction electrode form the transfer gate electrode and the inversion layer induction electrode by introducing impurities of different conductivity types in a semiconductor of the same layer. 8. A method for manufacturing a solid-state imaging device according to 7. Forming a complementary MOS transistor on the semiconductor substrate;
In the step of forming the transfer gate electrode, the complementary MOS transistor is configured, and the transfer gate electrode is formed in the same layer as the gate electrode of the MOS transistor whose channel is the first conductivity type,
8. The step of forming the inversion layer induction electrode includes forming the complementary MOS transistor and forming the inversion layer induction electrode in the same layer as a gate electrode of a MOS transistor having a second conductivity type channel. The manufacturing method of the solid-state imaging device of description. A solid-state imaging device in which a plurality of pixels are integrated on a light receiving surface;
An optical system for guiding incident light to the imaging unit of the solid-state imaging device;
A signal processing circuit for processing an output signal of the solid-state imaging device,
The solid-state imaging device
A photodiode having a semiconductor region of a first conductivity type formed separately for each pixel arranged in a matrix on a light receiving surface of a semiconductor substrate;
A transfer gate electrode of a first conductivity type that is formed on the semiconductor substrate via a gate insulating film in a region adjacent to the photodiode, and transfers a signal charge generated and accumulated in the photodiode;
A signal reading unit for reading a voltage corresponding to the signal charge or the signal charge;
The photodiode is formed on the semiconductor substrate through the gate insulating film in the region of the photodiode excluding a portion adjacent to the transfer gate electrode, and having a work function larger than that of the transfer gate electrode. An inversion layer induction electrode made of a conductor or a semiconductor, and
An inversion layer formed by accumulating carriers of a second conductivity type is induced on the surface of the semiconductor region on the inversion layer induction electrode side by the inversion layer induction electrode.

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