JP2008090422A - Power supply circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To realize a power supply circuit capable of reducing wiring for a supplying power. <P>SOLUTION: In the power supply circuit for supplying power to an electric power consumption means in an integrated circuit, the power supply circuit comprises a plurality of electric power consumption means, a power supply means for outputting electric currents supplied from a plurality of power sources by selecting the electric currents in time sharing, and a power distribution means for supplying the electric currents selected by the power supply means to the corresponding electric power consumption means by switching the selected currents in time sharing. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a power supply circuit that supplies power to a power consuming means such as a load circuit in an integrated circuit, and more particularly to a power supply circuit that can reduce the wiring of power to be supplied.

  Prior art documents related to a power supply circuit for supplying power to a power consuming means such as a load circuit in a conventional integrated circuit include the following.

JP 61-051219 A JP 63-084949 A Japanese Patent Laid-Open No. 03-125205 JP 11-338561 A JP 2003-256057 A

  FIG. 6 is a block diagram showing an example of a conventional power supply circuit. In FIG. 6, 1, 2 and 3 are power supplies for supplying a constant current provided in the integrated circuit, and 4, 5 and 6 are power consuming means provided in the integrated circuit for consuming the supplied constant current such as a load circuit. is there. 1, 2 and 3 constitute a power supply means 80.

  The constant current that is the output of the power supply 1 is supplied to the power consuming means 4. Similarly, the constant currents that are the outputs of the power supply 2 and the power supply 3 are supplied to the power consuming means 5 and the power consuming means 6, respectively.

  The operation of the conventional example shown in FIG. 6 will be described with reference to FIGS. FIG. 7 is a circuit showing a specific example of a power source. In FIG. 7, 7 and 8 are FET (Field Effect Transistor) transistors (hereinafter simply referred to as transistors), and 9 is a constant current with a constant output current. Is the source. 7, 8 and 9 constitute a power supply 81.

  The gate of the transistor 7 is connected to the drain of the transistor 7, the gate of the transistor 8, and one end of the constant current source 9. The sources of the transistors 7 and 8 are connected to a positive voltage source (VDD), respectively, and the other end of the constant current source 9 is connected to a negative voltage source (VSS). Further, a constant current is output from the drain of the transistor 8 as indicated by “OP11” in FIG.

  On the other hand, FIG. 8 is a circuit showing a specific example of the power consuming means. In FIG. 8, 10 and 11 are transistors, and 12 is a load circuit that consumes current (power). In addition, 10, 11 and 12 constitute a power consuming means 82.

  8 are supplied to the drain and gate of the transistor 10 and the gate of the transistor 11, respectively. The drain of the transistor 11 is connected to one end of the load circuit 12. The other end of the load circuit 12 is connected to a positive voltage source (VDD), and the sources of the transistors 10 and 11 are connected to a negative voltage source (VSS), respectively.

  As shown in FIG. 7, each of the power supplies 1 to 3 is composed of a current mirror circuit composed of a transistor 7 and a transistor 8 and a constant current source 9, and the current mirror circuit outputs a constant current that is an output of the constant current source 9. Mirrored and output as a current (constant current) indicated by “OP11” in FIG.

  On the other hand, such a constant current is supplied to the current mirror circuit composed of the transistor 10 and the transistor 11 as shown in FIG. 8, so that the load circuit 12 is supplied with a constant current having the same value as the supplied current. Will be consumed.

  As a result, a power source for supplying a constant current such as a current mirror circuit provided in the integrated circuit and a power consuming means for consuming the supplied constant current such as a load circuit provided in the integrated circuit are connected to each other. The power can be supplied to the power consuming means.

  However, in the conventional example shown in FIG. 6, the power supplied from the power supply means 80 is a static signal, and a signal that requires wiring over a short distance is given priority. Tend to be longer.

  Further, there are many cases where the power supply and the power consuming means are in one-to-one correspondence. Therefore, the number of wirings connecting the power supply and the power consuming means is the same as the number of power supplies. For example, in the case of the conventional example shown in FIG. 6, since the number of power supplies is three, it is necessary to provide three wires as indicated by “LN01”, “LN02”, and “LN03” in FIG.

For this reason, a plurality of wirings having a long wiring length must be arranged in the integrated circuit, which causes a problem that the chip area of the integrated circuit is increased and the wiring layout is complicated.
Therefore, the problem to be solved by the present invention is to realize a power supply circuit arrangement capable of reducing the wiring of the power supply to be supplied.

In order to achieve such a problem, the invention according to claim 1 of the present invention is:
In a power supply circuit for supplying power to a power consuming means in an integrated circuit,
A plurality of power consumption means, a power supply means for selecting and outputting currents supplied from a plurality of power supplies in a time-sharing manner, and the corresponding power consumption by switching the currents selected by the power supply means in a time-sharing manner By providing the power distribution means for supplying power to the means, it is possible to reduce the wiring of the power to be supplied.

The invention according to claim 2
In the power supply circuit according to claim 1,
The power supply means is
By comprising a plurality of the power supplies, a multiplexer circuit, and a control means for selecting and outputting the current supplied from the plurality of power supplies in a time-sharing manner by the multiplexer circuit, the wiring of the power supply to be supplied is reduced. It becomes possible.

The invention described in claim 3
In the power supply circuit according to claim 1,
The power distribution means is
A demultiplexer circuit, a plurality of holding means for supplying an output of the demultiplexer circuit to the corresponding power consuming means and supplying a constant current to the power consuming means when a non-selection signal is applied; By switching to time division in a demultiplexer circuit and outputting to the corresponding power consuming means via the holding means and the control means for applying the non-selection signal to the non-selected holding means, It is possible to reduce the power supply wiring to be supplied.

The invention according to claim 4
In the power supply circuit according to claim 1 or claim 2,
The power source is
By comprising the constant current source and the current mirror circuit that mirrors and outputs the output current of the constant current source, it is possible to reduce the power supply wiring to be supplied.

The invention according to claim 5
In the power supply circuit according to the invention of claim 3,
The holding means is
A transistor in which an output of the demultiplexer circuit is connected to a drain and a gate and a source is connected to a negative voltage source; a switch circuit which is connected to one end of the transistor gate and turned off when the non-selection signal is applied; One end is connected to a negative voltage source and the other end is connected to the other end of the switch circuit to hold a gate voltage value and to be connected to a power input terminal of the corresponding power consuming means. Therefore, it is possible to reduce the power supply wiring to be supplied.

The invention described in claim 6
In the power supply circuit according to any one of claims 1 to 5,
The power consuming means is
By comprising a transistor in which the output of the holding means is applied to the gate and the source is connected to a negative voltage source, and a load circuit having an end connected to the drain of the transistor and the other end connected to the positive voltage source Therefore, it is possible to reduce the power supply wiring to be supplied.

The invention described in claim 7
In the power supply circuit according to any one of claims 1 to 6,
The power source is
As a result of being shared by the plurality of power consuming means, it is possible to reduce the power supply wiring to be supplied.

The present invention has the following effects.
According to the first, second, third, fourth, fifth, and sixth aspects of the present invention, the currents supplied from the plurality of power supplies are selected in a time division manner by the multiplexer circuit, and the currents respectively selected by the demultiplexer circuit are selected. Are switched in a time division manner and output to the corresponding power consumption means via the holding means, and the unselected holding means to which the non-selection signal is applied holds the value of the gate voltage and causes a constant current to flow to the power consumption means. As a result, it is possible to reduce the power supply wiring to be supplied.

  Hereinafter, the present invention will be described in detail with reference to the drawings. FIG. 1 is a block diagram showing the configuration of an embodiment of a power supply circuit according to the present invention.

  In FIG. 1, 13, 14 and 15 are power supplies for supplying a constant current provided in the integrated circuit, 16 is a multiplexer circuit for selecting and outputting one of a plurality of inputs, and 17 is a control means for controlling the operation of the multiplexer circuit. , 18 is a demultiplexer circuit that selects one of a plurality of outputs and outputs the input, 19 is a control means for controlling the operation of the demultiplexer circuit, and 20, 21 and 22 supply the supplied constant current to the subsequent stage. In addition, holding means for passing a constant current to the power consuming means when no constant current is supplied (application of a non-selection signal), 23, 24 and 25 are provided in the integrated circuit and consume power supplied by the load circuit or the like. It is a means of consumption.

  13, 14, 15, 16, and 17 constitute a power supply means 83, and 18, 19, 20, 21, and 22 constitute a power distribution means 84, respectively.

  The constant currents that are the outputs of the power supplies 13 and 14 and the power supply 15 are respectively input to the three input terminals of the multiplexer circuit 16, and the control signal from the control means 17 is input to the control input terminal of the multiplexer circuit 16.

  The output terminal of the multiplexer circuit 16 is connected to the input terminal of the demultiplexer circuit 18, and the three output terminals of the demultiplexer circuit 18 are connected to the input terminals of the holding means 20, 21 and the holding means 23, respectively. Further, the control signal of the control means 19 is input to the control input terminal of the demultiplexer circuit 18, and the non-selection signal from the control means 19 is input to the control input terminals of the holding means 20, 21 and the holding means 22, respectively.

  The output terminal of the holding means 20 is connected to the power input terminal of the power consuming means 23. Similarly, the output terminals of the holding means 21 and 22 are connected to the power input terminals of the power consuming means 24 and 25, respectively.

  The operation of the embodiment shown in FIG. 1 will be described with reference to FIGS. However, the constant current supplied from the power supply 13 is supplied to the power consuming means 23, and similarly, the constant current supplied from the power supply 14 and the power supply 15 is supplied to the power consuming means 24 and the power consuming means 25, respectively.

  In other words, the power supplies 13, 14 and 15 correspond to the power consuming means 23, 24 and 25, respectively.

  2 is a circuit showing a specific example of a power source. In FIG. 2, reference numerals 26 and 27 denote FET (Field Effect Transistor) transistors (hereinafter simply referred to as transistors), and 28 denotes a constant output current. It is a constant current source. In addition, 26, 27 and 28 constitute a power source 85.

  The gate of the transistor 26 is connected to the drain of the transistor 26, the gate of the transistor 27, and one end of the constant current source 28. The sources of the transistors 26 and 27 are connected to a positive voltage source (VDD), respectively, and the other end of the constant current source 28 is connected to a negative voltage source (VSS). Further, a constant current is output from the drain of the transistor 27 as indicated by “OP41” in FIG.

  On the other hand, FIG. 3 is a circuit showing a specific example of the holding means and the power consuming means. In FIG. 3, 29 and 32 are transistors, and 30 is a switch circuit that performs an “OFF” operation (“ON” when selected) by a non-selection signal , 31 is a capacity for holding the value of the gate voltage, and 33 is a load circuit consuming current (power). 29, 30 and 31 constitute holding means 86, and 32 and 33 constitute power consumption means 87, respectively.

  The input indicated by “IP51” in FIG. 3 is supplied to the drain and gate of the transistor 29 and one end of the switch circuit 30, respectively. 3 is supplied to the control input terminal of the switch circuit 30 from the control means 19 (not shown) indicated by “CT51” in FIG.

  The other end of the switch circuit 30 is connected to one end of the capacitor 31 and to the power input terminal of the power consuming means 87. The source of the transistor 29 and the other end of the capacitor 31 are connected to a negative voltage source (VSS).

  The output of the holding means 86 is supplied to the gate of the transistor 32, and the drain of the transistor 32 is connected to one end of the load circuit 33. The other end of the load circuit 33 is connected to a positive voltage source (VDD), and the source of the transistor 32 is connected to a negative voltage source (VSS).

  As shown in FIG. 2, each of the power supplies 13 to 15 includes a current mirror circuit composed of a transistor 26 and a transistor 27 and a constant current source 28. The current mirror circuit outputs a constant current that is an output of the constant current source 28. Mirrored and output as a current indicated by “OP41” in FIG. 2 (constant currents having different values).

  On the other hand, the control means 17 and the control means 19 are constituted by, for example, a ring counter circuit or the like, and the multiplexer circuit 16 and the demultiplexer circuit 18 synchronize the selection of the input source and the selection of the output destination by the same clock signal or the like. To control. Further, the control means 19 applies a non-selection signal to the holding means connected to the outputs that are not selected at the same time.

  In other words, when the multiplexer circuit 16 selects the output of the power supply 13, the demultiplexer circuit 18 selects the holding unit 20 (power consumption unit 23) as the output destination. Similarly, when the multiplexer circuit 16 selects the output of the power supply 14, the demultiplexer circuit 18 selects the holding means 21 (power consumption means 24) as the output destination, and the multiplexer circuit 16 outputs the output of the power supply 15. When selected, the demultiplexer circuit 18 selects the holding means 22 (power consumption means 25) as the output destination.

  Further, when the demultiplexer circuit 18 selects the holding means 20 (power consumption means 23) as the output destination, the control means 19 applies a non-selection signal to the holding means 21 and 22, and the demultiplexer circuit 18 outputs it. When the holding means 21 (power consumption means 24) is selected as the destination, a non-selection signal is applied to the holding means 20 and 22, and the demultiplexer circuit 18 sets the holding means 22 (power consumption means 25) as the output destination. If selected, a non-selection signal is applied to the holding means 20 and 21.

  The control means 17 and the control means 19 perform the selection of the input source and the selection of the output destination continuously in a time division manner, and the control means 19 applies time to the other non-selected holding means. A non-selection signal is applied in the division.

  Here, the operation will be described by paying attention to the power supply 13, the holding means 20, and the power consumption means 23. When the multiplexer circuit 16 selects the output of the power supply 13, the constant current output from the power supply 13 is supplied to the input terminal of the holding means 20 via the multiplexer circuit 16 and the demultiplexer circuit 18.

  At this time, since the non-selection signal from the control means 19 indicated by “CT51” in FIG. 3 is not applied, the switch circuit 30 constituting the holding means 20 is “ON”.

  For this reason, the constant current (output current of the power source 13) from the demultiplexer circuit 18 indicated by “IP51” in FIG. 3 is supplied to the current mirror circuit composed of the transistors 29 and 32, and is therefore supplied to the load circuit 33. A constant current having the same value as the generated current (output current of the power supply 13) is supplied and consumed.

  When the multiplexer circuit 16 stops selecting the output of the power supply 13 and selects the output of the power supply 14 after a lapse of time, the demultiplexer circuit 18 naturally holds the holding means 21 (power consumption means 24) as the output destination. ), The supply of current from the demultiplexer circuit 18 stops, and a non-selection signal from the control means 19 indicated by “CT51” in FIG. 3 is applied. The switch circuit 30 to be configured transitions from “ON” to “OFF”.

  At this time, the gate voltage at the time when the current mirror circuit composed of the transistors 29 and 32 is operating is held in the capacitor 31, and the gate voltage held in the capacitor 31 is applied to the gate of the transistor 32. Therefore, the transistor 32 passes a constant current having the same value as the current (output current of the power supply 13) supplied from the demultiplexer circuit 18 to the load circuit 33.

  For this reason, even if the supply of current from the demultiplexer circuit 18 is momentarily stopped, the load circuit 33 is equal to the output current of the power supply 13 by the holding function of the holding means 20 controlled by the non-selection signal. Current will flow.

  In other words, currents supplied from a plurality of power supplies are selected in a time division manner by a multiplexer circuit, and the currents selected by the demultiplexer circuit are switched in a time division manner and output to the corresponding power consumption means via the holding means, and non- The non-selected holding means to which the selection signal is applied holds the value of the gate voltage and causes a constant current to flow to the power consuming means, so that one wiring having a long wiring length is shown as "LN31" in FIG. Will be enough.

  As a result, currents supplied from a plurality of power supplies are selected in a time division manner by the multiplexer circuit, and the currents selected by the demultiplexer circuit are switched in a time division manner and output to the corresponding power consumption means via the holding means. The holding means that is not selected to which the non-selection signal is applied holds the value of the gate voltage and allows a constant current to flow to the power consuming means, thereby reducing the power supply wiring to be supplied.

  In the embodiment shown in FIG. 1, the power supply and the power consuming means correspond one-to-one. However, the present invention is not limited to this, and a plurality of power consuming means may share a single power supply. I do not care.

  FIG. 4 is a block diagram showing the configuration of another embodiment of the power supply circuit according to the present invention. 4, 34 and 35 are power supplies provided in the integrated circuit for supplying a constant current, 36 is a multiplexer circuit for selecting and outputting one of a plurality of inputs, 37 is a control means for controlling the operation of the multiplexer circuit, 38 Is a demultiplexer circuit that selects one of a plurality of outputs and outputs an input, 39 is a control means for controlling the operation of the demultiplexer circuit, 40, 41 and 42 supply a constant current to be supplied to the subsequent stage and a constant value. Holding means 43, 44, and 45 for holding the power supply when no current is supplied are power consuming means provided in the integrated circuit for consuming a supplied constant current such as a load circuit.

  Reference numerals 34, 35, 36 and 37 constitute a power supply means 88, and reference numerals 38, 39, 40, 41 and 42 constitute a power distribution means 89, respectively.

  The constant currents that are the outputs of the power supply 34 and the power supply 35 are respectively input to the two input terminals of the multiplexer circuit 36, and the control signal from the control means 37 is input to the control input terminal of the multiplexer circuit 36.

  The output terminal of the multiplexer circuit 36 is connected to the input terminal of the demultiplexer circuit 38, and the three output terminals of the demultiplexer circuit 38 are connected to the input terminals of the holding means 40 and 41 and the holding means 43, respectively. Further, the control signal of the control means 39 is input to the control input terminal of the demultiplexer circuit 38, and the non-selection signal from the control means 39 is input to the control input terminals of the holding means 40 and 41 and the holding means 42, respectively.

  The output terminal of the holding means 40 is connected to the power input terminal of the power consuming means 43. Similarly, the output terminals of the holding means 41 and 42 are connected to the power input terminals of the power consuming means 44 and 45, respectively.

  Here, the operation of the embodiment shown in FIG. 4 will be described. However, description of operations similar to those in the embodiment shown in FIG. 1 is omitted. The constant current supplied from the power source 34 is supplied to each of the two power consuming means 43 and the power consuming means 44, and the constant current supplied from the power source 35 is supplied to the power consuming means 45.

  In other words, the power supply 34 corresponds to the two power consumption means 43 and 44, and the power supply 35 corresponds to the power consumption means 45.

  The control means 37 and the control means 39 are constituted by, for example, a ring counter circuit or the like, and the multiplexer circuit 36 and the demultiplexer circuit 38 synchronize the selection of the input source and the selection of the output destination by the same clock signal or the like. To control. Further, the control means 39 applies a non-selection signal to the holding means connected to the outputs not selected at the same time.

  In other words, when the multiplexer circuit 36 selects the output of the power supply 34, the demultiplexer circuit 38 time-divides the holding means 40 (power consumption means 43) and the holding means 41 (power consumption means 44) as output destinations. Select sequentially with.

  When the multiplexer circuit 36 selects the output of the power source 35, the demultiplexer circuit 38 selects the holding means 42 (power consumption means 45) as the output destination.

  Further, when the demultiplexer circuit 38 selects the holding means 40 (power consumption means 43) as the output destination, the control means 39 applies a non-selection signal to the holding means 41 and 42, and the demultiplexer circuit 38 outputs When the holding means 41 (power consumption means 44) is selected as the destination, a non-selection signal is applied to the holding means 40 and 42, and the demultiplexer circuit 38 sets the holding means 42 (power consumption means 45) as the output destination. If it is selected, a non-selection signal is applied to the holding means 40 and 41.

  The control means 37 and the control means 39 perform such input source selection and output destination selection continuously in a time-sharing manner, and the control means 39 applies time to other unselected holding means. A non-selection signal is applied in the division.

  With this operation, the output current of the power source 34 is consumed by the power consuming means 43 and 44, and the output current of the power source 35 is consumed by the power consuming means 45.

  In the embodiment shown in FIG. 1, the power supply means and the power distribution means correspond one-to-one. However, the present invention is not limited to this. Between the plurality of power supply means and the plurality of power distribution means. Separately, a multiplexer circuit and a demultiplexer circuit are provided, and currents supplied from a plurality of power supply means are selected in a time-division manner by the multiplexer circuit, and the currents selected by the demultiplexer circuit are switched in a time-division manner, thereby corresponding power distribution. You may output to a means.

  FIG. 5 is a block diagram showing the configuration of another embodiment of the power supply circuit according to the present invention. In FIG. 5, 46, 47 and 48 are power supply means, 49 is a multiplexer circuit which selects and outputs one of a plurality of inputs, 50 is a demultiplexer circuit which selects one of a plurality of outputs and outputs an input, Reference numerals 51, 52 and 53 denote power distribution means.

  However, in FIG. 5, the description of the control means for controlling the multiplexer circuit 49 and the demultiplexer circuit 50 and the power consuming means provided in the subsequent stage of each power distribution means 51 to 53 is omitted for the sake of simplicity.

  The currents that are the outputs of the power supply means 46 and 47 and the power supply means 48 are respectively input to three input terminals of the multiplexer circuit 49, and the output terminal of the multiplexer circuit 49 is connected to the input terminal of the demultiplexer circuit 50.

  The three output terminals of the demultiplexer circuit 50 are connected to the input terminals of the power distribution means 51 and 52 and the power distribution means 53, respectively.

  Here, the operation of the embodiment shown in FIG. 5 will be described. However, description of operations similar to those in the embodiment shown in FIG. 1 is omitted. The currents supplied by the power supply units 46 and 47 and the power supply unit 48 are supplied to the power distribution units 51 and 52 and the power distribution unit 53, respectively.

  That is, the currents supplied from the plurality of power supply means are selected in a time division manner by the multiplexer circuit 49, the currents selected by the demultiplexer circuit 50 are switched in a time division manner and output to the corresponding power distribution means, and FIG. As shown in the embodiment, each of the power supply means and the power distribution means corresponding to each other distributes the output current of the power supply to the corresponding power consumption means in a time-sharing manner, thereby reducing the power supply wiring to be supplied. become.

1 is a configuration block diagram showing an embodiment of a power supply circuit according to the present invention. It is a circuit which shows the specific example of a power supply. It is a circuit which shows the specific example of a holding means and a power consumption means. It is a block diagram showing the configuration of another embodiment of the power supply circuit according to the present invention. It is a block diagram showing the configuration of another embodiment of the power supply circuit according to the present invention. It is a block diagram showing an example of a conventional power supply circuit. It is a circuit which shows the specific example of a power supply. It is a circuit which shows the specific example of a power consumption means.

Explanation of symbols

1, 2, 3, 13, 14, 15, 34, 35, 81, 85 Power supply 4, 5, 6, 23, 24, 25, 43, 44, 45, 82, 87 Power consumption means 7, 8, 10, 11, 26, 27, 29, 32 Transistor 9, 28 Constant current source 12, 33 Load circuit 16, 36, 49 Multiplexer circuit 17, 19, 37, 39 Control means 18, 38, 50 Demultiplexer circuit 20, 21, 22 , 40, 41, 42, 86 Holding means 30 Switch circuit 31 Capacity 46, 47, 48, 80, 83, 88 Power supply means 51, 52, 53, 84, 89 Power distribution means

Claims (7)

In a power supply circuit for supplying power to a power consuming means in an integrated circuit,
Multiple power consuming means;
Power supply means for selecting and outputting current supplied from a plurality of power supplies in a time-sharing manner;
A power supply circuit comprising: a power distribution means for switching the current selected by the power supply means in a time division manner and supplying the selected current to the corresponding power consumption means. The power supply means is
A plurality of said power supplies;
A multiplexer circuit;
2. The power supply circuit according to claim 1, further comprising control means for selecting and outputting the current supplied from the plurality of power supplies in a time division manner by the multiplexer circuit. The power distribution means is
A demultiplexer circuit;
A plurality of holding means for supplying an output of the demultiplexer circuit to the corresponding power consuming means and for supplying a constant current to the power consuming means when a non-selection signal is applied;
Control means for switching each selected current to time division by the demultiplexer circuit and outputting the selected current to the corresponding power consuming means via the holding means and applying the non-selection signal to the non-selected holding means; The power supply circuit according to claim 1, comprising: The power source is
A constant current source;
3. The power supply circuit according to claim 1, further comprising a current mirror circuit that mirrors and outputs the output current of the constant current source. The holding means is
A transistor having an output of the demultiplexer circuit connected to a drain and a gate and a source connected to a negative voltage source;
A switch circuit that is turned off when one end is connected to the transistor gate and the non-selection signal is applied;
One end is connected to a negative voltage source and the other end is connected to the other end of the switch circuit to hold a gate voltage value and to be connected to a power input terminal of the corresponding power consuming means. The power supply circuit according to claim 3. The power consuming means is
A transistor in which the output of the holding means is applied to the gate and the source is connected to a negative voltage source;
6. The power supply circuit according to claim 1, further comprising: a load circuit having an end connected to the drain of the transistor and the other end connected to a positive voltage source. The power source is
The power supply circuit according to any one of claims 1 to 6, wherein the power supply circuit is shared by a plurality of the power consuming means.

Images