JP2008084962A - Solid-state image sensing device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a solid-state imaging apparatus reducing a leakage current among pixel cells, achieving a separation among the pixel cells proper to fining and improving the sensibility of an optoelectric transducer and a method for manufacturing the solid-state imaging apparatus. <P>SOLUTION: The solid-state imaging apparatus by one mode has a plurality of the pixel cells containing second conductivity type charge storage layers formed in second conductivity type semiconductor layers formed to the upper section of a first conductivity type substrate wafer. The solid-state imaging apparatus further has first conductivity type element isolation diffusion layers which are formed around the pixel cells to electrically isolate each pixel cell, and partially have different impurity concentrations in a plane. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a solid-state imaging device and a manufacturing method thereof, and more particularly to a solid-state imaging device that reduces leakage current between pixel cells and is suitable for miniaturization and a manufacturing method thereof.

  MOS (metal-oxide-semiconductor) type solid-state imaging device is a conventional CCD (charge coupled device) type solid-state imaging device (hereinafter referred to as a CCD image sensor), particularly for low voltage drive and low power consumption applications. Has been used instead.

  Since a MOS solid-state imaging device is basically manufactured by a CMOS process, it can be easily integrated with other CMOS circuits. A photoelectric conversion element (also called a photodiode) and a MOS transistor are provided on the same semiconductor wafer. The In a CMOS (complementary MOS) type amplification type solid-state imaging device (hereinafter referred to as a CMOS image sensor), an optical signal is detected by a photoelectric conversion element, and the generated signal charge is stored in a charge storage layer to modulate this potential. The pixel cell itself has an amplification function by modulating the amplification transistor inside the pixel cell by the potential of the charge storage layer. This CMOS image sensor is driven by, for example, a low voltage of 3 V and a single power source, and has a low power consumption of 50 mW.

  The CMOS image sensor has a large number of pixels like the CCD image sensor, and it is required to improve the sensitivity of the pixel in order to further reduce the pixel size.

In a conventional CMOS image sensor, a boron concentration is low in a semiconductor substrate wafer (for example, silicon wafer) containing a high concentration dopant (for example, boron (B) of about 1 to 3 × 10 ¹⁸ cm ⁻³ ) (for example, 1 × 10 ¹⁵ cm ⁻³ ) A so-called p / p ⁺ wafer in which 5 to 10 μm of epitaxial layers are stacked is used. The reason for using a p / p ⁺ wafer in a CMOS image sensor is that the lifetime of carriers (electrons) is short in a region with a high boron concentration located deep from the surface. Specifically, even when strong light is irradiated to the photoelectric conversion element and the generated carriers (electrons) reach the depth of the wafer, the electrons easily recombine and disappear in a region where the carrier lifetime is short. For this reason, it is because it can suppress that an electron (carrier) leaks through the deep position of a wafer to the photoelectric conversion element adjacent to the photoelectric conversion element irradiated with light. This suppresses blooming in terms of device characteristics.

Further, in the p / p ⁺ wafer, there is an interface that changes from a low boron concentration region to a high boron region at a deep position from the surface near the p ⁺ substrate wafer. Even if electrons generated by photoelectric conversion try to diffuse deep into the wafer, they are bounced back to the wafer surface by the electrical potential at this interface. In this case, a part of the bounced electrons gathers in the charge storage layer irradiated with light by diffusion or the like, so that compared with a photoelectric conversion element formed on a p-type semiconductor wafer having a uniform impurity concentration in the depth direction. , Improvement in sensitivity can be expected.

Also, a method of forming a photoelectric conversion element on an n-type semiconductor wafer like a CCD image sensor is effective in improving sensitivity because electrons generated by photoelectric conversion at a deeper position in the wafer can be used. In this case, it is necessary to form a p-type semiconductor layer (p well) at a depth of about 3 to 4 μm from the wafer surface, as employed in the CCD image sensor. Furthermore, in order to electrically isolate adjacent photoelectric conversion elements, it is necessary to form a p-type semiconductor region between the photoelectric conversion elements (see, for example, Patent Document 1). In this structure, when extremely intense light (for example, sunlight) is irradiated, a part of the generated electrons can be discarded on the substrate, so that blooming can be suppressed. However, since all electrons generated at a position deeper than the p-well are thrown away to the substrate, there is a problem that the sensitivity is lower than that of the p / p ⁺ wafer.

  In order to solve this problem of sensitivity reduction, in the CCD image sensor, a high voltage (for example, 5 V) is applied to the charge storage layer, and the depletion layer from the charge storage layer is greatly expanded to efficiently collect carriers in the charge storage layer. The method is taken.

However, the CMOS image sensor is characterized by low voltage driving compared to the CCD image sensor, and since a high voltage cannot be applied to the charge storage layer, the depletion layer of the charge storage layer does not spread compared to the CCD image sensor. It is difficult to improve the sensitivity of the photoelectric conversion element.
JP 2005-223134 A

  The present invention provides a solid-state imaging device that reduces the leakage current between pixel cells, realizes separation between pixel cells suitable for miniaturization, and improves the sensitivity of photoelectric conversion elements, and a method for manufacturing the same.

  A solid-state imaging device according to an aspect of the present invention includes a plurality of pixel cells including a second conductivity type charge storage layer formed in a second conductivity type semiconductor layer provided above a first conductivity type substrate wafer. And a first conductivity type element isolation diffusion layer provided around the pixel cell to electrically isolate each pixel cell and partially differ in impurity concentration in a plane.

  A method of manufacturing a solid-state imaging device according to another aspect of the present invention includes a step of forming element isolation made of an insulating film in a second conductivity type semiconductor layer provided above a first conductivity type substrate wafer; Forming a gate electrode on the semiconductor layer via a gate insulating film; and doping a second conductivity type impurity into one of the semiconductor layers adjacent to the gate electrode to form a second conductivity type signal detection layer Forming a second conductivity type charge storage layer by doping a second conductivity type impurity in the other semiconductor layer adjacent to the gate electrode, the gate electrode, and the signal detection layer , And a first mask covering a plurality of pixel cells including the charge storage layer, and a plurality of impurities of the first conductivity type are changed in the semiconductor layer below the element isolation between the pixel cells by changing the depth. The first doping step and the first mask The element around each pixel cell is repeated at least once by doping the first conductive type impurity into the semiconductor layer between the pixel cells using another mask covering the plurality of pixel cells of the combination. Forming a first conductivity type element isolation diffusion layer in the semiconductor layer below the isolation.

  According to the present invention, there is provided a solid-state imaging device and a method for manufacturing the same, which can reduce the leakage current between pixel cells, realize separation between pixel cells suitable for miniaturization, and improve the sensitivity of photoelectric conversion elements.

  Embodiments of the present invention disclose a solid-state imaging device that reduces the leakage current between pixel cells, realizes separation between pixel cells suitable for miniaturization, and improves the sensitivity of photoelectric conversion elements, and a manufacturing method thereof. To do.

  Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the drawings, corresponding parts are indicated by corresponding reference numerals. The following embodiment is shown as an example, and various modifications can be made without departing from the spirit of the present invention.

  In a solid-state imaging device, for example, a CMOS type amplification type solid-state imaging device (CMOS image sensor), a pixel cell includes a photoelectric conversion element including a charge storage layer, a transfer transistor, and a signal detection layer. Usually, one pixel unit is composed of four pixel cells.

As described above, in order to improve the performance of the CMOS image sensor, the selection of a semiconductor wafer as a starting material is important. FIG. 1 is a cross-sectional view showing an example of a CMOS image sensor. In this CMOS image sensor 100, by using a semiconductor wafer 10 (hereinafter referred to as n / p ⁺ wafer) in which an n-type epitaxial layer 14 (hereinafter referred to as an epi layer) is formed on a p ⁺ substrate wafer 12. In order to improve performance, such as improvement of sensitivity and suppression of blooming. This is because, for example, the charge storage layer of the photoelectric conversion element 20 formed in the n-type epi layer 14 is compared with the case of using a p / p ⁺ wafer in which a p-type epi layer is formed on a conventional p ⁺ substrate wafer. 26 is because the depletion layer is easy to spread and has an advantage that the sensitivity can be improved.

However, when a CMOS image sensor is formed on a conventional p / p ⁺ wafer, there are some problems when a solid-state imaging device is formed on an n / p ⁺ wafer. One of them is electrical separation between pixel cells Px including the photoelectric conversion elements 20.

When a conventional p / p ⁺ wafer is used, a photoelectric storage element is formed by providing a charge storage layer made of an n-type semiconductor layer in a p-type epi layer, so that between adjacent photoelectric conversion elements, that is, between pixel cells. Are automatically separated by a pn junction. However, in the n / p ⁺ wafer, since the photoelectric conversion element 20 is formed by providing the charge storage layer 26 made of an n-type semiconductor layer in the n-type epi layer 14, the adjacent pixel cells Px are electrically connected as they are. There is a problem that it leads to. Also, in the process of dicing from the wafer state into individual chips (dicing), in a conventional p / p ⁺ wafer, a p-type semiconductor layer appears on the cut surface of the chip. On the other hand, in an n / p ⁺ wafer, if dicing is performed as it is, a pn junction surface, that is, an interface between the substrate wafer 12 and the n-type epi layer 14 appears on the chip cut surface. When a pn junction surface appears on the chip cut surface, the cut surface becomes a source of leakage current or a leakage path, which causes an increase in leakage current.

  In order to solve the above problem, a p-type impurity is ion-implanted a plurality of times while changing the implantation depth into the adjacent pixel cell BA and the dicing region DA, and the n-type epitaxy to the p-type semiconductor layer inside the wafer 10 is performed. A technique for forming a p-type semiconductor element isolation diffusion layer 30 for isolating the layer 14 has been developed by the present inventors.

  However, there are points to be further improved in the developed technology. 2A and 2B are views for explaining ion implantation for forming the element isolation diffusion layer 30 shown in FIG. 1, in which FIG. 2A is a plan view and FIG. 2B is a schematic cross section. FIG. In FIG. 2B, functional elements such as photoelectric conversion elements formed in the semiconductor wafer are omitted. For the formation of the element isolation diffusion layer 30, a high acceleration voltage, that is, high energy ion implantation is used. In the ion implantation, the photoresist film 32 is used as a mask. For this reason, for example, it is necessary to cover the pixel cell Px with the resist film 32 formed to have a thickness of 4 to 5 μm and to expose the element isolation region BA in which ion implantation is performed. Further, as the miniaturization of the CMOS image sensor 100 progresses, the length of one side of the pixel cell Px is reduced from about 3 μm to a length shorter than that, and the width of the element isolation region BA is also reduced from 0.7 μm to less than that. Reduced. As a result, the mask resist film 32 for ion implantation has a shape with a small contact area with the semiconductor wafer 10 and a high height, and it is necessary to stand upright so as not to collapse. However, since the resist film 32 is an organic film, there is a limit in maintaining all the resist films 32 on the pixel cell region having such a shape formed, for example, 1 million or more vertically. If a part of the resist film 32 falls down and a part where the element isolation diffusion layer 30 cannot be formed occurs, a problem arises that the color mixture increases in some pixels of the CMOS image sensor 100.

  In a plurality of embodiments of the present invention, ion implantation for forming an element isolation diffusion layer is performed in a plurality of times using a resist film having a pattern including a plurality of pixel cells as a mask. In each ion implantation, a resist film having a pattern including a plurality of pixel cells in different combinations is used as a mask. Accordingly, there is provided a solid-state imaging device that realizes separation between pixel cells that reduces leakage current between adjacent pixel cells and is suitable for miniaturization, and a manufacturing method thereof. Furthermore, the solid-state imaging device according to the present invention can improve the reduction of the saturation output due to the reduction in the area of the photoelectric conversion element portion, and can increase the element isolation capability.

(Embodiment)
In one embodiment of the present invention, the ion implantation process is repeated twice using two masks, a first resist film having a vertical stripe pattern and a second resist film having a horizontal stripe pattern. A solid-state imaging device for forming an element isolation diffusion layer and a method for manufacturing the same.

  FIG. 3 is a cross-sectional view showing an example of a cross-sectional structure of the solid-state imaging device, for example, the CMOS image sensor 200 according to the present embodiment. 4A and 4B show two resist film patterns 32 and 34 used for forming the element isolation diffusion layer 30 according to the present embodiment, and FIG. 4C shows the formed CMOS. 4 is a plan view for explaining an element isolation diffusion layer 30 of the image sensor 200. FIG.

  The element isolation diffusion layer 30 that electrically isolates adjacent pixel cells Px is formed through two ion implantation steps. First, using the first resist film 32 covering the plurality of pixel cells Px arranged continuously in the vertical direction shown in FIG. 4A as a mask, the implantation energy (that is, the acceleration voltage) and the dose amount are changed. The ion implantation is performed a plurality of times and five times in FIG. 3 while changing the implantation depth. Thereby, the p-type element isolation diffusion layer 30 reaching the p-well 16 is formed in the n-type semiconductor layer 14a. The element isolation diffusion layer 30 is formed, for example, as 30-1 to 30-5 shown in FIG. Next, using the second resist film 34 covering the plurality of pixel cells Px arranged continuously in the horizontal direction shown in FIG. 4B as a mask, the implantation energy and the dose amount are similarly changed to change the implantation depth. The element isolation diffusion layer 30 is formed by performing ion implantation of different times.

  The element isolation diffusion layer 30 formed in this way has two intersections 30D between the element isolation diffusion layer 30 in the vertical direction and the element isolation diffusion layer 30 in the horizontal direction, as shown by hatching in FIG. Times of ion implantation. That is, a region 30D where the implanted impurity concentration is partially high, in this case, a region having twice the impurity concentration is formed.

Referring to the cross section of the CMOS image sensor according to the present embodiment shown in FIG. 3, the photoelectric conversion element 20 has a high concentration (for example, 1 to 5 × 10 ¹⁸ cm ⁻³ ) of a p-type impurity such as boron (B). ) Doped p ⁺ in the n-type epi layer 14a formed on the substrate wafer 12 (for example, a phosphorus (P) concentration of 1 to 5 × 10 ¹⁵ cm ⁻³ ). A p-type well 16 is formed between the p ⁺ substrate wafer 12 and the n-type epi layer 14a as described later. In the n-type epi layer 14a of the element isolation region BA around the pixel cell Px, an element isolation 18 made of an insulating film and an element isolation diffusion layer 30 made of a p-type semiconductor layer are formed. Thus, one pixel cell Px is surrounded by the element isolation 18 and the element isolation diffusion layer 30 and is electrically isolated from the adjacent pixel cells. The element isolation diffusion layer 30 is formed by multiple ion implantations as described above. Therefore, the element isolation diffusion layer 30 includes a plurality of portions having the same or different impurity concentration in the depth direction.

  The pixel cell Px includes an n-type charge storage layer 26 that is a photoelectric conversion unit formed in the n-type epi layer 14, a p-type surface shield layer 28 formed on the surface of the charge storage layer 26, and the charge storage layer 26. Includes a gate electrode 22 of a transfer transistor that controls reading of the accumulated charge and a signal detection layer 24 (drain of the transfer transistor) that temporarily accumulates charge to supply the read charge signal.

  Next, an example of the manufacturing process of the CMOS image sensor according to the present embodiment will be described with reference to the process cross-sectional view shown in FIG.

As shown in FIG. 5A, a p-type impurity (for example, boron (B) concentration 1 to 5 × 10 ¹⁸ cm ⁻³ ) having a high concentration is formed on the p ⁺ substrate wafer 12 with a thickness of 5 μm, for example. An n / p ⁺ wafer 10 having an epitaxially grown n-type semiconductor layer 14 (for example, phosphorus (P) 1 to 5 × 10 ¹⁵ cm ⁻³ ) (n-type epilayer) is used as a starting material.

Referring to FIG. 5B, in order to form the well 16 of the p-type semiconductor layer, for example, heat treatment is performed at 1150 ° C. for 1.5 hours, and boron in the p ⁺ substrate wafer 12 is converted into n-type epitaxial layer. Solid phase diffusion into layer 14. As a result, the boron concentration becomes about 1 to 5 × 10 ¹⁵ cm ⁻³ at a position of a depth of about 3 μm from the surface inside the n-type epi layer 14, and a thickness of p of about 2 μm from the interface with the p ⁺ substrate wafer 12. A mold well 16 is formed. As a result, the n-type epi layer 14 becomes an n-type epi layer 14a having an effective thickness of about 3 μm.

  Due to such impurity concentration distribution, at a position deeper than 5 μm in the wafer, since the boron concentration is high and the electron lifetime is short, the electrons generated by the light irradiation are immediately recombined and disappear. Electrons generated at a position shallower than 5 μm are potentialally pushed back to the surface and accumulated in the charge storage layer 26.

  Next, the element isolation 18 is formed in the element isolation region BA and the dicing region DA on the surface of the n-type epi layer 14a. As the element isolation 18, for example, STI (shallow trench isolation) can be used. Thereafter, a gate insulating film 21, a gate electrode 22, a gate wiring, a drain 24, and the like for forming transistors and capacitors are formed. The gate electrode 22 shown in FIG. 3 is a gate electrode of the transfer transistor, and the drain 24 functions as a signal detection layer.

The region other than the region where the charge storage layer 26 of the photoelectric conversion element 20 is formed is covered with a resist (not shown), and an n-type impurity such as phosphorus (P) is ion-implanted to form the charge storage layer 26. The ion implantation conditions of phosphorus are, for example, an acceleration voltage of 300 KV and a dose of 1 to 2 × 10 ¹² cm ⁻² . Thereby, for example, the charge storage layer 26 made of an n-type diffusion layer having a phosphorus concentration peak at a position of about 0.1 to 0.3 μm from the surface can be formed. In this way, the structure shown in FIG. 5B can be formed.

Next, in order to electrically isolate the pixel cells Px, the element isolation diffusion layer 30 is formed in the element isolation region BA and the dicing area DA surrounding the pixel cell Px. In the present embodiment, the element isolation diffusion layer 30 is formed by performing ion implantation below the STI by two ion implantation processes. First, for example, a first mask pattern having a vertically long opening, that is, an ion implantation region is formed so as to cover a plurality of pixel cells Px arranged in the vertical direction of the drawing as shown in FIG. 1 resist film 32 is used as a mask. In the ion implantation, in order to change the ion implantation depth, boron is performed a plurality of times, for example, five times while changing the ion implantation conditions to form the element isolation diffusion layer 30. Each ion implantation condition is, for example, an acceleration voltage of 100 to 300 KV and a dose amount of 1 × 10 ¹² cm ⁻² to 1 × 10 ¹³ cm ⁻² , and 300 to 500 KV of 1 × 10 ¹¹ cm ⁻² to 1 × 10 ¹² cm. ^-2 , 500 to 700 KV, 1 x 10 ¹¹ cm ^-2 to 1 x 10 ¹² cm ^-2 , 1000 to 1300 KV, 1 x 10 ¹¹ cm ^-2 to 1 x 10 ¹² cm ^-2 , 1600 to 1800 KV, 1 x 10 ¹¹ cm ⁻² to 1 × 10 ¹² cm ⁻² . It is preferable that the element isolation diffusion layer 30 has a boron concentration higher on the surface side near the charge storage layer 26 and the signal detection layer 24 which are n-type diffusion layers than at a deep portion. In this embodiment, the dose amount of the first ion implantation is increased by about one digit compared to the others.

  Next, as shown in FIG. 4B, the second resist film 34 having a second mask pattern that covers the plurality of pixel cells Px arranged in the horizontal direction in the drawing and has a horizontally long opening is masked. A second ion implantation step is performed. Thus, the element isolation diffusion layer 30 surrounding the pixel cell Px is formed by performing the ion implantation process a plurality of times in place of the resist film mask pattern.

  Thus, by using the resist films 32 and 34 covering the plurality of pixel cells Px as a mask pattern, the bottom area of the resist film can be increased, and the resist films 32 and 34 can be prevented from falling even if the pattern is miniaturized. . As a result, it is possible to prevent the element isolation diffusion layer 30 from being partially interrupted without performing ion implantation partially.

Thus, the p-type well 16 reaches the p-type well 16 from below the element isolation 18 (for example, STI), including further diffusion of boron from the p ⁺ substrate wafer 12 toward the surface during activation annealing of the ion-implanted boron. An element isolation diffusion layer 30 made of a mold diffusion layer can be formed. Therefore, the n-type epi layers 14a of the adjacent pixel cells Px are electrically isolated.

Next, a p-type semiconductor layer 28 is formed on the surface of the n-type epi layer 14 a above the charge storage layer 26. The p-type semiconductor layer 28 functions as a surface shield layer that suppresses the influence of the surface level on the surface of the semiconductor wafer. Specifically, a resist film (not shown) is formed on the surface, and the pattern of the surface shield layer is patterned. Using the resist film as a mask, p-type impurities such as boron are ion-implanted at an acceleration voltage of 10 KV and a dose of 1 to 3 × 10 ¹³ cm ⁻² . In this way, for example, a high concentration p-type diffusion layer 28 having a boron concentration of about 1 × 10 ¹⁹ cm ⁻³ can be formed from the surface to a depth of about 0.1 μm. As a result, the charge storage layer 26 can be embedded inside the wafer 10. Thus, the photoelectric conversion element 20 having a 3S (Surface Shield Sensor) structure is formed. In this way, the CMOS image sensor shown in FIG. 3 can be formed.

  Thereafter, steps necessary for the solid-state imaging device such as a wiring process are performed to complete the amplification type CMOS solid-state imaging device 200 according to the present embodiment.

  As described above, in this embodiment, in order to form the element isolation diffusion layer 30, the first resist film mask having a vertically long ion implantation region covering the plurality of pixel cells Px and the horizontally long ion implantation region. The ion implantation process is performed twice using the second resist film mask having The element isolation diffusion layer 30 formed in this way is ion-implanted twice in the portion 30D where the two ion-implanted regions intersect as shown by the oblique line in FIG. Doubled. The portion where the boron concentration is high is adjacent to the square pixel cell Px, that is, the corner of the photoelectric conversion element 20. Since electric field concentration is likely to occur at the corners of the photoelectric conversion element 20, it is preferable to enhance element isolation characteristics. In particular, when the amount of stored charge increases due to strong light, it is preferable to further enhance the element isolation characteristics because high electric field concentration may occur. Enhancing the element isolation characteristics can be realized by increasing the boron concentration of the element isolation diffusion layer 30. Therefore, in the amplification type CMOS solid-state imaging device 200 according to the present embodiment, the element isolation diffusion layer 30D adjacent to the corner portion of the photoelectric conversion element 20 has a higher boron concentration, that is, higher element isolation characteristics than other parts. Thus, it is possible to reduce the leakage current between the pixel cells Px, that is, reduce the color mixture.

  The above manufacturing method is an example, and can be executed by replacing the order of the steps or replacing with another step capable of creating an equivalent structure.

  The above embodiment can be implemented with various modifications. Next, some modifications of the resist film mask pattern used for ion implantation for forming the element isolation diffusion layer and the semiconductor wafer as a starting material will be described. However, the present invention is not limited to these examples.

(Modification 1)
FIG. 6 shows a resist film pattern used for ion implantation for forming the element isolation diffusion layer of Modification 1 of the present invention. This pattern is orthogonal to the vertical stripe and horizontal stripe resist film patterns shown in FIG. 4 used in the above embodiment for each n pixel cell Px (where n ≧ 2). It is a resist film pattern provided with an additional opening. n may be the same value or a different value in the first and second resist film patterns. FIGS. 6A and 6B are resist film patterns when n = 2, and FIG. 6C is shown for explaining the element isolation diffusion layer 30 of the CMOS image sensor after ion implantation. It is a top view.

  As described above, in the CMOS image sensor, one pixel unit is constituted by four pixel cells Px. When the patterns of the first and second resist films 32 and 34 as shown in FIGS. 6A and 6B with n = 2 are used, the element isolation diffusion layer 30 is hatched in FIG. 6C. Like the region, a region 30D in which the impurity concentration is twice increased by ion implantation twice is formed surrounding four pixel cells Px, that is, one pixel unit. Therefore, the element isolation capability can be increased for each pixel unit, and color mixing between the pixel units can be reduced. Further, a region 30D in which the impurity concentration is doubled is also formed at the center in the pixel unit. Since this is adjacent to the corner of the photoelectric conversion element in each pixel cell, the element isolation capability can be improved even within one pixel unit.

(Modification 2)
FIG. 7 shows a resist film pattern used for ion implantation for forming the element isolation diffusion layer of Modification 2 of the present invention. This pattern is a resist film pattern having the size of one pixel unit, that is, four (2 × 2) pixel cells Px. As shown in FIGS. 7A and 7B, the first and second patterns are used. The patterns of the resist films 32 and 34 are shifted by one pixel cell in the vertical and horizontal directions. FIG. 7C is a plan view for explaining the element isolation diffusion layer 30 of the CMOS image sensor after ion implantation.

  A region 30D hatched in FIG. 7C is a region with a high impurity concentration where ion implantation is performed twice. A region in which the impurity concentration is doubled is formed in the center of the pixel unit indicated by a broken line in FIG. Since this is adjacent to the corner of the photoelectric conversion element 20 in each pixel cell, the element isolation capability can be improved in one pixel unit. Furthermore, regions where the impurity concentration is doubled are also formed at the four corners of each pixel unit, and the element isolation capability can be partially improved between the pixel units.

(Modification 3)
Modification 3 of the present invention is a case where ion implantation for forming an element isolation diffusion layer is performed using three resist film patterns. A resist film pattern of Modification 3 is shown in FIG. In the present modification, as shown in FIG. 8A, the pattern of the first resist film 32 is a pattern having a rectangular wave-shaped opening having a period of two pixel cells and a vertical pattern obtained by inverting this vertically. This is a combination of a pattern shifted by a pixel cell. The other two resist film patterns, that is, the patterns of the second resist film 34 and the third resist film 26 are the same as the patterns of FIG. 8A as shown in FIGS. The pixel cells are sequentially shifted in the vertical direction. FIG. 8D is a plan view for explaining the element isolation diffusion layer 30 of the CMOS image sensor after ion implantation using these three resist film patterns.

  A hatched region 30D in FIG. 8C is a region where ion implantation is performed twice, and a meshed region 30T is a region where ion implantation is performed three times. The division of the pixel unit is indicated by a broken line in FIG. Each pixel unit is composed of one R pixel, two G pixels, and one B pixel. The R pixel is less likely to attenuate red light in silicon, and thus is more likely to cause color mixing than other pixels. As shown in FIG. 8D, according to this modification, one of the four pixel cells Px has a high impurity concentration in which all four sides are ion-implanted twice or more. Surrounded by diffusion layers 30D and 30T. R, G, and B pixels are assigned to each pixel unit as indicated by R, G, and B in the drawing so that this pixel cell becomes an R pixel. Thereby, the element isolation capability of the R pixel can be improved, and color mixing due to a leak current between the pixels can be effectively suppressed.

  The resist film pattern shown in the above modification is an exemplification, and other resist film patterns can be used. For example, a resist film pattern having 3 × 3 9 pixel cells as one block as shown in FIG. 9 can be used as a mask for ion implantation. In this case, the patterns of the three resist films 32, 34, and 36 shifted by one pixel in the vertical direction and the horizontal direction are used.

  Thus, by using a resist film pattern covering a plurality of pixel cells as a mask for ion implantation for forming an element isolation diffusion layer, the mask resist film can be prevented from falling in the ion implantation process, and the solid-state imaging device Even if the device is miniaturized, a desired element isolation diffusion layer can be formed.

(Modification 4)
Modification 4 of the present invention is a modification regarding the starting material. FIG. 10 is a cross-sectional view showing an example of a cross-sectional structure of a solid-state imaging device according to this modification. In the above embodiment, the n / p ⁺ wafer 10 is used as a starting material, and the p-well 16 is formed at the interface between the n-epi layer 14 and the p ⁺ substrate wafer 12 as shown in FIG. To the n-epi layer 14. In this modification, as shown in the cross-sectional view of FIG. 10, n / p / is formed by first forming a p-type epi layer 13 on a p ⁺ substrate wafer 12 and further forming an n-type epi layer 14 thereon. p ⁺ wafer 10a is used. The p well 16 is formed by thermally diffusing boron in the p ⁺ substrate wafer 12. The boron concentration in the p ⁺ substrate wafer 12 is within a specified range, but is not constant from wafer to wafer. Therefore, this variation in boron concentration causes a variation in the thickness of the p-well layer 16, and causes a variation in the thickness of the effective n-type semiconductor layer 14a that is a photoelectric conversion portion. That is, the photosensitivity of the solid-state image sensor is varied. By using the n / p / p ⁺ wafer 10a, variation in the thickness of the n-type semiconductor layer 14 of the photoelectric conversion unit can be suppressed.

(Modification 5)
In the above embodiment and the modification, the depth at which the element isolation diffusion layer can be formed is limited by the limit of the acceleration voltage of the ion implantation apparatus. As a result, the thickness of the n-type semiconductor layer of the photoelectric conversion unit is limited. However, in order to improve the sensitivity of the solid-state imaging device, it is preferable that the n-type semiconductor layer is thick. Modification 5 of the present invention uses a semiconductor wafer having a buried diffusion layer. In this modification, an n / p / p ⁺ wafer will be described as an example, but the present invention can also be applied to an n / p ⁺ wafer.

In the n / p / p ⁺ wafer 10a of this modification, as shown in the sectional view of FIG. 11A, after forming the p-type epi layer 13 on the p ⁺ substrate wafer 12, the n-type epi layer 14 is formed. Before forming the high-concentration boron diffusion layer, a high-concentration boron diffusion layer is formed on the surface of the p-type epi layer 13 corresponding to the element isolation region BA and the dicing region DA for forming the element isolation diffusion layer 30. The boron ion implantation conditions are, for example, an acceleration voltage of 100 KV and a dose of 1 × 10 ¹³ to 1 × 10 ¹⁵ cm ⁻² . As a result, the buried diffusion layer 40 of boron having a concentration similar to or higher than that of the p ⁺ substrate wafer 12 can be formed.

  Boron in the buried diffusion layer 40 is diffused into the n-type epi layer 14 by annealing after ion implantation for forming the element isolation diffusion layer 30 performed thereafter. Since the boron concentration in the buried diffusion layer 40 is higher than the boron concentration introduced by ion implantation, the diffusion distance toward the surface increases as shown in FIG. Therefore, the n-type semiconductor layer 14 can be thickened by the diffusion distance from the buried diffusion layer 40, and the sensitivity of the solid-state imaging device can be improved.

  As described above, according to the present invention, the leakage current between pixel cells is reduced and miniaturized by dividing the ion implantation process for forming the element isolation diffusion layer into a plurality of times including the resist process. It is possible to provide a solid-state imaging device and a method for manufacturing the same that achieve separation between pixel cells suitable for the above and improve the sensitivity of the photoelectric conversion element. Furthermore, the solid-state imaging device according to the present invention can improve the reduction of the saturation output due to the reduction in the area of the photoelectric conversion element portion, and can increase the element isolation capability.

  The present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the spirit and scope of the present invention. Therefore, the present invention is not intended to be limited to the embodiments disclosed herein, and can be applied to other embodiments without departing from the spirit of the present invention and can be applied to a wide range. It is.

FIG. 1 is a cross-sectional view illustrating an example of a cross section of a solid-state imaging device. 2A and 2B are diagrams for explaining ion implantation for forming an element isolation diffusion layer of the solid-state imaging device shown in FIG. 1, in which FIG. 2A is a plan view and FIG. 2B is a schematic diagram. FIG. FIG. 3 is a cross-sectional view for explaining an example of a cross-sectional structure of the solid-state imaging device according to the embodiment of the present invention. FIGS. 4A and 4B are examples of two resist film patterns used for forming the element isolation diffusion layer of the solid-state imaging device according to the embodiment of the present invention. FIG. It is a top view shown in order to demonstrate the element isolation diffusion layer formed using the resist film pattern shown to 4 (a), (b). 5A and 5B are process cross-sectional views shown to describe an example of a manufacturing process of the solid-state imaging device according to the embodiment of the present invention. FIGS. 6A and 6B are examples of two resist film patterns used for forming the element isolation diffusion layer of the solid-state imaging device according to the first modification of the present invention. FIG. It is a top view shown in order to demonstrate the element isolation diffusion layer of the CMOS image sensor after ion implantation. FIGS. 7A and 7B are examples of two resist film patterns used for forming the element isolation diffusion layer of the solid-state imaging device of Modification 2 of the present invention. FIG. It is a top view shown in order to demonstrate the element isolation diffusion layer of the CMOS image sensor after ion implantation. FIGS. 8A, 8B, and 8C are examples of three resist film patterns used for forming the element isolation diffusion layer of the solid-state imaging device of Modification 3 of the present invention. d) is a plan view for explaining an element isolation diffusion layer of a CMOS image sensor after ion implantation. FIGS. 9A, 9B, and 9C are examples of another three resist film patterns used for forming the element isolation diffusion layer of the solid-state imaging device of Modification 3 of the present invention. 9 (d) is a plan view shown for explaining the element isolation diffusion layer of the CMOS image sensor after ion implantation. FIG. 10 is a cross-sectional view for explaining an example of a solid-state imaging device according to Modification 4 of the present invention. FIGS. 11A and 11B are cross-sectional views shown for explaining an example of a solid-state imaging device according to Modification 5 of the present invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 ... Semiconductor wafer, 12 ... p ⁺ substrate wafer, 13 ... p-type epitaxial layer, 14 ... n-type epitaxial layer, 16 ... p-well, 18 ... Element isolation, 20 ... Photoelectric conversion element, 21 ... Gate insulating film, 22 ... Gate electrode, 24 ... signal detection layer, 26 ... charge storage layer, 28 ... surface shield layer, 30 ... element isolation diffusion layer, 32, 34, 36 ... resist film, BA ... element isolation area, DA ... dicing area, 100, 200: Solid-state imaging device, Px: Pixel cell.

Claims (5)

A plurality of pixel cells including a second conductivity type charge storage layer formed in a second conductivity type semiconductor layer provided above the first conductivity type substrate wafer;
A solid-state imaging device comprising a first conductivity type element isolation diffusion layer provided around the pixel cell to electrically isolate each pixel cell and partially differ in impurity concentration in a plane.   The solid-state imaging device according to claim 1, wherein the element isolation diffusion layer includes a plurality of portions having the same or different impurity concentration in the depth direction.   The element isolation diffusion layer is provided below the element isolation in contact with the element isolation made of an insulating film provided in the vicinity of the surface of the semiconductor layer, and the impurity concentration of the portion in contact with the element isolation is lower than that. The solid-state imaging device according to claim 1, wherein the concentration is higher than the impurity concentration of the portion.   The portion having a high impurity concentration in a plane in the element isolation diffusion layer has a concentration that is an integral multiple of the impurity concentration of the lowest impurity concentration in the plane in the element isolation diffusion layer. Item 4. The solid-state imaging device according to any one of Items 1 to 3. Forming an isolation made of an insulating film in a second conductivity type semiconductor layer provided above the first conductivity type substrate wafer;
Forming a gate electrode on the semiconductor layer via a gate insulating film;
Doping a second conductivity type impurity into one of the semiconductor layers adjacent to the gate electrode to form a second conductivity type signal detection layer;
Doping a second conductivity type impurity into the other semiconductor layer adjacent to the gate electrode to form a second conductivity type charge storage layer;
A first mask that covers a plurality of pixel cells including the gate electrode, the signal detection layer, and the charge storage layer is used to change the depth in the semiconductor layer below the element isolation between the pixel cells. A step of doping a conductivity type impurity multiple times;
The doping of the first conductivity type impurity into the semiconductor layer between the pixel cells is repeated at least once using another mask that covers a plurality of pixel cells in a combination different from the first mask, and Forming a first conductivity type element isolation diffusion layer in the semiconductor layer below the element isolation around each pixel cell.

Images