JP2016058635A - Semiconductor device manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve performance of a semiconductor device; and reduce manufacturing cost.SOLUTION: A semiconductor device comprises a plurality of photodiodes arranged on a principal surface of a semiconductor substrate in an array, ptype semiconductor regions PR each surrounding each photodiode in plan view and a plurality of transistors arranged among photodiodes adjacent to each other in a Y direction. A semiconductor device manufacturing method comprises: a process of forming ptype semiconductor regions PR by ion implantation of a p type impurity into a semiconductor substrate by using a mask layer KM having an opening for opening a scheduled area where the ptype semiconductor regions PR are to be formed; and a process of performing ion implantation of an n type impurity into the semiconductor substrate by using the mask layer MK. In the process of performing ion implantation of the n type impurity, ion implantation is performed on regions among photodiode formation scheduled regions PDA adjacent to each other in the Y direction but ion implantation is not performed on regions among the photodiode formation scheduled regions PDA adjacent to each other in an X direction.SELECTED DRAWING: Figure 29

Description

  The present invention relates to a method for manufacturing a semiconductor device, and can be suitably used for, for example, a method for manufacturing a semiconductor device including a solid-state imaging element.

  As a solid-state imaging device, development of a solid-state imaging device (CMOS image sensor) using a complementary metal oxide semiconductor (CMOS) has been advanced. This CMOS image sensor includes a plurality of pixels each having a photodiode and a transfer transistor.

  Japanese Patent Laying-Open No. 2008-91781 (Patent Document 1) describes a technique for forming an element isolation layer between adjacent photodiodes in a CMOS image sensor.

  Japanese Unexamined Patent Application Publication No. 2009-130252 (Patent Document 2) describes a technique related to multistage ion implantation.

JP 2008-91781 A JP 2009-130252 A

  Although there is a semiconductor device having a photoelectric conversion element, even in such a semiconductor device, it is desired to improve the performance of the semiconductor device as much as possible. Alternatively, it is desired to reduce the manufacturing cost of the semiconductor device. Alternatively, it is desired to improve performance and reduce manufacturing costs.

  Other problems and novel features will become apparent from the description of the specification and the accompanying drawings.

  According to an embodiment, a semiconductor device includes a plurality of photoelectric conversion elements arranged in an array in a first direction and a second direction intersecting the first direction on a main surface of a semiconductor substrate, and the semiconductor substrate A first conductive type first semiconductor region formed so as to surround each photoelectric conversion element in plan view, and a plurality of photoelectric conversion elements arranged between the photoelectric conversion elements adjacent in the second direction of the main surface of the semiconductor substrate And a transistor. In this method of manufacturing a semiconductor device, (a) forming a mask layer having an opening for opening a region where the first semiconductor region is to be formed on the semiconductor substrate; (b) forming the mask layer into an ion Forming the first semiconductor region of the first conductivity type in the semiconductor substrate by ion-implanting the first conductivity type impurity into the semiconductor substrate using the implantation blocking mask. The semiconductor device manufacturing method further includes (c) a step of ion-implanting the second conductivity type impurity into the semiconductor substrate using the mask layer as an ion implantation blocking mask. In the step (c), ions are implanted into the first region corresponding to the region between the photoelectric conversion elements adjacent in the second direction on the main surface of the semiconductor substrate. Ion implantation is not performed on the second region corresponding to the region between the adjacent photoelectric conversion elements.

  According to one embodiment, the performance of a semiconductor device can be improved.

  Alternatively, the manufacturing cost of the semiconductor device can be reduced.

  Alternatively, the performance of the semiconductor device can be improved and the manufacturing cost of the semiconductor device can be reduced.

1 is a circuit block diagram illustrating a configuration example of a semiconductor device according to an embodiment; It is a circuit diagram which shows the structural example of a pixel. It is a circuit diagram which shows the other structural example of a pixel. It is a top view which shows the semiconductor wafer and chip area | region in which the semiconductor device of one embodiment is formed. It is a principal part top view of the semiconductor device of one embodiment. It is a principal part top view of the semiconductor device of one embodiment. It is a principal part top view of the semiconductor device of one embodiment. It is a principal part top view of the semiconductor device of one embodiment. FIG. 6 is a partially enlarged plan view showing a part of FIG. 5 in an enlarged manner. It is principal part sectional drawing of the semiconductor device of one embodiment. It is principal part sectional drawing of the semiconductor device of one embodiment. It is principal part sectional drawing of the semiconductor device of one embodiment. It is principal part sectional drawing of the semiconductor device of one embodiment. It is principal part sectional drawing of the semiconductor device of one embodiment. It is a principal part top view in the manufacturing process of the semiconductor device which is one Embodiment. FIG. 16 is an essential part cross sectional view of the same semiconductor device as in FIG. 15 during a manufacturing step; FIG. 16 is an essential part cross sectional view of the same semiconductor device as in FIG. 15 during a manufacturing step; FIG. 16 is an essential part cross sectional view of the same semiconductor device as in FIG. 15 during a manufacturing step; FIG. 16 is an essential part cross sectional view of the same semiconductor device as in FIG. 15 during a manufacturing step; FIG. 20 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIGS. 15 to 19; FIG. 21 is an essential part cross sectional view of the same semiconductor device as in FIG. 20 during a manufacturing step; FIG. 21 is an essential part cross sectional view of the same semiconductor device as in FIG. 20 during a manufacturing step; FIG. 21 is an essential part cross sectional view of the same semiconductor device as in FIG. 20 during a manufacturing step; FIG. 24 is a fragmentary plan view of the semiconductor device during a manufacturing step following that of FIGS. 20 to 23; FIG. 25 is an essential part cross sectional view of the same semiconductor device as in FIG. 24 during a manufacturing step; FIG. 25 is an essential part cross sectional view of the same semiconductor device as in FIG. 24 during a manufacturing step; FIG. 25 is an essential part cross sectional view of the same semiconductor device as in FIG. 24 during a manufacturing step; FIG. 25 is an essential part cross sectional view of the same semiconductor device as in FIG. 24 during a manufacturing step; FIG. 29 is an essential part plan view of the semiconductor device in manufacturing process, following FIGS. 24 to 28; FIG. 30 is an essential part plan view of the same semiconductor device as in FIG. 29 in manufacturing process; FIG. 30 is an essential part cross sectional view of the same semiconductor device as in FIG. 29 during a manufacturing step; FIG. 30 is an essential part cross sectional view of the same semiconductor device as in FIG. 29 during a manufacturing step; FIG. 30 is an essential part cross sectional view of the same semiconductor device as in FIG. 29 during a manufacturing step; FIG. 34 is an essential part plan view of the semiconductor device in manufacturing process, following FIGS. 29 to 33; FIG. 35 is an essential part plan view of the same semiconductor device as in FIG. 34 in manufacturing process; FIG. 35 is an essential part cross sectional view of the same semiconductor device as in FIG. 34 during a manufacturing step; FIG. 35 is an essential part cross sectional view of the same semiconductor device as in FIG. 34 during a manufacturing step; FIG. 35 is an essential part cross sectional view of the same semiconductor device as in FIG. 34 during a manufacturing step; FIG. 39 is an essential part plan view of the semiconductor device in manufacturing process, following FIGS. 34 to 38; FIG. 40 is an essential part cross sectional view of the same semiconductor device as in FIG. 39 during a manufacturing step; FIG. 40 is an essential part cross sectional view of the same semiconductor device as in FIG. 39 during a manufacturing step; FIG. 40 is an essential part cross sectional view of the same semiconductor device as in FIG. 39 during a manufacturing step; FIG. 40 is an essential part cross sectional view of the same semiconductor device as in FIG. 39 during a manufacturing step; FIG. 44 is a substantial part plan view of the semiconductor device during a manufacturing step following that of FIGS. 39 to 43; FIG. 45 is an essential part cross sectional view of the same semiconductor device as in FIG. 44 during a manufacturing step; FIG. 45 is an essential part cross sectional view of the same semiconductor device as in FIG. 44 during a manufacturing step; FIG. 45 is an essential part cross sectional view of the same semiconductor device as in FIG. 44 during a manufacturing step; FIG. 45 is an essential part cross sectional view of the same semiconductor device as in FIG. 44 during a manufacturing step; FIG. 49 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIGS. 44 to 48; FIG. 50 is an essential part cross sectional view of the same semiconductor device as in FIG. 49 during a manufacturing step; FIG. 50 is an essential part cross sectional view of the same semiconductor device as in FIG. 49 during a manufacturing step; FIG. 50 is an essential part cross sectional view of the same semiconductor device as in FIG. 49 during a manufacturing step;

  In the following embodiments, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments. However, unless otherwise specified, they are not irrelevant to each other. There are some or all of the modifications, details, supplementary explanations, and the like. Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), especially when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and may be more or less than the specific number. Further, in the following embodiments, the constituent elements (including element steps and the like) are not necessarily indispensable unless otherwise specified and apparently essential in principle. Needless to say. Similarly, in the following embodiments, when referring to the shapes, positional relationships, etc. of the components, etc., the shapes are substantially the same unless otherwise specified, or otherwise apparent in principle. And the like are included. The same applies to the above numerical values and ranges.

  Hereinafter, embodiments will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof will be omitted. In the following embodiments, the description of the same or similar parts will not be repeated in principle unless particularly necessary.

  In the drawings used in the embodiments, hatching may be omitted even in a cross-sectional view so as to make the drawings easy to see. Further, even a plan view may be hatched to make the drawing easy to see.

(Embodiment)
Hereinafter, the structure and manufacturing process of the semiconductor device of the present embodiment will be described in detail with reference to the drawings. In the first embodiment, an example in which the semiconductor device is a CMOS image sensor as a surface irradiation type image sensor in which light is incident from the surface side of the semiconductor substrate will be described.

<Configuration of semiconductor device>
FIG. 1 is a circuit block diagram illustrating a configuration example of the semiconductor device of the present embodiment. FIG. 2 is a circuit diagram illustrating a configuration example of a pixel. FIG. 1 shows 16 pixels of 4 rows and 4 columns (4 × 4) arranged in an array (matrix), but the number of pixels is not limited to this and can be variously changed. For example, there are millions of pixels actually used in electronic devices such as cameras.

  In the pixel region 1A shown in FIG. 1, a plurality of pixels PU are arranged in an array, and a drive circuit such as a vertical scanning circuit VSC or a horizontal scanning circuit HSC is arranged around the pixel PU. Each pixel (cell, pixel unit) PU is arranged at the intersection of the selection line SL and the output line (output signal line) OL. The selection line SL is connected to the vertical scanning circuit VSC, and the output line OL is connected to the column circuit CLC. The column circuit CLC is connected to the output amplifier AP via the switch SWT. Each switch SWT is connected to the horizontal scanning circuit HSC and controlled by the horizontal scanning circuit HSC.

  For example, the electrical signal read from the pixel PU selected by the vertical scanning circuit VSC and the horizontal scanning circuit HSC is output via the output line OL and the output amplifier AP.

  The configuration of the pixel PU includes, for example, a photodiode PD and transistors RST, TX, SEL, and AMI as shown in FIG. 2 or FIG. These transistors RST, TX, SEL, and AMI are each formed of an n-channel type MISFET (Metal Insulator Semiconductor Field Effect Transistor). Among these, the transistor RST is a reset transistor (reset transistor), the transistor TX is a transfer transistor (transfer transistor), the transistor SEL is a selection transistor (selection transistor), and the transistor AMI is an amplification transistor (amplification transistor). Transistor). The transfer transistor TX is a transfer transistor that transfers the charge generated by the photodiode PD. In addition to these transistors, other transistors and capacitors may be incorporated. Further, there are various modifications and application forms for the connection form of these transistors.

  FIG. 2 shows a circuit configuration example of two pixels PU. That is, FIG. 2 shows a circuit configuration example of a total of two pixels PU, that is, the pixel PU having the photodiode PD1 and the pixel PU having the photodiode PD2.

  In the case of FIG. 2, a circuit example in which the amplification transistor AMI, the selection transistor SEL, and the reset transistor RST are shared by two pixels PU is illustrated. In this case, one transfer transistor TX is provided for one photodiode PD, whereas one pair of amplification transistor AMI, selection transistor SEL, and reset is provided for two photodiodes PD (PD1, PD2). A transistor RST is provided. The transfer transistor TX provided for the photodiode PD1 is a transfer transistor TX1, and the transfer transistor TX provided for the photodiode PD2 is a transfer transistor TX2.

  In the circuit example shown in FIG. 2, a photodiode PD1 and a transfer transistor TX1 are connected in series between a ground potential (ground potential) GND and a node N1, and a ground potential (ground potential) GND and a node N1 are connected to each other. A photodiode PD2 and a transfer transistor TX2 are connected in series. The photodiodes (PD1, PD2) are on the ground potential GND side, and the transfer transistors (TX1, TX2) are on the node N1 side. A series circuit of the photodiode PD1 and the transfer transistor TX1 and a series circuit of the photodiode PD2 and the transfer transistor TX2 are connected in parallel between the ground potential (ground potential) GND and the node N1. That is, the photodiode PD1 is connected to the common floating diffusion FD via the transfer transistor TX1, and the photodiode PD2 is connected to the common floating diffusion FD via the transfer transistor TX2. The photodiode PD is a PN junction diode and includes, for example, a plurality of n-type or p-type impurity diffusion regions (semiconductor regions). The floating diffusion FD has a function as a charge storage portion or a floating diffusion layer, and is constituted by, for example, an n-type impurity diffusion region (semiconductor region).

  A reset transistor RST is connected between the node N1 and the power supply potential (power supply potential line) VDD. A selection transistor SEL and an amplification transistor AMI are connected in series between the power supply potential VDD and the output line (output signal line) OL. The gate electrode of the amplification transistor AMI is connected to the node N1. The gate electrode of the reset transistor RST is connected to the reset line LRST. The gate electrode of the selection transistor SEL is connected to the selection line SL, and the gate electrode of the transfer transistor TX is connected to the transfer line (second selection line) LTX. However, the gate electrode of the transfer transistor TX1 is connected to the transfer line LTX1, and the gate electrode of the transfer transistor TX2 is connected to the transfer line LTX2.

  For example, the transfer line LTX (LTX1, LTX2) and the reset line LRST are raised (set to high level), and the transfer transistor TX (TX1, TX2) and the reset transistor RST are turned on. As a result, the charge of the photodiode PD (PD1, PD2) is removed and depleted. Thereafter, the transfer transistor TX (TX1, TX2) is turned off.

  Thereafter, for example, when a mechanical shutter of an electronic device such as a camera is opened, charges are generated and accumulated by incident light in the photodiode PD (PD1, PD2) while the shutter is opened. That is, the photodiode PD (PD1, PD2) receives incident light and generates charges.

  Next, after closing the shutter, the reset line LRST is lowered (set to low level), and the reset transistor RST is turned off. Further, the selection line SL and the transfer line LTX1 are raised (set to high level), and the selection transistor SEL and the transfer transistor TX1 are turned on. Thereby, the charge generated by the photodiode PD1 is transferred to the end (floating diffusion FD) of the transfer transistor TX1 on the node N1 side. At this time, the potential of the floating diffusion FD changes to a value corresponding to the charge transferred from the photodiode PD1, and this value is amplified by the amplification transistor AMI and appears on the output line OL. The potential of the output line OL becomes an electric signal (light reception signal) and is read out as an output signal from the output amplifier AP via the column circuit CLC and the switch SWT.

  Further, the transfer line LTX1 is shifted in timing and the transfer line LTX2 is raised (set to high level) to turn on the transfer transistor TX2, whereby the charge generated by the photodiode PD2 is transferred to the node N1 side of the transfer transistor TX2. Transferred to the end (floating diffusion FD). Also in this case, the potential of the floating diffusion FD is amplified by the amplification transistor AMI and appears on the output line OL. This potential of the output line OL becomes an electric signal (light reception signal), and is output via the column circuit CLC and the switch SWT. It is read out from the AP as an output signal.

  FIG. 3 shows a circuit configuration example of one pixel PU shown in FIG.

  Unlike the case of FIG. 2, in the case of FIG. 3, one set of transfer transistor TX, amplification transistor AMI, selection transistor SEL, and reset transistor RST is provided for one photodiode PD. That is, in the case of FIG. 2, the amplification transistor AMI, the selection transistor SEL, and the reset transistor RST are shared by the two pixels PU, but in the case of FIG. 3, the amplification transistor AMI, the selection transistor SEL, and the reset transistor. The RST is not shared by the two pixels PU but is provided for each pixel PU. Other than that, the connection relationship, function, and operation of the photodiode PD, the transfer transistor TX, the amplification transistor AMI, the selection transistor SEL, and the reset transistor RST are the same as in the case of the circuit configuration of FIG. Since they are the same, repeated description thereof is omitted here.

  FIG. 4 is a plan view showing a semiconductor wafer and a chip region on which the semiconductor device of the present embodiment is formed. As shown in FIG. 4, the semiconductor wafer WF (a semiconductor wafer corresponding to a semiconductor substrate SB described later) has a plurality of chip regions CHP, and the pixel region 1A shown in FIG. 1 has one chip together with the peripheral circuit region 2A. It is formed in region CHP. As described above, a plurality of pixels PU are arranged in an array in the pixel region 1A of each chip region CHP. A logic circuit (logic circuit) is arranged in the peripheral circuit region 2A of each chip region CHP. For example, the logic circuit calculates an output signal output from the pixel region 1A, and outputs image data based on the calculation result. The chip region CHP is a region from which one semiconductor chip is obtained, and each chip region CHP in the semiconductor wafer WF has the same configuration (pixel region 1A and peripheral circuit region 2A). The semiconductor wafer WF is later cut by dicing, and individual chip regions CHP that have been separated into individual chips become semiconductor chips.

<About planar layout of semiconductor devices>
5 to 8 are plan views showing a part of the pixel region 1A of the semiconductor device according to the present embodiment. FIGS. 5 to 8 show the same planar region. FIG. 9 is a partially enlarged plan view in which a part of FIG. 5 is enlarged. 10 to 14 are main-portion cross-sectional views of the semiconductor device of the present embodiment.

5 corresponds to FIG. 6 except for the gate electrodes GT and GE. FIG. 6 includes a layout of the p ⁺ type semiconductor region PR corresponding to FIG. The figure excluding the region ST corresponds to FIG. Therefore, FIG. 7 is a combination of FIG. 6 and FIG. 5 to 9 are plan views. In order to make the drawings easy to see, in FIG. 5 and FIG. 9, the photodiode PD, the gate electrodes GT and GE, and the element isolation region ST are hatched. In FIG. 6, the photodiode PD and the element isolation region ST are hatched. In FIG. 7, the photodiode PD and the element isolation region ST are hatched with hatching, and the p ⁺ type semiconductor region PR is hatched with dot. In FIG. 8, the photodiode PD is hatched with hatching. In addition, the p ⁺ type semiconductor region PR is hatched with dots. That is, in FIG. 7, but hatched marked area of the dot corresponds to the p ⁺ -type semiconductor region PR, a part of the p ⁺ -type semiconductor region PR overlaps the element isolation region ST in plan view.

  10 to 14 are cross-sectional views of main parts of the pixel region 1A (see FIG. 4), and FIG. 14 is a main part of the peripheral circuit region 2A (see FIG. 4). It is sectional drawing. 5 and 6 substantially corresponds to FIG. 10, and the sectional view taken along line BB of FIGS. 5 and 6 substantially corresponds to FIG. A cross-sectional view taken along a line CC substantially corresponds to FIG. 12, and cross-sectional views taken along a line DD in FIGS. 5 and 6 substantially correspond to FIG.

  Note that “plan view” or “view in plan” refers to a case where the semiconductor device is viewed in a plane parallel to a main surface of a semiconductor substrate (corresponding to a semiconductor substrate SB described later) constituting the semiconductor device. To do.

  First, the planar layout of the pixel region 1A of the semiconductor device of the present embodiment will be described with reference to FIGS.

  As described above, in the pixel region 1A, the plurality of pixels PU are arranged in an array (matrix), and specifically, are arranged in an array in the X direction and the Y direction. Here, the X direction and the Y direction are directions intersecting each other, preferably directions orthogonal to each other, and are shown in FIGS. Note that the X direction and the Y direction are also directions parallel to a main surface of a semiconductor substrate SB described later.

  As described with reference to FIG. 2 and FIG. 3, each pixel PU includes the photodiode PD and the transfer transistor TX. For this reason, as shown in FIGS. 5 to 9, a plurality of photodiodes PD are arranged in an array (matrix) in the pixel region 1 </ b> A. Specifically, the pixel regions 1 </ b> A are arrayed in the X and Y directions. Is arranged. In the pixel region 1A, the plurality of photodiodes PD arranged in an array in the X direction and the Y direction are separated from each other.

  In the present embodiment, the transfer transistor TX, the amplification transistor AMI, the selection transistor SEL, and the reset transistor RST are all disposed between the photodiodes PD adjacent in the Y direction. The circuit configuration and the circuit configuration shown in FIG. 3 are the same. None of the transfer transistor TX, the amplification transistor AMI, the selection transistor SEL, and the reset transistor RST is arranged between the photodiodes PD adjacent in the X direction. FIG. 5 shows a layout example in the case of the circuit configuration of FIG.

  Specifically, the transfer transistor TX is arranged on one end side of both ends in the Y direction of the photodiode PD in plan view. The gate electrode GT of the transfer transistor TX extends in the X direction along the end (end side) of the photodiode PD, the gate length direction of the gate electrode GT is the Y direction, and the gate of the gate electrode GT The width direction is the X direction. Therefore, in a plan view, the photodiode PD is disposed on one of both sides of the gate electrode GT of the transfer transistor TX (both sides in the Y direction which is the gate length direction), and the floating diffusion FD is disposed on the other side. Has been.

  Two transfer transistors TX (corresponding to the transfer transistor TX1 and the transfer transistor TX2 in FIG. 2) are arranged between the photodiodes PD adjacent in the Y direction so as to share the floating diffusion FD.

  Further, a reset transistor RST is arranged at a position adjacent to the floating diffusion FD in the X direction between the photodiodes PD adjacent in the Y direction via the two transfer transistors TX. The reset transistor RST is sandwiched in the Y direction by the gate electrode GT of the transfer transistor TX extending in the X direction.

  Further, in plan view, the amplification transistor AMI and the selection transistor SEL are disposed on the opposite end side of the photodiode PD in the Y direction to the side on which the transfer transistor TX is disposed. . For this reason, the amplification transistor AMI and the selection transistor SEL are disposed between the photodiodes PD adjacent in the Y direction.

  Therefore, in the region between the photodiodes PD adjacent in the Y direction, two transfer transistors TX and one reset transistor RST are arranged, or an amplification transistor AMI and a selection transistor SEL are arranged. Will be. That is, in the column in which the photodiodes PD are arranged in the Y direction, a location where the two transfer transistors TX and the reset transistor RST are arranged between the photodiodes PD adjacent in the Y direction, the amplification transistor AMI, and the selection transistor SEL. Are arranged alternately in the Y direction.

  When viewed in the X direction, portions where two transfer transistors TX and one reset transistor RST are arranged between the photodiodes PD adjacent in the Y direction are arranged in the X direction. In addition, portions where the amplification transistor AMI and the selection transistor SEL are arranged between the photodiodes PD adjacent in the Y direction are arranged in the X direction.

  On the other hand, none of the transfer transistor TX, the amplification transistor AMI, the selection transistor SEL, and the reset transistor RST is arranged between the photodiodes PD adjacent in the X direction. For this reason, no transistor (MISFET) is arranged between the photodiodes PD adjacent in the X direction.

  As described above, in this embodiment, the transfer transistor TX, the amplification transistor AMI, the selection transistor SEL, and the reset transistor RST are connected to the region between the photodiodes PD adjacent in the Y direction and the photodiode PD adjacent in the X direction. Rather than being arranged separately from the area between them, it is arranged only in the area between the photodiodes PD adjacent in the Y direction.

For this reason, it is preferable that the interval P ₂ between the photodiodes PD adjacent in the Y direction is larger than the interval P ₁ between the photodiodes PD adjacent in the X direction (P ₂ > P ₁ ). In other words, it is preferable that the interval P ₁ between the photodiodes PD adjacent in the X direction is smaller than the interval P ₂ between the photodiodes PD adjacent in the Y direction (P ₂ > P ₁ ). The intervals P ₁ and P ₂ are shown in FIG. Since the interval P _{2 in the} Y direction is larger than the interval P _{1 in the} X direction (P ₂ > P ₁ ), it becomes easier to arrange the transistors between the photodiodes PD adjacent in the Y direction, and the interval in the Y direction. by having a smaller distance _{P 1} in the X direction _(P 2> _{P 1)} than P _2, it is possible to increase the number of pixels PU that can be placed in the pixel region 1A. When the number of pixels PU is the same, the area of the pixel region 1A can be reduced, so that the semiconductor device can be reduced in size (reduced area).

The distance P ₁ of the photodiode PD adjacent in the X direction corresponds to the spacing of the n-type semiconductor region NW below adjacent in the X direction, the interval P ₂ of the photodiode PD adjacent in the Y direction, Y-direction Corresponds to the interval between the n-type semiconductor regions NW, which will be described later.

In one example, the interval _{P 1} of the photodiode PD adjacent in the X direction, for example, can be about 0.5～0.9Myuemu, spacing _{P 2} of the photodiode PD adjacent in the Y direction, for example, 0 It can be set to about 9 to 1.6 μm.

  In the present embodiment, an element isolation region ST made of an insulator (insulating film) is formed between the photodiodes PD adjacent in the Y direction in plan view. On the other hand, no element isolation region ST made of an insulator (insulating film) is formed between the photodiodes PD adjacent in the X direction.

  In the plan view, the element isolation region ST is formed between the photodiodes PD adjacent in the Y direction because the transistors (TX, AMI, SEL, RST) are formed between the photodiodes PD adjacent in the Y direction. However, this is because the transistor needs to be formed in the active region defined by the element isolation region ST. Therefore, an element isolation region ST and an active region AC defined (enclosed) by the element isolation region ST are arranged between the photodiodes PD adjacent in the Y direction. Transistors (TX, AMI, SEL, RST) are formed. Specifically, in plan view, an element isolation region ST extends in the X direction between photodiodes PD adjacent in the Y direction, and an active region (AC for transistor formation) is formed in the element isolation region ST. ) Is formed.

  That is, between the photodiodes PD adjacent in the Y direction, the gate electrodes (GT, GE) constituting the transistors (TX, AMI, SEL, RST) are arranged on the active region AC defined by the element isolation region ST. Then, source / drain regions (semiconductor regions for source or drain) are formed on both sides of the gate electrode (GT, GE) in the active region AC. Therefore, each of the amplification transistor AMI, the selection transistor SEL, and the reset transistor RST includes a gate electrode GE formed on the active region AC via a gate insulating film, and a source / drain region formed in the active region. Is formed. Note that the photodiode PD and the floating diffusion FD are also formed in the active region AC.

  As can be seen from the circuit diagrams of FIGS. 2 and 3, one of the source and drain of the amplification transistor AMI and one of the source and drain of the selection transistor SEL are electrically connected. Therefore, the amplification transistor AMI and the selection transistor SEL can be formed in one active region (AC) surrounded by the element isolation region ST. In this case, one of the source / drain regions of the amplification transistor AMI The one of the source / drain regions of the selection transistor SEL can be constituted by a common semiconductor region. On the other hand, no other transistor is formed in the active region (AC) where the reset transistor RST is formed.

  In FIGS. 5 and 9, the gate electrode of the transfer transistor TX is shown as a gate electrode GT with reference symbol GT, and the gate electrodes of the amplification transistor AMI, the selection transistor SEL, and the reset transistor RST are indicated by reference symbol GE. It is shown as a gate electrode GE. 5 and 9, the gate length direction of the gate electrode GE is the X direction, and the gate width direction of the gate electrode GE is the Y direction.

  Although it is possible to form the element isolation region ST between the photodiodes PD adjacent in the X direction, in the present embodiment, the element isolation region ST is formed between the photodiodes PD adjacent in the X direction. Preferably not.

  It is possible not to form the element isolation region ST between the photodiodes PD adjacent in the X direction by not forming a transistor between the photodiodes PD adjacent in the X direction. That is, when a transistor is formed between photodiodes PD adjacent in the X direction, an element isolation region ST that defines an active region for forming the transistor is formed between photodiodes PD adjacent in the X direction. There is a need to. However, in the present embodiment, no transistor is formed between the photodiodes PD adjacent in the X direction, so that it is not necessary to form the element isolation region ST between the photodiodes PD adjacent in the X direction.

  In the present embodiment, not only the transistor is not disposed between the photodiodes PD adjacent in the X direction but also the element isolation region ST is not formed, thereby obtaining the following advantages.

That is, not only to place the transistors between the photodiode PD adjacent in the X direction, by not also form the element isolation region ST, it is possible to reduce the distance P ₁ of the photodiode PD adjacent in the X direction. For this reason, the number of pixels PU that can be arranged in the pixel region 1A can be further increased. Further, when the number of pixels PU is the same, the area of the pixel region 1A can be further reduced, so that the semiconductor device can be further reduced in size (area reduction).

  The element isolation region ST can be preferably formed by an STI (Shallow Trench Isolation) method, but it tends to cause stress and crystal defects in the substrate region adjacent to the element isolation region ST. If the element isolation region ST exists near the photodiode PD and stress or crystal defects are generated due to the element isolation region ST, noise may be caused. In contrast, in the present embodiment, the element isolation region ST is not provided between the photodiodes PD adjacent in the X direction, so that the element isolation region ST is also provided between the photodiodes PD adjacent in the X direction. Compared to the case where the device isolation region ST is present, the amount of the element isolation region ST existing at a position adjacent to the photodiode PD in plan view can be reduced. For this reason, the influence of the stress and crystal defect resulting from the element isolation region ST can be suppressed, and the generation of noise can be suppressed. Therefore, the performance of the semiconductor device can be improved.

Further, in the present embodiment, as shown in FIGS. 7 and 8, in the pixel region 1A, the p ⁺ type semiconductor region PR so as to surround each of the plurality of photodiodes PD arranged in an array in a plan view. Is provided. 7 and 8, the hatched region of the dot corresponds to the region where the p ⁺ type semiconductor region PR is formed. As can be seen from FIGS. 7 and 8, each photodiode PD is surrounded by the p ⁺ type semiconductor region PR in plan view. The p ⁺ type semiconductor region PR is provided to electrically isolate the photodiodes PD adjacent in the X direction or the Y direction.

Specifically, the p ⁺ type semiconductor region PR is formed in a lattice shape in plan view, and the photodiode PD is disposed inside the lattice. That is, the p ⁺ type semiconductor region PR extends in the X direction between a portion extending between the photodiodes PD adjacent in the X direction in the Y direction and between the photodiode PD adjacent in the Y direction in plan view. The p ⁺ type semiconductor region PR is configured by connecting them together. Since the element isolation region ST is also formed between the photodiodes PD adjacent in the Y direction as described above, a part of the p ⁺ type semiconductor region PR overlaps the element isolation region ST in plan view. That is, between the photodiodes PD adjacent in the Y direction, the p ⁺ type semiconductor region PR extends in the X direction under the element isolation region ST.

The p ⁺ type semiconductor region PR can function to suppress or prevent signal (charge) leakage (leakage current) between pixels PU adjacent in the X direction or the Y direction. For this reason, it is preferable to form the p ⁺ -type semiconductor region PR so that each photodiode PD is surrounded by the p ⁺ -type semiconductor region PR in plan view, whereby the pixel PU adjacent in the X direction or the Y direction is formed. Signal (charge) leakage (leakage current) between (photodiode PD) can be suppressed or prevented more accurately.

The width W ₂ of the p ⁺ type semiconductor region PR extending in the Y direction is preferably smaller than the width W _{3 of} the p ⁺ type semiconductor region PR extending in the X direction (W ₂ <W ₃ ). In other words, the width W ₃ of the p ⁺ type semiconductor region PR extending in the X direction may be larger than the width W _{2 of} the p ⁺ type semiconductor region PR extending in the Y direction (W ₂ <W ₃ ). preferable. The width W ₂ of the p ⁺ -type semiconductor region PR extending in the Y direction corresponds to the X dimension of the p ⁺ -type semiconductor region PR extending in the Y direction (width), shown in Figure 8 Yes. The width W ₃ of the p ⁺ -type semiconductor region PR extending in the X direction corresponds to the Y direction dimension of the p ⁺ -type semiconductor region PR extending in the X direction (width), shown in Figure 8 Yes. The width W ₂ is made smaller than the width W ₃ (W ₂ <W ₃ ), as described above, between the photodiodes PD adjacent in the X direction rather than the interval P ₂ between the photodiodes PD adjacent in the Y direction. Write interval _{P 1} is less _(P 1 _{<P 2)} in order.

As an example, the width W ₃ of the p ⁺ type semiconductor region PR extending in the Y direction can be set to, for example, about 0.6 to 1.2 μm, and the p ⁺ type semiconductor region PR extending in the X direction. the width _{W 2} of the may be, for example 0.3~0.6μm about.

  Here, the planar layout of the pixel region 1A described with reference to FIGS. 5 to 9 describes a preferred embodiment, the circuit configuration of the pixel PU can be changed, and the transistors configuring the pixel PU The layout can be changed. However, even when the circuit configuration of the pixel PU and the layout of the transistors constituting the pixel PU are changed, it is desirable to follow the technical idea described with reference to FIGS. For example, FIG. 5 shows a preferred example of the layout of the pixel transistors (TX, RST, SEL, AMI) in the case of following the circuit configuration of FIG. 2, but in the case of following the circuit configuration of FIG. , The number of pixel transistors arranged between the photodiodes PD adjacent in the Y direction is larger than in the case of FIGS.

<Structure of semiconductor device>
Next, the structure (cross-sectional structure) of the semiconductor device of the present embodiment will be described with reference to the plan views of FIGS. 5 to 9 and the cross-sectional views of FIGS.

  First, the structure (cross-sectional structure) in the pixel region 1A will be described.

On the semiconductor substrate SB constituting the semiconductor device of the present embodiment, a photodiode PD and a transfer transistor TX are formed in the pixel region 1A as shown in FIGS. The photodiode PD includes a p-type well PW1, an n-type semiconductor region NW, and a p ⁺ -type semiconductor region HP formed in the semiconductor substrate SB.

The semiconductor substrate SB is formed on the main surface of the substrate body (semiconductor substrate, semiconductor wafer) SB1 made of, for example, p-type single crystal silicon into which p-type impurities are introduced, and the substrate body SB1, for example, n ^A semiconductor layer (epitaxial layer, epitaxial semiconductor layer) EP made of -type single crystal silicon. The semiconductor layer EP is an epitaxial layer (epitaxial semiconductor layer), and is formed on the main surface of the substrate body SB1 by epitaxial growth. For this reason, the semiconductor substrate SB is a so-called epitaxial wafer. As another form, the substrate body SB1 may be n-type instead of p-type. As yet another form, the semiconductor substrate SB can be a semiconductor substrate (semiconductor wafer) made of n-type single crystal silicon into which an n-type impurity is introduced, instead of an epitaxial wafer.

  The p-type well (p-type semiconductor region) PW1 is formed from the main surface of the semiconductor substrate SB to a predetermined depth. The p-type well PW1 is formed over a region where the photodiode PD is formed and a region where the transfer transistor TX is formed. The p-type well PW1 is a p-type semiconductor region into which a p-type impurity such as boron (B) is introduced.

  As shown in FIGS. 10 to 12, in the semiconductor substrate SB, an n-type semiconductor region NW is formed so as to be included in the p-type well PW1. The n-type semiconductor region NW is an n-type semiconductor region into which an n-type impurity such as phosphorus (P) or arsenic (As) is introduced. The planar shape of the n-type semiconductor region NW is substantially rectangular.

  The n-type semiconductor region NW is an n-type semiconductor region for forming the photodiode PD, but the source region of the transfer transistor TX is also formed by the n-type semiconductor region NW. That is, the n-type semiconductor region NW is mainly formed in a region where the photodiode PD is formed, but a part of the n-type semiconductor region NW is planarly (planar) with the gate electrode GT of the transfer transistor TX. It is formed in the position where it overlaps (by visual observation). The depth of the n-type semiconductor region NW (bottom surface) is shallower than the depth of the p-type well PW1 (bottom surface), and the n-type semiconductor region NW is formed so as to be included in the p-type well PW1. The region shown as the photodiode PD in the plan views of FIGS. 5 to 9 corresponds to the region where the n-type semiconductor region NW is formed.

A p ⁺ type semiconductor region HP is formed on a part of the surface of the n type semiconductor region NW. p ⁺ -type semiconductor region HP is boron (B) is a p ⁺ -type semiconductor region p-type impurity is introduced at a high concentration (doping), such as the impurity concentration (p-type impurity concentration of the p ⁺ -type semiconductor region HP ) Is higher than the impurity concentration (p-type impurity concentration) of the p-type well PW1. For this reason, the conductivity (electric conductivity) of the p ⁺ type semiconductor region HP is higher than the conductivity (electric conductivity) of the p type well PW1.

The depth of the p ⁺ type semiconductor region HP (the bottom surface thereof) is shallower than the depth of the n type semiconductor region NW (the bottom surface thereof). The p ⁺ type semiconductor region HP is mainly formed in the surface layer portion (surface portion) of the n type semiconductor region NW. Therefore, when viewed in the thickness direction of the semiconductor substrate SB, the n-type semiconductor region NW exists under the uppermost p ⁺ -type semiconductor region HP, and the p-type well PW1 exists under the n-type semiconductor region NW. It becomes a state.

In the region where the n-type semiconductor region NW is not formed, a part of the p ⁺ -type semiconductor region HP is in contact with the p-type well PW1. That is, the p ⁺ type semiconductor region HP is a portion where the n-type semiconductor region NW exists immediately below and contacts the n-type semiconductor region NW, and a portion where the p-type well PW1 exists immediately below and contacts the p-type well PW1. And have.

A PN junction is formed between the p-type well PW1 and the n-type semiconductor region NW. Further, a PN junction is formed between the p ⁺ type semiconductor region HP and the n type semiconductor region NW. A photodiode (PN junction diode) PD is formed by the p-type well PW1 (p-type semiconductor region), the n-type semiconductor region NW, and the p ⁺ -type semiconductor region HP.

  The photodiode (PN junction diode) PD is mainly formed by the n-type semiconductor region NW and the p-type well PW1 (that is, by a PN junction between the n-type semiconductor region NW and the p-type well PW1).

The p ⁺ type semiconductor region HP is a region formed for the purpose of suppressing the generation of electrons based on the interface states that are formed in large numbers on the surface of the semiconductor substrate SB. That is, in the surface region of the semiconductor substrate SB, electrons are generated due to the influence of the interface state, which may cause an increase in dark current even when light is not irradiated. Therefore, by forming a p ⁺ type semiconductor region HP having holes as majority carriers on the surface of the n-type semiconductor region NW having electrons as majority carriers, electrons in a state where no light is irradiated. Can be suppressed, and an increase in dark current can be suppressed. Therefore, the p ⁺ type semiconductor region HP has a role of reducing the dark current by recombining electrons springing from the outermost surface of the photodiode with holes of the p ⁺ type semiconductor region HP.

  The photodiode PD is a light receiving element. The photodiode PD can also be regarded as a photoelectric conversion element. The photodiode PD has a function of photoelectrically converting input light to generate charges and storing the generated charges, and the transfer transistor TX transfers the charges accumulated in the photodiode PD from the photodiode PD. It has a role as a switch.

  Further, the gate electrode GT is formed so as to overlap a part of the n-type semiconductor region NW in plan view. The gate electrode GT is a gate electrode of the transfer transistor TX, and is formed (arranged) on the semiconductor substrate SB via the gate insulating film GF. A sidewall insulating film called a sidewall spacer may be formed on the sidewall of the gate electrode GT.

In the semiconductor substrate SB, the n-type semiconductor region NW is formed on one side of both sides (both sides in the gate length direction) of the gate electrode GT, and the n-type semiconductor region NR is formed on the other side. Is formed. The n-type semiconductor region NR is an n ⁺ -type semiconductor region into which n-type impurities such as phosphorus (P) or arsenic (As) are introduced (doped) at a high concentration. The n-type semiconductor region NR is a semiconductor region as a floating diffusion (floating diffusion layer) FD, and is also a drain region of the transfer transistor TX. The n-type semiconductor region NR can be formed in the p-type well PW1, but under the n-type semiconductor region NR, a p ⁺ -type semiconductor region PR (a portion of the p ⁺ -type semiconductor region PR extending in the X direction). Is extended.

  The n-type semiconductor region NR functions as a drain region of the transfer transistor TX, but can also be regarded as a floating diffusion (floating diffusion layer) FD. The n-type semiconductor region NW is a constituent element of the photodiode PD, but can also function as a semiconductor region for the source of the transfer transistor TX. That is, the source region of the transfer transistor TX is formed by the n-type semiconductor region NW. Therefore, the n-type semiconductor region NW and the gate electrode GT are in a positional relationship such that a part (source side) of the gate electrode GT overlaps a part of the n-type semiconductor region NW in plan view. preferable. The n-type semiconductor region NW and the n-type semiconductor region NR are formed so as to be separated from each other with a channel formation region (corresponding to a substrate region immediately below the gate electrode GT) of the transfer transistor TX interposed therebetween. Note that a gate insulating film GF is interposed between the gate electrode GT and the channel formation region of the transfer transistor TX.

A cap insulating film CP is formed on the surface of the photodiode PD, that is, on the surfaces of the n-type semiconductor region NW and the p ⁺ -type semiconductor region HP. The cap insulating film CP can function as a protective film, and can function to keep the surface characteristics of the semiconductor substrate SB, that is, the interface characteristics good. In addition, the cap insulating film CP may have a function as an antireflection film. A part (end part) of the cap insulating film CP can run over the gate electrode GT.

A p ⁺ type semiconductor region PR is formed in the semiconductor substrate SB. The p ⁺ type semiconductor region PR is a p type semiconductor region into which a p type impurity such as boron (B) is introduced at a high concentration. As shown in FIGS. 7 and 8, in plan view, the p ⁺ type semiconductor region PR extends between the photodiodes PD adjacent in the X direction in the Y direction, and is adjacent to the photo diodes adjacent in the Y direction. It extends in the X direction between the diodes PD. Therefore, in plan view, the p-type well PW1 is surrounded by ^{p +} -type semiconductor region PR, the ^{p +} -type semiconductor region p-type well PW1 surrounded by PR, and n-type semiconductor region NW is formed Yes. Accordingly, the n-type semiconductor region NW constituting the photodiode PD is surrounded by the p ⁺ -type semiconductor region PR in plan view.

Specifically, the p ⁺ -type semiconductor region PR is formed in a lattice shape in plan view, p-type well PW1 are partitioned by the lattice-shaped p ⁺ -type semiconductor region PR, p ⁺ -type semiconductor region An n-type semiconductor region NW is formed in the p-type well PW1 partitioned by PR. That is, the n-type semiconductor region NW is formed in the p-type well PW1 surrounded by the p ⁺ -type semiconductor region PR in plan view.

The p ⁺ type semiconductor region PR is formed to a position considerably deeper than the bottom surface (lower surface) of the n type semiconductor region NW, and is formed to a depth of about 2 to 4 μm, for example. That is, the bottom surface (lower surface) of the p ⁺ type semiconductor region PR is deeper than the bottom surface (lower surface) of the n type semiconductor region NW, for example, at a depth position of about 2 to 4 μm from the surface of the semiconductor substrate SB.

Further, the bottom surface (lower surface) of the p ⁺ type semiconductor region PR is at a position considerably deeper than the bottom surface (lower surface) of the element isolation region ST. That is, the p ⁺ type semiconductor region PR is formed to a position deeper than the element isolation region ST. The bottom surface (lower surface) of the element isolation region ST is, for example, at a depth position of about 0.1 to 0.4 μm from the surface of the semiconductor substrate SB, while the p ⁺ type semiconductor region PR is, for example, as described above In this way, the semiconductor substrate SB is formed to a depth of about 2 to 4 μm from the surface. Therefore, as can be seen from FIGS. 7, 10, 11, and 13, the p ⁺ type semiconductor region PR extending in the X direction extends below the element isolation region ST. That is, since the element isolation region ST is formed between the photodiodes PD adjacent in the Y direction, the p ⁺ type semiconductor region PR is between the photodiode PD adjacent in the Y direction. Extends in the X direction.

  Further, the position of the bottom surface (lower surface) of the n-type semiconductor region NW is, for example, at a depth position of about 0.25 to 0.5 μm from the surface of the semiconductor substrate SB. Further, the position of the bottom surface (lower surface) of the n-type semiconductor region NR is, for example, at a depth position of about 0.2 to 0.5 μm from the surface of the semiconductor substrate SB.

The p ⁺ type semiconductor region PR does not need to be formed from the surface of the semiconductor substrate SB, and the upper surface of the p ⁺ type semiconductor region PR may be separated from the surface of the semiconductor substrate SB by a predetermined distance. That is, the p ⁺ type semiconductor region PR can be formed avoiding the surface layer portion of the semiconductor substrate SB. For example, the position of the upper surface of the p ⁺ type semiconductor region PR can be set to a depth position comparable to the bottom surface (lower surface) of the element isolation region ST. For example, the position of the upper surface of the p ⁺ type semiconductor region PR can be set to a depth position of about 0.1 to 0.4 μm from the surface of the semiconductor substrate SB.

Also, in plan view, the p ⁺ type semiconductor region PR extending in the Y direction crosses the n type semiconductor region NR, but at the intersection of the p ⁺ type semiconductor region PR and the n type semiconductor region NR, the n type Under the semiconductor region NR, the p ⁺ type semiconductor region PR extends in the Y direction. In the case of FIG. 10, the p ⁺ type semiconductor region PR is in contact with the bottom surface (lower surface) of the n type semiconductor region NR, but the bottom surface (lower surface) of the n type semiconductor region NR is separated from the p ⁺ type semiconductor region PR. In this case, a part of the p-type well PW1 exists between the bottom surface (lower surface) of the n-type semiconductor region NR and the p ⁺ -type semiconductor region PR.

In addition, a p ⁺ type semiconductor layer (p ⁺ type semiconductor region) PW2 having a higher impurity concentration than the p type well PW1 is preferably formed below the p ⁺ type semiconductor region PR. The p ⁺ type semiconductor layer PW2 is a p type semiconductor region into which a p type impurity such as boron (B) is introduced at a high concentration. The p ⁺ type semiconductor layer PW2 is formed over the entire pixel region 1A and is located in the middle of the thickness of the semiconductor substrate SB. That is, the p ⁺ type semiconductor layer PW2 is formed at a position considerably deeper than the bottom surface (lower surface) of the n type semiconductor region NW, and the p type well is formed between the n type semiconductor region NW and the p ⁺ type semiconductor layer PW2. PW1 exists. For this reason, the bottom surface (lower surface) of the p-type well PW1 is adjacent to the upper surface of the p ⁺ -type semiconductor layer PW2.

The bottom of the p ⁺ type semiconductor region PR preferably reaches the p ⁺ type semiconductor layer PW2. Therefore, the n-type semiconductor region NW is formed in the p-type well PW1, and the p-type well PW1 has a bottom surface (lower surface) surrounded by the p ⁺ -type semiconductor layer PW2, and a side surface other than the surface layer portion is formed on the p ⁺ -type semiconductor. It is in a state surrounded by the region PR. That is, the n-type semiconductor region NW is formed in the p-type well PW1, the bottom surface (lower surface) of the p-type well PW1 is adjacent to the p ⁺ -type semiconductor layer PW2, and the p-type well of the side surface of the p-type well PW1. Portions other than the side surface of the surface layer portion of PW1 are adjacent to the p ⁺ type semiconductor region PR. That is, the n-type semiconductor region NW is formed in the p-type well PW1, and the p-type well PW1 is substantially surrounded by the high impurity concentration p ⁺ type semiconductor region PR and the p ⁺ type semiconductor layer PW2.

The impurity concentration of the p ⁺ type semiconductor region PR (p type impurity concentration) is higher than the impurity concentration of the p type well PW1 (p type impurity concentration), and the impurity concentration of the p ⁺ type semiconductor layer PW2 (p type impurity concentration). ) Is higher than the impurity concentration (p-type impurity concentration) of the p-type well PW1. In other words, the impurity concentration of the p-type well PW1 (p-type impurity concentration), ^{p +} -type impurity concentration of the semiconductor region PR (p-type impurity concentration) lower than, and the impurity concentration of the ^{p +} -type semiconductor layer PW2 (p Type impurity concentration). Therefore, the conductivity (electric conductivity) of the p ⁺ type semiconductor region PR is higher than the conductivity (electric conductivity) of the p type well PW1, and the conductivity (electric conductivity) of the p ⁺ type semiconductor layer PW2. ) Is higher than the conductivity (electric conductivity) of the p-type well PW1.

For example, an impurity concentration (p-type impurity concentration) of the ^{p +} -type semiconductor region PR is, 1 × ¹⁰ 17 ~1 × be a ¹⁰ 18 / cm ³ or so, the impurity concentration (p-type ^{p +} -type semiconductor layer PW2 The impurity concentration can be about 1 × 10 ¹⁷ to 1 × 10 ¹⁸ / cm ^3, and the impurity concentration (p-type impurity concentration) of the p-type well PW 1 is 1 × 10 ^{16 to} 5 × 10 ¹⁶ / cm. It can be about ³ .

Therefore, when viewed in plan, the p-type well PW1 and the n-type semiconductor region NW constituting a certain photodiode PD, and the p-type wells PW1 and n constituting the photodiode PD adjacent to the photodiode PD in the Y direction. Between the type semiconductor region NW, there are an element isolation region ST extending in the X direction and a p ⁺ type semiconductor region PR extending in the X direction below the element isolation region ST. The element isolation region ST and the p ⁺ type semiconductor region PR can suppress or prevent signal (charge) leakage (leakage current) between the photodiodes PD adjacent in the Y direction. Further, when viewed in plan, the p-type well PW1 and the n-type semiconductor region NW constituting a certain photodiode PD, and the p-type well PW1 and the n-type constituting the photodiode PD adjacent to the photodiode PD in the X direction. A p ⁺ type semiconductor region PR extending in the Y direction exists between the semiconductor region NW. This p ⁺ type semiconductor region PR can suppress or prevent signal (charge) leakage (leakage current) between photodiodes PD adjacent in the X direction. Furthermore, by providing the p ⁺ -type semiconductor layer PW2, signal (charge) leakage (leakage current) between the photodiodes PD adjacent in the X direction or the Y direction can be further suppressed or prevented. .

  Further, as shown in the plan views of FIGS. 5 and 9 and the cross-sectional views of FIGS. 10 to 13, the reset transistor RST and the amplification transistor AMI are arranged between the photodiodes PD adjacent in the Y direction in plan view. The selection transistor SEL is formed in the active region surrounded by the element isolation region ST.

  That is, in the active region for forming the reset transistor RST, as shown in FIG. 11, the gate electrode GE for the reset transistor RST is formed on the semiconductor substrate SB (p-type well PW3) via the gate insulating film GF. The source / drain regions SD for the reset transistor RST are formed in the semiconductor substrate SB (p-type well PW3) on both sides of the gate electrode GE. In the active region for forming the amplification transistor AMI and the selection transistor SEL, as shown in FIGS. 11 and 13, the amplification transistor AMI is formed on the semiconductor substrate SB (p-type well PW3) via the gate insulating film GF. A gate electrode GE for the selection transistor and a gate electrode GE for the selection transistor SEL are formed. Further, in the active region for forming the amplification transistor AMI and the selection transistor SEL, as shown in FIGS. 11 and 13, the amplification transistor AMI is provided in the semiconductor substrate SB (p-type well PW3) on both sides of the gate electrode GE. A source / drain region SD for the selection transistor and a source / drain region SD for the selection transistor SEL are formed. Since the selection transistor SEL and the amplification transistor AMI are connected in series, one of the source / drain regions SD is shared. A sidewall insulating film called a sidewall spacer may be formed on the sidewall of the gate electrode GE. The source / drain region SD is made of an n-type semiconductor region, but can also have an LDD (Lightly Doped Drain) structure.

The p-type well PW3 is formed in the active region semiconductor substrate SB for forming the reset transistor RST, the amplification transistor AMI, or the selection transistor SEL, and is surrounded by the element isolation region ST in plan view. . Further, the p ⁺ type semiconductor region PR may exist under the p type well PW3.

  In addition, a channel dope layer CD is formed in the channel formation region (corresponding to the substrate region immediately below the gate electrode GE) of the reset transistor RST, the amplification transistor AMI, and the selection transistor SEL. This channel dope layer CD is a region (semiconductor region) into which impurities are introduced (implanted) by ion implantation IM2 described later.

  Next, the structure (cross-sectional structure) of the peripheral circuit region 2A (see FIG. 4) of the semiconductor device of the present embodiment will be described with reference to FIG.

  As shown in FIG. 14, a peripheral transistor LT is formed on the semiconductor substrate SB in the peripheral circuit region 2A.

  That is, the p-type well PW4 is formed in the semiconductor substrate SB in the peripheral circuit region 2A, and the gate electrode GL of the peripheral transistor LT is formed on the p-type well PW4 via the gate insulating film GF. The source / drain regions SDL of the peripheral transistor LT are formed in the p-type well PW4 on both sides of the gate electrode GL. A sidewall insulating film called a sidewall spacer may be formed on the sidewall of the gate electrode GL. The source / drain region SDL is composed of an n-type semiconductor region, but may have an LDD structure.

  Actually, a plurality of n-channel MISFETs and a plurality of p-channel MISFETs are formed in the peripheral circuit region 2A as transistors constituting the logic circuit. FIG. One n-channel type MISFET of the constituting transistors is shown as a peripheral transistor LT.

The p-type wells PW1, PW3, PW4, n-type semiconductor region NR, n-type semiconductor region NW, p ⁺ type semiconductor region HP, p ⁺ type semiconductor region PR, p ⁺ type semiconductor layer PW2, channel dope described so far The layer CD and the source / drain regions SD and SDL are formed in the semiconductor substrate SB, and when the semiconductor substrate SB is an epitaxial wafer, it is formed in the semiconductor layer EP.

  Next, an interlayer insulating film and wiring formed on the semiconductor substrate SB will be described with reference to FIGS.

  As shown in FIG. 10 to FIG. 14, interlayer insulation is performed so as to cover the gate electrodes GT, GE, GL and the cap insulating film CP over the entire main surface of the semiconductor substrate SB including the pixel region 1A and the peripheral circuit region 2A. A film IL1 is formed. The interlayer insulating film IL1 is formed over the entire main surface of the semiconductor substrate SB.

  The interlayer insulating film IL1 is formed of, for example, a silicon oxide film using TEOS (Tetra Ethyl Ortho Silicate) as a raw material. A contact hole (through hole) is formed in the interlayer insulating film IL1, and a conductive plug PG is embedded in each contact hole. The plug PG is formed on, for example, the n-type semiconductor region NR, the source / drain regions SD and SDL, the gate electrodes GT, GE, and GL.

  A wiring M1 is formed on the interlayer insulating film IL1 in which the plug PG is embedded. The wiring M1 is a wiring in the first wiring layer. 10 to 13 show the case where the wiring M1 is formed by the damascene method, the wiring M1 is embedded in the wiring trench of the interlayer insulating film IL2 formed over the interlayer insulating film IL1. . In this case, the wiring M1 is, for example, a copper wiring (embedded copper wiring).

  On the interlayer insulating film IL2 on which the wiring M1 is formed, an interlayer insulating film IL3 made of, for example, a silicon oxide film is formed, and the wiring M2 is formed in the interlayer insulating film IL3. An interlayer insulating film IL4 made of, for example, a silicon oxide film is formed on the interlayer insulating film IL3 on which the wiring M2 is formed, and the wiring M3 is formed in the interlayer insulating film IL4. The wiring M2 is a wiring of the second wiring layer, and the wiring M3 is a wiring of the third wiring layer. The wirings M1, M2, and M3 are not limited to damascene wiring (embedded wiring), and can be formed by a method of patterning a conductive film formed on an interlayer insulating film, and for example, aluminum wiring can be used. Further, although the case where the number of wiring layers formed on the semiconductor substrate SB is three is shown and described, the number of wiring layers is not limited to three.

  The wirings M1, M2, and M3 are formed so as not to overlap the photodiode PD in plan view. This is to prevent light incident on the photodiode PD from being blocked by the wirings M1, M2, and M3.

  Further, in the pixel region 1A, a microlens (not shown) can be mounted on the interlayer insulating film IL4 in which the wiring M3 is formed. In addition, a color filter (not shown) can be provided between the microlens and the interlayer insulating film IL4.

  When light is applied to the pixel PU (see FIG. 1), first, incident light passes through a microlens (not shown), and then passes through interlayer insulating films IL4 to IL1 that are transparent to visible light. Thereafter, the light enters the cap insulating film CP. In the cap insulating film CP, reflection of incident light is suppressed, and a sufficient amount of incident light is incident on the photodiode PD. In the photodiode PD, since the energy of incident light is larger than the band gap of silicon, the incident light is absorbed by photoelectric conversion and a hole electron pair is generated. The electrons generated at this time are accumulated in the n-type semiconductor region NW. Then, the transfer transistor TX is turned on at an appropriate timing. Specifically, a voltage equal to or higher than the threshold voltage is applied to the gate electrode GT of the transfer transistor TX. Then, a channel region (inversion layer) is formed in the channel formation region immediately below the gate insulating film GF below the gate electrode GT of the transfer transistor TX, and the n-type semiconductor region NW as the source region of the transfer transistor TX and the transfer transistor The n-type semiconductor region NR as the drain region of TX is electrically connected. As a result, electrons accumulated in the n-type semiconductor region NW reach the drain region (n-type semiconductor region NR) through the channel region, and are amplified from the drain region (n-type semiconductor region NR) through the plug PG and wiring. Input to the gate electrode GE of the transistor AMI.

<Method for Manufacturing Semiconductor Device>
Next, a method for manufacturing the semiconductor device of the present embodiment will be described with reference to FIGS.

  15 to 52 are main part plan views or main part cross-sectional views during the manufacturing process of the semiconductor device of the present embodiment. 15, FIG. 24, FIG. 29, FIG. 30, FIG. 34, FIG. 35, FIG. 39, FIG. 44 are plan views, and a plan view of the region corresponding to FIG. Has been. 15 to 52, FIGS. 16, 20, 25, 31, 36, 40, 45, and 49 are sectional views corresponding to FIG. 10, that is, FIG. 5. It is sectional drawing in the position equivalent to an AA line. 15 to 52, FIGS. 17, 21, 26, 32, 37, 41, 46, and 50 are sectional views corresponding to FIG. 12, that is, FIG. It is sectional drawing in the position equivalent to CC line. 15 to 52, FIGS. 18, 22, 27, 33, 38, 42, 47, and 51 are cross-sectional views corresponding to FIG. 13, that is, FIG. It is sectional drawing in the position equivalent to DD line. 15 to 52, FIGS. 19, 23, 28, 43, 48, and 52 are cross-sectional views corresponding to FIG. 14, that is, a cross-sectional view of the peripheral circuit region 2A.

  In order to manufacture the semiconductor device of this embodiment, first, as shown in FIGS. 15 to 19, a semiconductor substrate (semiconductor wafer) SB is prepared (prepared).

The semiconductor substrate SB is formed on the main surface of the substrate body (semiconductor substrate, semiconductor wafer) SB1 made of, for example, p-type single crystal silicon into which p-type impurities are introduced, and the substrate body SB1, for example, n ^- it has a semiconductor layer EP consisting -type single crystal silicon, a. The semiconductor layer EP is an epitaxial layer, and is formed on the main surface of the substrate body SB1 by epitaxial growth. For this reason, the semiconductor substrate SB is a so-called epitaxial wafer. As another form, the substrate body SB1 may be n-type instead of p-type. As yet another form, the semiconductor substrate SB can be a semiconductor substrate (semiconductor wafer) made of n-type single crystal silicon into which an n-type impurity is introduced, instead of an epitaxial wafer.

  Next, an element isolation region ST made of an insulator (an insulator embedded in a trench) is formed on the main surface of the semiconductor substrate SB using, for example, an STI (Shallow Trench Isolation) method.

  That is, an element isolation groove (groove) is formed on the main surface of the semiconductor substrate SB by etching or the like, and then an insulating film made of silicon oxide (for example, ozone TEOS oxide film) is filled on the semiconductor substrate SB so as to fill the element isolation groove. To form. Then, the insulating film is polished using a CMP (Chemical Mechanical Polishing) method or the like to remove an unnecessary insulating film outside the element isolation groove, and the insulating film is formed in the element isolation groove. By leaving the element, the element isolation region ST made of an insulating film (insulator) that fills the element isolation trench can be formed. The active region of the semiconductor substrate SB is defined (defined) by the element isolation region ST. 15 to 19 show the stage where the element isolation region ST is formed.

  Although FIG. 15 is a plan view, the element isolation region ST is hatched in order to make the drawing easy to see. Further, in order to facilitate understanding of the formation position of the element isolation region ST, the photodiode formation scheduled region PDA is indicated by a dotted line. Here, the photodiode formation scheduled area PDA is an area in which the photodiode PD is to be formed later (more specifically, an area in which the n-type semiconductor area NW is to be formed later).

The element isolation region ST can also be formed by using a LOCOS (Local oxidation of silicon) method instead of the STI method. However, if the element isolation region ST is formed by the STI method, the distance P ₂ (see FIG. 5) between the photodiodes PD adjacent in the Y direction can be reduced as compared with the case where the LOCOS method is used. Can be obtained. As a result, the number of pixels (PU) that can be arranged in the pixel region 1A can be increased, and when the number of pixels (PU) is the same, the area of the pixel region 1A can be reduced. The apparatus can be reduced in size (reduced area). For this reason, the element isolation region ST is preferably formed by the STI method.

  When the element isolation region ST is formed, the element isolation region ST and an active region surrounded by the element isolation region ST (active for transistor formation) are formed between the photodiode formation scheduled regions PDA adjacent in the Y direction in plan view. Area) exists. On the other hand, the element isolation region ST is not formed between the photodiode formation scheduled regions PDA adjacent in the X direction in plan view.

Next, as shown in FIGS. 20 to 23, the p-type well (p-type semiconductor region) PW1 and the p ⁺ -type semiconductor layer (p ⁺ -type semiconductor region) are formed on the semiconductor substrate SB (semiconductor layer EP) in the pixel region 1A. PW2 is formed, and a p-type well (p-type semiconductor region) PW4 is formed in the semiconductor substrate SB (semiconductor layer EP) in the peripheral circuit region 2A.

  The p-type well PW1 is a p-type semiconductor region for forming the photodiode PD, and is also a p-type well region for forming the n-channel type transfer transistor TX. The p-type well PW4 is a p-type well region for forming the n-channel peripheral transistor LT.

The p-type well PW1, the p ⁺ -type semiconductor layer PW2, and the p-type well PW4 can be formed by ion-implanting a p-type impurity such as boron (B) into the semiconductor substrate SB, respectively.

The p-type well PW1 and the p-type well PW4 are each formed to a predetermined depth from the main surface of the semiconductor substrate SB, but the p ⁺ -type semiconductor layer PW2 is deeper than the main surface of the semiconductor substrate SB. That is, it is formed in the middle of the thickness of the semiconductor substrate SB. Therefore, the p ⁺ type semiconductor layer PW2 can also be regarded as a p ⁺ type buried layer. When the p-type well PW1 and the p ⁺ -type semiconductor layer PW2 are formed, the p ⁺ -type semiconductor layer PW2 is formed below the p-type well PW1 in the pixel region 1A, and the p-type well PW1 is formed above the p ⁺ -type semiconductor layer PW2. Will be formed.

At this stage, the p-type well PW1 is formed over the entire pixel region 1A. Since the p ⁺ type semiconductor region PR has not yet been formed, the p type well PW1 is not partitioned by the p ⁺ type semiconductor region PR.

  Further, the impurity concentration of the p-type well PW1 may not be uniform in the depth direction. For example, in the depth direction, it may have a concentration distribution in which the impurity concentration (p-type impurity concentration) decreases as the depth decreases.

FIG. 23 shows a case where the p ⁺ type semiconductor layer PW2 is not formed in the peripheral circuit region 2A. However, as another form, p ⁺ is not only applied to the pixel region 1A but also to the peripheral circuit region 2A. It is also possible to form the type semiconductor layer PW2. Also, the p-type well PW4 in the peripheral circuit region 2A can be formed by ion implantation common to the p-type well PW1, and in this case, the depth of the p-type well PW4 is equal to the depth of the p-type well PW1. It will be almost the same.

  Next, channel dope ion implantation for transistors (corresponding to the transfer transistor TX, amplification transistor AMI, selection transistor SEL, and reset transistor RST) formed in the pixel region 1A, and for the peripheral transistor LT formed in the peripheral circuit region 2A Channel dope ion implantation is performed. In channel dope ion implantation for transistors (TX, AMI, SEL, RST) formed in the pixel region 1A, n-type or p-type impurities are removed from the surface layer portion (more specifically, the pixel of the semiconductor substrate SB in the pixel region 1A). Ions are implanted into the surface layer portion of the active region for the transistor formed in the region 1A. In channel doping ion implantation for the peripheral transistor LT formed in the peripheral circuit region 2A, n-type or p-type impurities are formed on the surface layer portion of the semiconductor substrate SB in the peripheral circuit region 2A (more specifically, in the peripheral circuit region 2A). Ions are implanted into the surface layer portion of the active region for the peripheral transistor LT. At this time, since the transistors (TX, AMI, SEL, RST) formed in the pixel region 1A are n-channel transistors, the n-channel peripheral transistor LT formed in the peripheral circuit region 2A and the channel dope ion implantation are performed. Are preferably shared. That is, the channel dope ion implantation for the transistors (TX, AMI, SEL, RST) formed in the pixel region 1A and the channel dope ion implantation for the n-channel peripheral transistor LT formed in the peripheral circuit region 2A are the same. Preferably, it is performed by (common) ion implantation. That is, by the same (common) ion implantation, the surface layer portion of the semiconductor substrate SB in the active region for the transistors (TX, AMI, SEL, RST) formed in the pixel region 1A and the n-channel type formed in the peripheral circuit region 2A. Preferably, an n-type or p-type impurity is implanted into the surface layer portion of the semiconductor substrate SB in the active region for the peripheral transistor LT. Thereby, the number of manufacturing steps of the semiconductor device can be reduced.

  Next, as shown in FIGS. 24 to 28, a mask layer MK is formed on the main surface of the semiconductor substrate SB. The mask layer MK is made of a resist pattern such as a photoresist pattern. For example, a mask layer MK made of a photoresist pattern can be formed by forming a photoresist film on the main surface of the semiconductor substrate SB and then exposing and developing the photoresist film.

  24 to 28 show a stage where the mask layer MK is formed. Although FIG. 24 is a plan view, the mask layer MK is hatched in order to make the drawing easier to see, and the photodiode is scheduled to be formed in order to make the position of the mask layer MK easier to understand. Area PDA is indicated by a dotted line.

The mask layer MK has an opening OP that opens a region where the p ⁺ type semiconductor region PR is to be formed. That is, the planar layout of the opening OP of the mask layer MK substantially matches the planar layout of the p ⁺ type semiconductor region PR shown in FIGS.

  Specifically, the opening OP has a plurality of grooves TR1 extending in the X direction and a plurality of grooves TR2 extending in the Y direction, respectively. The plurality of grooves TR1 extending in the X direction and the plurality of grooves TR2 extending in the Y direction intersect with each other. By connecting these trenches TR1 and TR2, an opening OP is formed. That is, the openings OP are formed in a lattice shape in plan view. Each trench TR1 extends in the X direction between the photodiode formation scheduled areas PDA adjacent in the Y direction, and each trench TR2 extends in the Y direction between the photodiode formation scheduled areas PDA adjacent in the X direction. It is extended. As shown in FIG. 28, the entire peripheral circuit region 2A is covered with the mask layer MK.

The mask layer MK preferably has a sufficient thickness to function as an ion implantation blocking mask in ion implantation IM1 and IM2 described later. An ion implantation IM2, which will be described later, has a shallower implantation depth than an ion implantation IM1, which will be described later. For this reason, the thickness of the mask layer MK may be set so that impurity ions are not implanted into the semiconductor substrate SB in the region covered with the mask layer MK by the ion implantation IM1. That is, the mask layer MK is made thicker than the impurity ion implantation depth for the semiconductor substrate SB exposed from the opening OP in the ion implantation IM1. That is, the thickness of the mask layer MK is made larger than the depth (distance) from the surface of the semiconductor substrate SB to the bottom surface (lower surface) of the p ⁺ type semiconductor region PR formed by ion implantation IM1 described later. Therefore, the thickness of the mask layer MK is thus the height _{H 1} of the sidewalls of the trenches TR2 may be, for example 4~8μm about.

Further, in a plan view, the opening OP of the mask layer MK is consistent with the formation region of the p ⁺ -type semiconductor region PR, therefore, after performing the ion implantation IM1 is p ⁺ -type semiconductor region PR is formed Is almost the same as the marked area. Therefore, in plan view, the trench TR1 extending in the X direction substantially coincides with the region where the p ⁺ type semiconductor region PR extending in the X direction is formed, and the trench TR2 extending in the Y direction is Y The region substantially coincides with the region where the p ⁺ type semiconductor region PR extending in the direction is formed. Therefore, the width _{W 1} of the groove TR2 extending in the Y direction, substantially coincides with ^{p +} -type semiconductor region width _{W 2} of the PR extending in the Y direction shown in FIG. 8 _(W 1 _{= W} 2) , The width W ₄ of the trench TR1 extending in the X direction substantially coincides with the width W _{3 of} the p ⁺ type semiconductor region PR extending in the X direction shown in FIG. 8 (W ₃ = W ₄ ). . The width _{W 1} of the groove TR2 corresponds to the X direction of the grooves TR2 that Zanzai the Y direction width (dimension), is shown in FIGS. 24 and 26, the width _{W 4} of the groove TR1 is X This corresponds to the width (dimension) in the Y direction of the groove TR1 remaining in the direction, and is shown in FIGS. As described above, the width W ₂ of the p ⁺ type semiconductor region PR extending in the Y direction is smaller than the width W _{3 of} the p ⁺ type semiconductor region PR extending in the X direction (W ₂ <W ₃ ). Therefore preferably, the width _{W 1} of the groove TR2 extending in the Y direction is smaller than the width _{W 4} of the groove TR1 extending in the X direction _(W 1 _{<W 4)} is preferred.

Next, as shown in FIGS. 29 to 33, p ⁺ type impurities are ion-implanted into the semiconductor substrate SB using the mask layer MK as an ion implantation blocking mask, whereby p ^{+ is} implanted into the semiconductor substrate SB in the pixel region 1A. A type semiconductor region PR is formed. Hereinafter, the ion implantation for forming the p ⁺ type semiconductor region PR is referred to as ion implantation IM1. 31 to 33, the ion implantation IM1 is schematically shown by arrows. The direction of the arrow is the traveling direction (incident direction) of impurity ions (ion beam) and corresponds to the direction of ion implantation.

Note that FIG. 29 is a plan view, but in order to make the drawing easier to see, the hatched hatching similar to that of FIG. 24 is applied to the mask layer MK, and dot hatching is performed in the region where impurity ions are implanted by the ion implantation IM1. The photodiode formation scheduled area PDA is indicated by a dotted line. FIG. 30 is a plan view showing the same region as FIG. 29. In order to facilitate understanding of the positional relationship between the element isolation region ST and the p ⁺ type semiconductor region PR, FIG. 30 shows the element isolation region ST. The hatched area similar to FIG. 15 is shown with hatching, the area into which impurity ions are implanted by the ion implantation IM1 is shown with dot hatching, and the photodiode formation scheduled area PDA is shown with a dotted line It is.

  In the ion implantation IM1, ion implantation is performed so that p-type impurity ions are implanted into the semiconductor substrate SB exposed from the opening OP. That is, ion implantation is performed so that p-type impurity ions are implanted into the semiconductor substrate SB exposed from the trench TR1 and the semiconductor substrate SB exposed from the trench TR2.

  For this reason, in the ion implantation IM1, the direction of ion implantation is set so that p-type impurity ions are implanted into the semiconductor substrate SB exposed from the trench TR1 and the semiconductor substrate SB exposed from the trench TR2. Specifically, the ion implantation IM1 is vertical ion implantation.

  Note that the vertical ion implantation is ion implantation in which the direction of ion implantation is a direction substantially perpendicular to the main surface of the semiconductor substrate SB (that is, the normal direction of the main surface of the semiconductor substrate SB). In the vertical ion implantation, impurity ions are incident substantially perpendicular to the main surface of the semiconductor substrate SB. The direction of ion implantation corresponds to the direction in which impurity ions (ion beams) are incident on the main surface of the semiconductor substrate SB in the ion implantation.

Therefore, in the ion implantation IM1, p-type impurity ions can be implanted into the semiconductor substrate SB from both the trench TR1 and the trench TR2. That is, in the ion implantation IM1, impurity ions are not implanted into the region immediately below the mask layer MK in the semiconductor substrate SB, but impurity ions are implanted into a region overlapping the opening OP of the mask layer MK in plan view. . Thereby, the planar layout of the p ⁺ type semiconductor region PR is substantially the same as the planar layout of the opening OP of the mask layer MK. For this reason, in plan view, the p ⁺ type semiconductor region PR is formed in a lattice shape, and each photodiode formation planned region PDA is surrounded by the p ⁺ type semiconductor region PR. Therefore, a photodiode to be formed later The PD is also surrounded by the p ⁺ type semiconductor region PR in plan view.

Further, by forming the p ⁺ -type semiconductor region PR by ion implantation IM1, under the element isolation region ST extending between the photodiode forming region PDA adjacent in the Y direction in the X direction, the p ⁺ -type semiconductor region PR Will extend in the X direction. For this reason, between the photodiode formation scheduled areas PDA adjacent in the Y direction, the portion of the p-type well PW1 formed in the semiconductor substrate SB in the active region surrounded by the element isolation region ST is directly below it. A p ⁺ type semiconductor region PR will be formed. Here, a portion of the p-type well PW1 formed on the semiconductor substrate SB in the active region surrounded by the element isolation region ST between the photodiode formation scheduled regions PDA adjacent in the Y direction is defined as a p-type well. It will be referred to as PW3. Under the p-type well PW3 is a p ⁺ -type semiconductor region PR, and the p-type well PW3 is surrounded by an element isolation region ST in plan view. On the surface layer portion of the p-type well PW3, a channel dope layer CD is formed by ion implantation IM2 (described later) (see FIGS. 36 and 38 described later), and then a source / drain region SD is formed (described later). FIG. 51).

In the ion implantation IM1 for forming the p ⁺ type semiconductor region PR, it is preferable to perform ion implantation a plurality of times while changing the implantation energy. That is, the ion implantation IM1 for forming the p ⁺ type semiconductor region PR is preferably performed by so-called multistage ion implantation. In multi-stage ion implantation, a plurality of ion implantations having different implantation energies are performed on the same planar region. That is, in multi-stage ion implantation, ion implantation is performed a plurality of times in the same plane region, and the implantation energies of the plurality of ion implantations are different from each other.

Even when the ion implantation IM1 for forming the p ⁺ -type semiconductor region PR is performed by multistage ion implantation, the multiple ion implantation constituting the multistage ion implantation is vertical ion implantation without changing the ion implantation direction, In addition, the mask layer MK functions as an ion implantation blocking mask.

The p ⁺ type semiconductor region PR is preferably formed up to a considerably deep position of the semiconductor substrate SB. Therefore, rather than forming a p ⁺ -type semiconductor region PR with only a single ion implantation, who form a p ⁺ -type semiconductor region PR by multistage ion implantation, the p ⁺ type to a much deeper position of the semiconductor substrate SB The semiconductor region PR can be formed more accurately.

When the ion implantation IM1 is performed by multi-stage ion implantation, for example, the p ⁺ type semiconductor region PR can be formed by performing ion implantation with different implantation energy multiple times while changing the implantation energy from about 100 keV to about 2000 keV. .

  When performing the ion implantation IM1, as shown in FIG. 28, since the entire peripheral circuit region 2A is covered with the mask layer MK, impurities are implanted (ion ions) into the semiconductor substrate SB in the peripheral circuit region 2A. Not injected).

  Next, as shown in FIGS. 34 to 38, ion implantation IM2 is performed on the semiconductor substrate SB using the mask layer MK as an ion implantation blocking mask. In this ion implantation IM2, an impurity having a conductivity type opposite to that of the impurity implanted in the ion implantation IM1 is ion implanted into the semiconductor substrate SB. That is, in the ion implantation IM2, n-type impurities are ion-implanted.

  36 to 38, the ion implantation IM2 is schematically shown by arrows. The direction of the arrow is the traveling direction (incident direction) of impurity ions (ion beam) and corresponds to the direction of ion implantation. The ion implantation IM2 is oblique ion implantation. Further, the implantation depth in the ion implantation IM2 is shallower than the implantation depth in the ion implantation IM1.

  Note that FIG. 34 is a plan view, but in order to make the drawing easier to see, the mask layer MK is hatched in the same manner as in FIG. 24 and dots are hatched in the region where impurity ions are implanted by the ion implantation IM2. The photodiode formation scheduled area PDA is indicated by a dotted line. FIG. 35 is a plan view showing the same region as that in FIG. 34. The element isolation region ST is hatched in the same manner as in FIG. 15 and impurity ions are implanted by ion implantation IM2. The region to be processed is indicated by dot hatching, and the photodiode formation scheduled region PDA is indicated by a dotted line.

  Further, when ion implantation IM2 is performed, as shown in FIG. 28, since the entire peripheral circuit region 2A is covered with the mask layer MK, impurities are implanted into the semiconductor substrate SB in the peripheral circuit region 2A (ion ions). Not injected).

  In the ion implantation IM2, the ion implantation angle is set so that the impurity ions are not incident substantially perpendicular to the main surface of the semiconductor substrate SB but are incident in an oblique direction. That is, the ion implantation IM1 is oblique ion implantation.

  The oblique ion implantation refers to ion implantation in which the direction of ion implantation is a direction inclined from the normal direction of the main surface of the semiconductor substrate SB. In the oblique ion implantation, impurity ions are incident at an oblique incident angle that is not substantially perpendicular to the main surface of the semiconductor substrate SB. The direction of ion implantation corresponds to the direction in which impurity ions (ion beams) are incident on the main surface of the semiconductor substrate SB in the ion implantation.

  In the ion implantation IM1, on the main surface of the semiconductor substrate SB, with respect to a region between the photodiode formation scheduled regions PDA adjacent in the Y direction and a region between the photodiode formation scheduled regions PDA adjacent in the X direction. , P-type impurities are ion-implanted. On the other hand, in the ion implantation IM2, ions are implanted into the region between the photodiode formation scheduled areas PDA adjacent in the Y direction on the main surface of the semiconductor substrate SB, but adjacent photodiodes in the X direction are formed. Ions are not implanted into the region between the planned regions PDA.

  Specifically, in the ion implantation IM1, since vertical ion implantation is applied, impurity ions are implanted into the semiconductor substrate SB from both the trench TR1 extending in the X direction and the trench TR2 extending in the Y direction. Therefore, the planar region into which the impurity has been implanted substantially coincides with the opening OP in plan view. On the other hand, in the ion implantation IM2, oblique ion implantation is applied, and impurity ions are implanted into the semiconductor substrate SB from the trench TR1 extending in the X direction, but from the trench TR2 excluding a portion intersecting with the trench TR1. The impurity ions are prevented from being implanted into the semiconductor substrate SB by being shielded by the mask layer MK.

  For this reason, in the ion implantation IM2, impurity ions are implanted into the semiconductor substrate SB exposed from the trench TR1, but the semiconductor substrate exposed from the trench TR2 except for the intersection of the trench TR1 and the trench TR2. For SB, the direction of ion implantation is set so that impurity ions are not implanted by being shielded by mask layer MK.

  Specifically, in the ion implantation IM2, the semiconductor substrate SB exposed from the trench TR1 extending in the X direction is ion-implanted so that impurity ions can be implanted without being shielded by the mask layer MK. The direction is a direction parallel to a plane parallel to both the normal direction of the main surface of the semiconductor substrate SB and the X direction. From another viewpoint, the direction of ion implantation is set in a direction parallel to the plane parallel to the X direction and orthogonal to the main surface of the semiconductor substrate SB. Thereby, even if the ion implantation IM2 is oblique ion implantation, impurity ions can be implanted into the semiconductor substrate SB at the bottom of the trench TR1 extending in the X direction.

In order to prevent impurity ions from being implanted into the semiconductor substrate SB exposed from the trench TR2 except for the portion intersecting the trench TR1, tan θ> W ₁ / What is necessary is just to set the inclination angle (tilt angle) θ of ion implantation in the ion implantation IM2 so that H ₁ is established. Thereby, impurity ions can be prevented from being implanted into the semiconductor substrate SB at the bottom of the trench TR2 except for the intersection between the trench TR1 and the trench TR2.

Therefore, for the ion implantation IM2, oblique ion implantation is used, and the direction of ion implantation is set to a direction parallel to a plane parallel to both the normal direction of the main surface of the semiconductor substrate SB and the X direction. It is desirable to set the inclination angle θ of the ion implantation in the ion implantation IM2 so that tan θ> W ₁ / H ₁ is satisfied.

Here, H ₁ is that the height of the side wall of the trench TR2, is shown in Figure 37. The height H ₁ of the side walls of the groove TR2 is consistent with the thickness of the mask layer MK at a position adjacent to the groove TR2. W ₁ is the width W ₁ of the trench TR2 and corresponds to the width (dimension) in the X direction of the trench TR2 extending in the Y direction, which is shown in FIGS. 24, 26, and 37 above. Has been. In addition, θ is an inclination angle θ of ion implantation in the ion implantation IM2, and corresponds to an inclination angle of the direction of ion implantation with respect to the normal direction of the main surface of the semiconductor substrate SB, which is shown in FIG. Yes. That is, in the ion implantation IM2, the angle (intersection angle) formed by the direction of ion implantation (incidence direction of impurity ions or ion beam) and the normal direction of the main surface of the semiconductor substrate SB is the tilt angle θ. The tilt angle θ is also referred to as a tilt angle.

In the ion implantation IM2, if the incident angle of impurity ions (ion beam) with respect to the main surface of the semiconductor substrate SB is close to vertical (that is, if the tilt angle θ is sufficiently small), even at the bottom of the trench TR2 extending in the Y direction, Impurity ions are implanted without being shielded by the mask layer MK. On the other hand, in the ion implantation IM2, if the incident angle of the impurity ions (ion beam) with respect to the main surface of the semiconductor substrate SB is sufficiently small (that is, if the inclination angle θ is sufficiently large), except for the intersection of the trench TR1 and the trench TR2. At the bottom of the trench TR2, impurity ions are not implanted by being shielded by the mask layer MK. When the inclination angle of the ion implantation IM2 is θ, the incident angle of impurity ions (ion beam) with respect to the main surface of the semiconductor substrate SB in the ion implantation IM2 is represented by 90 ° −θ. For this reason, when the inclination angle θ of the ion implantation in the ion implantation IM2 is set so that tan (90 ° −θ) ≧ H ₁ / W ₁ , the trench TR2 is formed at a portion other than the intersection of the trench TR1 and the trench TR2. Impurities are implanted into at least a part of the bottom semiconductor substrate SB. On the other hand, if the inclination angle θ of the ion implantation IM2 is set so that tan (90 ° −θ) <H ₁ / W ₁ holds, the semiconductor is formed at the bottom of the trench TR2 except for the intersection of the trench TR1 and the trench TR2. Impurities can be prevented from being implanted into the substrate SB. Here, since tan (90 ° −θ) = 1 / tanθ, tan (90 ° −θ) <H ₁ / W ₁ is equivalent to tanθ> W ₁ / H ₁ . Therefore, if the inclination angle θ of the ion implantation IM2 is set so that tan θ> W ₁ / H ₁ is satisfied, impurities are not implanted into the semiconductor substrate SB at the bottom of the trench TR2, except for the intersection of the trench TR1 and the trench TR2. Can be.

Although the p ⁺ type semiconductor region PR is formed by the ion implantation IM1, since it is desirable to form the p ⁺ type semiconductor region PR up to a considerably deep position in the semiconductor substrate SB, the thickness of the mask layer MK is inevitably increased. Thus the height _{H 1} of the sidewall of the trench TR2 increases. Further, in order to reduce the area of several to or increase or pixel region 1A, the pixel PU to be formed in the pixel region 1A, it is necessary to reduce the width W ₂ of the p ⁺ -type semiconductor region PR Therefore, it is desirable to somewhat smaller width _{W 1} of the groove TR2. Therefore, since the value of W ₁ / H ₁ can be reduced to some extent, the ion implantation IM 2 can be performed so that tan θ> W ₁ / H ₁ is satisfied without increasing the inclination angle θ.

If the inclination angle θ is excessively increased, ion implantation is performed on the semiconductor substrate SB between the photodiode formation scheduled areas PDA adjacent in the Y direction even in the outermost peripheral pixel PU of the plurality of pixels PU arranged in an array. In order to be able to implant impurity ions with IM2, the position of the end of the trench TR2 needs to be separated from the photodiode formation planned area PDA. However, this leads to providing a margin (a region where a peripheral circuit cannot be formed) around the pixel region 1A, which is disadvantageous for downsizing (smaller area) of the semiconductor device. From this viewpoint, it is desirable that the inclination angle θ of the ion implantation IM2 is not too large as long as tan θ> W ₁ / H ₁ is satisfied. For example, the inclination angle θ is preferably 30 ° or less (θ ≦ 30 °). Further, if the inclination angle θ of the ion implantation IM2 is 30 ° or less (θ ≦ 30 °), the ion implantation IM2 can be performed easily and accurately using a general ion implantation apparatus.

Further, the ion implantation IM2 can be performed by one ion implantation, whereby the time required for the ion implantation IM2 can be shortened and the throughput of the semiconductor device can be improved. As another form, ion implantation IM2 can also be performed by multiple times of ion implantation. In that case, there may be a case where the ion implantation directions are made the same or different in a plurality of ion implantations constituting the ion implantation IM2. When different ion implantation directions are used by multiple ion implantations, oblique ion implantation is used in each ion implantation, and the ion implantation direction is set to both the normal direction of the main surface of the semiconductor substrate SB and the X direction. A parallel plane is set to a parallel direction, and tan θ> W ₁ / H ₁ is established.

  In FIG. 34 and FIG. 35, the region where the impurity ions are implanted by the ion implantation IM2 is shown by dot hatching. As shown in FIGS. 34 and 35, the planar region into which the impurity is implanted by the ion implantation IM2 is substantially coincident with the trench TR1 extending in the X direction in a plan view. However, in the ion implantation IM2, impurity ions are not implanted into the semiconductor substrate SB at a position overlapping the trench TR2 in a plan view except for the intersection of the trench TR1 and the trench T2.

  For this reason, at a position overlapping the trench TR1 extending in the X direction in plan view, impurity ions are implanted into the semiconductor substrate SB (including the element isolation region ST) by the ion implantation IM1, and also in the ion implantation IM2. Impurity ions are implanted. On the other hand, impurity ions are implanted into the semiconductor substrate SB by the ion implantation IM1 at a position overlapping the trench TR2 in plan view except for the intersection of the trench TR1 and the trench TR2, but the impurity ions are implanted in the ion implantation IM2. Not.

The ion implantation IM1 is performed to form the p ⁺ type semiconductor region PR. For this reason, in the ion implantation IM1, a p-type impurity is ion-implanted.

  On the other hand, the ion implantation IM2 is an impurity in a transistor to be formed later between the photodiode formation scheduled areas PDA adjacent in the Y direction, specifically, in the channel formation area of the amplification transistor AMI, the selection transistor SEL, and the reset transistor RST. This is done to adjust the density. For this reason, the ion implantation IM2 has a function as channel doping ion implantation of a transistor formed between the photodiodes PD adjacent in the Y direction. By adjusting the impurity concentration in the channel formation region of the amplification transistor AMI, the selection transistor SEL, and the reset transistor RST by the ion implantation IM2, the threshold voltages of the transistors AMI, SEL, RST are controlled to desired values. be able to.

  In the ion implantation IM2, it is desirable to ion-implant n-type impurities. This is because, in the ion implantation IM1, p-type impurities are ion-implanted, and the p-type impurities are also applied to the surface layer portion of the semiconductor substrate SB in the active region for forming the amplification transistor AMI, the selection transistor SEL, and the reset transistor RST. This is because it is injected. If p-type impurities are implanted into the surface layer portion of the semiconductor substrate SB in the active region where the amplification transistor AMI, the selection transistor SEL, and the reset transistor RST are formed by the ion implantation IM1, channel formation of the transistors AMI, SEL, and RST is performed. There is a possibility that the p-type impurity concentration in the region becomes excessive, and the threshold voltages of these transistors AMI, SEL, and RST are shifted from desired values.

  Therefore, the p-type impurity implanted during the ion implantation IM1 into the surface layer portion of the semiconductor substrate SB in the active region that forms the amplification transistor AMI, the selection transistor SEL, and the reset transistor RST, and the n-type impurity by the ion implantation IM2. Compensation can be achieved by ion implantation. Since the amount of the n-type impurity implanted by the ion implantation IM2 can be adjusted to a desired value, the ion implantation IM2 conditions (implantation energy, dose, number of times of ion implantation, etc.) are taken into consideration. Injection energy, dose, etc.) can be set. Thereby, the impurity concentration in the channel formation region of the amplification transistor AMI, the selection transistor SEL, and the reset transistor RST can be controlled to a desired value (optimum value), and the threshold values of these transistors AMI, SEL, RST can be controlled. The voltage can be controlled to a desired value (optimum value).

Note that the trenches TR1 and TR2 are designed so that the channel formation region of the transfer transistor TX to be formed later is covered with the mask layer MK without overlapping the trenches TR1 and TR2 in plan view. This is because the p ⁺ type semiconductor region PR is formed so as to be separated from the channel formation region of the transfer transistor TX to some extent so as not to overlap the channel formation region of the transfer transistor TX in plan view. For this reason, the ion implantation IM1 hardly affects the impurity concentration in the channel formation region of the transfer transistor TX. For this reason, no impurity is implanted into the channel formation region of the transfer transistor TX to be formed later by either the ion implantation IM1 or the ion implantation IM2. However, since the p-type impurity is not implanted by the ion implantation IM1, the ion implantation IM2 Thus, the problem does not easily occur even if n-type impurities are not implanted.

On the other hand, the channel formation region of the amplification transistor AMI, the selection transistor SEL, and the reset transistor RST, which will be formed later, overlaps with the trench TR1 in plan view and is not covered with the mask layer MK. If the trenches TR1 and TR2 are designed so that the channel formation regions of the amplification transistor AMI, the selection transistor SEL, and the reset transistor RST to be formed later are covered with the mask layer MK, the photodiode PD adjacent in the Y direction is formed. It is necessary to increase the interval P ₂ (see FIG. 5). However, increasing the distance P ₂ of the photodiode PD adjacent in the Y direction, reduces the number of pixels (PU) that can be placed in the pixel region 1A, also when the number of pixels (PU) is the same, This leads to an increase in the area of the pixel region 1A. For this reason, channel formation regions of the amplification transistor AMI, the selection transistor SEL, and the reset transistor RST that are formed later overlap with the trench TR1 in plan view. Accordingly, n-type impurities are implanted into the channel formation regions of the amplification transistor AMI, the selection transistor SEL, and the reset transistor RST to be formed later by the ion implantation IM2 because the p-type impurities are implanted by the ion implantation IM1. It is necessary to compensate the p-type impurity and adjust the impurity concentration.

  In the present embodiment, in the ion implantation IM2, impurity ions are prevented from being implanted into the semiconductor substrate SB at a position overlapping the trench TR2 excluding the intersection of the trench TR1 and the trench TR2 in plan view. That is, impurities are not implanted into the region between the photodiode formation scheduled regions PDA adjacent in the X direction by the ion implantation IM2. The reason is to suppress or prevent leakage between photodiodes PD (n-type semiconductor regions NW) adjacent in the X direction as much as possible.

That is, unlike the present embodiment, in the ion implantation IM2, impurity ions are implanted into the semiconductor substrate SB at a position overlapping with the trench TR2 in plan view, whereby the photodiode formation scheduled region PDA adjacent in the X direction is formed. It is assumed that an impurity is implanted into the region between by ion implantation IM2. However, in this case, there is a risk of increasing leakage between photodiodes PD (n-type semiconductor regions NW) adjacent in the X direction. That is, the p-type semiconductor regions (p-type well PW1 and p ⁺ -type semiconductor region PR) are interposed between the n-type semiconductor regions NW constituting the photodiode PD adjacent in the X direction. If an n-type impurity is implanted by ion implantation IM2 between the photodiodes PD (n-type semiconductor regions NW) adjacent in the X direction, the n-type semiconductor regions NW constituting the photodiode PD adjacent in the X direction. It becomes easy to leak between each other. That is, an n-type region (n-type layer) is formed between the n-type semiconductor regions NW adjacent in the X direction, and there is a possibility that leakage may easily occur through the n-type region. For this reason, it is desirable to prevent the n-type impurity from being implanted as much as possible between the photodiodes PD (n-type semiconductor regions NW) adjacent in the X direction.

On the other hand, in the present embodiment, in the ion implantation IM2, impurity ions are prevented from being implanted into the semiconductor substrate SB at a position overlapping with the trench TR2 excluding the intersection of the trench TR1 and the trench TR2 in plan view. . For this reason, the impurity does not need to be implanted by the ion implantation IM2 in the region between the photodiode formation scheduled regions PDA adjacent in the X direction. This prevents an n-type impurity having a conductivity type opposite to that of the p-type well PW1 or the p ⁺ -type semiconductor region PR from being introduced between the photodiodes PD (n-type semiconductor regions NW) adjacent in the X direction. Therefore, leakage between photodiodes PD (n-type semiconductor regions NW) adjacent in the X direction can be suppressed or prevented.

On the other hand, not only the p ⁺ type semiconductor region PR but also the element isolation region ST is formed between the photodiode formation scheduled regions PDA adjacent in the Y direction. For this reason, even if an n-type impurity is implanted between the photodiode formation scheduled areas PDA adjacent in the Y direction by the ion implantation IM2, leakage to the photodiodes PD (n-type semiconductor areas NW) adjacent in the X direction is prevented. The impact is minimal.

Further, the p ⁺ type semiconductor region PR can be formed apart from the main surface of the semiconductor substrate SB to some extent (for example, about the depth of the element isolation region ST). However, in the ion implantation IM1, there may occur a phenomenon in which the impurity ions that have come in collide with the sidewalls of the trenches TR1 and TR2 before entering the semiconductor substrate SB to attenuate energy and then enter the semiconductor substrate SB. In this case, the impurity ions whose energy is attenuated remain in a shallow position of the semiconductor substrate SB, and act to increase the p-type impurity concentration in the channel formation region. In addition, if the ion implantation IM1 is performed by multistage ion implantation, the frequency of occurrence of this phenomenon increases as the number of ion implantations increases, and the p-type impurity concentration in the channel formation region increases further. In addition, it is desirable to form the p ⁺ type semiconductor region PR up to a considerably deep position of the semiconductor substrate SB. In this case, the mask layer MK is thick so that the mask layer MK can function as an ion implantation blocking mask. This leads to an increase in the height of the side walls of the trenches TR1 and TR2 of the mask layer MK. When the height of the sidewalls of the trenches TR1 and TR2 of the mask layer MK increases, the ion ions IM1 impinge on the sidewalls of the trenches TR1 and TR2 before the incident impurity ions enter the semiconductor substrate SB to attenuate energy. Thereafter, the frequency of occurrence of a phenomenon incident on the semiconductor substrate SB increases. For this reason, the p-type impurity concentration in the channel formation region is further increased.

  On the other hand, in the present embodiment, the p-type implanted into the surface layer portion of the semiconductor substrate SB by the ion implantation IM1 by ion-implanting the n-type impurity by the ion implantation IM2 in the region overlapping the trench TR1 in plan view. Impurities can be compensated, and the impurity concentration of the surface layer portion of the semiconductor substrate SB can be controlled. Thereby, the impurity concentration in the channel formation region of the transistor (AMI, SEL, RST) formed later in the region overlapping with the trench TR1 in plan view can be controlled to a desired value (optimum value). The threshold voltage (AMI, SEL, RST) can be controlled to a desired value (optimum value).

  On the other hand, in a plan view, since a transistor is not formed in the region between the photodiode formation scheduled regions PDA adjacent to the X direction, even if the p-type impurity is implanted into the surface layer portion of the semiconductor substrate SB by the ion implantation IM1, There is no problem.

  36 and 38, a region (semiconductor region) into which impurities are introduced (implanted) by ion implantation IM2 in the semiconductor substrate SB is shown as a channel dope layer CD. In the ion implantation IM2, in the region overlapping the trench TR1 in plan view, impurity ions can be implanted in the semiconductor substrate SB or the element isolation region ST. Therefore, the impurity is also implanted by the ion implantation IM2 into the surface layer portion of the element isolation region ST exposed from the trench TR1.

  37 shows a cross section that crosses the trench TR2 instead of the trench TR1, the channel dope layer CD is not formed in the cross section of FIG. That is, the channel dope layer CD is not formed on the portion of the semiconductor substrate SB exposed from the trench TR2 except for the intersection between the trench TR1 and the trench TR2.

  As shown in FIGS. 36 and 38, the channel dope layer CD is formed in the surface layer portion of the semiconductor substrate SB exposed from the trench TR1. The depth of the channel dope layer CD is preferably shallower than the depth of the element isolation region ST. That is, the bottom surface (lower surface) of the channel dope layer CD is preferably shallower than the bottom surface (lower surface) of the element isolation region ST. In other words, the bottom surface (lower surface) of the element isolation region ST is preferably deeper than the bottom surface (lower surface) of the channel dope layer CD. Therefore, it is preferable that the impurity ion implantation depth in the ion implantation IM2 is shallower than the element isolation region ST. Thus, when ion implantation IM2 is performed, n-type impurity ions do not need to be implanted deeper than the bottom surface (lower surface) of element isolation region ST. , It is possible to prevent leakage between the photodiodes PD adjacent in the Y direction.

Further, the implantation depth in the ion implantation IM2 is shallower than the implantation depth in the ion implantation IM1. That is, in the semiconductor substrate SB, the depth at which the impurity ions are implanted by the ion implantation IM2 is shallower than the depth at which the impurity ions are implanted by the ion implantation IM1. That is, the p ⁺ type semiconductor region PR is formed to a position that is considerably deeper than the bottom surface (lower surface) of the channel dope layer CD. For this reason, although depending on the type of impurity ions to be implanted, the implantation energy of the ion implantation IM2 can be made smaller than the implantation energy of the ion implantation IM2.

The reason why the implantation depth in the ion implantation IM2 is shallower than the implantation depth in the ion implantation IM1 is to compensate for the p-type impurity implanted in the ion implantation IM1 with the n-type impurity implanted in the ion implantation IM2. This is because the surface layer portion of the semiconductor substrate SB can function as a channel formation region of the transistor. If n-type impurity ions are implanted to a deep position by the ion implantation IM2, the impurity concentration of the p ⁺ type semiconductor region PR formed in a region overlapping the trench TR1 in plan view may be lowered by the ion implantation IM2. There is a possibility that the function of the p ⁺ type semiconductor region PR may be deteriorated. For this reason, in the ion implantation IM2, the implantation depth is set shallow.

  In the present embodiment, ion implantation IM1 and ion implantation IM2 are performed using the same (common) mask layer MK as an ion implantation blocking mask. For this reason, compared with the case where ion implantation IM1 and ion implantation IM2 are performed using separate mask layers (photoresist patterns) as ion implantation blocking masks, the number of steps for forming the mask layer (photoresist pattern) can be reduced. The number of manufacturing steps of the device can be reduced. That is, it is possible to reduce the photoresist layer coating process, the exposure process, the developing process, and the photoresist layer removing process. Thereby, the manufacturing time of the semiconductor device can be shortened. In addition, the manufacturing cost of the semiconductor device can be reduced. In addition, the throughput of the semiconductor device can be improved.

  Further, it is desirable to reduce the photoresist pattern forming process and the subsequent removing process as much as possible because the semiconductor substrate SB may be scraped or contaminated. In addition, when a light receiving element (photoelectric conversion element) such as a photodiode PD is formed on the semiconductor substrate SB, the surface state of the semiconductor substrate SB tends to affect the characteristics. It is desirable to reduce the number of processes as much as possible to prevent the semiconductor substrate SB from being scraped or contaminated. Therefore, as in the present embodiment, the ion implantation IM1 and the ion implantation IM2 are performed using the same (common) mask layer MK, thereby reducing the photoresist pattern forming process and the subsequent removal process. Therefore, it is possible to suppress or prevent the semiconductor substrate SB from being scraped or contaminated due to the photoresist pattern forming process and the subsequent removing process. Thereby, the manufacturing yield of the semiconductor device can be improved. In addition, the reliability of the semiconductor device can be improved. In addition, the performance of the semiconductor device can be improved.

  In the present embodiment, after the mask layer MK is formed, the ion implantation IM1 is performed first, and then the ion implantation IM2 is performed. As another form, after the mask layer MK is formed, the ion implantation IM2 can be performed first, and then the ion implantation IM1 can be performed. In addition, when the ion implantation IM1 is performed by multistage ion implantation, the ion implantation IM2 can be performed during the multistage ion implantation. In any case, the ion implantation IM1 and the ion implantation IM2 are performed using the same mask layer MK. However, since the ion implantation IM1 and the ion implantation IM2 are different in ion species to be implanted and have different ion implantation directions, even when the ion implantation IM1 is performed by multistage ion implantation, the ion implantation IM1 and the ion implantation IM2 are in the middle of the multistage ion implantation. It is preferable to perform the ion implantation IM2 after the entire multistage ion implantation is completed or before the multistage ion implantation is performed, instead of performing the ion implantation IM2. Thereby, the time and effort which ion implantation IM1, IM2 requires can be reduced.

  In the present embodiment, when performing channel dope ion implantation for the n-channel peripheral transistor LT formed in the peripheral circuit region 2A, the transistors (transfer transistor TX, amplification transistor AMI, selection transistor) formed in the pixel region 1A. Channel doped ion implantation of SEL and reset transistor RST) can be performed together. In this case, if neither ion implantation IM1 nor ion implantation IM2 is performed, the impurity concentration in the channel formation region of the n-channel type peripheral transistor LT in the peripheral circuit region 2A and the transistors (TX, AMI, SEL in the pixel region 1A). , RST), the impurity concentration of the channel forming region can be made substantially the same. In this case, the threshold voltages of the n-channel peripheral transistor LT in the peripheral circuit region 2A and the transistors (TX, AMI, SEL, RST) in the pixel region 1A can be made substantially the same.

However, the ion implantation IM1 is performed in order to form a p ⁺ type semiconductor region PR for separation between adjacent photodiodes PD, and reliability of a semiconductor device having a photoelectric conversion element such as the photodiode PD is improved. It is important to improve performance. Therefore, in this embodiment, the ion implantation IM1 is performed to form the p ⁺ type semiconductor region PR. Therefore, in this embodiment, by forming the p ⁺ -type semiconductor region PR by ion implantation IM1, as compared with the case of not forming the p ⁺ -type semiconductor region PR without ion implantation IM1, the semiconductor device Reliability and performance can be improved.

  However, if the ion implantation IM1 is performed but the ion implantation IM2 is not performed, the channel formation region of the n-channel peripheral transistor LT in the peripheral circuit region 2A is equivalent to the amount of the p-type impurity implanted by the ion implantation IM1. In contrast, the p-type impurity concentration is higher in the channel formation region of the transistors (AMI, SEL, RST) in the pixel region 1A. In this case, the threshold voltage differs between the n-channel peripheral transistor LT in the peripheral circuit region 2A and the transistors (AMI, SEL, RST) in the pixel region 1A, and the difference in threshold voltage is large. Therefore, it becomes difficult to control the circuit in the semiconductor device.

On the other hand, in this embodiment, not only the ion implantation IM1 is performed to form the p ⁺ type semiconductor region PR but also the ion implantation IM2. For this reason, in the surface layer portion of the semiconductor substrate SB in the active region of the transistor (AMI, SEL, RST) in the pixel region 1A, the n-type impurity in which the p-type impurity injected by the ion implantation IM1 is implanted by the ion implantation IM2. Can compensate. As a result, the impurity concentration of the channel formation region of the n-channel peripheral transistor LT in the peripheral circuit region 2A and the impurity concentration of the channel formation region of the transistor (TX, AMI, SEL, RST) in the pixel region 1A are substantially the same. Will be able to. Therefore, the threshold voltages of the n-channel peripheral transistor LT in the peripheral circuit region 2A and the transistors (TX, AMI, SEL, RST) in the pixel region 1A can be made substantially the same. For this reason, it becomes easy to control the circuit in the semiconductor device, and the performance of the semiconductor device can be improved.

  After performing the ion implantation IM2 in this way, the mask layer MK is removed.

  Next, as shown in FIGS. 39 to 43, gate electrodes GT, GE, and GL are formed. The gate electrodes GT, GE, and GL are formed on the semiconductor substrate SB via the gate insulating film GF. The step of forming the gate electrodes GT, GE, and GL can be performed as follows, for example.

  That is, first, after the main surface of the semiconductor substrate SB is cleaned by a cleaning process or the like, an insulating film (for example, a silicon oxide film) for the gate insulating film GF is formed on the main surface of the semiconductor substrate SB using a thermal oxidation method or the like. To do. Then, after forming a conductive film for a gate electrode (for example, a doped polysilicon film) on the semiconductor substrate SB, that is, on the insulating film for the gate insulating film GF, using a CVD (Chemical Vapor Deposition) method or the like, The conductive film for the gate electrode is patterned using a photolithography method and a dry etching method. Thereby, the gate electrodes GT, GE, and GL made of the patterned conductive film can be formed.

  The gate electrode GT functions as a gate electrode of the transfer transistor TX, and is formed on the semiconductor substrate SB (p-type well PW1) via the gate insulating film GF in the pixel region 1A. In addition, each gate electrode GE of the amplification transistor AMI, the selection transistor SEL, and the reset transistor RST is formed on the semiconductor substrate SB (p-type well PW3) via the gate insulating film GF in the pixel region 1A. The gate electrode GL of the peripheral transistor LT is formed on the semiconductor substrate SB (p-type well PW4) via the gate insulating film GF in the peripheral circuit region 2A. A part of each gate electrode GT, GE, GL may be located on the element isolation region ST.

  Next, as shown in FIGS. 44 to 48, the n-type semiconductor region NW is formed by ion implantation in the semiconductor substrate SB (p-type well PW1) in the pixel region 1A. The n-type semiconductor region NW can be formed by ion-implanting n-type impurities such as phosphorus (P) or arsenic (As) into the semiconductor substrate SB (p-type well PW1) in the pixel region 1A.

  The n-type semiconductor region NW is an n-type semiconductor region for forming the photodiode PD, and the depth of the n-type semiconductor region NW (the bottom surface) is shallower than the depth of the p-type well PW1 (the bottom surface). The n-type semiconductor region NW is formed so as to be enclosed in the p-type well PW1. Since the n-type semiconductor region NW is formed so as to be included in the p-type well PW1, the bottom surface and the side surface of the n-type semiconductor region NW are in contact with the p-type well PW1.

  At the time of ion implantation for forming the n-type semiconductor region NW, a photoresist pattern (not shown) having an opening in the region where the n-type semiconductor region NW is to be formed is formed on the semiconductor substrate SB. An n-type semiconductor region NW can be formed by ion-implanting n-type impurities using the photoresist pattern as an ion implantation blocking mask. At this time, in the semiconductor substrate SB of the pixel region 1A, the region in which the n-type semiconductor region NR is to be formed later, and the active region in which the amplification transistor AMI, the selection transistor SEL, and the reset transistor RST are formed Since it is covered with a resist pattern (not shown), impurity ions are not implanted. At this time, since the entire peripheral circuit region 2A is covered with the photoresist pattern, impurity ions are not implanted into the semiconductor substrate SB in the peripheral circuit region 2A. That is, at the time of ion implantation for forming the n-type semiconductor region NW, the semiconductor substrate SB other than the region where the n-type semiconductor region NW is to be formed is covered with a photoresist pattern (not shown). An n-type impurity is selectively ion-implanted into the region NW formation scheduled region. Thereafter, the photoresist pattern (not shown) is removed.

Next, ap ⁺ type semiconductor region HP is formed in the semiconductor substrate SB in the pixel region 1A by ion implantation. The p ⁺ type semiconductor region HP can be formed by ion-implanting a p-type impurity such as boron (B) into the semiconductor substrate SB (p-type well PW1) in the pixel region 1A.

p ⁺ -type semiconductor region HP is, p-type impurity is a semiconductor region of p ⁺ -type introduced (doped) at a high concentration, impurity concentration (p-type impurity concentration) of the p ⁺ -type semiconductor region HP is, p-type well It is higher than the impurity concentration of PW1 (p-type impurity concentration). The depth of the p ⁺ type semiconductor region HP (bottom surface) is shallower than the depth of the n type semiconductor region NW (bottom surface), and the p ⁺ type semiconductor region HP is mainly formed in the surface layer portion of the n type semiconductor region NW. Is done.

during the ion implantation for forming the p ⁺ -type semiconductor region HP is previously formed photoresist pattern having an opening in the p ⁺ -type semiconductor region HP formation region (not shown) on the semiconductor substrate SB The p ⁺ type semiconductor region HP can be formed by ion-implanting p-type impurities using the photoresist pattern as an ion implantation blocking mask. At this time, in the semiconductor substrate SB of the pixel region 1A, the region in which the n-type semiconductor region NR is to be formed later, and the active region in which the amplification transistor AMI, the selection transistor SEL, and the reset transistor RST are formed Since it is covered with a resist pattern (not shown), impurity ions are not implanted. At this time, since the entire peripheral circuit region 2A is covered with the photoresist pattern, impurity ions are not implanted into the semiconductor substrate SB in the peripheral circuit region 2A. That is, when the ion implantation for forming the p ⁺ -type semiconductor region HP includes a semiconductor substrate SB other than p ⁺ -type semiconductor region HP formation region is previously covered with the photoresist pattern (not shown), p ^A p-type impurity is selectively ion-implanted into the region where the ⁺ -type semiconductor region HP is to be formed. Thereafter, the photoresist pattern (not shown) is removed.

A photodiode (PN junction diode) PD is formed by the p-type well PW1, the n-type semiconductor region NW, and the p ⁺ -type semiconductor region HP.

After the p ⁺ type semiconductor region HP is formed by ion implantation, it is preferable to perform an annealing process for recovering crystal defects (mainly crystal defects caused by ion implantation), that is, heat treatment. By this annealing treatment, crystal defects such as the n-type semiconductor region NW and the p ⁺ -type semiconductor region HP can be recovered. In addition, this annealing treatment can recover crystal defects in the ion-implanted regions (for example, the n-type semiconductor region NW and the p ⁺ -type semiconductor region HP), and can also activate the implanted impurities.

  Next, as shown in FIGS. 49 to 52, the n-type semiconductor region NR, the source / drain regions SD of the amplification transistor AMI, the selection transistor SEL, and the reset transistor RST, and the source / drain regions of the peripheral transistor LT SDL is formed. The n-type semiconductor region NR, the source / drain region SD, and the source / drain region SDL can be formed by ion implantation of n-type impurities, respectively. The n-type semiconductor region NR, the source / drain region SD, and the source / drain region SDL may be formed by the same ion implantation or different ion implantation, and in any case, with respect to the semiconductor substrate SB. It is formed by ion implantation of n-type impurities.

  Further, after forming an n-type extension region having a low impurity concentration by ion implantation, a sidewall insulating film called a sidewall spacer is formed on the sidewalls of the gate electrodes GT, GE, GL, and then ion implantation is performed. The n-type semiconductor region NR, the source / drain region SD, and the source / drain region SDL can also be formed. In this case, the n-type semiconductor region NR, the source / drain region SD, and the source / drain region SDL have an LDD structure. Further, in the n-type semiconductor region NR, the source / drain region SD, and the source / drain region SDL, those to which the LDD structure is applied and those to which the LDD structure is not applied can be mixed.

  The n-type semiconductor region NR is formed in the drain-side semiconductor substrate SB (p-type well PW1) on both sides of the gate electrode GT. The drain side corresponds to the side opposite to the side where the n-type semiconductor region NW is formed. The source / drain regions SD are formed in the semiconductor substrate SB (p-type well PW3) on both sides of the gate electrode GE. The source / drain regions SDL are formed in the semiconductor substrate SB (p-type well PW4) on both sides of the gate electrode GL.

  Next, annealing treatment (heat treatment) for activating the impurities introduced by the conventional ion implantation is performed.

  In this manner, the photodiode PD, the transfer transistor TX, the amplification transistor AMI, the selection transistor SEL, and the reset transistor RST are formed on the semiconductor substrate SB in the pixel region 1A, and the peripheral transistor LT is formed on the semiconductor substrate SB in the peripheral circuit region 2A. Is formed.

Next, as shown in FIGS. 10 to 14, an insulating film is formed on the main surface of the semiconductor substrate SB, and then the insulating film is patterned using a photolithography method and a dry etching method, A cap insulating film (protective film) CP is formed in the pixel region 1A. The cap insulating film CP can be formed of, for example, a silicon oxide film. As another form, the cap insulating film CP is formed after the n-type semiconductor region NW and the p ⁺ -type semiconductor region HP are formed, and before the n-type semiconductor region NR and the source / drain regions SD and SDL are formed. It can also be formed.

  Next, nickel silicide or cobalt silicide is formed on the n-type semiconductor region NR, the source / drain region SD, the source / drain region SDL, and the gate electrodes GT, GE, and GL by using salicide (Salicide: Self Aligned Silicide) technology. It is also possible to form a low-resistance metal silicide layer (not shown) made of the above. By forming this metal silicide layer, diffusion resistance, contact resistance, and the like can be reduced.

  Next, as shown in FIGS. 10 to 14, an interlayer is formed as an insulating film so as to cover the gate electrodes GT, GE, GL and the cap insulating film CP on the main surface (entire main surface) of the semiconductor substrate SB. An insulating film IL1 is formed. After the formation of the interlayer insulating film IL1, the upper surface of the interlayer insulating film IL1 can be planarized by polishing the surface of the interlayer insulating film IL1 by a CMP (Chemical Mechanical Polishing) method.

  Next, as shown in FIGS. 10 to 14, the interlayer insulating film IL1 is dry-etched using a photoresist pattern (not shown) formed on the interlayer insulating film IL1 as an etching mask, so that the interlayer A contact hole (through hole) is formed in the insulating film IL1. Then, a conductive plug PG made of tungsten (W) or the like is formed as a conductor portion for connection in the contact hole of the interlayer insulating film IL1. For the plug PG, for example, a conductive film for the plug PG is formed on the interlayer insulating film IL1 so as to fill the contact hole, and then an unnecessary conductive film outside the contact hole is formed by a CMP method or an etch back method. It can be formed by removing.

  Next, as shown in FIGS. 10 to 14, interlayer insulating films IL2 to IL4 and wirings M1 to M3 are formed on the interlayer insulating film IL1 in which the plug PG is embedded.

  For example, after forming the interlayer insulating film IL2 over the interlayer insulating film IL1, a wiring trench is formed in the interlayer insulating film IL2 using a photolithography technique and a dry etching technique. Then, after forming a barrier conductor film on the interlayer insulating film IL2 including the bottom surface and inner wall of the wiring trench, a thin copper film as a seed film is deposited on the barrier conductor film by a sputtering method or the like, and then by an electrolytic plating method. A copper plating film is deposited as a main conductor film on the seed film, and the inside of the wiring trench is filled with this copper plating film. Thereafter, unnecessary copper plating film, seed film and barrier conductor film outside the wiring trench are removed by CMP or the like, whereby the first layer wiring M1 can be formed in the wiring trench.

  Further, similarly, as shown in FIGS. 10 to 14, the interlayer insulating film IL3 is formed on the interlayer insulating film IL2 on which the wiring M1 is formed, and the wiring M2 is formed in the interlayer insulating film IL3. An interlayer insulating film IL4 is formed on the interlayer insulating film IL3 on which M2 is formed, and a wiring M3 is formed in the interlayer insulating film IL4. The wiring M1 is formed by a single damascene method, but the wiring M2 and the wiring M3 can be formed by a single damascene method or a dual damascene method.

  In the interlayer insulating film IL3, a via portion that is disposed between the wiring M2 and the wiring M1 and connects the wiring M2 and the wiring M1 is also formed. In the interlayer insulating film IL4, the wiring M3 and the wiring M2 are formed. Is also formed between the wiring M3 and the wiring M2.

  Next, a microlens (not shown) as an on-chip lens can be attached on the uppermost interlayer insulating film IL4 so as to overlap the n-type semiconductor region NW constituting the photodiode PD in plan view. Further, a color filter may be provided between the microlens and the interlayer insulating film IL4.

  Through the above steps, the semiconductor device of this embodiment can be manufactured.

  In the present embodiment, the charges accumulated in the photodiode PD (n-type semiconductor region NW) and transferred to the floating diffusion FD (n-type semiconductor region NR) by the transfer transistor TX are electrons. As another form, the conductivity types described in this embodiment can be reversed. In that case, the charge accumulated in the photodiode PD and transferred to the floating diffusion FD by the transfer transistor TX is a hole. (Hall). However, since electrons have higher mobility than holes, the present embodiment is applied, and the charges accumulated in the photodiode PD and transferred to the floating diffusion FD by the transfer transistor TX are defined as electrons. Is more preferable.

<Main features and effects>
The various features and effects of the present embodiment have already been described above, but here, some of the main features will be described.

The semiconductor device according to the present embodiment includes a semiconductor substrate SB, a plurality of photodiodes PD arranged in an array in the X direction and the Y direction intersecting the X direction on the main surface of the semiconductor substrate SB, and a semiconductor substrate SB. It has ap ⁺ type semiconductor region PR formed so as to surround the photodiode PD in plan view, and a plurality of transistors arranged between the photodiodes PD adjacent in the Y direction on the main surface of the semiconductor substrate SB. . The photodiode PD is formed as a photoelectric conversion element.

The manufacturing process of the semiconductor device according to the present embodiment includes a process of forming a mask layer MK having an opening OP that opens a region where a p ⁺ type semiconductor region PR is to be formed on the semiconductor substrate SB. A step (ion implantation IM1) of forming a p ⁺ type semiconductor region PR in the semiconductor substrate SB by ion-implanting p-type impurities into the semiconductor substrate SB using the mask layer MK as an ion implantation blocking mask. . The manufacturing process of the semiconductor device further includes a step (ion implantation IM2) of ion-implanting n-type impurities into the semiconductor substrate SB using the mask layer MK as an ion implantation blocking mask. In the step of ion-implanting n-type impurities into the semiconductor substrate SB using the mask layer MK as an ion implantation blocking mask (ion implantation IM2), between the photodiodes PD adjacent in the Y direction on the main surface of the semiconductor substrate SB. Ions are implanted into the first region corresponding to this region, but ions are not implanted into the second region corresponding to the region between the photodiodes PD adjacent in the X direction.

In the present embodiment, the n-type impurity is implanted into the first region corresponding to the region between the photodiodes PD adjacent in the Y direction in the step of ion-implanting the n-type impurity (ion implantation IM2). Therefore, the characteristics of the transistor disposed between the photodiodes PD adjacent in the Y direction can be controlled. For example, the threshold voltage can be controlled to a desired value by adjusting the impurity concentration in the channel formation region of the transistor disposed between the photodiodes PD adjacent in the Y direction. On the other hand, since the n-type impurity is not implanted into the second region corresponding to the region between the photodiodes PD adjacent in the X-direction in the step of ion-implanting the n-type impurity (ion implantation IM2), the X-direction The function of the p ⁺ type semiconductor region PR between the photodiodes PD adjacent to each other can be prevented from being lowered by the implantation of n type impurities. Therefore, the performance of the semiconductor device can be improved and the reliability can be improved. Also, ion implantation (ion implantation IM1) of p-type impurities and ion implantation (ion implantation IM2) of n-type impurities for forming the p ⁺ -type semiconductor region PR are performed using the same mask layer MK. Yes. For this reason, the number of manufacturing steps of the semiconductor device can be reduced. Therefore, the manufacturing cost of the semiconductor device can be reduced. In addition, since the step of forming a mask layer for ion implantation and the removal step thereof can be reduced, it is possible to suppress or prevent the semiconductor substrate SB from being scraped or contaminated. For this reason, the manufacturing yield of the semiconductor device can be improved. In addition, the reliability of the semiconductor device can be improved.

  Note that the region between the photodiodes PD adjacent in the Y direction and the region between the photodiode formation target regions PDA adjacent in the Y direction substantially coincide, and between the photodiodes PD adjacent in the X direction. The region substantially coincides with the region between the photodiode formation scheduled regions PDA adjacent in the X direction. For this reason, the first region corresponding to the region between the photodiodes PD adjacent in the Y direction is a region between the photodiode formation scheduled regions PDA adjacent in the Y direction at the stage before the photodiode PD is formed. In the stage after the formation of the photodiode PD, it is a region between the photodiodes PD adjacent in the Y direction. The second region corresponding to the region between the photodiodes PD adjacent in the X direction is a region between the photodiode formation scheduled regions PDA adjacent in the X direction at the stage before the photodiode PD is formed. Yes, in the stage after the formation of the photodiode PD, it is a region between the photodiodes PD adjacent in the X direction.

  Furthermore, in this embodiment, as described above, various devices are provided in relation to the configuration and layout of each component, the ion implantation IM1, the ion implantation IM2, the mask layer MK, and the like. The repeated explanation is omitted.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

1A Pixel area 2A Peripheral circuit area AC Active area AMI Amplifying transistor AP Output amplifier CHP Chip area CLC Column circuit CP Cap insulating film EP Semiconductor layer FD Floating diffusion GE, GL, GT Gate electrode GF Gate insulating film GND Ground potential HP p ⁺ type Semiconductor region HSC Horizontal scanning circuit IL1, IL2, IL3, IL4 Interlayer insulating film LRST Reset line LT Peripheral transistor LTX, LTX1, LTX2 Transfer line M1, M2, M3 Wiring MK Mask layer N1 Node NR, NW n-type semiconductor region OL Output line OP opening PD, PD1, PD2 photodiodes PDA photodiode formation region PG plug PR ^{p +} -type semiconductor regions PU pixel PW1, PW3, PW4 p-type well PW2 ^{p +} -type semiconductor layer RST reset transitional scan SB semiconductor substrate SB1 substrate body SD, SDL source-drain regions SEL select transistor SL selection line SS supporting substrate ST isolation region SWT switch TR1, TR2 groove TX transfer transistor VDD supply potential VSC vertical scanning circuit WF semiconductor wafer

Claims (19)

A semiconductor substrate, a plurality of photoelectric conversion elements arranged in an array in a first direction and a second direction intersecting the first direction on the main surface of the semiconductor substrate, and each photoelectric conversion element on the semiconductor substrate in a plane A semiconductor having a first semiconductor region of a first conductivity type formed so as to be surrounded by a view, and a plurality of transistors arranged between the photoelectric conversion elements adjacent to each other in the second direction of the main surface of the semiconductor substrate A device manufacturing method comprising:
(A) preparing the semiconductor substrate;
(B) forming the first conductivity type first semiconductor region on the semiconductor substrate;
(C) forming the plurality of photoelectric conversion elements each having a second semiconductor region of a second conductivity type opposite to the first conductivity type and the plurality of transistors on the semiconductor substrate;
Have
The step (b)
(B1) forming on the semiconductor substrate a mask layer having an opening for opening a region where the first semiconductor region is to be formed;
(B2) The first conductivity type first semiconductor region is formed in the semiconductor substrate by ion-implanting the first conductivity type impurity into the semiconductor substrate using the mask layer as an ion implantation blocking mask. Process,
Including
Furthermore,
(D) a step of ion-implanting the second conductivity type impurity into the semiconductor substrate using the mask layer as an ion implantation blocking mask;
Have
In the step (d), ions are implanted into the first region corresponding to the region between the photoelectric conversion elements adjacent in the second direction on the main surface of the semiconductor substrate. A method for manufacturing a semiconductor device, wherein ions are not implanted into a second region corresponding to a region between adjacent photoelectric conversion elements. In the manufacturing method of the semiconductor device according to claim 1,
The method of manufacturing a semiconductor device, wherein each of the photoelectric conversion elements is a photodiode. The method of manufacturing a semiconductor device according to claim 2.
A method for manufacturing a semiconductor device, wherein a depth of the first semiconductor region is deeper than a depth of the second semiconductor region. In the manufacturing method of the semiconductor device according to claim 1,
The method for manufacturing a semiconductor device, wherein the first semiconductor region is formed in a lattice shape in a plan view on the semiconductor substrate. In the manufacturing method of the semiconductor device according to claim 1,
Each of the second semiconductor regions is formed in a third semiconductor region of the first conductivity type formed in the semiconductor substrate and surrounded by the first semiconductor region in plan view,
The method for manufacturing a semiconductor device, wherein an impurity concentration of the first semiconductor region is higher than an impurity concentration of the third semiconductor region. In the manufacturing method of the semiconductor device according to claim 1,
In the step (b2), the first semiconductor region is formed by performing ion implantation a plurality of times while changing the implantation energy using the mask layer as an ion implantation blocking mask. In the manufacturing method of the semiconductor device according to claim 1,
The implantation depth in the step (d) is shallower than the implantation depth in the step (b2).
A method for manufacturing a semiconductor device. In the manufacturing method of the semiconductor device according to claim 1,
The method of manufacturing a semiconductor device, wherein the ion implantation in the step (d) functions as channel doping ion implantation of the plurality of transistors. In the manufacturing method of the semiconductor device according to claim 1,
A method of manufacturing a semiconductor device, wherein a transistor is not formed between the photoelectric conversion elements adjacent in the first direction. In the manufacturing method of the semiconductor device according to claim 1,
(E) forming an element isolation region made of an insulator on the main surface of the semiconductor substrate;
Further comprising
When the step (e) and the step (c) are performed, the element isolation region and the active region surrounded by the element isolation region are provided between the photoelectric conversion elements adjacent in the second direction in plan view. A method of manufacturing a semiconductor device. The method of manufacturing a semiconductor device according to claim 10.
A method of manufacturing a semiconductor device, wherein the element isolation region is not formed between the photoelectric conversion elements adjacent in the first direction when the steps (e) and (c) are performed. The method of manufacturing a semiconductor device according to claim 11.
In the first region, the first semiconductor region is formed under the element isolation region. In the manufacturing method of the semiconductor device according to claim 1,
The method for manufacturing a semiconductor device, wherein the ion implantation in the step (b2) is vertical ion implantation. In the manufacturing method of the semiconductor device according to claim 1,
The method for manufacturing a semiconductor device, wherein the ion implantation in the step (d) is oblique ion implantation. 15. The method of manufacturing a semiconductor device according to claim 14,
The opening of the mask layer has a plurality of first grooves extending in the first direction and a plurality of second grooves extending in the second direction, respectively.
The method for manufacturing a semiconductor device, wherein the plurality of first grooves and the plurality of second grooves intersect each other. In the manufacturing method of the semiconductor device according to claim 15,
In the step (b2), the direction of ion implantation is performed so that impurity ions are implanted into the semiconductor substrate exposed from the plurality of first grooves and the semiconductor substrate exposed from the plurality of second grooves. Is set,
In the step (d), impurity ions are implanted into the semiconductor substrate exposed from the plurality of first grooves, except for the intersections of the plurality of first grooves and the plurality of second grooves. The semiconductor substrate is exposed from the plurality of second grooves, and the ion implantation direction is set so that impurity ions are not implanted by being shielded by the mask layer. Method. In the manufacturing method of the semiconductor device according to claim 16,
The method of manufacturing a semiconductor device, wherein the direction of ion implantation in the step (d) is a direction parallel to a plane parallel to both the normal direction of the main surface of the semiconductor substrate and the first direction. The method of manufacturing a semiconductor device according to claim 17.
The inclination angle of the ion implantation direction in the step (d) with respect to the normal direction of the main surface of the semiconductor substrate is θ,
The width in the first direction of each of the second grooves is W1,
When the height of the side wall of each second groove is H1,
A method for manufacturing a semiconductor device, wherein tan θ> W1 / H1 is satisfied. In the manufacturing method of the semiconductor device according to claim 1,
The first conductivity type is p-type;
The method for manufacturing a semiconductor device, wherein the second conductivity type is an n-type.

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