JP2015023150A - Method of manufacturing semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the performance of a semiconductor device.SOLUTION: A method of manufacturing a semiconductor device comprises the steps of: forming a p-type well PW1, used for a photo diode PD, within a semiconductor substrate SB; forming an n-type semiconductor region NW, used for the photo diode PD, within the semiconductor substrate SB so as to be included in the p-type well PW1; and forming a ptype semiconductor region PR in a surface layer portion of the n-type semiconductor region NW. The ptype semiconductor region PR is formed by ion-implanting a cluster composed of multiple boron and hydrogen atoms.

Description

  The present invention relates to a method for manufacturing a semiconductor device, and can be suitably used for, for example, a method for manufacturing a semiconductor device including a solid-state imaging element.

  As a solid-state imaging device, development of a solid-state imaging device (CMOS image sensor) using a complementary metal oxide semiconductor (CMOS) has been advanced. This CMOS image sensor includes a plurality of pixels each having a photodiode and a transfer transistor.

  In Japanese Patent Laid-Open No. 2008-226925 (Patent Document 1), an impurity region containing at least a part of boron in the form of an octahedral cluster composed of six boron atoms is formed in a predetermined region of a semiconductor layer or a semiconductor substrate. A technique related to the provided semiconductor device is described.

JP 2008-226925 A

  There is a semiconductor device having a photodiode, and it is desired to improve the performance of such a semiconductor device as much as possible. Alternatively, it is desired to improve the manufacturing yield. Alternatively, it is desired to improve the performance and improve the manufacturing yield.

  Other problems and novel features will become apparent from the description of the specification and the accompanying drawings.

  According to one embodiment, a step of forming a p-type first semiconductor region for a photodiode in a semiconductor substrate, and a step of forming an n-type second semiconductor region for the photodiode in the semiconductor substrate. And a step of forming a p-type third semiconductor region in the semiconductor substrate. The second semiconductor region is included in the first semiconductor region, and the third semiconductor region is formed in a surface layer portion of the second semiconductor region. The third semiconductor region is formed by ion implantation of a cluster composed of a plurality of boron atoms and a plurality of hydrogen atoms.

  According to one embodiment, the performance of a semiconductor device can be improved.

  Alternatively, the manufacturing yield of the semiconductor device can be improved.

  Alternatively, the performance of the semiconductor device can be improved and the manufacturing yield of the semiconductor device can be improved.

1 is a circuit block diagram illustrating a configuration example of a semiconductor device according to an embodiment; It is a circuit diagram which shows the structural example of a pixel. It is a top view which shows the pixel of the semiconductor device of one embodiment. It is a top view which shows the example of a connection of each plug. It is a top view which shows the semiconductor wafer and chip area | region in which the semiconductor device of one embodiment is formed. 3 is a plan view showing a transistor formed in a peripheral circuit region of the semiconductor device of one embodiment. FIG. It is a top view showing a plurality of pixels formed in a pixel region of a semiconductor device of one embodiment. It is principal part sectional drawing of the semiconductor device of one embodiment. It is principal part sectional drawing of the semiconductor device of one embodiment. It is a process flow figure showing a manufacturing process of a semiconductor device of one embodiment. It is a process flow figure showing a manufacturing process of a semiconductor device of one embodiment. It is principal part sectional drawing in the manufacturing process of the semiconductor device which is one Embodiment. FIG. 13 is an essential part cross sectional view of the same semiconductor device as in FIG. 12 during a manufacturing step; FIG. 13 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 12; FIG. 15 is an essential part cross sectional view of the same semiconductor device as in FIG. 14 during a manufacturing step; FIG. 15 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 14; FIG. 17 is an essential part cross sectional view of the same semiconductor device as in FIG. 16 during a manufacturing step; FIG. 17 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 16; FIG. 19 is an essential part cross sectional view of the same semiconductor device as in FIG. 18 during a manufacturing step; FIG. 19 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 18; FIG. 21 is an essential part cross sectional view of the same semiconductor device as in FIG. 20 during a manufacturing step; FIG. 21 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 20; FIG. 23 is an essential part cross sectional view of the same semiconductor device as in FIG. 22 during a manufacturing step; FIG. 23 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 22; FIG. 25 is an essential part cross sectional view of the same semiconductor device as in FIG. 24 during a manufacturing step; FIG. 25 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 24; FIG. 27 is an essential part cross sectional view of the same semiconductor device as in FIG. 26 during a manufacturing step; FIG. 27 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 26; FIG. 29 is an essential part cross sectional view of the same semiconductor device as in FIG. 28 during a manufacturing step; FIG. 29 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 28; FIG. 31 is an essential part cross sectional view of the same semiconductor device as in FIG. 30 during a manufacturing step; FIG. 31 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 30; FIG. 33 is an essential part cross sectional view of the same semiconductor device as in FIG. 32 during a manufacturing step; FIG. 33 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 32; FIG. 35 is an essential part cross sectional view of the same semiconductor device as in FIG. 34 during a manufacturing step; It is explanatory drawing which shows typically the crystal structure of a p ⁺ type semiconductor region. It is a graph which shows the result of having compared sheet resistance. It is a graph which shows the result of having compared sheet resistance. It is a graph which shows the result of having compared dark current. It is a graph which shows the result of having compared the incidence rate of a white spot. It is principal part sectional drawing of the semiconductor device of other embodiment. It is principal part sectional drawing in the manufacturing process of the semiconductor device which is other Embodiment. FIG. 43 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 42; FIG. 44 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 43; FIG. 45 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 44; FIG. 46 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 45; FIG. 47 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 46;

  In the following embodiments, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments. However, unless otherwise specified, they are not irrelevant to each other. There are some or all of the modifications, details, supplementary explanations, and the like. Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), especially when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and may be more or less than the specific number. Further, in the following embodiments, the constituent elements (including element steps and the like) are not necessarily indispensable unless otherwise specified and apparently essential in principle. Needless to say. Similarly, in the following embodiments, when referring to the shapes, positional relationships, etc. of the components, etc., the shapes are substantially the same unless otherwise specified, or otherwise apparent in principle. And the like are included. The same applies to the above numerical values and ranges.

  Hereinafter, embodiments will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof will be omitted. In the following embodiments, the description of the same or similar parts will not be repeated in principle unless particularly necessary.

  In the drawings used in the embodiments, hatching may be omitted even in a cross-sectional view so as to make the drawings easy to see. Further, even a plan view may be hatched to make the drawing easy to see.

(Embodiment 1)
Hereinafter, the structure and manufacturing process of the semiconductor device according to the first embodiment will be described in detail with reference to the drawings. In the first embodiment, an example in which the semiconductor device is a CMOS image sensor as a surface irradiation type image sensor in which light is incident from the surface side of the semiconductor substrate will be described.

<Configuration of semiconductor device>
FIG. 1 is a circuit block diagram illustrating a configuration example of the semiconductor device of the present embodiment. FIG. 2 is a circuit diagram illustrating a configuration example of a pixel. FIG. 1 shows 16 pixels of 4 rows and 4 columns (4 × 4) arranged in an array (matrix), but the number of pixels is not limited to this and can be variously changed. For example, there are millions of pixels actually used in electronic devices such as cameras.

  In the pixel region 1A shown in FIG. 1, a plurality of pixels PU are arranged in an array, and a drive circuit such as a vertical scanning circuit VSC or a horizontal scanning circuit HSC is arranged around the pixel PU. Each pixel (cell, pixel unit) PU is arranged at the intersection of the selection line SL and the output line OL. The selection line SL is connected to the vertical scanning circuit VSC, and the output line OL is connected to the column circuit CLC. The column circuit CLC is connected to the output amplifier AP via the switch SWT. Each switch SWT is connected to the horizontal scanning circuit HSC and controlled by the horizontal scanning circuit HSC.

  For example, the electrical signal read from the pixel PU selected by the vertical scanning circuit VSC and the horizontal scanning circuit HSC is output via the output line OL and the output amplifier AP.

  The configuration of the pixel PU is configured by, for example, a photodiode PD and four transistors RST, TX, SEL, and AMI as shown in FIG. These transistors RST, TX, SEL, and AMI are each formed of an n-channel type MISFET (Metal Insulator Semiconductor Field Effect Transistor). Among these, the transistor RST is a reset transistor (reset transistor), the transistor TX is a transfer transistor (transfer transistor), the transistor SEL is a selection transistor (selection transistor), and the transistor AMI is an amplification transistor (amplification transistor). Transistor). The transfer transistor TX is a transfer transistor that transfers the charge generated by the photodiode PD. In addition to these transistors, other transistors and capacitors may be incorporated. Further, there are various modifications and application forms for the connection form of these transistors.

  In the circuit example shown in FIG. 2, a photodiode PD and a transfer transistor TX are connected in series between a ground potential (GND) and a node N1. A reset transistor RST is connected between the node N1 and the power supply potential (power supply potential line) VDD. The power supply potential VDD is a potential of a power supply potential line LVDD (see FIG. 4 described later). A selection transistor SEL and an amplification transistor AMI are connected in series between the power supply potential VDD and the output line OL. The gate electrode of the amplification transistor AMI is connected to the node N1. The gate electrode of the reset transistor RST is connected to the reset line LRST. The gate electrode of the selection transistor SEL is connected to the selection line SL, and the gate electrode of the transfer transistor TX is connected to the transfer line (second selection line) LTX.

  For example, the transfer line LTX and the reset line LRST are raised (set to H level), and the transfer transistor TX and the reset transistor RST are turned on. As a result, the charge of the photodiode PD is removed and depleted. Thereafter, the transfer transistor TX is turned off.

  Thereafter, for example, when a mechanical shutter of an electronic device such as a camera is opened, electric charges are generated and accumulated in the photodiode PD by incident light while the shutter is opened. That is, the photodiode PD receives incident light and generates charges.

  Next, after closing the shutter, the reset line LRST is lowered (set to L level), and the reset transistor RST is turned off. Further, the selection line SL and the transfer line LTX are raised (set to H level), and the selection transistor SEL and the transfer transistor TX are turned on. As a result, the charge generated by the photodiode PD is transferred to the end of the transfer transistor TX on the node N1 side (corresponding to a floating diffusion FD in FIGS. 3 and 4 described later). At this time, the potential of the floating diffusion FD changes to a value corresponding to the charge transferred from the photodiode PD, and this value is amplified by the amplification transistor AMI and appears on the output line OL. The potential of the output line OL becomes an electric signal (light reception signal) and is read out as an output signal from the output amplifier AP via the column circuit CLC and the switch SWT.

  FIG. 3 is a plan view showing a pixel of the semiconductor device of the present embodiment. FIG. 4 is a plan view showing an example of connection of each plug, and shows the connection state added to FIG.

  As shown in FIGS. 3 and 4, the pixel PU (see FIG. 1) of the semiconductor device of the present embodiment includes an active region AcTP in which the photodiode PD and the transfer transistor TX are arranged, and a reset transistor RST. The active region AcR is disposed. Further, the pixel PU has an active region AcAS in which the selection transistor SEL and the amplification transistor AMI are arranged, and an active region AcG in which a plug Pg connected to the ground potential line LGND is arranged.

  A gate electrode Gr is disposed in the active region AcR, and plugs Pr1 and Pr2 are disposed on the source / drain regions on both sides thereof. The gate electrode Gr and the source / drain regions constitute a reset transistor RST.

  In the active region AcTP, a gate electrode Gt is disposed. In a plan view, a photodiode PD is disposed on one of both sides of the gate electrode Gt, and a floating diffusion FD is disposed on the other side. The photodiode PD is a PN junction diode and includes, for example, a plurality of n-type or p-type impurity diffusion regions (semiconductor regions). The floating diffusion FD has a function as a charge storage portion or a floating diffusion layer, and is constituted by, for example, an n-type impurity diffusion region (semiconductor region). A plug Pfd is disposed on the floating diffusion FD.

  In the active region AcAS, a gate electrode Ga and a gate electrode Gs are disposed, a plug Pa is disposed at an end of the active region AcAS on the gate electrode Ga side, and a plug is disposed at an end of the active region AcAS on the gate electrode Gs side. Ps is arranged. Both sides of the gate electrode Ga and the gate electrode Gs are a source / drain region, and a selection transistor SEL and an amplification transistor AMI connected in series are configured by the gate electrode Ga, the gate electrode Gs and the source / drain region. Yes.

  A plug Pg is disposed on the active region AcG. This plug Pg is connected to the ground potential line LGND. Therefore, the active region AcG is a power feeding region for applying the ground potential GND to the well region of the semiconductor substrate.

  Further, a plug Prg, a plug Ptg, a plug Pag, and a plug Psg are arranged on the gate electrode Gr, the gate electrode Gt, the gate electrode Ga, and the gate electrode Gs, respectively.

  The plugs Pr1, Pr2, Pg, Pfd, Pa, Ps, Prg, Ptg, Pag, and Psg are connected as necessary by a plurality of wiring layers (for example, wirings M1 to M3 shown in FIG. 8 described later). Thereby, the circuit shown in FIGS. 1 and 2 can be formed. FIG. 4 shows an example of plug connection.

  FIG. 5 is a plan view showing a semiconductor wafer and a chip region on which the semiconductor device of the present embodiment is formed. As shown in FIG. 5, the semiconductor wafer WF (a semiconductor wafer corresponding to a semiconductor substrate SB described later) has a plurality of chip regions CHP, and the pixel region 1A shown in FIG. 1 has one chip together with the peripheral circuit region 2A. It is formed in region CHP. A logic circuit (logic circuit) is arranged in the peripheral circuit region 2A. For example, the logic circuit calculates an output signal output from the pixel region 1A, and outputs image data based on the calculation result. The chip region CHP is a region from which one semiconductor chip is obtained, and each chip region CHP in the semiconductor wafer WF has the same configuration (pixel region 1A and peripheral circuit region 2A). The semiconductor wafer WF is later cut by dicing, and individual chip regions CHP that have been separated into individual chips become semiconductor chips.

  FIG. 6 is a plan view showing a transistor formed in the peripheral circuit region of the semiconductor device of the present embodiment.

  As shown in FIG. 6, a peripheral transistor LT as a logic transistor is arranged in the peripheral circuit region 2A. Actually, a plurality of n-channel MISFETs and a plurality of p-channel MISFETs are formed in the peripheral circuit region 2A as transistors constituting the logic circuit. FIG. 6 shows the logic circuit. One n-channel MISFET of the transistors is shown as a peripheral transistor LT.

As shown in FIG. 6, an active region AcL is formed in the peripheral circuit region 2A, and in this active region AcL, the gate electrode Glt of the peripheral transistor LT is arranged, on both sides of the gate electrode Glt, Inside the region AcL, source / drain regions of a peripheral transistor LT including an n ⁺ type semiconductor region SD described later are formed. In addition, plugs Pt1 and Pt2 are disposed on the source / drain regions of the peripheral transistor LT.

  In FIG. 6, only one peripheral transistor LT is shown, but actually, a plurality of transistors are arranged in the peripheral circuit region 2A. A logic circuit can be configured by connecting plugs on the source / drain regions of these transistors or plugs on the gate electrodes with a plurality of wiring layers (wirings M1 to M3 described later). In addition, an element other than the MISFET, for example, a capacitor or a transistor having another structure may be incorporated in the logic circuit.

  Hereinafter, an example in which the peripheral transistor LT is an n-channel MISFET will be described, but the peripheral transistor LT may be a p-channel MISFET.

  FIG. 7 is a plan view showing a plurality of pixels formed in the pixel region of the semiconductor device of this embodiment.

  As shown in FIG. 7, in the pixel area 1A, a plurality of pixels PU shown in FIG. 3 are arranged in the X direction and the Y direction to constitute a pixel array. In FIG. 7, a total of four 2 × 2 pixels PU are shown as an example, but the number of pixels can be variously changed.

<Element structure of pixel area and peripheral circuit area>
Next, the structure of the semiconductor device of this embodiment will be described with reference to cross-sectional views (FIGS. 8 and 9) of the semiconductor device of this embodiment. 8 and 9 are cross-sectional views of the main part of the semiconductor device according to the present embodiment. FIG. 8 substantially corresponds to the cross-sectional view taken along the line AA of FIG. 3, and FIG. Corresponds substantially to the cross-sectional view taken along the line BB.

As shown in FIG. 8, a photodiode PD and a transfer transistor TX are formed in the active region AcTP of the pixel region 1A of the semiconductor substrate SB. The photodiode PD includes a p-type well PW1, an n-type semiconductor region (n-type well) NW, and a p ⁺ -type semiconductor region PR formed in the semiconductor substrate SB. Also, as shown in FIG. 9, a peripheral transistor LT is formed in the active region AcL of the peripheral circuit region 2A of the semiconductor substrate SB.

The semiconductor substrate SB is a semiconductor substrate (semiconductor wafer) made of n-type single crystal silicon into which an n-type impurity (donor) such as phosphorus (P) or arsenic (As) is introduced. As another form, the semiconductor substrate SB can be a so-called epitaxial wafer. When the semiconductor substrate SB is an epitaxial wafer, for example, an n-type impurity (for example, phosphorus (P)) is formed on the main surface of an n ⁺ type single crystal silicon substrate into which an n-type impurity (for example, arsenic (As)) is introduced. The semiconductor substrate SB can be formed by growing an epitaxial layer made of n ⁻ type single crystal silicon into which is introduced.

  An element isolation region LCS made of an insulator is arranged on the outer periphery of the active region AcTP. Thus, the exposed region of the semiconductor substrate SB surrounded by the element isolation region LCS becomes an active region such as the active region AcTP and the active region AcL.

  P-type wells (p-type semiconductor regions) PW1 and PW2 are formed from the main surface of the semiconductor substrate SB to a predetermined depth. The p-type well PW1 is formed over the entire active region AcTP. That is, the p-type well PW1 is formed across a region where the photodiode PD is formed and a region where the transfer transistor TX is formed. The p-type well PW2 is formed over the entire active region AcL. That is, the p-type well PW2 is formed in a region where the peripheral transistor LT is formed. Each of the p-type well PW1 and the p-type well PW2 is a p-type semiconductor region into which a p-type impurity such as boron (B) is introduced.

  As shown in FIG. 8, in the semiconductor substrate SB in the active region AcTP, an n-type semiconductor region (n-type well) NW is formed so as to be included in the p-type well PW1. The n-type semiconductor region NW is an n-type semiconductor region into which an n-type impurity such as phosphorus (P) or arsenic (As) is introduced.

  The n-type semiconductor region NW is an n-type semiconductor region for forming the photodiode PD, but the source region of the transfer transistor TX is also formed by the n-type semiconductor region NW. That is, the n-type semiconductor region NW is mainly formed in a region where the photodiode PD is formed, but a part of the n-type semiconductor region NW is planarly (planar) with the gate electrode Gt of the transfer transistor TX. It is formed in the position where it overlaps (by visual observation). The depth of the n-type semiconductor region NW (bottom surface) is shallower than the depth of the p-type well PW1 (bottom surface), and the n-type semiconductor region NW is formed so as to be included in the p-type well PW1.

A p ⁺ type semiconductor region PR is formed on a part of the surface of the n type semiconductor region NW. p ⁺ -type semiconductor region PR is boron (B) is a p ⁺ -type semiconductor region p-type impurity is introduced at a high concentration (doping), such as the impurity concentration (p-type impurity concentration of the p ⁺ -type semiconductor region PR ) Is higher than the impurity concentration (p-type impurity concentration) of the p-type well PW1. Therefore, the conductivity (electric conductivity) of the p ⁺ type semiconductor region PR is higher than the conductivity (electric conductivity) of the p type well PW1.

The depth of the p ⁺ type semiconductor region PR (the bottom surface thereof) is shallower than the depth of the n type semiconductor region NW (the bottom surface thereof). The p ⁺ type semiconductor region PR is mainly formed in the surface layer portion (surface portion) of the n type semiconductor region NW. Therefore, when viewed in the thickness direction of the semiconductor substrate SB, the n-type semiconductor region NW exists under the uppermost p ⁺ -type semiconductor region PR, and the p-type well PW1 exists under the n-type semiconductor region NW. It becomes a state.

In the region where the n-type semiconductor region NW is not formed, a part of the p ⁺ -type semiconductor region PR is in contact with the p-type well PW1. That is, the p ⁺ type semiconductor region PR includes a portion where the n-type semiconductor region NW exists immediately below and contacts the n-type semiconductor region NW, and a portion where the p-type well PW1 exists immediately below and contacts the p-type well PW1. And have.

A PN junction is formed between the p-type well PW1 and the n-type semiconductor region NW. A PN junction is formed between the p ⁺ type semiconductor region PR and the n type semiconductor region NW. A photodiode (PN junction diode) PD is formed by the p-type well PW1 (p-type semiconductor region), the n-type semiconductor region NW, and the p ⁺ -type semiconductor region PR.

The p ⁺ type semiconductor region PR is a region formed for the purpose of suppressing the generation of electrons based on interface states that are formed on the surface of the semiconductor substrate SB. That is, in the surface region of the semiconductor substrate SB, electrons are generated due to the influence of the interface state, which may cause an increase in dark current even when light is not irradiated. For this reason, by forming a p ⁺ type semiconductor region PR having holes as majority carriers on the surface of the n-type semiconductor region NW having electrons as majority carriers, electrons in a state where no light is irradiated. Can be suppressed, and an increase in dark current can be suppressed. Therefore, the p ⁺ type semiconductor region PR has a role of reducing dark current by recombining electrons springing from the outermost surface of the photodiode with holes in the p ⁺ type semiconductor region PR.

  The photodiode PD is a light receiving element. The photodiode PD can also be regarded as a photoelectric conversion element. The photodiode PD has a function of photoelectrically converting input light to generate charges and storing the generated charges, and the transfer transistor TX transfers the charges accumulated in the photodiode PD from the photodiode PD. It has a role as a switch.

  Further, the gate electrode Gt is formed so as to overlap with a part of the n-type semiconductor region NW in a plan view. The gate electrode Gt is a gate electrode of the transfer transistor TX, and is formed (arranged) on the semiconductor substrate SB via the gate insulating film GOX. A sidewall spacer SW is formed as a sidewall insulating film on the sidewall of the gate electrode Gt.

In the semiconductor substrate SB (p-type well PW1) of the active region AcTP, the n-type semiconductor region NW is formed on one side of both sides of the gate electrode Gt, and the n-type semiconductor is formed on the other side. Region NR is formed. The n-type semiconductor region NR is an n ⁺ -type semiconductor region into which n-type impurities such as phosphorus (P) or arsenic (As) are introduced (doped) at a high concentration, and is formed in the p-type well PW1. The n-type semiconductor region NR is a semiconductor region as a floating diffusion (floating diffusion layer) FD, and is also a drain region of the transfer transistor TX.

  The n-type semiconductor region NR functions as a drain region of the transfer transistor TX, but can also be regarded as a floating diffusion (floating diffusion layer) FD. The n-type semiconductor region NW is a constituent element of the photodiode PD, but can also function as a semiconductor region for the source of the transfer transistor TX. That is, the source region of the transfer transistor TX is formed by the n-type semiconductor region NW. For this reason, the n-type semiconductor region NW and the gate electrode Gt have a positional relationship such that a part (source side) of the gate electrode Gt overlaps a part of the n-type semiconductor region NW in plan view. It is preferable that The n-type semiconductor region NW and the n-type semiconductor region NR are formed so as to be separated from each other with a channel formation region (corresponding to a substrate region immediately below the gate electrode Gt) of the transfer transistor TX interposed therebetween.

A cap insulating film CP is formed on the surface of the photodiode PD (see FIG. 3), that is, on the surfaces of the n-type semiconductor region NW and the p ⁺ -type semiconductor region PR. The cap insulating film CP is formed to keep the surface characteristics of the semiconductor substrate SB, that is, the interface characteristics good. An antireflection film ARF is formed on the cap insulating film CP. That is, the antireflection film ARF is formed on the n-type semiconductor region NW and the p ⁺ -type semiconductor region PR via the cap insulating film CP. A part (end part) of the antireflection film ARF can also run on the gate electrode Gt.

On the other hand, as shown in FIG. 9, the gate electrode Glt of the peripheral transistor LT is formed on the p-type well PW2 in the active region AcL via the gate insulating film GOX, and the sidewalls on both sides of the gate electrode Glt. A sidewall spacer SW is formed on the top. In the p-type well PW2 on both sides of the gate electrode Glt, source / drain regions of the peripheral transistor LT are formed. The source / drain regions of the peripheral transistor LT have an LDD (Lightly Doped Drain) structure, and an n ⁻ type semiconductor region NM that is an n-type low concentration semiconductor region and an n type high concentration semiconductor region. ^{It comprises a +} type semiconductor region SD.

  On the semiconductor substrate SB, an interlayer insulating film IL1 is formed so as to cover the gate electrode Gt, the antireflection film ARF, and the gate electrode Glt. The interlayer insulating film IL1 is formed over the entire main surface of the semiconductor substrate SB including the pixel region 1A and the peripheral circuit region 2A.

  The interlayer insulating film IL1 is formed of, for example, a silicon oxide film using TEOS (Tetra Ethyl Ortho Silicate) as a raw material. In the interlayer insulating film IL1, conductive plugs PG such as the plugs Pr1, Pr2, Pg, Pfd, Pa, Ps, Prg, Ptg, Pag, Psg, Pt1, and Pt2 are embedded. For example, as shown in FIG. 8, a plug Pfd is formed as a plug PG on the n-type semiconductor region NR as the floating diffusion FD, and this plug Pfd penetrates the interlayer insulating film IL1 and forms the n-type semiconductor region. NR is reached and is electrically connected to the n-type semiconductor region NR.

  Conductive plugs PG such as the plugs Pr1, Pr2, Pg, Pfd, Pa, Ps, Prg, Ptg, Pag, Psg, Pt1, and Pt2 are formed in contact holes formed in the interlayer insulating film IL1, for example, barrier conductors. It is formed by embedding a film and a tungsten film formed on the barrier conductor film. The barrier conductor film is made of, for example, a laminated film of a titanium film and a titanium nitride film formed on the titanium film (that is, a titanium / titanium nitride film).

  Although not shown in FIGS. 8 and 9, the reset transistor RST, the selection transistor SEL, and the amplification transistor AMI are also formed on the p-type well formed in the semiconductor substrate SB via a gate insulating film. It has a gate electrode and source / drain regions formed in p-type wells on both sides of the gate electrode (see FIG. 3 above). Since the selection transistor SEL and the amplification transistor AMI are connected in series, they share one source / drain region (see FIG. 3).

  On the interlayer insulating film IL1 in which the plug PG (Pr1, Pr2, Pg, Pfd, Pa, Ps, Prg, Ptg, Pag, Psg) is embedded, for example, an interlayer insulating film IL2 is formed. A wiring M1 is formed in the film IL2.

  The interlayer insulating film IL2 is formed of, for example, a silicon oxide film, but is not limited to this, and may be formed of a low dielectric constant film having a dielectric constant lower than that of the silicon oxide film. An example of the low dielectric constant film is a SiOC film.

  The wiring M1 is formed of, for example, a copper wiring, and can be formed using a damascene method. Note that the wiring M1 is not limited to a copper wiring, and can be formed of an aluminum wiring. When the wiring M1 is a buried copper wiring (damascene copper wiring) (FIGS. 8 and 9 correspond to this case), the buried copper wiring is buried in a wiring trench formed in the interlayer insulating film IL1. However, when the wiring M1 is an aluminum wiring, the aluminum wiring is formed by patterning a conductive film formed on the interlayer insulating film.

  On the interlayer insulating film IL2 on which the wiring M1 is formed, for example, an interlayer insulating film IL3 made of a silicon oxide film or a low dielectric constant film is formed, and the wiring M2 is formed in the interlayer insulating film IL3. An interlayer insulating film IL4 is formed on the interlayer insulating film IL3 on which the wiring M2 is formed, and the wiring M3 is formed in the interlayer insulating film IL4. The wirings M1 to M3 form a wiring layer. The wirings M1 to M3 are formed so as not to overlap the photodiode in plan view. This is to prevent light incident on the photodiode from being blocked by the wirings M1 to M3.

  Further, a microlens ML is mounted on the interlayer insulating film IL4 on which the wiring M3 is formed. A color filter may be provided between the microlens ML and the interlayer insulating film IL4.

  In FIG. 8, when light is irradiated to the pixel PU (see FIG. 1), first, incident light passes through the microlens ML. Thereafter, the light passes through the interlayer insulating films IL4 to IL1 transparent to visible light, and then enters the antireflection film ARF. In the antireflection film ARF, reflection of incident light is suppressed, and a sufficient amount of incident light is incident on the photodiode PD. In the photodiode PD, since the energy of incident light is larger than the band gap of silicon, the incident light is absorbed by photoelectric conversion and a hole electron pair is generated. The electrons generated at this time are accumulated in the n-type semiconductor region NW. Then, the transfer transistor TX is turned on at an appropriate timing. Specifically, a voltage equal to or higher than the threshold voltage is applied to the gate electrode Gt of the transfer transistor TX. Then, a channel region is formed in the channel formation region immediately below the gate insulating film GOX of the transfer transistor TX, and the n-type semiconductor region NW as the source region of the transfer transistor TX and the n-type semiconductor region NR as the drain region of the transfer transistor TX. Is electrically conducted. As a result, electrons accumulated in the n-type semiconductor region NW pass through the channel region to reach the drain region (n-type semiconductor region NR), and are transmitted from the drain region (n-type semiconductor region NR) to the plug Pfd and the wiring layer. Taken out to an external circuit.

<Method for Manufacturing Semiconductor Device>
Next, a method for manufacturing the semiconductor device of the present embodiment will be described with reference to FIGS.

  10 and 11 are process flowcharts showing a part of the manufacturing process of the semiconductor device of the present embodiment. 12 to 35 are fragmentary cross-sectional views of the semiconductor device of the present embodiment during the manufacturing process. 12 to 35, FIGS. 12, 14, 16, 18, 20, 20, 22, 24, 26, 28, 30, 30, 32, and 34 correspond to FIG. 8 above. 4 is a cross-sectional view taken along the line AA in FIG. 12 to 35, FIGS. 13, 15, 17, 19, 21, 23, 25, 27, 29, 31, 33, and 35 correspond to FIG. 9 described above. FIG. 7 is a cross-sectional view taken along the line BB in FIG. 6.

  To manufacture the semiconductor device of the present embodiment, first, as shown in FIGS. 12 and 13, a semiconductor substrate (semiconductor wafer) SB is prepared (prepared) (step S1 in FIG. 10).

The semiconductor substrate SB is a semiconductor substrate (semiconductor wafer) made of n-type single crystal silicon into which an n-type impurity such as phosphorus (P) or arsenic (As) is introduced, for example. As another form, the semiconductor substrate SB can be a so-called epitaxial wafer. When the semiconductor substrate SB is an epitaxial wafer, for example, an n-type impurity (for example, phosphorus (P)) is formed on the main surface of an n ⁺ type single crystal silicon substrate into which an n-type impurity (for example, arsenic (As)) is introduced. The semiconductor substrate SB can be formed by growing an epitaxial layer made of n ⁻ type single crystal silicon into which is introduced.

  Next, the element isolation region LCS is formed in the semiconductor substrate SB (Step S2 in FIG. 10).

  The element isolation region LCS is made of an insulating film such as an oxide film. For example, the semiconductor substrate SB is not covered with the silicon nitride film by thermally oxidizing the semiconductor substrate SB in a state where the active regions such as the active region AcTP and the active region AcL are covered with the silicon nitride film. An element isolation region LCS made of a thermal oxide film can be formed on the main surface of the semiconductor substrate SB in the region. Such a method for forming an element isolation region is called a LOCOS (Local oxidation of silicon) method. The active regions such as the active region AcTP and the active region AcL are partitioned (defined) by the element isolation region LCS.

  The element isolation region LCS may be formed using an STI (Shallow Trench Isolation) method instead of the LOCOS method. When the STI method is used, the element isolation region LCS is made of an insulating film (for example, a silicon oxide film) embedded in the trench of the semiconductor substrate SB. For example, the semiconductor substrate SB is covered with a silicon nitride film in regions that become active regions such as the active region AcTP and the active region AcL, and then the semiconductor substrate SB is etched using the silicon nitride film as an etching mask. An element isolation region LCS can be formed by forming a groove for element isolation in SB and then embedding an insulating film such as a silicon oxide film in the groove for element isolation.

  The active region AcTP is formed in the pixel region 1A, and the active region AcL is formed in the peripheral circuit region 2A.

  Next, as shown in FIGS. 14 and 15, a p-type well (p-type semiconductor region) PW1 is formed in the semiconductor substrate SB in the pixel region 1A, and a p-type well (p-type well) is formed in the semiconductor substrate SB in the peripheral circuit region 2A. Type semiconductor region) PW2 is formed (step S3 in FIG. 10).

  The p-type well PW1 is a p-type semiconductor region for forming the photodiode PD, and is also a p-type well region for forming the n-channel type transfer transistor TX. The p-type well PW2 is a p-type well region for forming the n-channel peripheral transistor LT.

  The p-type wells PW1 and PW2 are each formed over a predetermined depth from the main surface of the semiconductor substrate SB. The p-type wells PW1 and PW2 can be formed by ion-implanting a p-type impurity such as boron (B) into the semiconductor substrate SB.

  The p-type well PW1 is formed in the pixel region 1A over a region where the photodiode PD is to be formed and a region where the transfer transistor TX is to be formed. That is, in the pixel region 1A, the p-type well PW1 is formed in the entire active region AcTP. The p-type well PW2 is formed in the peripheral circuit region 2A. The ion implantation for forming the p-type well PW1 and the ion implantation for forming the p-type well PW2 are performed in different ion implantation processes or in the same ion implantation process.

  The conductivity type of the p-type wells PW1 and PW2 is p-type, and is the conductivity type opposite to the n-type which is the conductivity type of the semiconductor substrate SB.

  In the present embodiment, the case where the peripheral transistor LT formed in the peripheral circuit region 2A is an n-channel type MISFET is described. However, the conductivity type is reversed and the peripheral transistor LT is replaced with a p-channel type. It may be a MISFET, or both an n-channel MISFET and a p-channel MISFET may be formed in the peripheral circuit region 2A.

  Next, as shown in FIGS. 16 and 17, in the pixel region 1A, the gate electrode Gt for the transfer transistor TX is formed on the semiconductor substrate SB (p-type well PW1) via the gate insulating film GOX, In the circuit region 2A, the gate electrode Glt for the peripheral transistor LT is formed on the semiconductor substrate SB (p-type well PW2) via the gate insulating film GOX (step S4 in FIG. 10).

  Specifically, step S4 can be performed as follows.

  That is, first, the main surface of the semiconductor substrate SB is cleaned by a cleaning process or the like, and then an insulating film for the gate insulating film GOX is formed on the main surface of the semiconductor substrate SB. The insulating film for the gate insulating film GOX is made of, for example, a silicon oxide film, and can be formed using a thermal oxidation method or the like. As another form, a high dielectric constant insulating film such as a silicon oxynitride film or a metal oxide film (for example, a hafnium oxide film) can be used as the insulating film for the gate insulating film GOX. Then, a conductive film (for example, a polycrystalline silicon film) for a gate electrode is formed on the semiconductor substrate SB, that is, the insulating film for the gate insulating film GOX by using a CVD (Chemical Vapor Deposition) method or the like. The electrode conductive film is patterned using a photolithography method and a dry etching method. Thereby, gate electrodes Gt and Glt made of a patterned conductive film (for example, a polycrystalline silicon film) can be formed. The insulating film for the gate insulating film GOX remaining under the gate electrodes Gt and Glt becomes the gate insulating film GOX. Also, the insulating film for the gate insulating film GOX in the region not covered with the gate electrodes Gt and Glt is removed by dry etching for patterning the conductive film for the gate electrode or wet etching after the dry etching. Can be done. When patterning the conductive film for the gate electrode to form the gate electrodes Gt and Glt, for example, other transistors shown in FIG. 3, that is, the reset transistor RST, the selection transistor SEL, the gate electrode Gr of the amplification transistor AMI, the gate The electrode Gs and the gate electrode Ga can also be formed together.

  The gate electrode Gt functions as a gate electrode of the transfer transistor TX, and is formed on the semiconductor substrate SB (p-type well PW1) via the gate insulating film GOX in the pixel region 1A. The gate insulating film GOX below the gate electrode Gt functions as the gate insulating film of the transfer transistor TX. The gate electrode Glt functions as a gate electrode of the peripheral transistor LT, and is formed on the semiconductor substrate SB (p-type well PW2) via the gate insulating film GOX in the peripheral circuit region 2A. The gate insulating film GOX under the gate electrode Glt functions as the gate insulating film of the peripheral transistor LT.

  Note that the step S4 (gate electrode formation step) is performed after step S3 is performed to form the p-type wells PW1 and PW2, and before step S10 (n-type semiconductor region NR formation step) described later is performed. At some point.

  Next, as shown in FIGS. 18 and 19, an n-type semiconductor region NW is formed by ion implantation in the semiconductor substrate SB in the active region AcTP of the pixel region 1A (step S5 in FIG. 10). The n-type semiconductor region NW can be formed by ion-implanting n-type impurities such as phosphorus (P) or arsenic (As) into the semiconductor substrate SB in the active region AcTP of the pixel region 1A.

  The n-type semiconductor region NW is an n-type semiconductor region for forming the photodiode PD, and the depth of the n-type semiconductor region NW (the bottom surface) is shallower than the depth of the p-type well PW1 (the bottom surface). The n-type semiconductor region NW is formed so as to be enclosed in the p-type well PW1. Since the n-type semiconductor region NW is formed so as to be included in the p-type well PW1, the bottom surface and the side surface of the n-type semiconductor region NW are in contact with the p-type well PW1.

  The n-type semiconductor region NW is not formed in the entire active region AcTP of the pixel region 1A, but is formed on one side (source side) of the regions on both sides of the gate electrode Gt in the semiconductor substrate SB of the active region AcTP. However, it is not formed on the other side (drain side).

  Specifically, the n-type semiconductor region NW can be formed as follows, for example. That is, as shown in FIGS. 18 and 19, first, a photoresist pattern (photoresist layer) RS1 is formed as a resist layer on the semiconductor substrate SB by using a photolithography technique. The photoresist pattern RS1 has an opening OP1 that opens (exposes) one side (source side) of both sides of the gate electrode Gt in the active region AcTP of the pixel region 1A, and the active region of the pixel region 1A. The other side (drain side) of both sides of the gate electrode Gt in AcTP is covered with a photoresist pattern RS1. Then, n-type impurity ions are ion-implanted into the semiconductor substrate SB using the photoresist pattern RS1 as a mask (ion implantation blocking mask). Thereby, in the pixel region 1A, n-type impurities are ion-implanted into the semiconductor substrate SB at a position overlapping the opening OP1 in plan view, whereby the p-type well PW1 is implanted into the semiconductor substrate SB in the active region AcTP of the pixel region 1A. An n-type semiconductor region NW is formed so as to be included in the. Thereafter, the photoresist pattern RS1 is removed.

  In the ion implantation process for forming the n-type semiconductor region NW, as shown in FIG. 19, the photoresist pattern RS1 is formed in the entire peripheral circuit region 2A, that is, in the entire peripheral circuit region 2A. A photoresist pattern RS1 is formed on the semiconductor substrate SB so as to cover the gate electrode Glt. Therefore, in the ion implantation step for forming the n-type semiconductor region NW, the photoresist pattern RS1 functions as a mask (ion implantation blocking mask) in the semiconductor substrate SB (p-type well PW2) in the peripheral circuit region 2A. Therefore, ions are not implanted. That is, at the time of ion implantation for forming the n-type semiconductor region NW, the semiconductor substrate SB other than the region where the n-type semiconductor region NW is to be formed is covered with the photoresist pattern RS1, and the n-type semiconductor region NW is to be formed. An n-type impurity is selectively ion-implanted into the region.

Next, as shown in FIGS. 20 and 21, a p ⁺ -type semiconductor region PR is formed in the semiconductor substrate SB in the active region AcTP of the pixel region 1A by ion implantation (step S6 in FIG. 10).

In step S6, the p ⁺ -type semiconductor region PR is ion-implanted with a cluster (B _x H _y , where x and y are integers of 2 or more) composed of a plurality of boron atoms and a plurality of hydrogen atoms into the semiconductor substrate SB. To form.

p ⁺ -type semiconductor region PR is, p-type impurity is a semiconductor region of p ⁺ -type introduced (doped) at a high concentration, impurity concentration (p-type impurity concentration) of the p ⁺ -type semiconductor region PR is, p-type well It is higher than the impurity concentration of PW1 (p-type impurity concentration). Since the p ⁺ type semiconductor region PR is formed by ion-implanting a cluster (B _x H _y ) composed of a plurality of boron atoms and a plurality of hydrogen atoms into the semiconductor substrate SB, it is introduced into the p ⁺ type semiconductor region PR. The formed p-type impurity is mainly boron (B: boron).

The depth of the p ⁺ type semiconductor region PR (the bottom surface thereof) is shallower than the depth of the n type semiconductor region NW (the bottom surface thereof). The p ⁺ type semiconductor region PR is mainly formed in the surface layer portion (surface region) of the n type semiconductor region NW. Therefore, when viewed in the thickness direction of the semiconductor substrate SB, the n-type semiconductor region NW exists under the uppermost p ⁺ -type semiconductor region PR, and the p-type well PW1 exists under the n-type semiconductor region NW. It becomes a state.

In addition, when a cluster (B _x H _y ) composed of a plurality of boron atoms and a plurality of hydrogen atoms is ion-implanted into the semiconductor substrate SB in step S6, a plurality of boron atoms constituting the cluster (B _x H _y ) are formed. (B) The atoms and the plurality of hydrogen (H) atoms are dispersed in the semiconductor substrate SB (p ⁺ type semiconductor region PR). For this reason, in the semiconductor substrate SB to be the p ⁺ type semiconductor region PR, boron (B) does not exist in a cluster state, but individual boron (B) atoms exist in a dispersed state.

Specifically, the p ⁺ type semiconductor region PR can be formed as follows, for example. That is, as shown in FIGS. 20 and 21, first, a photoresist pattern (photoresist layer) RS2 is formed as a resist layer on the semiconductor substrate SB by using a photolithography technique. The photoresist pattern RS2 has an opening OP2 that opens (exposes) a p ⁺ -type semiconductor region PR formation region in the active region AcTP of the pixel region 1A. Then, using this photoresist pattern RS2 as a mask (ion implantation blocking mask), a cluster (B _x H _y , where x and y are each 2 consisting of a plurality of boron atoms and a plurality of hydrogen atoms is formed on the semiconductor substrate SB. The above integer) is ion-implanted. As a result, in the pixel region 1A, the cluster (B _x H _y ) is ion-implanted into the semiconductor substrate SB (specifically, the surface layer portion of the n-type semiconductor region NR) at a position overlapping the opening OP2 in plan view. Thus, the p ⁺ type semiconductor region PR is formed in the semiconductor substrate SB (specifically, the surface layer portion of the n type semiconductor region NW) of the active region AcTP in the pixel region 1A. Thereafter, the photoresist pattern RS2 is removed.

In the ion implantation step for forming the p ⁺ type semiconductor region PR, as shown in FIG. 21, the photoresist pattern RS2 is formed in the entire peripheral circuit region 2A, that is, the entire peripheral circuit region 2A. , A photoresist pattern RS2 is formed on the semiconductor substrate SB so as to cover the gate electrode Glt. For this reason, in the ion implantation process for forming the p ⁺ type semiconductor region PR, the photoresist pattern RS2 functions as a mask (ion implantation blocking mask) in the semiconductor substrate SB (p type well PW2) in the peripheral circuit region 2A. Therefore, ions are not implanted. That is, when the ion implantation for forming the p ⁺ -type semiconductor region PR includes a semiconductor substrate SB other than the p ⁺ -type semiconductor region PR formation region is previously covered with photoresist pattern RS2, p ⁺ -type semiconductor region A cluster (B _x H _y ) composed of a plurality of boron atoms and a plurality of hydrogen atoms is selectively ion-implanted into the PR formation planned region.

In the region where the n-type semiconductor region NW is not formed, a part of the p ⁺ -type semiconductor region PR is in contact with the p-type well PW1. That is, the p ⁺ type semiconductor region PR includes a portion where the n-type semiconductor region NW exists immediately below and contacts the n-type semiconductor region NW, and a portion where the p-type well PW1 exists immediately below and contacts the p-type well PW1. And have.

The p-type well PW1 is a p-type semiconductor region for forming the photodiode PD, the n-type semiconductor region NW is an n-type semiconductor region for forming the photodiode PD, and the p ⁺ -type semiconductor region PR is , A p-type semiconductor region for forming the photodiode PD. A photodiode (PN junction diode) PD is formed by the p-type well PW1 (p-type semiconductor region), the n-type semiconductor region NW, and the p ⁺ -type semiconductor region PR. A PN junction is formed between the p-type well PW1 and the n-type semiconductor region NW, and a PN junction is formed between the p ⁺ -type semiconductor region PR and the n-type semiconductor region NW.

  The photodiode (PN junction diode) PD is mainly formed by the n-type semiconductor region NW and the p-type well PW1 (that is, by a PN junction between the n-type semiconductor region NW and the p-type well PW1). Further, since the n-type semiconductor region NW also functions as a source region of the transfer transistor TX, it is preferable that a part of the n-type semiconductor region NW overlaps with the gate electrode Gt of the transfer transistor TX in plan view. The transfer transistor TX is a transfer transistor that transfers the charge generated by the photodiode PD. The photodiode PD is a light receiving element. The photodiode PD can also be regarded as a photoelectric conversion element.

A p ⁺ type semiconductor region PR is formed in a part of the surface of the n type semiconductor region NW. The p ⁺ type semiconductor region PR is mainly based on interface states formed in large numbers on the surface of the semiconductor substrate SB. This is a region formed for the purpose of suppressing the generation of electrons. That is, in the surface region of the semiconductor substrate SB, electrons are generated due to the influence of the interface state even in a state where no light is irradiated, thereby causing an increase in dark current. For this reason, by forming a p ⁺ type semiconductor region PR having holes as majority carriers on the surface of the n-type semiconductor region NW having electrons as majority carriers, electrons in a state where no light is irradiated. Can be suppressed, and an increase in dark current can be suppressed.

In addition, after the p ⁺ type semiconductor region PR is formed by ion implantation in step S6, it is preferable to perform an annealing process for recovering crystal defects (mainly crystal defects caused by ion implantation), that is, a heat treatment. By this annealing treatment, crystal defects in the n-type semiconductor region NW and the p ⁺ -type semiconductor region PR can be recovered.

  The annealing process (heat treatment) performed after the ion implantation in step S6 can be performed by, for example, laser annealing, microwave annealing, RTA (Rapid thermal anneal), furnace annealing, or a combination thereof. The temperature of the annealing process (heat treatment) performed after the ion implantation in step S6 can be set to about 300 to 1200 ° C., for example. Here, laser annealing is annealing (heat treatment) by irradiating laser, microwave annealing is annealing (heat treatment) by irradiating microwave, and RTA is a short time using lamp heating or the like. It is annealing and furnace annealing is annealing (heat treatment) by heating in an annealing furnace.

In this embodiment, annealing treatment (heat treatment) is performed after the ion implantation in step S6. After the annealing treatment (heat treatment) is performed, the boron (B) atoms implanted in step S6 are p ⁺ type. In the semiconductor region PR, it is located at a silicon site (Si lattice point) of the silicon crystal constituting the semiconductor substrate SB (see FIG. 36 described later). Therefore, in the p ⁺ type semiconductor region PR, boron (B) does not exist in a cluster state, but a part of the Si site (Si lattice point) of the silicon crystal is replaced with boron (B) atoms. It will be in the state.

Further, the annealing process (heat treatment) performed after the ion implantation in step S6 recovers the crystal defects in the ion-implanted regions (for example, the n-type semiconductor region NW and the p ⁺ -type semiconductor region PR) and removes the implanted impurities. It can also be activated.

Further, after the p ⁺ -type semiconductor region PR are formed by ion implantation in the step S6, it is preferable to perform annealing treatment for recovering crystal defects such as p ⁺ -type semiconductor region PR (heat treatment), annealing at this point When the treatment is not performed, annealing treatment (heat treatment) is performed at any stage of the subsequent steps. In addition, after forming by ion implantation in step S6, if annealing is not performed until step S11 described later, annealing processing (heat treatment) in step S11 described later recovers crystal defects such as the p ⁺ type semiconductor region PR. It also serves as an annealing process for the

Next, as shown in FIGS. 22 and 23, in the peripheral circuit region 2A, n ⁻ type semiconductor regions (source / drain extension regions) in the semiconductor substrate SB (p-type well PW2) on both sides of the gate electrode Glt. NM is formed by ion implantation (step S7 in FIG. 10).

Specifically, the n ⁻ type semiconductor region NM can be formed as follows, for example. That is, as shown in FIGS. 22 and 23, first, a photoresist pattern (photoresist layer) RS3 that opens (exposes) the peripheral circuit region 2A as a resist layer on the semiconductor substrate SB is formed using a photolithography technique. Form. Then, using the photoresist pattern RS3 as a mask (ion implantation blocking mask), an n-type impurity such as phosphorus (P) or arsenic (As) is added to the semiconductor substrate SB (p-type well PW2) in the peripheral circuit region 2A. Ion implantation. At this time, since the gate electrode Glt functions as a mask (ion implantation blocking mask) in the peripheral circuit region 2A, impurity implantation is prevented in the region immediately below the gate electrode Glt in the semiconductor substrate SB. Therefore, an n ⁻ type semiconductor region NM is formed by ion-implanting an n type impurity into the regions on both sides of the gate electrode Glt in the semiconductor substrate SB (p type well PW2) in the peripheral circuit region 2A. Thereafter, the photoresist pattern RS3 is removed.

In the ion implantation process for forming the n ⁻ type semiconductor region NM, as shown in FIG. 22, in the pixel region 1A, the photoresist pattern RS3 is formed on the semiconductor substrate SB including the surface of the gate electrode Gt. Is formed. That is, the active region AcTP in the pixel region 1A is covered with the photoresist pattern RS3. For this reason, in the ion implantation process for forming the n ⁻ type semiconductor region NM, the photoresist pattern RS3 functions as a mask (ion implantation blocking mask) in the semiconductor substrate SB in the active region AcTP, so that ions are not implanted. For this reason, in the ion implantation step for forming the n ⁻ type semiconductor region NM, ions are not implanted into the p type well PW1, the n type semiconductor region NW, and the p ⁺ type semiconductor region PR of the active region AcTP.

  Next, as shown in FIGS. 24 and 25, a cap insulating film CP is formed on the semiconductor substrate SB in the pixel region 1A (step S8 in FIG. 11).

The cap insulating film CP can be formed, for example, by forming an insulating film on the main surface of the semiconductor substrate SB and then patterning the insulating film using a photolithography method and a dry etching method. The cap insulating film CP can be formed of, for example, a silicon oxide film or a silicon nitride film. Cap insulating film CP is formed on the surfaces (exposed surfaces) of n type semiconductor region NW and p ⁺ type semiconductor region PR. The cap insulating film CP is formed to keep the surface characteristics of the semiconductor substrate SB, that is, the interface characteristics good.

  Next, an antireflection film ARF and a sidewall spacer SW are formed (step S9 in FIG. 11). The antireflection film ARF is formed on the cap insulating film CP, and the side wall spacer SW is formed on the side walls of the gate electrodes Gt and Glt.

  The antireflection film ARF and the sidewall spacer SW can be formed, for example, as follows. That is, first, the insulating film ZM is formed on the main surface of the semiconductor substrate SB so as to cover the gate electrodes Gt and Glt. This insulating film ZM also serves as an insulating film for forming the antireflection film ARF and an insulating film for forming the sidewall spacer SW. Then, a photoresist pattern (not shown) is formed on the insulating film ZM in a region where the antireflection film ARF is to be formed by using a photolithography technique. Then, using the photoresist pattern as a mask (etching mask), the insulating film ZM is etched back by anisotropic etching. Accordingly, the insulating film ZM is locally left on the side walls of the gate electrodes Gt and Glt, thereby forming the sidewall spacer SW and leaving the insulating film ZM under the photoresist pattern, thereby preventing the antireflection film ARF. Form. Thereafter, the photoresist pattern is removed, and this stage is shown in FIGS.

The antireflection film ARF is formed on the n-type semiconductor region NW and the p ⁺ type semiconductor region PR via the cap insulating film CP, and a part (end part) of the antireflection film ARF runs on the gate electrode Gt. You can also.

  Sidewall spacers SW are formed on both side walls of the gate electrode Glt. For the gate electrode Gt, the side wall spacers SW are formed on the side walls on the drain side (floating diffusion FD side) on both side walls of the gate electrode Gt. Is formed. The side wall on the source side of the gate electrode Gt is covered with the antireflection film ARF.

  Here, the case where the antireflection film ARF and the sidewall spacer SW are formed in the same process using the same insulating film ZM will be described, and FIGS. 24 and 25 correspond to that case.

As another form, the antireflection film ARF and the sidewall spacer SW can be formed in separate steps. In that case, first, an insulating film for forming the sidewall spacer SW is formed on the semiconductor substrate SB so as to cover the gate electrodes Gt and Glt, and then the insulating film is etched back by anisotropic etching. Sidewall spacers SW are formed on both side walls of the gate electrodes Gt and Glt. Then, after forming the cap insulating film CP on the surfaces of the n-type semiconductor region NW and the p ⁺ -type semiconductor region PR, an insulating film for the antireflection film ARF is formed on the semiconductor substrate SB, and the insulating film is formed. By patterning, the antireflection film ARF can be formed. In this case, the side wall spacer SW is formed on both side walls of the gate electrode Gt, and the antireflection film ARF covers the side wall spacer SW on the side wall on the source side of the gate electrode Gt, and a part of the antireflection film ARF. The (end part) rides on the gate electrode Gt.

  Next, as shown in FIGS. 26 and 27, in the active region AcTP of the pixel region 1A, in the semiconductor substrate SB (p-type well PW1) on the other side (drain side) of both sides of the gate electrode Gt. The n-type semiconductor region NR is formed by ion implantation (step S10 in FIG. 11). The drain side corresponds to the side opposite to the side where the n-type semiconductor region NW is formed.

  In the ion implantation process for forming the n-type semiconductor region NR, since the antireflection film ARF and the gate electrode Gt can function as a mask (ion implantation prevention mask), the antireflection film ARF and the gate electrode Gt of the semiconductor substrate SB Implantation of impurities is prevented in the region immediately below. As a result, as shown in FIG. 26, the semiconductor substrate on the other side (the drain side, that is, the side opposite to the side where the n-type semiconductor region NW is formed) of both sides of the gate electrode Gt of the transfer transistor TX. An n-type semiconductor region NR can be formed in SB (p-type well PW1). Further, ion implantation for forming the n-type semiconductor region NR can be performed in a state where the antireflection film ARF is covered with a photoresist layer (not shown). In this case, the n-type semiconductor region NR is scheduled to be formed. The region is exposed from the photoresist layer.

  Accordingly, the n-type semiconductor region NW is formed on one side (source side) of the active region AcTP on both sides of the gate electrode Gt in the semiconductor substrate in step S5 and on the other side (drain side) in step S10. An n-type semiconductor region NR is formed.

  The n-type semiconductor region NW and the n-type semiconductor region NR are formed so as to be separated from each other with a channel formation region (corresponding to a substrate region immediately below the gate electrode Gt) of the transfer transistor TX interposed therebetween. The n-type semiconductor region NR is an n-type high concentration semiconductor region that functions as a drain region of the transfer transistor TX. The n-type semiconductor region NR functions as a drain region of the transfer transistor TX, but can also be regarded as a floating diffusion (floating diffusion layer) FD.

In step S10, in the peripheral circuit region 2A, an n ⁺ type semiconductor region SD is formed by ion implantation in the semiconductor substrate SB (p-type well PW2) on both sides of the composite of the gate electrode Glt and the sidewall spacer SW. To do. At the time of ion implantation for forming the n ⁺ type semiconductor region SD, the gate electrode Glt and the sidewall spacer SW on the sidewall thereof can function as a mask (ion implantation blocking mask). Therefore, the regions on both sides of the composite gate electrode Glt and the sidewall spacers SW in the semiconductor substrate SB in the peripheral circuit region 2A (p-type well PW2), by which the n-type impurity is ion-implanted, n ⁺ -type A semiconductor region SD is formed.

n ⁺ -type semiconductor region SD is, n ^- -type semiconductor regions the same conductivity type as NM but (here n-type) is a semiconductor region of, n ^- -type than semiconductor regions NM, higher impurity concentration (n-type impurity concentration) And the depth (junction depth) is deep. As a result, in the peripheral circuit region 2A, a semiconductor region (source / drain region) functioning as a source or drain of the peripheral transistor LT is formed by the n ⁺ type semiconductor region SD and the n ⁻ type semiconductor region NM. Therefore, the source / drain regions of the peripheral transistor LT have an LDD structure.

The n-type semiconductor region NR and the n ⁺ -type semiconductor region SD can be formed by the same ion implantation process, but can also be formed by separate ion implantation.

Further, by using this step S10, for example, the other transistors shown in FIG. 3, that is, the source / drain regions of the reset transistor RST, the selection transistor SEL, and the amplification transistor AMI can be formed. The source / drain regions of the reset transistor RST, selection transistor SEL, and amplification transistor AMI can be formed by the same ion implantation process as one or both of the n-type semiconductor region NR and the n ⁺ -type semiconductor region SD. The region NR and the n ⁺ type semiconductor region SD can be formed by ion implantation different from those of the region NR and the n ⁺ type semiconductor region SD.

Further, when a p-channel type MISFET is formed in the peripheral circuit region 2A, a p ⁺ type semiconductor region that becomes a source / drain region of the p-type MISFET may be formed in the peripheral circuit region 2A. For example, by implanting p-type impurities into n-type wells on both sides of a gate electrode of a p-channel MISFET (not shown) in the peripheral circuit region 2A, a p ⁺ -type semiconductor region serving as a source / drain region of the p-type MISFET is formed. Can be formed. At this time, p-type impurities may be ion-implanted into the active region AcG.

  Next, annealing treatment (heat treatment) for activating the impurities introduced by the conventional ion implantation is performed (step S11 in FIG. 11).

  Through the above steps, the photodiode PD, the transfer transistor TX, and other transistors not shown in the cross-sectional views of FIGS. 26 and 27, that is, the reset transistor RST, the selection transistor SEL, and the amplification are formed in each pixel region 1A of the semiconductor substrate SB. A transistor AMI is formed (see FIG. 3 above). Further, a peripheral transistor LT as a MISFET is formed in the peripheral circuit region 2A of the semiconductor substrate SB.

Next, as shown in FIGS. 28 and 29, the salicide (Salicide: Self Aligned Silicide) technique is used to upper the n-type semiconductor region NR and the n ⁺ -type semiconductor region SD (surface layer portion) and the upper portion of the gate electrode Glt. A low-resistance metal silicide layer SIL is formed on the (surface layer portion) or the like (step S12 in FIG. 11).

In order to form the metal silicide layer SIL, for example, a metal film for forming a metal silicide layer is formed on the semiconductor substrate SB, and then the heat treatment is performed to form the metal film in the n-type semiconductor regions NR, n ^+. After reacting with the surface layer portion of the type semiconductor region SD and the gate electrode Glt, the unreacted portion of the metal film is removed. Thereby, the metal silicide layers SIL can be formed on the n-type semiconductor region NR and the n ⁺ -type semiconductor region SD (surface layer portion), on the gate electrode Glt (surface layer portion), and the like. At this time, the gate electrode Gr, the gate electrode Gs and the gate electrode Ga, and the upper portions of the source / drain regions of the other transistors shown in FIG. 3, for example, the reset transistor RST, the selection transistor SEL, and the amplification transistor AMI The metal silicide layer SIL can also be formed on the (surface layer portion). By forming the metal silicide layer SIL, diffusion resistance, contact resistance, and the like can be reduced.

In addition, before forming the metal film for forming the metal silicide layer, an insulating film (silicide block film) may be formed so as to cover the silicon substrate region and the gate electrode that do not require silicidation. Since the metal film for forming the metal silicide layer is not in contact with the silicon substrate region and the gate electrode covered with the insulating film, the metal silicide layer SIL is not formed. For example, after forming an insulating film (silicide block film) that covers the gate electrode Gt and the antireflection film ARF and exposes the n-type semiconductor region NR, the n ⁺ -type semiconductor region SD, and the gate electrode Glt, the metal silicide is formed. A metal film for forming a layer is formed and heat treatment is performed. Thereby, the metal silicide layer SIL is formed on the n-type semiconductor region NR, the n ⁺ -type semiconductor region SD, and the gate electrode Glt, but is not formed on the gate electrode Gt.

Further, the metal silicide layer SIL may not be formed, or among the n-type semiconductor region NR, the n ⁺ -type semiconductor region SD, and the gate electrode Glt, the one that forms the metal silicide layer SIL and the one that does not form the metal silicide layer SIL. It can also be provided. The subsequent FIGS. 30 to 35 illustrate the case where the metal silicide layer SIL is not formed, that is, the case where the step of forming the metal silicide layer SIL in step S12 is omitted. In FIGS. A silicide layer SIL may be formed.

  Next, as shown in FIGS. 30 and 31, an interlayer insulating film IL1 is formed as an insulating film on the main surface (entire main surface) of the semiconductor substrate SB (step S13 in FIG. 11). That is, the interlayer insulating film IL1 is formed over the semiconductor substrate SB so as to cover the gate electrodes Gt and Glt, the sidewall spacer SW, and the antireflection film ARF. As the interlayer insulating film IL1, for example, a silicon oxide film can be deposited on the semiconductor substrate SB by a CVD method using TEOS (tetraethyl orthosilicate) gas as a source gas.

  After the interlayer insulating film IL1 is formed, the upper surface of the interlayer insulating film IL1 is planarized by polishing the surface (upper surface) of the interlayer insulating film IL1 by a CMP (Chemical Mechanical Polishing) method. You can also. By polishing the surface of the interlayer insulating film IL1 after the film formation by the CMP method even when the surface of the interlayer insulating film IL1 is uneven due to the base step at the stage of forming the interlayer insulating film IL1. The interlayer insulating film IL1 whose surface is planarized can be obtained.

  Next, as shown in FIGS. 32 and 33, the interlayer insulating film IL1 is dry-etched using a photoresist pattern (not shown) formed on the interlayer insulating film IL1 as an etching mask, thereby providing interlayer insulation. Contact holes (through holes, holes, openings) CT are formed in the film IL1 (step S14 in FIG. 11).

The contact hole CT is formed so as to penetrate the interlayer insulating film IL1. The contact hole CT is formed, for example, on the n-type semiconductor region NR or the n ⁺ -type semiconductor region SD. At the bottom of the contact hole CT formed on the n-type semiconductor region NR, the surface of the n-type semiconductor region NR (if the metal silicide layer SIL is formed above the n-type semiconductor region NR, the metal silicide layer SIL Part of the surface is exposed. Further, the n ⁺ -type semiconductor region the bottom of the contact hole CT formed on the SD, when n ⁺ -type semiconductor region SD of the surface (n ⁺ -type semiconductor region the metal silicide layer SIL on top of the SD is formed that A part of the surface of the metal silicide layer SIL is exposed. Although not shown, contact holes CT are also formed on the gate electrodes Gt and Glt, and the other transistors shown in FIG. 3, that is, the gate electrodes of the reset transistor RST, the selection transistor SEL, and the amplification transistor AMI. Contact holes CT are also formed on (Gr, Gs, Ga) and the source / drain regions.

  Next, a conductive plug PG made of tungsten (W) or the like is formed in the contact hole CT as a conductive portion for connection (step S15 in FIG. 11). The plug PG can be formed as follows, for example.

  To form the plug PG, first, a barrier conductor film is formed on the interlayer insulating film IL1 including the inside of the contact hole CT (on the bottom surface and the inner wall). This barrier conductor film is made of, for example, a laminated film of a titanium film and a titanium nitride film formed on the titanium film (that is, a titanium / titanium nitride film), and can be formed using a sputtering method or the like. Then, a main conductor film made of a tungsten film or the like is formed by CVD or the like so as to fill the contact hole CT on the barrier conductor film. Thereafter, unnecessary main conductor film and barrier conductor film outside the contact hole CT (on the interlayer insulating film IL1) are removed by a CMP method, an etch back method, or the like. As a result, the upper surface of the interlayer insulating film IL1 is exposed, and the plug PG is formed by the barrier conductor film and the main conductor film that remain buried in the contact hole CT of the interlayer insulating film IL1. For simplification of the drawings, in FIGS. 32 and 33, the barrier conductor film and the main conductor film constituting the plug PG are shown integrally.

The plugs PG include the plugs Pr1, Pr2, Pg, Pfd, Pa, Ps, Prg, Ptg, Pag, Psg, Pt1, and Pt2. Among these, the plug Pfd is embedded in the contact hole CT formed on the n-type semiconductor region NR, penetrates the interlayer insulating film IL1, reaches the n-type semiconductor region NR, and is electrically connected to the n-type semiconductor region NR. Connected. Further, each of plugs Pt1, Pt2, ^{n +} -type semiconductor region is embedded on the contact hole CT formed in SD, it reaches the ^{n +} -type semiconductor region SD through the interlayer insulating film IL1, ^{n +} It is electrically connected to the type semiconductor region SD.

  Next, as shown in FIGS. 34 and 35, interlayer insulating films IL2 to IL4 and wirings M1 to M3 are formed on the interlayer insulating film IL1 in which the plug PG is embedded.

  For example, a stacked film of a silicon nitride film and a silicon oxide film over the silicon nitride film is formed as an interlayer insulating film IL2 over the interlayer insulating film IL1 by using a CVD method or the like, and then the photolithography is applied to the stacked film. A wiring trench is formed using a technique and a dry etching technique. Then, a barrier conductor film is formed on the interlayer insulating film IL2 including the inside of the wiring trench (on the bottom surface and the inner wall). This barrier conductor film is made of, for example, a laminated film of a tantalum (Ta) film and a tantalum nitride (TaN) film on the tantalum film, and can be formed using a sputtering method or the like. Then, after depositing a thin copper film as a seed film on the barrier conductor film by a sputtering method or the like, a copper plating film is deposited as a main conductor film on the seed film by an electrolytic plating method. Embed the inside. Then, unnecessary copper plating film, seed film, and barrier conductor film outside the wiring trench (on the interlayer insulating film IL2) are removed by CMP or the like, so that copper is used as the main conductive material in the wiring trench. A layer wiring M1 is formed. For simplification of the drawings, in FIG. 34 and FIG. 35, the copper plating film, the seed layer, and the barrier conductor film constituting the wiring M1 are shown integrally. Thus, the wiring M1 can be formed by embedding the barrier film, the seed film, and the copper plating film in the wiring groove.

  Further, similarly, as shown in FIGS. 34 and 35, an interlayer insulating film IL3 is formed on the interlayer insulating film IL2 on which the wiring M1 is formed, and a wiring M2 is formed in the interlayer insulating film IL3. An interlayer insulating film IL4 is formed on the interlayer insulating film IL3 on which the layer is formed, and a wiring M3 is formed in the interlayer insulating film IL4. The wiring M1 is formed by a single damascene method, but the wiring M2 and the wiring M3 can be formed by a single damascene method or a dual damascene method.

  In the interlayer insulating film IL3, a via portion that is disposed between the wiring M2 and the wiring M1 and connects the wiring M2 and the wiring M1 is also formed. In the interlayer insulating film IL4, the wiring M3 and the wiring M2 are formed. Is also formed between the wiring M3 and the wiring M2. When the wiring M2 is formed by the dual damascene method, the via portion connecting the wiring M2 and the wiring M1 is integrally formed with the wiring M2 together with the wiring M2, but the wiring M2 is formed by the single damascene method. In this case, the via portion that connects the wiring M2 and the wiring M1 is formed separately from the wiring M2. Similarly, when the wiring M3 is formed by the dual damascene method, the via portion connecting the wiring M3 and the wiring M2 is formed integrally with the wiring M3 together with the wiring M3. However, the wiring M3 is formed by the single damascene method. In this case, the via portion that connects the wiring M3 and the wiring M2 is formed separately from the wiring M3.

  Next, as shown in FIG. 34, a microlens ML as an on-chip lens is attached on the uppermost interlayer insulating film IL4 so as to overlap the n-type semiconductor region NW constituting the photodiode PD in plan view. . A color filter may be provided between the microlens ML and the interlayer insulating film IL4. Further, if unnecessary, the attachment of the microlens ML can be omitted.

  Through the above steps, the semiconductor device of this embodiment can be manufactured.

<About the problem of this embodiment>
As a solid-state image sensor, development of a solid-state image sensor (CMOS image sensor) using a CMOS is underway. This CMOS image sensor includes a plurality of pixels each having a photodiode and a transfer transistor. In the CMOS image sensor device, in order to improve the processing performance of the sensor, it is desired to reduce the peripheral circuit and improve the operation speed. On the other hand, in the CMOS image sensor device, since the imaging sensitivity is proportional to the capacitance of the photodiode, if the capacitance area (junction area) of the photodiode is reduced by miniaturization, the imaging sensitivity is lowered. A decrease in imaging sensitivity leads to a decrease in performance of the semiconductor device. For this reason, it is desirable to increase the imaging sensitivity as much as possible, and in order to increase the imaging sensitivity, it is desirable to increase the capacitance area (junction area) of the photodiode as much as possible. On the other hand, in the CMOS image sensor device, it is necessary to reduce the power supply voltage with miniaturization. However, reducing the power supply voltage makes it difficult to transfer the charge accumulated in the photodiode through the transfer transistor. . Therefore, in order to maintain the imaging sensitivity without deteriorating the transfer characteristic of the charge accumulated in the photodiode, the structural design of the photodiode is important.

  A generally used photodiode is a pnp-type embedded photodiode and has a structure in which electrons are accumulated in an n-type layer (an n-type layer corresponding to the n-type semiconductor region NW in the present embodiment). The planar dimensions of the photodiode are limited by the chip size, the number of pixels, and the like. Therefore, in order to increase the capacitance of the photodiode, it is effective to increase the depth of the n-type layer (the n-type layer corresponding to the n-type semiconductor region NW in the present embodiment). Increasing the depth of the n-type layer increases the area of the pn junction that constitutes the photodiode, so that the capacitance of the photodiode can be increased and the imaging sensitivity can be improved. However, simply increasing the depth of the n-type layer leads to difficulty in transferring charges accumulated in the photodiode via the transfer transistor. This deteriorates the transfer characteristic of the charge accumulated in the photodiode, and causes a transfer failure of the charge accumulated in the photodiode when the power supply voltage is lowered. This leads to a decrease in the performance of the semiconductor device.

Therefore, the present inventor makes it possible to accurately transfer the charge accumulated in the photodiode via the transfer transistor, and in order to improve the imaging sensitivity, the uppermost p-type layer (in the pnp type photodiode ( It has been found that it is effective to form a shallow p-type layer corresponding to the p ⁺ -type semiconductor region PR of the present embodiment. In a pnp type photodiode, if the uppermost p-type layer is made shallow without changing the depth of the n-type layer, the area of the pn junction constituting the photodiode increases, so that the capacitance of the photodiode can be increased. Imaging sensitivity can be improved. Further, even if the uppermost p-type layer in the pnp photodiode is shallow, the transfer characteristic of the charge accumulated in the photodiode is not deteriorated. For this reason, the performance of the semiconductor device can be improved.

However, when the uppermost p-type layer in the pnp-type photodiode (p-type layer corresponding to the p ⁺ -type semiconductor region PR in the present embodiment) is formed by ion implantation of B (boron), the atomic weight of ions to be implanted Is small, channeling phenomenon is likely to occur. Here, the channeling phenomenon is a phenomenon in which implanted ions reach a deep position of the semiconductor substrate through a gap in the atomic arrangement. If a channeling phenomenon occurs by ion implantation for forming the uppermost p-type layer (p-type layer corresponding to the p ⁺ -type semiconductor region PR) in the pnp-type photodiode, the p-type layer (p ⁺ -type semiconductor region) It becomes difficult to form a shallow and uniform p-type layer corresponding to PR. Further, when an uppermost p-type layer (p-type layer corresponding to the p ⁺ -type semiconductor region PR) of the pnp photodiode is to be formed shallowly, the p-type layer (p ⁺ corresponding to the p ⁺ -type semiconductor region PR) is formed. It is necessary to reduce the implantation energy for ion implantation for forming the mold layer). However, if the implantation energy is small, it is difficult to stably generate an ion beam at the time of ion implantation. is there. Therefore, it is difficult to shallow p-type layer of the top layer in a pnp photodiode (p-type layer corresponding to the p ⁺ -type semiconductor region PR), forcibly to its p-type layer (p ⁺ -type semiconductor region PR If an attempt is made to make the corresponding p-type layer shallow, the performance of the semiconductor device and the manufacturing yield of the semiconductor device are reduced.

<Main features and effects of the present embodiment>
Therefore, in this embodiment, a technique of ion-implanting a cluster composed of a plurality of boron (B) atoms and a plurality of hydrogen (H) atoms is employed as ion implantation for forming the p ⁺ type semiconductor region PR. This is one of the assertive features of the present embodiment. That is, in step S6, the p ⁺ type semiconductor region PR is formed by ion-implanting a cluster composed of a plurality of boron (B) atoms and a plurality of hydrogen (H) atoms.

  Here, a cluster composed of a plurality of boron (B) atoms and a plurality of hydrogen (H) atoms can be regarded as a molecule composed of a plurality of boron (B) atoms and a plurality of hydrogen (H) atoms. A cluster composed of a plurality of boron (B) atoms and a plurality of hydrogen (H) atoms can also be regarded as a cluster of boron hydride.

A cluster composed of a plurality of boron (B) atoms and a plurality of hydrogen (H) atoms can be expressed as B _x H _y (where x and y are integers of 2 or more, respectively). That is, in step S6, B _x H _y, which is a molecule composed of x boron (B) atoms and y hydrogen (H) atoms (where x and y are integers of 2 or more, respectively) is ion-implanted. As a result, the p ⁺ type semiconductor region PR is formed.

The number of boron (B) atoms contained in the cluster (molecule) to be ion-implanted in step S6 is 2 or more (that is, x is an integer of 2 or more when expressed as B _x H _y ), but ion implantation is performed in step S6. It is more preferable if the number of boron (B) atoms contained in the cluster (molecule) is 5 or more (that is, x is an integer of 5 or more when expressed as B _x H _y ).

Examples of clusters (molecules) to be ion-implanted in step S6 include B ₁₀ H ₁₄ (decaborane) or B ₁₈ H ₂₂ (octadecaborane). Here, B ₁₀ H ₁₄ (decaborane) is a molecule composed of 10 boron (B) atoms and 14 hydrogen (H) atoms, and B ₁₈ H ₂₂ (octadecaborane) consists of 18 A molecule composed of boron (B) atoms and 22 hydrogen (H) atoms.

In the present embodiment, the p ⁺ type semiconductor region PR is formed by ion implantation of a cluster (B _x H _y ) composed of a plurality of boron atoms and a plurality of hydrogen atoms. Effects can be obtained.

That is, when ions are implanted into a cluster, the implantation energy is increased to reflect an increase in mass per cluster. When the implantation energy is large, an ion beam at the time of ion implantation can be stably generated, so that ion implantation can be performed stably. In this embodiment, for forming the p ⁺ -type semiconductor region PR by a cluster of a plurality of boron atoms and a plurality of hydrogen atoms (B x _{H y)} is ion-implanted, shallow p ⁺ -type semiconductor region PR Even so, since the ion implantation energy can be increased, an ion beam can be stably generated, and ion implantation for forming the p ⁺ -type semiconductor region PR can be performed stably. . Thereby, even if the p ⁺ type semiconductor region PR is shallow, the p ⁺ type semiconductor region PR can be stably and accurately formed. Therefore, the performance of the semiconductor device can be improved. In addition, the manufacturing yield of the semiconductor device can be improved.

In addition, when ion implantation is performed on clusters, the collision energy increases reflecting the increase in mass per cluster, which leads to less channeling phenomenon. This is because when the collision energy is large, an amorphous layer is likely to be formed on the surface layer portion of the semiconductor substrate into which ions are implanted, and when the amorphous layer is formed, channeling phenomenon is less likely to occur. In the present embodiment, the p ⁺ type semiconductor region PR is formed by ion implantation of a cluster (B _x H _y ) composed of a plurality of boron atoms and a plurality of hydrogen atoms, thereby forming the p ⁺ type semiconductor region PR. It is possible to suppress or prevent the occurrence of a channeling phenomenon at the time of ion implantation for forming. Thereby, the p ⁺ type semiconductor region PR can be formed shallowly and uniformly. Therefore, the performance of the semiconductor device can be improved. In addition, the manufacturing yield of the semiconductor device can be improved.

Further, if boron (B) is present in the form of clusters in the p ⁺ type semiconductor region PR, the crystal is distorted, which leads to an increase in dark current. Further, if boron (B) is present in the form of clusters in the p ⁺ type semiconductor region PR, defects (transition) are likely to occur, which also leads to an increase in dark current. This may lead to a decrease in performance of the semiconductor device and a decrease in manufacturing yield of the semiconductor device.

In the present embodiment, the p ⁺ type semiconductor region PR is formed by ion implantation of a cluster (B _x H _y ) composed of a plurality of boron atoms and a plurality of hydrogen atoms. When a cluster (B _x H _y ) composed of a plurality of boron atoms and a plurality of hydrogen atoms is ion-implanted into the semiconductor substrate SB, a plurality of boron (B) atoms constituting the cluster (B _x H _y ) The plurality of hydrogen (H) atoms are dispersed and dispersed in the semiconductor substrate SB. That is, the cluster _(B x _{H y)} until impinging on the semiconductor substrate SB is the state of the cluster of a plurality of boron (B) atoms and a plurality of hydrogen (H) atoms _(B x _{H y)} are maintained However, when the cluster (B _x H _y ) collides with the semiconductor substrate SB, a plurality of boron (B) atoms and a plurality of hydrogen (H) atoms constituting the cluster (B _x H _y ) are separated. It enters and diffuses into the semiconductor substrate SB. That is, in the semiconductor substrate SB that becomes the p ⁺ type semiconductor region PR, boron does not exist in a cluster state, but individual boron atoms exist in a dispersed state.

When an annealing process (heat treatment) for recovering crystal defects is performed after the ion implantation in step S6 (that is, ion implantation for forming the p ⁺ type semiconductor region PR), as schematically shown in FIG. in implanted boron (B) atom is step S6, the ^{p +} -type semiconductor region PR, the silicon of the silicon crystal constituting the semiconductor substrate SB ^{(p +} -type semiconductor region PR) (Si) sites (the lattice point of silicon) It will be in the state located. That is, the p ⁺ type semiconductor region PR is in a state where a part of the Si site (silicon lattice point) of the silicon crystal is replaced with a boron (B) atom. Here, FIG. 36 is an explanatory view schematically showing the crystal structure of the p ⁺ type semiconductor region PR. At this time, in the p ⁺ type semiconductor region PR, boron (B) atoms are uniformly dispersed to some extent, and atoms adjacent to each boron (B) atom are silicon (Si) atoms. In the p ⁺ -type semiconductor region PR, boron (B) does not exist in the form of clusters, but individual boron (B) atoms exist in a dispersed manner, so that it is easy to prevent crystal distortion and defects. , Dark current can be suppressed or prevented.

In the present embodiment, the p ⁺ type semiconductor region PR is formed by cluster ion implantation in step S6. As a cluster to be implanted, a cluster (a cluster composed of a plurality of boron (B) atoms and a plurality of hydrogen (H) atoms ( it is important to use a B _x H _y). A cluster (B _x H _y ) in which a plurality of boron (B) atoms and a plurality of hydrogen (H) atoms are bonded to each other has a weak bonding force, so that the bonds are broken when they are injected into the semiconductor substrate SB. Prone. In this embodiment, in step S6, a cluster (B _x H _y ) composed of a plurality of boron (B) atoms and a plurality of hydrogen (H) atoms, that is, a plurality of boron (B) atoms and a plurality of hydrogen (H ) By implanting a cluster (B _x H _y ) in which atoms are bonded to each other, boron (B) does not exist in a cluster state in the p ⁺ type semiconductor region PR, but individual boron (B) The atoms are dispersed and exist. That is, when a plurality of boron (B) consisting of atoms and a plurality of hydrogen (H) atom cluster _(B x _{H y)} are ion-implanted into the semiconductor substrate SB in step S6, constitute a cluster _(B x _{H y)} The plurality of boron (B) atoms and the plurality of hydrogen (H) atoms that have been dispersed are dispersed in the semiconductor substrate SB (p ⁺ type semiconductor region PR). Thereby, in the p ⁺ type semiconductor region PR, crystal distortion and defects (transition) can be prevented, and dark current can be suppressed or prevented more accurately. Therefore, the performance of the semiconductor device can be improved. In addition, the manufacturing yield of the semiconductor device can be improved.

In step S6, ion implantation for forming the p ⁺ type semiconductor region PR is performed. As the ion implantation, a cluster (B _x H) composed of a plurality of boron (B) atoms and a plurality of hydrogen (H) atoms is used. _When the ion implantation of _y ) is used, the activation rate of the implanted boron (B) atoms can be increased as compared with the case where the cluster ion implantation is not used. For this reason, the effect of suppressing dark current by the p ⁺ type semiconductor region PR can be enhanced. In addition, the occurrence of white spots (dark white spots) can be suppressed. In addition, the amount of dose at the time of ion implantation can be reduced as the activation rate increases, and the amount of damage at the time of ion implantation (damage of the substrate region into which ions are implanted) can be reduced by the amount that can be reduced. Therefore, the p ⁺ type semiconductor region PR can be formed more accurately, and the dark current suppression effect by the p ⁺ type semiconductor region PR can be enhanced. Therefore, the performance of the semiconductor device can be improved. In addition, the manufacturing yield of the semiconductor device can be improved.

FIG. 37 is a graph showing a result of comparing the sheet resistance of the p-type semiconductor region corresponding to the p ⁺ -type semiconductor region PR. Here, the graph of FIG. 37 shows the case where a p-type semiconductor region corresponding to the p ⁺ -type semiconductor region PR is formed using ion implantation of B _x H _y (x and y are each an integer of 2 or more). The sheet resistance of the p-type semiconductor region and the sheet resistance of the p-type semiconductor region when a p-type semiconductor region corresponding to the p ⁺ -type semiconductor region PR is formed by ion implantation of B (boron) are shown. . As shown in the graph of FIG. 37, when ion implantation of a cluster (B _x H _y ) composed of a plurality of boron (B) atoms and a plurality of hydrogen (H) atoms is used, cluster ion implantation is not used. Compared to the case, the sheet resistance of the p-type semiconductor region (corresponding to the p ⁺ -type semiconductor region PR) formed by ion implantation can be lowered. This is because the ion implantation of a cluster (B _x H _y ) composed of a plurality of boron (B) atoms and a plurality of hydrogen (H) atoms is implanted as compared with the case where cluster ion implantation is not used. This suggests that the activation rate of boron (B) atoms is increased.

FIG. 38 is a graph showing the result of comparing the sheet resistance of the n-type semiconductor region corresponding to the n-type semiconductor region NW. Here, in the graph of FIG. 38, the p-type semiconductor corresponding to the p ⁺ -type semiconductor region PR using the same implantation energy and ion implantation of B _x H _y (x and y are each an integer of 2 or more). The n-type semiconductor region corresponding to the n-type semiconductor region NW when the region is formed and when the p-type semiconductor region corresponding to the p ⁺ -type semiconductor region PR is formed using B (boron) ion implantation. Sheet resistance is shown. If the implantation energies are the same, as shown in the graph of FIG. 38, when the B _x H _y cluster ion implantation is used to form the p-type semiconductor region corresponding to the p ⁺ -type semiconductor region PR. The sheet resistance of the n-type semiconductor region corresponding to the n-type semiconductor region NW can be reduced as compared with the case where cluster ion implantation is not used. This is because the p-type semiconductor region corresponding to the p ⁺ -type semiconductor region PR is formed by using B _x H _y cluster ion implantation as compared with the case where no cluster ion implantation is used. This suggests that the effective thickness of the n-type semiconductor region corresponding to the semiconductor region NW is increased, thereby reducing the sheet resistance of the n-type semiconductor region. That, p ⁺ -type semiconductor to form the region PR in the case of using a cluster ion implantation B _x H _y, in comparison with the case of using no cluster ion implantation, p ⁺ -type semiconductor region PR shallow and high activity This suggests that the effective thickness of the n-type semiconductor region NW under the p ⁺ -type semiconductor region PR can be increased. Increasing the effective thickness of the n-type semiconductor region NW increases the effective area of the pn junction (the pn junction between the p-type well PW1 and the n-type semiconductor region NW) constituting the photodiode PD. Leading to an improvement in imaging sensitivity.

FIG. 39 is a graph showing a result of comparing dark currents, and FIG. 40 is a graph showing a result of comparing white dot occurrence rates. Here, the “comparative example” shown in FIGS. 39 and 40 is different from the present embodiment in that boron ions are used without ion implantation of B _x H _y (x and y are integers of 2 or more, respectively). This corresponds to the case where the p ⁺ type semiconductor region PR is formed by implantation. Further, “Embodiment 1” shown in FIGS. 39 and 40 corresponds to the case where the p ⁺ type semiconductor region PR is formed by using ion implantation of B _x H _y (x and y are integers of 2 or more, respectively). doing. As shown in the graphs of FIGS. 39 and 40, the dark current can be reduced by forming the p ⁺ type semiconductor region PR by using ion implantation of B _x H _y (x and y are integers of 2 or more, respectively). It is possible to suppress the occurrence of white spots. The effect of suppressing dark current and the effect of suppressing generation of white spots obtained by forming the p ⁺ type semiconductor region PR by ion implantation of B _x H _y (x and y are each an integer of 2 or more) are p ^This effect is obtained regardless of the depth of the ⁺ type semiconductor region PR.

Further, in the ion implantation for forming the p ⁺ -type semiconductor region PR, if the dose amount is too large, there is a concern that damage at the time of ion implantation is large, leading to an increase in dark current and white spots. For this reason, the p ⁺ type semiconductor region PR is formed by ion-implanting a cluster (B _x H _y ) composed of a plurality of boron (B) atoms and a plurality of hydrogen (H) atoms in step S6. Is preferably 1 × 10 ¹⁴ / cm ² or less, for example, about 1 × 10 ¹³ to 1 × 10 ¹⁴ / cm ² . The dose referred to here corresponds to the number of boron (B) atoms implanted per 1 cm ² area. Thereby, since the damage at the time of ion implantation in step S6 can be reduced, the effect of suppressing dark current by the p ⁺ type semiconductor region PR can be accurately enhanced. Moreover, generation | occurrence | production of a white spot can be suppressed exactly. Therefore, the performance of the semiconductor device can be improved. In addition, the manufacturing yield of the semiconductor device can be improved.

In the present embodiment, the p ⁺ type semiconductor region PR is formed by ion-implanting clusters (B _x H _y ) composed of a plurality of boron (B) atoms and a plurality of hydrogen (H) atoms in step S6. Thus, it is possible to prevent problems when the depth of the p ⁺ type semiconductor region PR is reduced. For example, as described above, the channeling phenomenon at the time of ion implantation can be prevented, and the ion beam at the time of ion implantation can be stably generated. For this reason, in the present embodiment, the shallow p ⁺ type semiconductor region PR can be accurately formed.

Therefore, this embodiment has a great effect when applied to the case where the depth of the p ⁺ type semiconductor region PR is reduced. Then, by reducing the depth of the p ⁺ type semiconductor region PR, the effective area of the pn junction (pn junction between the p type well PW1 and the n type semiconductor region NW) constituting the photodiode PD is increased. Therefore, the capacitance of the photodiode PD can be increased. In addition, the saturation charge amount of the photodiode PD can be increased. Thereby, imaging sensitivity can be improved. Further, even if the depth of the p ⁺ type semiconductor region PR is reduced, the transfer characteristic of the charge accumulated in the photodiode PD is not deteriorated. Therefore, the performance of the semiconductor device can be improved. In addition, the manufacturing yield of the semiconductor device can be improved.

For this reason, the present embodiment is highly effective when applied to a case where the depth of the p ⁺ type semiconductor region PR is reduced, and in particular, the p ⁺ type semiconductor region PR formed in step S6 of the semiconductor substrate SB. The effect is particularly great when applied when the depth T1 from the surface is 30 nm or less (T1 ≦ 30 nm). Incidentally, ^{p +} -type semiconductor region depth T1 of the PR is shown in Figure 20, when forming the ^{p +} -type semiconductor region PR in step S6, from the surface of the semiconductor substrate SB in ^{the p +} -type semiconductor region PR It corresponds to the distance (depth) to the bottom. Therefore, in other words, in the present embodiment, when the p ⁺ type semiconductor region PR is formed in step S6, the distance (that is, the depth) from the surface of the semiconductor substrate SB to the bottom surface of the p ⁺ type semiconductor region PR. The effect is particularly great when T1) is 30 nm or less (T1 ≦ 30 nm). In the region where the p ⁺ type semiconductor region PR is formed, the surface of the semiconductor substrate SB is the upper surface of the p ⁺ type semiconductor region PR. Therefore, the depth T1 of the p ⁺ type semiconductor region PR is determined in step S6. It can also be regarded as the thickness of the formed p ⁺ type semiconductor region PR.

If the depth T1 of the ^{p.sup. +} type semiconductor region PR is set to 30 nm or less (T1.ltoreq.30 nm), if cluster ion implantation is not used, a channeling phenomenon occurs and an ion beam is stably generated during ion implantation. For example, the p ⁺ type semiconductor region PR cannot be formed successfully. On the other hand, in this embodiment, the p ⁺ type semiconductor region PR is obtained by ion-implanting a cluster (B _x H _y ) composed of a plurality of boron (B) atoms and a plurality of hydrogen (H) atoms in step S6. By forming the p ⁺ type semiconductor region PR, the p ⁺ type semiconductor region PR can be accurately formed even if the depth T1 of the p ⁺ type semiconductor region PR is 30 nm or less (T1 ≦ 30 nm). Therefore, in the present embodiment, the p ⁺ type semiconductor region PR having a depth of 30 nm or less can be accurately formed. Therefore, the effect of reducing the depth of the p ⁺ type semiconductor region PR, for example, a photodiode The effect of increasing the capacitance of the photodiode PD by increasing the effective area of the pn junction constituting the PD and improving the imaging sensitivity can be enjoyed without causing any problems.

Further, the depth T1 of the p ⁺ type semiconductor region PR formed in step S6 from the surface of the semiconductor substrate SB is more preferably 5 nm or more (T1 ≧ 5 nm). That is, in this embodiment, when the p ⁺ type semiconductor region PR is formed in step S6, the distance from the surface of the semiconductor substrate SB to the bottom surface of the p ⁺ type semiconductor region PR (that is, the depth T1) is 5 nm or more ( (T1 ≧ 5 nm) is more preferable. As a result, the dark current suppressing effect due to the provision of the p ⁺ type semiconductor region PR can be obtained accurately.

Therefore, the depth T1 of the p ⁺ type semiconductor region PR formed in step S6 from the surface of the semiconductor substrate SB is most preferably 5 nm or more and 30 nm or less (5 nm ≦ T1 ≦ 30 nm).

  Further, the depth T2 of the n-type semiconductor region NW formed in step S5 from the surface of the semiconductor substrate SB can be set to, for example, about 0.2 to 1 μm (that is, 0.2 μm ≦ T2 ≦ 1 μm). Note that the depth T2 of the n-type semiconductor region NW is shown in FIG. 18, and from the surface of the semiconductor substrate SB to the bottom surface of the n-type semiconductor region NW when the n-type semiconductor region NW is formed in step S5. It corresponds to the distance (depth).

In the present embodiment, by forming the p ⁺ type semiconductor region PR by ion implantation of B _x H _y (x and y are each an integer of 2 or more), the effect of preventing channeling phenomenon during ion implantation, Although an effect of stably generating an ion beam at the time of implantation can be obtained, this is a particularly beneficial effect when the shallow p ⁺ type semiconductor region PR is formed. Furthermore, by forming the p ⁺ type semiconductor region PR by ion implantation of B _x H _y (x and y are each an integer of 2 or more), the effect of suppressing dark current and the effect of suppressing the generation of white spots can be obtained. but this is the p ⁺ type when semiconductor region PR is shallow, of course, even if the p ⁺ -type semiconductor region PR is not shallow, an effect obtained. Therefore, this embodiment is particularly effective when applied to the formation of a shallow p ⁺ type semiconductor region PR, but is effective even when the p ⁺ type semiconductor region PR is not shallow.

(Embodiment 2)
In the first embodiment, the example in which the semiconductor device is a surface irradiation type image sensor that receives light from the surface side of the semiconductor substrate has been described. On the other hand, in the second embodiment, an example will be described in which the semiconductor device is a backside illumination type image sensor in which light is incident from the backside of the semiconductor substrate.

  For example, in a front-illuminated image sensor (corresponding to the semiconductor device of the first embodiment), light incident on the microlens (ML) is transmitted through an interlayer insulating film (IL1 to IL4) and is a photodiode (PD). Is irradiated. Wirings (M1 to M3) are not formed in the portions of the interlayer insulating films (IL1 to IL4) located above the photodiodes (PD) and serve as light transmission regions. As the number of pixels is increased and the size is reduced, the area of the light transmission region is reduced, and in the surface irradiation type image sensor, the amount of light incident on the photodiode may be reduced.

  In view of this, a back-illuminated image sensor has been proposed in which light is incident from the back side of the semiconductor substrate and the incident light efficiently reaches the photodiode. In the second embodiment, an application example to this back-illuminated image sensor will be described.

  Regarding the configuration of the semiconductor device of the second embodiment and the element structure of the peripheral circuit region, the configuration of the semiconductor device of the first embodiment described with reference to FIGS. 1 to 7 and FIG. This is the same as the element structure in the circuit region, and the description thereof is omitted.

<Element structure of pixel region>
Next, the element structure of the pixel region of the semiconductor device according to the second embodiment will be described. FIG. 41 is a cross-sectional view showing a configuration of the semiconductor device of Second Embodiment. 41 is a main-portion cross-sectional view of the semiconductor device according to the second embodiment, which substantially corresponds to the cross-sectional view taken along the line AA in FIG. 3, and corresponds to FIG. 8 in the first embodiment. To do.

  As shown in FIG. 41, a photodiode PD and a transfer transistor TX are formed on a semiconductor substrate SB, and interlayer insulating films (IL1 to IL4) are formed on the surface side of the semiconductor substrate SB (corresponding to the lower side in FIG. 41). The second embodiment is the same as the first embodiment in that the wiring layers (M1 to M3) are formed. Further, in the second embodiment, as shown in FIG. 41, the adhesion film OXF is formed under the interlayer insulating film (IL4), and the support substrate SS is arranged under the adhesion film OXF. Has been.

In the second embodiment, the thickness of the semiconductor substrate SB is thinner than the thickness of the semiconductor substrate SB in the first embodiment, and the back surface of the semiconductor substrate SB (the upper side in FIG. 41). For example, an antireflection film ARF made of a silicon oxynitride film is formed, and a microlens ML is mounted on the antireflection film ARF. A p ⁺ type semiconductor region may be formed between the semiconductor substrate SB and the antireflection film ARF.

  In the pixel region 1A configured as described above, when light is incident on the microlens ML, the light incident on the microlens ML reaches the back surface of the semiconductor substrate SB via the antireflection film ARF. Then, the light that reaches the back surface of the semiconductor substrate SB enters the semiconductor substrate SB and is irradiated to the photodiode PD.

<Method for Manufacturing Semiconductor Device>
Next, a method for manufacturing the semiconductor device according to the second embodiment will be described. Hereinafter, a manufacturing process in the pixel region will be described. 42 to 47 are fragmentary cross-sectional views of the semiconductor device of the second embodiment during the manufacturing steps thereof. 42 to 47 are cross-sectional views corresponding to FIG. 41, that is, cross-sectional views at positions corresponding to the AA line in FIG.

  In the second embodiment, the same processes (steps S1 to S9) as those of the first embodiment are performed except that the antireflection film ARF is not formed, and the structure of FIG. 42 corresponding to FIG. 26 is obtained. . As shown in FIG. 42, in the second embodiment, sidewall spacers SW are formed on both sidewalls of the gate electrode Gt, but the antireflection film ARF is not yet formed on the semiconductor substrate SB. . In the second embodiment, the antireflection film ARF is formed in the process of FIG. 47 described later.

  Next, as shown in FIG. 43, also in the second embodiment, step S10 is performed to form an n-type semiconductor region NR. Since the formation position and function of the n-type semiconductor region NR are basically the same as in the first embodiment, the repeated description thereof is omitted here. The step S10 can be performed in the second embodiment in substantially the same manner as the first embodiment. However, in the second embodiment, since the antireflection film ARF is not formed, the transfer transistor TX is configured. Ion implantation is performed to form an n-type semiconductor region NR with the source side covered with a photoresist layer (not shown) on both sides of the gate electrode Gt and the drain side exposed from the photoresist layer.

  Next, also in the second embodiment, similarly to the first embodiment, the steps S11 to S15 and the steps of forming the interlayer insulating films IL2 to IL4 and the wirings M1 to M3 are performed, as shown in FIG. Get the structure. The steps S11 to S15 and the steps of forming the interlayer insulating films IL2 to IL4 and the wirings M1 to M3 are basically the same as those of the first embodiment. Then, the repeated explanation is omitted. However, in the second embodiment, the antireflection film ARF is not yet formed.

  FIG. 44 shows the case where the metal silicide layer SIL is not formed above the n-type semiconductor region NR, but the metal silicide layer SIL is formed above the n-type semiconductor region NR. You can also.

  Next, as shown in FIG. 45, the surface of the interlayer insulating film IL4 on which the wiring M3 is formed is directed downward, and the surface of the interlayer insulating film IL4 is formed on the surface of the interlayer insulating film IL4 via, for example, an adhesion film OXF made of a silicon oxide film. A support substrate SS is disposed. Accordingly, the stacked structure including the semiconductor substrate SB and the insulating films IL1 to 1L4 is fixed to the support substrate SS with the back surface of the semiconductor substrate SB facing upward. Then, as shown in FIG. 46, the back surface of the semiconductor substrate SB facing upward is ground. Thereby, the thickness of the semiconductor substrate SB can be reduced.

Next, as shown in FIG. 47, an antireflection film ARF made of, for example, a silicon oxynitride film is formed on the back surface of the semiconductor substrate SB. In addition, by using a photolithography technique and an ion implantation method, a p-type impurity such as boron (B) is introduced into the back surface facing the top surface side of the semiconductor substrate SB, and the semiconductor substrate SB, the antireflection film ARF, A p ⁺ type semiconductor region may be formed between the two.

  Next, as shown in FIG. 47, the microlens ML is attached on the antireflection film ARF so as to overlap with the n-type semiconductor region NW constituting the photodiode PD in plan view. As described above, the semiconductor device as the image sensor according to the second embodiment can be manufactured.

  In the second embodiment, the method for forming the photodiode PD and the transistor is the same as that in the first embodiment. For this reason, also in this Embodiment 2, the effect similar to having demonstrated in the said Embodiment 1 can be acquired.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

1A Pixel region 2A Peripheral circuit region AcAS, AcG, AcL, AcR, AcTP Active region AMI Amplifying transistor ARF Antireflection film AP Output amplifier CHP Chip region CLC Column circuit CP Cap insulating film CT Contact hole FD Floating diffusion Ga, Glt, Gr, Gs, Gt Gate electrode GND Ground potential GOX Gate insulating film HSC Horizontal scanning circuit IL1, IL2, IL3, IL4 Interlayer insulating film LCS Element isolation region LGND Ground potential line LRST Reset line LT Peripheral transistor LTX Transfer line LVDD Power supply potential line M1, M2 , M3 wiring ML micro lens N1 node NM n ⁻ type semiconductor region NR, NW n type semiconductor region OL output line OP1, OP2 opening OXF adhesion film Pa, Pag, Pfd, Pg, Pr1, Pr2, Pr g plug PD photodiode PG plug PR p ⁺ type semiconductor region Ps, Psg, Pt1, Pt2, Ptg plug PU pixel PW1, PW2 p type well RS1, RS2, RS3 photoresist pattern RST reset transistor SB semiconductor substrate SD n ⁺ type semiconductor Region SEL Select transistor SIL Metal silicide layer SL Select line SS Support substrate SWT Switch SW Side wall spacer TX Transfer transistor VDD Power supply potential VSC Vertical scanning circuit WF Semiconductor wafer

Claims (7)

(A) preparing a semiconductor substrate;
(B) forming a p-type first semiconductor region for a photodiode in the semiconductor substrate;
(C) forming an n-type second semiconductor region for the photodiode in the semiconductor substrate;
(D) forming a p-type third semiconductor region in the semiconductor substrate;
Have
The second semiconductor region is included in the first semiconductor region;
The third semiconductor region is formed in a surface layer portion of the second semiconductor region,
In the step (d), the third semiconductor region is formed by ion-implanting a cluster composed of a plurality of boron atoms and a plurality of hydrogen atoms. In the manufacturing method of the semiconductor device according to claim 1,
(E) forming a gate electrode of a transfer transistor for transferring charges generated by the photodiode on the semiconductor substrate via a gate insulating film;
(F) forming a drain region of the transfer transistor in the semiconductor substrate;
Further comprising
The method of manufacturing a semiconductor device, wherein the second semiconductor region also functions as a source region of the transfer transistor. The method of manufacturing a semiconductor device according to claim 2.
When the cluster is ion-implanted into the semiconductor substrate in the step (d), a plurality of boron atoms and a plurality of hydrogen atoms constituting the cluster are dispersed in the semiconductor substrate. . In the manufacturing method of the semiconductor device according to claim 3,
(G) a step of performing a heat treatment after the step (d),
Further comprising
After performing the step (g), the boron atom implanted in the step (d) is located in a silicon site of a silicon crystal constituting the semiconductor substrate in the third semiconductor region. Manufacturing method. In the manufacturing method of the semiconductor device according to claim 1,
The depth of the third semiconductor region formed in the step (d) from the surface of the semiconductor substrate is 30 nm or less. In the manufacturing method of the semiconductor device according to claim 1,
The method for manufacturing a semiconductor device, wherein an impurity concentration of the third semiconductor region is higher than an impurity concentration of the first semiconductor region. In the manufacturing method of the semiconductor device according to claim 1,
A method of manufacturing a semiconductor device, wherein a part of the third semiconductor region is in contact with the first semiconductor region.

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