JP2008084516A - Semiconductor memory device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor memory device which reduces loading of global lines by dividing bank regions in the read and write operations and generates bank strobe signals in the bank area which is not in a peripheral area. <P>SOLUTION: The semiconductor storage device includes: a global input/output line; a 1st global core line; a 2nd global core line; a global core line controller disposed between the global input/output line and the 1st and 2nd global core lines; a 1st bank coupled to the global core line controller through the 1st global core line; and a 2nd bank coupled to the global core line controller through the 2nd global core line. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor design technique, and more particularly, to a semiconductor memory device having a multi bank.

  In recent years, DRAMs (Dynamic Random Access Memory) have been increased in memory density from 256M to 512M and from 512M to 1G in order to increase performance, and the cost has also increased. In addition, the conventional 4-bank structure has been developed to support the 8-bank structure and the 8-bank structure to the 16-bank structure.

  As described above, there are various problems in the increase in the degree of integration and the multi-bank. In the present invention, in order to transmit the data inputted from the outside to the cell of the designated bank, the write global is transmitted. I / O lines (hereinafter referred to as “WGIO_IO”), write global core lines (hereinafter referred to as “WGIO_CORE”), and read globals that transmit data in order to transmit data of cells in a specified bank to the outside A core line (hereinafter “RGIO_CORE”) and a read global input / output line (hereinafter “RGIO_IO”) will be described.

  FIG. 1 is a block diagram for explaining a layout of a part of a conventional DRAM, in particular, having a memory capacity of 512M, 8 banks BANK0, BANK1, BANK2, BANK3, BANK4, BANK5, BANK6, BANK7, A DRAM having an “x32” operation mode (with 32 DQ pads) in which data is read and written by 32 bits by one column operation and having a 4-bit prefetch architecture is shown. Yes.

  For reference, the DRAM has a multi-bit input / output path designed in accordance with a data option mode (for example, x4, x8, x16, x32). For this reason, even semiconductor memory devices having the same capacity may have different configurations. In other words, the semiconductor memory device is designed and manufactured to satisfy all of the “x4”, “x8”, “x16”, and “x32” operation modes, and then an optional process is performed to finally obtain “x4”. ”,“ X8 ”,“ x16 ”, and“ x32 ”modes of operation.

  As shown in FIG. 1, the entire 512M memory is divided into four quarters QA, QB, QC, and QD. Each quarter QA, QB, QC, QD in the unit of 128M performs a data read operation and a write operation via a corresponding pad (DQ <0:31>). That is, the “QA” quarter corresponds to “DQ <0: 7>”, the “QB” quarter corresponds to “DQ <8:15>”, and the “QC” quarter corresponds to “DQ <16:23”. > ”And the“ QD ”quarter performs a read operation and a write operation corresponding to“ DQ <24:31> ”, respectively.

  For example, in the case of a write operation in the “x32” operation mode, data input to 32 pads (DQ <0:31>) are stored in banks (BANK0, BANK1, Any one of BANK2, BANK3, BANK4, BANK5, BANK6, and BANK7). On the other hand, in the case of a read operation, it corresponds from each bank (any one of BANK0, BANK1, BANK2, BANK3, BANK4, BANK5, BANK6, BANK7) corresponding to each quarter QA, QB, QC, QD. 32-bit data is output via the pad (DQ <0:31>).

  On the other hand, the strobe decoder 10 arranged in the center of the chip receives a bank strobe signal MSTROBE_BANK <0: 7> that activates the corresponding bank among the banks BANK0, BANK1, BANK2, BANK3, BANK4, BANK5, BANK6, and BANK7. The data is output and provided to the central side 20A, 20B, 20C, 20D of each quarter QA, QB, QC, QD. As shown in FIG. 1, the central side 20A, 20B, 20C, 20D of each quarter QA, QB, QC, QD is shown as one block, but in effect receives the bank strobe signal MSTROBE_BANK <0: 7>. A read / write strobe signal generator (to be described with reference to FIG. 3), an input data buffer (to be described with reference to FIG. 4), and an output data buffer (to be described with reference to FIG. 5). Has been.

  FIG. 2 is a block diagram for explaining the strobe decoder 10 of FIG.

  As shown in the figure, the strobe decoder 10 includes a column strobe signal STROBE_PRE that is activated during a column operation in a read operation and a write operation, and eight banks BANK0, BANK1, BANK2, BANK3, BANK4, BANK5, BANK6, BANK7 information (CAST <0: 2>) is received and a bank strobe signal MSTROBE_BANK <0: 7> is output.

  The read / write strobe signal generation unit 23A in FIG. 3 reads, for example, a bank strobe signal MSTROBE_BANK <0> for activating the bank indicated by “BANK0” from the 8-bit bank strobe signal MSTROBE_BANK <0: 7>. The write signal WTRZT is received, and the read strobe signal RSTROBE_BANK <0> and the write strobe signal WSTROBE_BANK <0> corresponding to the corresponding bank are output.

  Here, the read / write signal WTRZT is a signal that becomes a logic “high” in the case of a write operation, and a logic “low” in the case of a read operation. Therefore, when the read or write operation is determined, the read strobe signal RSTROBE_BANK <0: 7> or the write strobe signal WSTROBE_BANK <0: 7> corresponding to each bank is generated according to the bank strobe signal MSTROBE_BANK <0: 7>. As a result, the selected bank becomes active, and a read operation and a write operation are performed.

  On the other hand, the read / write strobe signal generation unit 23A uses the first delay for more stable timing matching of the read strobe signal RSTROBE_BANK <0: 7> and the write strobe signal WSTROBE_BANK <0: 7> in the read operation and the write operation. A part D1 and a second delay part D2 are provided.

  Again, a more detailed conventional structure and operation will be described with reference to FIG.

  For convenience of explanation, the “QA” quarter will be mainly described. Also, the write global input / output lines WGIO_IO_EV0 <0: 7>, WGIO_IO_OD0 <0: 7>, WGIO_IO_EV1 <0: 7>, WGIO_IO_OD1 <0: connected to the pad DQ <0: 7> corresponding to the “QA” quarter. 7>, read global I / O lines RGIO_IO_EV0 <0: 7>, RGIO_IO_OD0 <0: 7>, RGIO_IO_EV1 <0: 7>, RGIO_IO_OD1 <0: 7>, write global core line WGIO_CORE_EV0 <0: connected to each bank 7>, WGIO_CORE_OD0 <0: 7>, WGIO_CORE_EV1 <0: 7>, WGIO_CORE_OD1 <0: 7>, and read global core lines RGIO_CORE_EV0 <0: 7>, RGIO_CORE_OD0 <0: 7>, RGIO_COR _EV1 <0: 7>, RGIO_CORE_OD1 <0: 7>, because it is intended for a 4-bit prefetch operation, hereinafter, prefetch operations will be omitted. That is, among the write global input / output lines WGIO_IO_EV0 <0: 7>, WGIO_IO_OD0 <0: 7>, WGIO_IO_EV1 <0: 7>, and WGIO_IO_OD1 <0: 7> that transmit data during the write operation, “WGIO_IO_EV0 <0”. : 7> ”as representatives of the write global core lines WGIO_CORE_EV0 <0: 7>, WGIO_CORE_OD0 <0: 7>, WGIO_CORE_EV1 <0: 7>, WGIO_CORE_OD1 <0: 7> A write global core line indicated by “WGIO_CORE_EV0 <0: 7>” will be described as a representative. Further, among the read global core lines RGIO_CORE_EV0 <0: 7>, RGIO_CORE_OD0 <0: 7>, RGIO_CORE_EV1 <0: 7>, and RGIO_CORE_OD1 <0: 7> that transmit data during the read operation, “RGIO_CORE_EV0 <0: “RGIO_IO_EV0 <0: 7>, RGIO_IO_EV0 <0: 7>, RGIO_IO_EV1 <0: 7>, and RGIO_IO_OD1 <0: 7> as representatives of the read global core line indicated by“ 7> ”. This will be described using a read global input / output line indicated by <0: 7> ”.

  Hereinafter, the write operation will be described. The 8-bit data input from the outside to the corresponding “QA” quarter bank is written via the “DQ <0: 7>” pad, and the write global input / output line WGIO_IO_EV0 <0: 7>. Is input. This input data is input to the input data buffer and transmitted to the corresponding bank that has become active via the write global core line WGIO_CORE_EV0 <0: 7>.

  FIG. 4 is a circuit diagram for explaining the input data buffer 21A. Hereinafter, for the convenience of description, the write global input / output line indicated by “WGIO_IO_EV0 <0>” among the write global input / output lines WGIO_IO_EV0 <0: 7> will be described as a representative. Further, among the write global core lines WGIO_CORE_EV0 <0: 7>, the write global core line indicated by “WGIO_CORE_EV0 <0>” will be described as a representative.

  The input data buffer 21A includes inverters INV1 and INV2 that buffer data input through the write global input / output line WGIO_IO_EV0 <0>, and inverters INV3 and INV4 that repeat data. The data write global core line WGIO_CORE_EV0 < Output to 0>.

  The read operation will be described again with reference to FIG.

  For example, 8-bit data in the bank indicated by “BANK0” is input to the read data buffer via the read global core line RGIO_CORE_EV0 <0: 7>, and the output signal of the read data buffer is read global input / output line RGIO_IO_EV0 <0. : Is transmitted to the pad DQ <0: 7> via 7> and output.

  FIG. 5 is a circuit diagram for explaining the output data buffer 22A. Hereinafter, for convenience of explanation, the read global input / output line indicated by “RGIO_IO_EV0 <0>” among the read global input / output lines RGIO_IO_EV0 <0: 7> will be described as a representative. Further, among the read global core lines RGIO_CORE_EV0 <0: 7>, the read global core line indicated by “RGIO_CORE_EV0 <0>” will be described as a representative.

  The output data buffer 22A shown in FIG. 5 includes inverters INV5 and INV6 that repeat data input via the read global core line RGIO_CORE_EV0 <0>, and inverters INV7 and INV8 that buffer the data. Output to line RGIO_IO_EV0 <0>.

  As described above, in recent years, the degree of integration tends to increase from 512M to 1G and multi-banks from 8 banks to 16 banks. Thus, in the conventional structure, loading and junction of each global line (junction) ) Is more than doubled, a timing delay of data moving through each global line and a voltage level slope occur, and eventually a normal operation cannot be performed.

The bank strobe signal MSTROBE_BANK <0: 7> output from the strobe decoder 10 located in the center of the chip, that is, in the peripheral (peri) region, increases as the number of banks increases, and the global line transmitting the signal The number also increases and the shielding line increases. Eventually, there arises a problem that the layout becomes large.
JP-A-10-199292 JP 2006-173643 A

  The present invention has been made to solve the above-mentioned problems of the prior art, and its purpose is to reduce the loading of global lines to be used by partitioning the bank area during read and write operations. Another object of the present invention is to provide a semiconductor memory device that generates a bank strobe signal in a bank region that is not a peripheral region.

  To achieve the above object, the present invention provides a global input / output line, a first global core line, a second global core line, the global input / output line, a first global core line, and a second global core line. A global core line controller formed between, a first bank connected via the global core line controller and the first global core line, and the global core line controller and the second global core line. And a second bank connected through the semiconductor memory device.

  Preferably, the global core line controller controls the first global core line and the second global core line separately.

  In the present invention, for example, a global core line controller arranged in the center of the “QA” quarter is divided into a left area bank and a right area bank, and data is transmitted during a read operation and a write operation. Reduce global core line loading. In particular, during a read operation, the global core line connected to the selected bank region transmits data, and the global core lines connected to other bank regions are precharged. In addition, by generating a bank strobe signal in the bank region, the global lines that transmit the signal are reduced.

  That is, in the first invention, a global input / output line, a first global core line, a second global core line, and the global input / output line are formed between the first global core line and the second global core line. A global core line controller, a first bank connected via the global core line controller and the first global core line, and a global bank line controller connected via the global core line controller and the second global core line. A semiconductor memory device comprising a second bank is provided.

  According to a second aspect of the invention, there is provided a semiconductor memory device based on the first aspect, wherein the global core line controller controls the first global core line and the second global core line separately. To do.

  In a third invention, based on the first invention, the first global core line further comprises a first read global core line and a first write global core line, and the second global core line is a second read global line. Provided is a semiconductor memory device comprising a core line and a second write global core line.

  The fourth invention is based on the third invention, and further transmits data via any one of the first read global core line and the second read global core line during the read operation, One read global core line is precharged to provide a semiconductor memory device.

  In a fifth aspect based on the third aspect, the global core line controller further responds to the first bank information and the second bank information, the read strobe signal and the write strobe signal, Provided is a semiconductor memory device comprising bank activation means for activating any one of the second banks.

  The sixth invention is based on the fifth invention, and further receives the read / write information and the strobe signal for the column operation, and becomes active during the read operation and the read strobe signal during the write operation. And a read / write strobe signal activating means for outputting the write strobe signal that becomes active.

  In a seventh aspect based on the fifth aspect, the global core line controller further comprises the first read global core line and the first read global core line in response to the read strobe signal and the first bank information and the second bank information. Control signal generating means for generating a control signal for precharging any one of the second read global core lines (read global core line connected to a bank outside the activated bank). A featured semiconductor memory device is provided.

  According to an eighth aspect of the invention, there is provided a semiconductor memory device according to the seventh aspect, wherein the control signal becomes active before the bank becomes active.

  According to a ninth aspect of the invention, there is provided a semiconductor memory device according to the seventh aspect, wherein the global input / output line includes a read global input / output line and a write global input / output line.

  In a tenth aspect based on the ninth aspect, the global core line controller receives the read strobe signal and transmits data of the read global core line to the read global input / output line. There is provided a semiconductor memory device comprising output strobe signal generation means for generating an output strobe signal.

  According to an eleventh aspect of the present invention, there is provided a semiconductor memory device according to the tenth aspect of the present invention, wherein the output strobe signal is activated after the bank is activated.

  In a twelfth invention based on the tenth invention, the control signal further includes a first control signal for precharging the first read global core line and a second control signal for precharging the second read global core line. Provided is a semiconductor memory device characterized by being a control signal.

  In a thirteenth aspect based on the twelfth aspect, the global core line controller is responsive to the first bank information and the second bank information and receives data input via the write global input / output line. The semiconductor memory device is characterized by comprising input data transmission means for transmitting the data to any one of the first write global core line and the second write global core line.

  In a fourteenth aspect based on the thirteenth aspect, the input data transmitting means further includes a control unit that receives at least one of the bank information and read / write information, and the write global input. One of the first write global core line and the second write global core line that receives the output signal of the input unit in response to the output signal of the input unit that receives data via the output line and the control unit There is provided a semiconductor memory device comprising a transmission unit that selectively transmits data to one.

  According to a fifteenth aspect of the present invention, there is provided a semiconductor memory device according to the fourteenth aspect of the present invention, further comprising a latch unit that latches an output signal of the transmission unit.

  In a sixteenth aspect based on the twelfth aspect, the global core line controller further comprises the first read global core line and the second read global core in response to the first control signal and the second control signal. Provided is a semiconductor memory device comprising output data transmission means for transmitting data of any one of the lines to the read global input / output line.

  In a seventeenth aspect based on the sixteenth aspect, the output data transmitting means is responsive to the first control signal and the second control signal for the first read global core line and the second read global core. A selector that selectively outputs line data; a transmitter that transmits the output signal of the selector in response to the output strobe signal; and outputs the output signal of the transmitter to the read global input / output line Provided is a semiconductor memory device comprising an output unit.

  According to an eighteenth aspect of the present invention, there is provided a semiconductor memory device according to the seventeenth aspect of the present invention, further comprising a latch unit that latches an output signal of the transmission unit.

  For a full understanding of the invention and its operational advantages, as well as the objectives achieved by the practice of the invention, reference is made to the accompanying drawings which illustrate preferred embodiments of the invention and the contents described in the accompanying drawings. Should be referenced.

  Hereinafter, a most preferred embodiment of the present invention will be described with reference to the accompanying drawings.

  FIG. 6 is a block diagram for explaining a layout of a part of the DRAM according to the present invention. In particular, the memory capacity is 1 G, and 16 banks BANK0, BANK1, BANK2, BANK3, BANK4, BANK5, BANK6, BANK7 , BANK8, BANK9, BANK10, BANK11, BANK12, BANK13, BANK14, BANK15, and "x32" operation mode in which data read and write operations are performed 32 bits each in one column operation, 4 bits 1 shows a DRAM having a prefetch architecture.

  As shown in the figure, the entire 1G memory is divided into four quarters QA, QB, QC, and QD. Each quarter QA, QB, QC, QD in 256M units performs a data read operation and a write operation via a corresponding pad (DQ <0:31>). That is, the “QA” quarter corresponds to “DQ <0: 7>”, the “QB” quarter corresponds to “DQ <8:15>”, and the “QC” quarter corresponds to “DQ <16:23”. > ”And the“ QD ”quarter performs a read operation and a write operation corresponding to“ DQ <24:31> ”, respectively.

  The detailed description of the structure and operation will be made by omitting the description of the prefetch operation, focusing on the “QA” quarter as in the prior art.

  BANK0, BANK1, BANK2, BANK3, BANK4, BANK5, BANK6, BANK7, BANK8, BANK9, BANK10, BANK11, BANK12, BANK13, BANK14, and BANK15 are the central core line controllers 100. BANK0, BANK2, BANK4, BANK6, BANK8, BANK10, BANK12, BANK14 (hereinafter referred to as “LEFT_BANK”) in the left area and banks BANK1, BANK3, BANK5, BANK7, BANK13, BANK13, BANK13, And BANK 15 (hereinafter, “RIGHT_BANK”). The bank (LEFT_BANK) and the global core line controller 100 in the left area are connected to the left global core lines WGIO_CORE_LEFT_EV0 <0: 7> and RGIO_CORE_LEFT_EV0 <0: 7>, and the bank (RIGHT_BANK) and the global core line controller in the right area 100 is connected to the right global core lines WGIO_CORE_RIGHT_EV0 <0: 7> and RGIO_CORE_RIGHT_EV0 <0: 7>. The global core line controller 100 and the pads DQ <0: 7> are connected to the global input / output lines WGIO_IO_RIGHT_EV0 <0: 7> and RGIO_IO_RIGHT_EV0 <0: 7>.

  Such a configuration according to the present invention uses the global core line controller 100 arranged on the center side of the “QA” quarter, and uses the left global core lines WGIO_CORE_LEFT_EV0 <0: 7>, RGIO_CORE_LEFT_EV0 <0: 7> The right global core lines WGIO_CORE_RIGHT_EV0 <0: 7> and RGIO_CORE_RIGHT_EV0 <0: 7> are separately controlled.

  Here, the left global core lines WGIO_CORE_LEFT_EV0 <0: 7> and RGIO_CORE_LEFT_EV0 <0: 7> are used for the left write global core line WGIO_CORE_LEFT_EV0 <0: 7> that transmits data during the write operation and the data during the read operation. Left global core lines RGIO_CORE_LEFT_EV0 <0: 7>, and right global core lines WGIO_CORE_RIGHT_EV0 <0: 7> and RGIO_CORE_RIGHT_EV0 <0: 7> are also transmitted on the right write global Core line WGIO_CORE_RIGHT_EV0 <0: 7> and right read global core line RGIO_CORE_RIG that transmits data during a read operation T_EV0 <0: 7> is divided into a. In addition, the global input / output lines WGIO_IO_RIGHT_EV0 <0: 7> and RGIO_IO_RIGHT_EV0 <0: 7> also have write global input / output lines WGIO_IO_RIGHT_EV0 <0: 7> that transmit data during a write operation, and data during a read operation. The read global input / output line RGIO_IO_RIGHT_EV0 <0: 7> is divided.

  On the other hand, the global core line controller 100 arranged on the center side of the “QA” quarter includes a bank activation unit that activates a desired bank among the 16 banks (LEFT_BANK, RIGHT_BANK) in the “QA” quarter. An output strobe signal generation unit, a control signal generation unit, an input data transmission unit, and an output data transmission unit.

  FIG. 7 is a diagram for explaining the bank activation unit 110 of the global core line controller 100 of FIG.

  As shown in the figure, the bank activation unit 110 that has received 16 banks (LEFT_BANK, RIGHT_BANK) information (CAST <0: 3>), a write strobe signal WSTROBE_PRE, and a read strobe signal RSTROBE_PRE Bank strobe signals RSTROBE_BANK <0, 2, 4, 6, 8, 10, 12, 14>, RSTOBE_BANK <1, 3, 5, 7, 9, 11, 13, 15>, WSTROBE_BANK <0, 2 4, 6, 8, 10, 12, 14> and WSTROBE_BANK <1, 3, 5, 7, 9, 11, 13, 15> are output.

  Here, “RSTROBE_BANK <0, 2, 4, 6, 8, 10, 12, 14>” is a strobe signal that activates one of the banks in the left region during a read operation. , “RSTROBE_BANK <1, 3, 5, 7, 9, 11, 13, 15>” is a strobe signal for activating any one of the banks in the right region during a read operation, WSTROBE_BANK <0, 2, 4, 6, 8, 10, 12, 14> ”is a strobe signal for activating any one of the banks in the left region during a write operation, and“ WSTROBE_BANK < 1, 3, 5, 7, 9, 11, 13, 15> ”is a strobe signal that activates one of the banks in the right region during the write operation.

  On the other hand, the strobe signal activation unit 111 receives the column strobe signal STROBE_PRE that becomes active during the column operation and the read / write signal WTRZT in the read operation and the write operation, and writes that become active during the write operation. A strobe signal WSTROBE_PRE and a read strobe signal RSTROBE_PRE that becomes active during a read operation are output.

  FIG. 8 is a diagram for explaining the output strobe signal generation unit 120 of the global core line controller 100 of FIG.

  As shown in the figure, the output strobe signal generation unit 120 includes a third delay unit 121 that receives the read strobe signal RSTROBE_PRE and outputs it as the output strobe signal RSTROBE_IO after a predetermined time. In the actual read operation, 8-bit data in the bank area is transmitted to the read global input / output line RGIO_IO_EV0 <0: 7> in response to the output strobe signal RSTROBE_IO. Such an operation will be described in more detail with reference to FIGS. 11 and 13.

  FIG. 9 is a diagram for explaining the control signal generation unit 130 of the global core line controller 100 of FIG.

  As shown in the figure, the control signal generation unit 130 includes, for example, bank information (CAST <0 >>) indicated by “CAST <0>” in the bank information (CAST <0: 3>). Control signals RSTROBE_PCG_RIGHT_B and RSTROBE_PCG_B_PC_B_PC_B_T_B______________________________________________________________ To do.

  Here, the “RSTROBE_PCG_RIGHT_B” control signal is activated by a logic “low”, and the left read global core line RGIO_CORE_LEFT_EV0 <0: 7> is precharged to a logic “low”, and the “RSTROBE_PCG_LEFT_B” control signal is , A signal that becomes active at a logic “low” and precharges the right read global core line RGIO_CORE_RIGHT_EV0 <0: 7> to a logic “low”.

  On the other hand, the fourth extension part 131, the fifth delay part 132 in FIG. 9, and the third delay part 121 in FIG. 8 are for more stable timing matching in the read operation. For example, when a read operation is performed in any one of the banks (LEFT_BANK) in the left region, a bank strobe signal (RSTROBE_BANK <0, 2 for activating any one of the banks (LEFT_BANK) in the left region) 4, 6, 8, 8, 10, 12, 14>) and activation of the control signal RSTROBE_PCG_LEFT_B and the output strobe signal RSTROBE_IO for precharging the right read global core line RGIO_CORE_RIGHT_EV0 <0: 7> The control signal RSTROBE_PCG_LEFT_B becomes active earlier than the selected bank strobe signal, and the output strobe signal RSTROBE_IO is more active than the selected bank strobe signal. Will become active later.

  FIG. 10 is a diagram for explaining the input data transmission unit 140 provided in the global core line controller 100 of FIG.

  For convenience of explanation, the write global input / output line indicated by “WGIO_IO_EV0 <0>” in the write global input / output line WGIO_IO_EV0 <0: 7> will be described as a representative. The left-side write global core line WGIO_CORE_LEFT_EV0 <0: 7> will be described with the left-side write global core line indicated by “WGIO_CORE_LEFT_EV0 <0>” as a representative, and the right-side write global core line WGIO_CORE_RIGHT_EV0 <0: 7> The right write global core line indicated by “WGIO_CORE_RIGHT_EV0 <0>” will be described as a representative.

  As shown in the figure, the input data transmission unit 140 includes a data input unit 141 that receives data via a write global input / output line WGIO_IO_EV0 <0>, a read / write signal WTRZT, and bank information (for example, CAST <0 >) And in response to the output signal of the control unit 142, the output signal of the data input unit 141 is transmitted to the left write global core line WGIO_CORE_LEFT_EV0 <0> or the right write global core line WGIO_CORE_RIGHT_EV0 <0>. A transmission unit 143. The first latch unit 144 latches data input to the left write global core line WGIO_CORE_LEFT_EV0 <0>, and the second latch unit latches data input to the right write global core line WGIO_CORE_RIGHT_EV0 <0>. 145.

  FIG. 11 is a diagram for explaining the output data transmission unit 150 provided in the global core line controller 100 of FIG.

  For convenience of explanation, the read global input / output line indicated by “RGIO_IO_EV0 <0>” in the read global input / output line RGIO_IO_EV0 <0: 7> will be described as a representative. Further, among the left read global core lines RGIO_CORE_LEFT_EV0 <0: 7>, the “RGIO_CORE_LEFT_EV0 <0>” left read global core line will be described as a representative, and among the right read global core lines RGIO_CORE_RIGHT_EV0 <0: 7>, “RGIO_CORE_RIGHT0 EV0 <0: 7> 0> ”right-side read global core line will be described as a representative.

  As shown in the figure, the output data transfer unit 150 responds to the control signals RSTROBE_PCG_LEFT_B, RSTROBE_PCG_RIGHT_B and outputs one of the left read global core line RGIO_CORE_LEFT_EV0 <0> or the right read global core line RGIO_CORE_RIGHT_EV0 <0>. A selection unit 151 that selectively outputs, a transmission unit 152 that transmits the output signal SEL_OUT of the selection unit 151 to the latch unit 154 in response to the output strobe signal RSTROBE_IO, and a latch unit 154 that latches the output signal of the transmission unit 152 And an output unit 153 that reads the latched data and outputs the read data to the global input / output line RGIO_IO_EV0 <0>.

  FIG. 12 is a timing diagram relating to a write operation according to the present invention.

  As shown in the figure, the write strobe signal WSTROBE_PRE is generated according to the column strobe signal STROBE_PRE and the read / write signal WTRZT (logic “high” during the write operation). When the write strobe signal WSTROBE_PRE becomes active, one of the bank strobe signals (RSTROBE_BANK <0:15>) corresponding to the bank information (CAST <0: 3>), RSTROBE_BANK <4:15>. Is omitted). Therefore, the data input through the write global input / output line WGIO_IO_EV0 <0> is transmitted to the selected bank and used.

  Again, as shown in FIG. 10, the input data transfer unit 140 receives the data received via the write global input / output line WGIO_IO_EV0 <0> according to the bank information (for example, CAST <0>) as the left write global core line. This is transmitted to WGIO_CORE_LEFT_EV0 <0> or the right write global core line WGIO_CORE_RIGHT_EV0 <0>.

  FIG. 13 is a timing diagram relating to a read operation according to the present invention.

  As shown in the figure, the read strobe signal RSTROBE_PRE is generated according to the column strobe signal STROBE_PRE and the read / write signal WTRZT (logic “low” during the read operation). Then, the control signal RSTROBE_PCG_LEFT_B for precharging the left read global core line RGIO_CORE_LEFT_EV0 <0> or the right read global core line RGIO_CORE_RIGHT_EV0 <0> connected outside the bank area selected by the bank information (CAST <0: 3>). , RSTROBE_PCG_RIGHT_B transitions to a logic “low” to precharge the line to a logic “low”. After that, when the bank strobe signal (one of RSTROBE_BANK <0:15>, RSTROBE_BANK <4:15> is activated) is logic high, the left read global core connected to the activated bank Data is transmitted to the line RGIO_CORE_LEFT_EV0 <0> or the right read global core line RGIO_CORE_RIGHT_EV0 <0>.

  In this way, the transmitted data is selectively output from the selection unit 151 in FIG. 11 according to the control signals RSTROBE_PCG_LEFT_B and RSTROBE_PCG_RIGHT_B, and the output signal SEL_OUT is read in response to the output strobe signal RSTROBE_IO. It is output to RGIO_IO_EV0 <0>. For reference, the control signals RSTROBE_PCG_LEFT_B and RSTROBE_PCG_RIGHT_B are control signals that precharge the left read global core line RGIO_CORE_LEFT_EV0 <0> or the right read global core line RGIO_CORE_RIGHT_EV0 <0> and the E_L This is a selection signal for selecting any one of the right read global core line RGIO_CORE_RIGHT_EV0 <0>.

  As described above, the banks in the “QA” quarter are divided into the right-side bank and the left-side bank, and the read operation and the write operation are performed, so that 1G and 16 banks are configured with the conventional structure. From time to time, the loading and joining of each global core wire used has been reduced by more than 1/2.

  Conventionally, since there is no need for a global line for transmitting a bank strobe signal from the peripheral region to the bank region, it is possible to reduce a shielding line configured according to each global line.

  In the present invention described above, the bank area is divided into two or more, the global line corresponding to each bank is connected, and the timing delay and the voltage level of the data moving through the global line connected to the bank to be activated The slop can be minimized, and an effect of increasing the overall utilization of the global line by precharging the global line connected to another bank can be obtained.

  In addition, by generating the bank strobe signal in the bank region, there is an effect of reducing the layout by reducing the global line that has conventionally transmitted the bank strobe signal and the shield line thereby.

  The present invention is not limited to the above-described embodiment, and various modifications are possible without departing from the scope of the technical idea according to the present invention, and these are also within the technical scope of the present invention. Belonging to.

  For example, in the present specification, an example of a problem caused by increasing from 8 banks to 16 banks has been described. However, it is obvious to those skilled in the art that such a problem is caused by an increase in the number of multibanks. Therefore, the true technical protection scope of the present invention should be determined by the technical idea of the appended claims.

It is a block diagram for demonstrating the layout of a part of conventional DRAM. It is a block diagram for demonstrating the strobe decoder of FIG. FIG. 2 is a diagram for explaining a read / write strobe signal generation unit in FIG. 1. FIG. 2 is a circuit diagram for explaining an input data buffer of FIG. 1. FIG. 2 is a circuit diagram for explaining an output data buffer of FIG. 1. It is a block diagram for demonstrating the layout of a part of DRAM which concerns on this invention. FIG. 7 is a diagram for explaining a bank activation unit of the global core line controller of FIG. 6. It is a figure for demonstrating the output strobe signal generation part of the global core line controller of FIG. It is a figure for demonstrating the control signal production | generation part of the global core line controller of FIG. It is a figure for demonstrating the input data transmission part of the global core line controller of FIG. It is a figure for demonstrating the output data transmission part of the global core line controller of FIG. FIG. 6 is a timing diagram relating to a write operation according to the present invention. FIG. 6 is a timing diagram related to a read operation according to the present invention.

Explanation of symbols

100 Global core line controllers BANK0 to BANK15 Bank DQ <0:31> Pad WGIO_CORE_LEFT_EV0 <0: 7>
Left write global core line WGIO_CORE_RIGHT_EV0 <0: 7>
Right write global core line RGIO_CORE_LEFT_EV0 <0: 7>
Left read global core line RGIO_CORE_RIGHT_EV0 <0: 7>
Right readout global core line

Claims (18)

Global I / O lines,
The first global core line,
The second global core line,
A global core line controller formed between the global input / output line and the first global core line and the second global core line;
A first bank connected via the global core line controller and the first global core line;
A semiconductor memory device, comprising: a second bank connected via the global core line controller and the second global core line.   The semiconductor memory device according to claim 1, wherein the global core line controller controls the first global core line and the second global core line separately.   The first global core line includes a first read global core line and a first write global core line, and the second global core line includes a second read global core line and a second write global core line. The semiconductor memory device according to claim 1.   In a read operation, data is transmitted through one of the first read global core line and the second read global core line, and the other read global core line is precharged. The semiconductor memory device according to claim 3.   The global core line controller activates one of the first bank and the second bank in response to the first bank information and the second bank information and the read strobe signal and the write strobe signal. 4. The semiconductor memory device according to claim 3, further comprising bank activation means.   Read / write information and a strobe signal for column operation are received, and the read strobe signal that becomes active during the read operation and the write strobe signal that becomes active during the write operation are output. 6. The semiconductor memory device according to claim 5, further comprising means for activating a write strobe signal.   The global core line controller is responsive to the read strobe signal and the first bank information and the second bank information to select one of the first read global core line and the second read global core line ( 6. The semiconductor memory device according to claim 5, further comprising control signal generation means for generating a control signal for precharging a read global core line connected to a bank other than the activated bank.   8. The semiconductor memory device according to claim 7, wherein the control signal becomes active before the bank becomes active.   The semiconductor memory device according to claim 7, wherein the global input / output line includes a read global input / output line and a write global input / output line.   The global core line controller includes output strobe signal generating means for receiving the read strobe signal and generating an output strobe signal for transmitting data of the read global core line to the read global input / output line. The semiconductor memory device according to claim 9.   11. The semiconductor memory device according to claim 10, wherein the output strobe signal becomes active after a time when the bank becomes active.   11. The control signal according to claim 10, wherein the control signals are a first control signal for precharging the first read global core line and a second control signal for precharging the second read global core line. Semiconductor memory device.   In response to the first bank information and the second bank information, the global core line controller sends data input through the write global input / output line to the first write global core line and the second write global core line. 13. The semiconductor memory device according to claim 12, further comprising input data transmission means for transmitting to any one of them. The input data transmission means is
A control unit for receiving at least one of the bank information and read / write information;
An input unit for receiving data via the write global input / output line;
A transmission unit that selectively transmits the output signal of the input unit to one of the first write global core line and the second write global core line in response to the output signal of the control unit. The semiconductor memory device according to claim 13.   The semiconductor memory device of claim 14, further comprising a latch unit that latches an output signal of the transmission unit.   The global core line controller reads data from one of the first read global core line and the second read global core line in response to the first control signal and the second control signal. 13. The semiconductor memory device according to claim 12, further comprising output data transmission means for transmitting to the memory. The output data transmission means is
A selector for selectively outputting data of the first read global core line and the second read global core line in response to the first control signal and the second control signal;
A transmission unit for transmitting an output signal of the selection unit in response to the output strobe signal;
The semiconductor memory device according to claim 16, further comprising: an output unit that outputs an output signal of the transmission unit to the read global input / output line.   The semiconductor memory device of claim 17, further comprising a latch unit that latches an output signal of the transmission unit.

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