JP2008084276A - Programmable logic controller device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an extendable programmable logic controller device transmitting and receiving data between a base block and respective extension blocks at high speed, and further early detecting the occurrence of a communication trouble due to a contact failure of an external connector. <P>SOLUTION: A cable checking means sends a plurality of bit data having a predetermined test pattern to an extension unit located on the downstream side via a group of signal lines obtained by bisecting a bus line in an extension cable in response to an arrival of a predetermined check start command, and also determines whether the bit data having the predetermined test pattern are normally returned from the extension unit located on the downstream side via the remaining group of signal lines to store the determination result in an internal register. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a programmable controller device (hereinafter referred to as a PLC device) in which a basic block and one or more extension blocks are connected in series via an extension cable.

  2. Description of the Related Art Conventionally, a PLC device in which a basic block and one or more extension blocks are connected via an extension cable has been known.

  An example of such a PLC device is shown in FIG. As shown in the figure, the PLC device 200 is configured by connecting one basic block 6 and two extension blocks 7 and 8 through extension cables 91 and 92.

  The illustrated basic block 6 includes a power supply unit 61, a CPU unit 62, three I / O units 63, and an inter-block connection unit 64. In addition to the above, the basic block 6 can also include various special function units such as a motion control unit, a PID arithmetic unit, a communication unit, and the like.

  These units 62 and 63 are electrically and mechanically connected to an internal bus (not shown) laid on the backplane 60 via a connector (not shown).

  The inter-block connection unit 64 has a downstream external connector 64b on the front surface thereof. The downstream side external connector 64 b is electrically connected to the internal bus inside the inter-block connection unit 64.

  The expansion block 7 includes a power supply unit 71, five I / O units 72, and an inter-block connection unit 73. Of course, the extension block 7 can also include various special function units such as a motion control unit, a PID arithmetic unit, a communication unit, and the like.

  These I / O units 72 are electrically and mechanically connected to an internal bus (not shown) laid on the backplane 70 via a connector (not shown).

  The inter-block connection unit 73 has an upstream external connector 73a and a downstream external connector 73b on the front surface thereof. These external connectors 73 a and 73 b are electrically connected to the internal bus inside the inter-block connection unit 73.

  Similarly, the extension block 8 includes a power supply unit 81, five I / O units 82, and an inter-block connection unit 83. Of course, the expansion block 8 can also include various special function units such as a motion control unit, a PID arithmetic unit, a communication unit, and the like.

  These I / O units 82 are electrically and mechanically connected to an internal bus (not shown) laid on the backplane 80 via a connector (not shown).

  The inter-block connection unit 83 has an upstream external connector 83a and a downstream external connector 83b on the front surface thereof. These external connectors 83a and 83b are electrically connected to the internal bus inside the inter-block connection unit 83.

  The basic block 6 and the extension block 7 are connected by an extension cable 91 that connects the external connectors 64b and 73a. The extension block 7 and the extension block 8 are connected by the external connectors 73b and 83a. They are connected by an extension cable 92.

  According to the PLC device having such a configuration, the internal buses included in the basic block 6 and the extension blocks 7 and 8 are directly led to the external connectors 64b, 73a, 73b, 83a, and 83b. There is an advantage that high-speed signal exchange between the basic block 6 and each of the expansion blocks 7 and 8 can be realized at low cost by simply connecting the external connectors with an expansion cable.

  That is, if the basic block 6 and each of the additional blocks 7 and 8 are connected by serial communication, in addition to the occurrence of a delay time for communication processing including serial / parallel conversion processing, Cost increases due to the need to install a microcomputer in each block.

  Regarding the duplex configuration device that provides a pilot signal loopback at one end of the cable connecting the active system and the standby system, and determines the diagnostic signal from the active system only when pilot signals are transmitted and received normally Is conventionally known (see Patent Document 1).

Also, a monitoring circuit of a duplex device having a detection circuit that outputs a start signal of the second device when an abnormal state signal of the first device in operation is continuously detected twice or more is also conventionally known. (See Patent Document 2).
Japanese Patent Laid-Open No. 11-96088 JP-A 63-305623

  However, in the type of PLC device that can be connected directly to each other via such an extension cable, there is an advantage that data can be exchanged between the basic block and each extension block at a high speed. Since all the signal lines that make up the internal bus are derived from each external connector, the number of connection pins of the external connector is large, and communication problems due to poor contact at the external connector are likely to occur. There is.

  The present invention has been made paying attention to the above-mentioned problems, and the object of the present invention is to enable high-speed exchange of data between the basic block and each additional block, and an external connector. It is an object of the present invention to provide an expandable PLC device that can early detect the occurrence of a communication failure due to poor contact or the like.

  The above problem can be solved by the following PLC device. That is, the PLC device is configured by connecting a basic block and one or more extension blocks via an extension cable.

  The basic block includes a plurality of control units including a CPU unit and an I / O unit, an internal bus that connects the control units, and a downstream external connector that leads the internal bus to the outside.

  The expansion block is a plurality of control units including I / O units, an internal bus connecting these control units, an upstream external connector that leads the internal bus to the outside, or an upstream side that leads the internal bus to the outside An external connector and a downstream external connector are included.

  The basic block and the extension block, and the extension block and the extension block are connected via an extension cable that connects the external connectors.

  The basic block includes cable check means. In response to the arrival of a predetermined check start command, this cable check means transmits a plurality of bits of data having a predetermined test pattern downstream via a group of signal lines obtained by dividing the extension cable bus line into two. To determine whether or not a plurality of bit data having a predetermined test pattern has been normally returned from the extension unit located downstream via the remaining group of signal lines. The determination result is stored in an internal register.

  Each of the extension blocks includes a cable check unit and a cable check return unit. In response to the arrival of a predetermined check start command, the cable check means transmits a plurality of bits of data having a predetermined test pattern to the downstream side through a group of signal lines obtained by dividing the extension cable bus line into two. While determining whether or not the multi-bit data having a predetermined test pattern has been normally returned from the extension unit located downstream through the remaining group of signal lines, The determination result is stored in an internal register.

  In response to the arrival of a predetermined check start command, the cable check loop-back means transmits a predetermined signal from a basic block or expansion block located upstream via a group of signal lines that bisect the bus line in the expansion cable. It is determined whether or not the multi-bit data having the test pattern is normally received. When the multi-bit data is normally received, it is predetermined to the basic block or the additional block located on the upstream side through the remaining group of signal lines. And a cable check loop-back means configured to return multi-bit data having the following test pattern.

  According to such a configuration, the basic block includes the cable check means, and each extension block includes the cable check means and the cable check folding means. Alternatively, if it is operated at any time in response to a command from the CPU unit, each means performs a cable check spontaneously, and the check result is stored and stored in an internal register in each block. By appropriately referencing, high-speed signal exchange between blocks, while monitoring the connection status of each extension cable, early detection of the occurrence of communication failures due to poor contact in external connectors, etc. be able to.

  More specifically, this PLC device can also be configured as follows. That is, in this PLC device, the basic block includes an interface circuit interposed between the internal bus and the downstream external connector, and the extension block is between the internal bus and the upstream external connector, or the internal bus. And an upstream side external connector and a downstream side external connector.

  Each of the external connectors includes an external connector of the first system and an external connector of the second system that are in parallel with each other. Between the basic block and the expansion block, and between the expansion block and the expansion block, The first system extension cable connecting the first system external connectors and the second system extension cable connecting the second system external connectors are connected in parallel.

  Each of the interface circuits includes a plurality of branch circuits that branch-connect each signal line constituting the internal bus to the first system external connector and the second system external connector, and each of the branch circuits is The outflow signal is allowed to be diverted to the first system and the second system, while the inflow signal is configured to allow the merge by logical sum from the first system and the second system.

  According to such a configuration, the connection between the internal buses between the basic block and the extension block and between the extension block and the extension block is always made through the extension cables of the first system and the second system parallel to each other. Therefore, even if a communication failure occurs due to contact failure or the like in the external connector in any of the systems, signal transmission / reception can be continued in the remaining systems.

  The plurality of control units in the basic block and the extension block may include special function units such as a motion control unit, a PID arithmetic unit, and a communication unit in addition to the CPU unit and the I / O unit.

  In addition, the internal bus connecting these control units is not limited to a structure laid on the backplane, and a part of the bus is included in each control unit, and a plurality of connectors are connected. It may have a structure in which a series of buses appear by being connected adjacently (so-called backplane-less type).

  Furthermore, the present invention can also be applied to a PLC device having an all-in-one basic block and an additional block that cannot be increased or decreased in units.

  According to the present invention, data can be exchanged between the basic block and each additional block at high speed, and the occurrence of a communication failure due to a contact failure in the external connector can be detected at an early stage. An expandable PLC device can be provided.

  Hereinafter, a preferred embodiment of a PLC apparatus to which the present invention is applied will be described in detail with reference to the accompanying drawings.

  An external view of a PLC device to which the present invention is applied is shown in FIG. As shown in the figure, the PLC device 100 includes one basic block 1 and one or more (two in this example) additional blocks 2 and 3.

  The illustrated basic block 1 includes one power supply unit 11, one CPU unit 12, two I / O units 13, a first inter-block connection unit 14, and a second system block. The connection unit 15 is included. In addition to the above, the basic block 1 may include various special function units such as a motion control unit, a PID arithmetic unit, a communication unit, and the like.

  These units 12 and 13 are electrically and mechanically connected to an internal bus 10B (see FIGS. 3 and 4) laid on the backplane 10 via a connector (not shown).

  The first block inter-block connection unit 14 has a downstream external connector 14b on the front surface thereof. As will be described later in detail, the downstream side external connector 14b is electrically connected to the internal bus 10B via the internal connector CN in the inter-block connection unit 14 (see FIGS. 3 and 4). Similarly, the inter-block connection unit 15 of the second system also has a downstream external connector 15b on the front surface thereof. This downstream external connector 15b is also electrically connected to the internal bus 10B via the internal connector CN inside the inter-block connection unit 15 (see FIGS. 3 and 4).

  The expansion block 2 includes a power supply unit 21, four I / O units 22, a first system inter-block connection unit 23, and a second system inter-block connection unit 24. Of course, the extension block 2 can also include various special function units such as a motion control unit, a PID arithmetic unit, a communication unit, and the like.

  The four I / O units 22 are electrically and mechanically connected to an internal bus 20B (see FIGS. 3 and 4) laid on the backplane 20 via connectors (not shown).

  The first block inter-block connection unit 23 includes an upstream external connector 23a and a downstream external connector 23b on the front surface thereof. These external connectors 23a and 23b are electrically connected to the internal bus 20B via the internal connector CN in the inter-block connection unit 23 (see FIGS. 3 and 4). Similarly, the inter-block connection unit 24 of the second system also has an upstream external connector 24a and a downstream connector 24b on the front surface thereof. These external connectors 24a and 24b are also electrically connected to the internal bus 20B via the internal connector CN within the inter-block connection unit 24 (see FIGS. 3 and 4).

  The expansion block 3 includes a power supply unit 31, four I / O units 32, a first system inter-block connection unit 33, and a second system inter-block connection unit 34. Of course, the extension block 3 can also include various special function units such as a motion control unit, a PID arithmetic unit, a communication unit, and the like.

  These I / O units 32 are electrically and mechanically connected to an internal bus 30B (see FIG. 7) laid on the backplane 30 via a connector (not shown).

  The inter-block connection unit 33 of the first system has an upstream external connector 33a and a downstream external connector 33b on the front surface. These external connectors 33a and 33b are electrically connected to the internal bus 30B via the internal connector CN inside the inter-block connection unit 33. Similarly, the inter-block connection unit 34 of the second system also has an upstream external connector 34a and a downstream connector 34b on the front surface thereof. These external connectors 34a and 34b are also electrically connected to the internal bus 30B via the internal connector CN inside the inter-block connection unit 34.

  The basic block 1 and the two extension blocks 2 and 3 are sequentially connected by two extension cables 41 and 51 of the first system and two extension cables 42 and 52 of the second system.

  Specifically, when the first system is observed, the downstream external connector 14b of the first block inter-block connection unit 14 of the basic block 1 and the upstream external connector of the first block inter-block connection unit 23 of the expansion block 2 are observed. 23a is connected via an extension cable 41 of the first system. Similarly, between the downstream external connector 23b of the first block inter-block connection unit 23 of the extension block 2 and the upstream external connector 33a of the first block inter-block connection unit 33 of the extension block 3, the first It is connected via an extension cable 51 of the system.

  When observing the second system, the space between the downstream external connector 15b of the second block inter-block connection unit 15 of the basic block 1 and the upstream external connector 24a of the second block inter-block connection unit 24 of the expansion block 2 is The second extension cable 42 is connected. Similarly, between the downstream external connector 24 b of the second block inter-block connection unit 24 of the expansion block 2 and the upstream external connector 34 a of the second block inter-block connection unit 34 of the expansion block 3, the second They are connected via an extension cable 52 of the system.

  A schematic internal configuration diagram of the basic block 1 and the extension block 2 is shown in FIG. As shown in the figure, focusing on the basic block 1, the external connector 14b and the external connector 15b are in parallel with each other, and an interface circuit is provided between the connectors 14b and 15b and the internal bus 10B. 10A is interposed.

  Focusing on the extension block 2, the external connector 23a and the external connector 24a are in parallel with each other, and the external connector 23b and external connector 24b are also in parallel with each other. An interface circuit 20A is interposed between the two pairs of external connectors and the internal bus 20B.

  A detailed configuration diagram (one-way signal line portion) of the basic block and the extension block is shown in FIG. 3, and a detailed configuration diagram (bidirectional signal line portion) is shown in FIG.

  As is apparent from these drawings, the interface circuit 10A includes a plurality of branch circuits that branch-connect each signal line constituting the internal bus 10B to the first system external connector 14b and the second system external connector 15b. And each of the branch circuits allows branching of the outflow signal to the first system and the second system, while the inflowing signal is joined by the logical sum from the first system and the second system. It is structured to allow. Similarly, the interface circuit 20A includes a plurality of branch circuits that branch-connect each signal line constituting the internal bus 20B to the first system external connectors 23a and 23b and the second system external connectors 24a and 24b. Contains.

  More specifically, in this example, the internal buses 10B and 20B each have 16 data signal lines (bidirectional) and 5 address signal lines (one direction from upstream to downstream). There are 10 control signal lines (one direction from upstream to downstream) and four control signal lines (one direction from downstream to upstream). The 16 data signal lines also serve as address signal lines.

  In FIG. 3, among the signal lines constituting the internal bus, there are a first control signal line in one direction from upstream to downstream and a second control signal line in one direction from downstream to upstream. Taken out and shown.

  Focusing on the first signal line, in the interface circuit 10A of the basic block 1, a branch circuit is configured by the main line 101 on the backplane and the two branch lines 101a and 101b on the backplane. The branch lines 101a and 101b are led to the first external connector 14b and the second external connector 15b via the branch lines 141 and 151 in the inter-block connection units 14 and 15, respectively. In the interface circuit 20A of the extension block 2, a branch circuit is configured by the main line 201 on the backplane and the two branch lines 201a and 201b on the backplane. In this case, an OR circuit 203 is interposed at the branch point of these three lines in the direction of merging from the two branch lines 201a and 201b to the one main line 201. The branch lines 201a and 201b are led out to the first system external connectors 23a and 23b and the second system external connectors 24a and 24b via the branch lines 231 and 241 in the inter-block connection units 23 and 24, respectively. .

  Focusing on the second signal line, in the interface circuit 10A of the basic block 1, a branch circuit is constituted by the main line 102 on the backplane and the two branch lines 102a and 102b on the backplane. In this case, the OR circuit 103 is interposed at the branch point of these three lines toward the flow in the joining direction from the two branch lines 102a and 102b to the one main line 102. The branch lines 102a and 102b are led to the external connector 14b of the first system and the external connector 15b of the second system via the branch lines 142 and 152 in the inter-block connection units 14 and 15. In the interface circuit 20A of the extension block 2, a branch circuit is configured by the main line 202 on the backplane and the two branch lines 202a and 202b on the backplane. The branch lines 202a and 202b are led to the first system external connectors 23a and 23b and the second system external connectors 24a and 24b via the branch lines 232 and 242 in the inter-block connection units 23 and 24, respectively. The

  FIG. 4 shows a signal line for switching the direction for switching the direction of the data signal and a data signal line for allowing a bidirectional flow out of the signal lines constituting the internal bus. Yes.

  Focusing on the control signal line for switching the direction, in the interface circuit 10A of the basic block 1, a branch circuit is constituted by the main line 104 on the backplane and the two branch lines 104a and 104b on the backplane. . The branch lines 104a and 104b are led to the external connector 14b of the first system and the external connector 15b of the second system via the branch lines 143 and 153 in the inter-block connection units 14 and 15. In the interface circuit 20A of the extension block 2, a branch circuit is configured by the main line 204 on the backplane and the two branch lines 204a and 204b on the backplane. In this case, an OR circuit 206 is interposed at the branch point of these three lines in the direction of merging from the two branch lines 204a and 204b to the one main line 204. The branch lines 204a and 204b are led to the first system external connectors 23a and 23b and the second system external connectors 24a and 24b via the branch lines 233 and 243 in the inter-block connection units 23 and 24, respectively. The

  Focusing on the data signal line, in the interface circuit 10A of the basic block 1, a branch circuit is configured by the main line 105 on the backplane and the two branch lines 105a and 105b on the backplane.

  More specifically, this branch circuit includes two branch paths 105-1 and 105-2 having a parallel relationship with each other. The OR circuit 106 and the three-state buffer 107a are interposed in the first branch path 105-1 in the direction of receiving a signal from the outside, and the three-state buffer 107b is provided in the second branch path 105-2. Is interposed in the direction of sending a signal to the outside. The switching control signal line 104 is connected to the switching input terminal of the three-state buffer 107a via the inverter element 107c, whereas the switching input terminal of the three-state buffer 107b is connected to the switching control terminal. The signal line 104 is directly connected. Therefore, the two three-state buffers 107 a and 107 b are alternatively enabled according to the logic state of the direction switching signal line 104.

  The branch lines 105a and 105b are led to the external connector 14b of the first system and the external connector 15b of the second system via the branch lines 144 and 154 in the inter-block connection units 14 and 15, respectively. In the interface circuit 20A of the extension block 2, a branch circuit is configured by the main line 205 on the backplane and the two branch lines 205a and 205b on the backplane.

  More specifically, this branch circuit includes two branch paths 205-1 and 205-2 having a parallel relationship with each other. In the first branch path 205-1, an OR circuit 206 and a three-state buffer 207a are interposed in the direction of receiving a signal from the outside, and in the second branch path 105-2, the three-state buffer 107b. Is interposed in the direction of sending a signal to the outside. The switching control signal line 204 is directly connected to the switching input terminal of the three-state buffer 207a, whereas the switching control signal line 204 is connected to the inverter at the switching input terminal of the three-state buffer 207b. It is connected via the element 207c. Therefore, these two three-state buffers 207a and 207b are alternatively enabled according to the logic state of the signal line 204 for direction switching.

  The branch lines 204a and 204b are led to the first system external connectors 23a and 23b and the second system external connectors 24a and 24b via the branch lines 233 and 243 in the inter-block connection units 23 and 24, respectively. The

  The I / O refresh operation of the PLC device 100 will be described. As is well known, when the CPU unit 12 of the PLC device is activated when the power is turned on, it is created appropriately by the user by repeatedly executing common processing, I / O refresh processing, user program execution processing, and peripheral service processing. The desired control is realized while executing the program (referred to as a user program).

  At this time, in the I / O refresh process, the IN process is performed not only on the I / O unit 13 mounted on the basic block 1 but also on the I / O units 22 and 32 mounted on the extension units 2 and 3. In addition, OUT processing is executed. Here, in the OUT process, the OUT data is read from the OUT area of the I / O memory (not shown) built in the CPU unit 12 and written in the output area of the designated I / O unit. On the other hand, in the IN process, the IN data is read from the input area of the designated I / O unit and is written in the IN area of the I / O memory built in the CPU unit 12.

  When executing the OUT process, the microprocessor (not shown) of the CPU unit 12 sets the logic level of the direction switching signal line 104 to “H” so that the interface circuit 10A of the basic block 1 has a buffer. 107a is disabled and the buffer 107b is enabled. At the same time, in the interface circuit 20A of the additional block 2, the buffer 207a is enabled and the buffer 207b is disabled.

  Then, as shown in FIG. 5, in the basic block 1, the data signal output from the CPU unit 12 onto the data signal line 105 is transferred to the enabled buffer 107b as shown by a thick line in the figure. After passing, it is branched into two systems and sent out in parallel to each of the two additional cables 41 and 42. On the other hand, in the extension block 2, the data signals received from the two extension cables 41 and 42 are logically ORed through the OR circuit 206 and then passed through the buffer 207a in the enabled state. / O unit 22 is written.

  At this time, the transmission of the data signal from the basic block 1 to the extension block 2 is performed through the two extension cables 41 and 42 in parallel with each other. Therefore, even if there is a signal loss due to a contact failure of the connector pin on one of the two systems of cables 41 and 42, the other side is normal. , Communication will not be hindered.

  When executing the IN process, the microprocessor (not shown) of the CPU unit 12 sets the logic level of the direction switching signal line 104 to “L” so that the interface circuit 10A of the basic block 1 has a buffer. 107a is enabled and the buffer 107b is disabled. At the same time, in the interface circuit 20A of the additional block 2, the buffer 207a is disabled and the buffer 207b is enabled.

  Then, as shown in FIG. 6, in the extension block 2, the data signal output from the I / O unit 22 onto the data signal line 205 is the buffer in the enabled state as shown by the bold line in the figure. After passing through 207b, it is branched into two systems and sent out in parallel to each of the two additional cables 41 and 42. On the other hand, in the basic block 1, the data signals received from the two additional cables 41 and 42 are logically ORed via the OR circuit 106 and then passed through the buffer 107a in the enabled state to the CPU. Written to unit 12.

  At this time, the transmission of the data signal from the extension block 2 to the basic block 1 is performed through the two extension cables 41 and 42 in parallel with each other, and the two data signals are sent to the OR circuit 106. Therefore, even if there is a signal loss due to a contact failure of the connector on one of the two systems of cables 41 and 42, as long as the other side is normal, It will not interfere with communication.

  Next, on the premise of the PLC device 100 having the above configuration (see FIGS. 1 to 6), it is checked whether each extension cable 41, 42, 51, 52 (see FIG. 9) is normal or abnormal during operation. The process for this is demonstrated.

  As described above, the PLC device 100 described above connects the basic block and the extension block and between the extension blocks with two extension cables parallel to each other, and on the signal receiving side, Since the logical sum (OR) of the two extension cable signal lines is taken, even if a connector pin contact failure occurs in one of the two extension cables, the other is normal. However, it has the advantage that operation can be continued without hindrance. However, if the state where the continuity failure exists in such one cable is left as it is, if the same continuity failure occurs in the other cable, It will no longer be necessary to stop driving.

  Therefore, the PLC device 100 is configured to check whether each extension cable 41, 42, 51, 52 (see FIG. 9) is normal or abnormal during operation.

  FIG. 7 shows a schematic configuration diagram of a main part for the cable check. In the figure, for convenience of explanation, only one extension cable is shown, but actually, as shown in FIG. 9, between the basic block 1 and the extension block 2, as well as the extension block 2 , 3 are connected by two parallel extension cables (41 and 42, 51 and 52).

  As shown in the figure, on the backplane 10 of the basic block 1, an internal register 108 and a cable check means 109 are mounted in a state of being connected to the internal bus 10B. In this example, the cable check means 109 is composed of an ASIC having a predetermined function. The function of the ASIC constituting the cable check means 109 will be described in detail later with reference to the flowchart of FIG.

  On the backplanes 20 and 30 of the respective extension blocks 2 and 3, internal registers 208 and 308, cable check means 209 and 309 made of ASIC, and cable check turn-back means 210 and 310 made of ASIC, Each is mounted in a state of being connected to the internal buses 20B and 30B. The function of the ASIC constituting the cable check folding means 210 and 310 will be described in detail later with reference to the flowchart of FIG.

  FIG. 10 is a conceptual diagram of the cable check process, FIG. 11 is an explanatory diagram showing the flow of data (test pattern) in the cable check process, and FIG. 12 is an explanatory diagram of the check test pattern.

  As is apparent from these drawings, the cable check method employed here is a first step in which predetermined test pattern data is sent from the upstream block to the downstream block for each cable. And a second step for determining whether the received test pattern data is correct in the downstream block, and if the received test pattern data is correct, the predetermined test pattern data is transferred from the downstream block to the upstream block. This includes a third step of flowing and a fourth step of determining whether the received test pattern data is correct or not in the upstream block (see FIG. 10).

  At this time, for the test pattern data to flow in the cable, instead of using all the signal lines included in the cable in a batch, the signal lines are divided into two groups and from the upstream side to the downstream side. For the test pattern data flow, one of the signal lines of the two groups is used, and for the test pattern data to flow from the downstream side to the upstream side, the signal lines of the two groups are used. The other group of signal lines is used. (See FIG. 11).

  In this example, as shown in FIG. 12, each signal includes 31 signal lines. The breakdown is composed of 5 address signal lines, 10 control signal lines, and 16 data signal lines. Then, for the test pattern data to flow from the upstream block to the downstream block, a total of 15 address signal lines (address signals 1 to 5) and 10 control signal lines (control signals 1 to 10) are combined. Use one signal line. On the other hand, for the flow of test pattern data from the downstream block to the upstream block, 16 data signal lines (data signals 1 to 16) are used.

  In this way, all signal lines included in the cable are divided into two groups, and the reason for flowing test pattern data for each group is that there is a limitation in the direction of data flow by the signal lines, and the test pattern data that can be flowed at once. This is because the data width is limited. When there is no restriction on the direction of data flow and test pattern data can be flowed to all signal lines at once, it is not necessary to divide into two groups.

  The actual cable check processing includes the CPU unit 12 mounted in the basic block 1, the internal register 108, the cable check means 109, the internal registers 208 and 308 mounted in the respective expansion blocks 2 and 3, the cable check means 209, 309 and the cable folding means 201 and 310 cooperate to realize this.

  The cable check process will be described below with reference to the flowcharts of FIGS. 13 to 15 and the detailed configuration diagram of the main part for cable check in FIG. In addition, the code | symbol (a)-(g) used on the flowchart of FIGS. 13-15 corresponds with the code | symbol (a)-(g) used in FIG.

  FIG. 13 is a flowchart showing a cable check related process on the CPU unit side. The processing shown in this flowchart can be executed by, for example, CPU unit common processing, peripheral service processing, or scheduled interruption processing. That is, as is well known to those skilled in the art, the CPU unit of the PLC device, after being activated upon power-on, is used for common processing, I / O refresh processing, user program execution processing, and peripheral services. The process is repeatedly executed.

  When the processing is started in the flowchart of FIG. 13, first, as shown in FIG. 8, the cable check start register 108a included in the internal register 108 on the basic block 1 is set (“1”) (a ), A cable check start notification is sent to the cable check means 109 (step 1301). After that, the CPU unit 12 waits for a certain period of time (NO in step 1302). On the other hand, on the side of the cable check means 109, the state of the cable check start register 108a is constantly monitored, the contents thereof are set ("1"), and the operation of the cable check mode is started (b). .

  A flowchart showing the function of the cable check means 109 is shown in FIG. In the figure, when the cable check mode is started, first, a process (c) for notifying the start of the cable check mode to the cable check return means 210 and the cable check means 209 of the extension block 2 located on the downstream side is executed. (Step 1401). At this time, the downstream cable check unit 209 that has received the notification further notifies the start of the cable check mode to the cable check return unit and the cable check unit of the additional block located downstream from itself (c). As a result, the cable check folding means 210 and 310 and the cable check means 209 and 309 on the series of extension blocks 2, 3 and 4 are activated almost simultaneously.

  Subsequently, in each of the cable check means 209 and 309, five address signal lines (address signals 1 to 5) and ten control signal lines (address signals 1 to 5) are transferred to a block located downstream with data having a predetermined test pattern. The control signals 1 to 10) are sent together using 15 signal lines (d) (step 1402). As a test pattern used at this time, as shown in FIG. 12A, a test pattern in which the logical value of a signal is always different between two adjacent signal lines can be used. According to such a test pattern, it is easy to determine a short circuit between adjacent signal lines. After that, until a prescribed cable check end condition is satisfied (step 1404), it waits for a normal response (predetermined test pattern) to be received from the downstream block (step 1403 NO). Here, the prescribed cable check end condition in step 1404 is, for example, that the cable check start register 108 a is reset (“0”) by the CPU unit 12. If it is determined that a normal response is received (step 1403 YES), the cable check result OK is written in the cable check register (f) (step 1405), and the cable check mode is terminated. On the other hand, if it is determined that the cable check has been completed after a predetermined time has elapsed (NO in step 1403) without being determined as normal response reception (YES in step 1404), the cable check result NG is written to the cable check result register ( f) (Step 1406), the cable check mode is terminated.

  A flowchart showing the functions of the cable check folding means 210, 310 is shown in FIG. As shown in the figure, when the cable check mode is started by receiving the cable check start signal (c), each of the cable check return means 210 and 310 until the prescribed cable check end condition is satisfied. (Step 1502), it waits for a normal response (predetermined test pattern) to be received from the block located upstream (NO in Step 1501).

  If a normal response (predetermined test pattern) is received from the upstream block (step 1501 YES) until the prescribed cable check end condition is satisfied (step 1502), each of the cable check loopback means 210 and 310 is received. Sends data having a predetermined test pattern to the block located upstream (e) using the 16 data signal lines (data signals 1 to 16) (step 1503). As the test pattern used at this time, as shown in FIG. 12B, a test pattern in which the logical value of the signal is always different between two adjacent signal lines can be used. According to such a test pattern, it is easy to determine a short circuit between adjacent signal lines. Thereafter, the cable check mode is terminated after waiting for the cable check end condition to be satisfied (step 1504 YES). On the other hand, if a normal cable check end condition is satisfied without receiving a normal response (step 1502 YES), the cable check mode is immediately ended. Here, the prescribed cable check end condition in steps 1502 and 1504 is, for example, that the cable check start register 108 a is reset (“0”) by the CPU unit 12.

  Returning to the flowchart of FIG. 14, if a normal response (predetermined test pattern) is received from the block located on the lower side (step 1403 YES) until the prescribed cable check end condition is satisfied (step 1404 NO), the cable After data corresponding to “cable check result OK” is written in the check result registers 108b, 208b, and 308b (f), the cable check mode is terminated. On the other hand, if a normal cable check end condition is satisfied without receiving a normal response (YES in step 1404), data corresponding to “cable check result NG” is written in the cable check result registers 108b, 208b, and 308b. Thereafter (f), the cable check mode is terminated.

  Returning to the flowchart of FIG. 13, the CPU unit 12 waits for a certain period of time to elapse (YES in step 1302), and resets the cable check start register 108 a (“0”), whereby the cable check unit 109. After notifying the end of the cable check (a) (step 1303), the contents of the cable check result registers 108b, 208b, 308b in the internal registers of the blocks 1, 2, 3 are read (g). Then, the cable check result is confirmed (step 1304).

  Thereafter, on the CPU unit 12 side, the confirmed cable check result is reflected in an internal flag that can be referred to by an instruction constituting the user program in the CPU unit (step 1305).

  As shown in FIG. 9, the above series of processing (FIGS. 13, 14, and 15) is executed for each of all the extension cables, so that data indicating normality and abnormality of each extension cable is obtained. Since it is generated as the contents of the internal flag, the user of the PLC device can appropriately cope with the abnormality of the cable by incorporating the user program with these flags as execution conditions for various abnormality countermeasure processing.

  In other words, the PLC device 100 connects the basic block and the extension block and between the extension blocks with two extension cables parallel to each other, and on the signal receiving side, the two extension cables are connected. Since the logical sum (OR) of the signal lines is taken, even if a connector pin contact failure occurs in one of these two extension cables, if the other is normal, operation continues without any problems. However, if such a continuity failure exists in one of the cables, and if a similar continuity failure occurs in the other cable, the operation is stopped immediately. It will be an unavoidable situation.

  Therefore, by incorporating such a cable check function, if an abnormal situation occurs in which only one cable is operating, an appropriate maintenance is performed immediately by warning the user. Thus, it is possible to return to a normal state in which two cables are used, and further reliability can be improved.

  According to the PLC apparatus 100 described above, the basic block 1 includes the cable check means 109, and each of the additional blocks 2 and 3 includes the cable check means 209 and 309 and the cable check return means 210 and 310. Therefore, if these means are operated periodically, for example, by a timer, or at any time according to a command from the CPU unit, each means performs a cable check spontaneously, and the internal registers 108, 208, Since the check result is stored and saved in 308, the connection status of each extension cable is monitored while high-speed signal exchange is performed between the blocks by appropriately referring to this on the CPU unit 12 side. It is possible to detect the occurrence of a communication failure due to poor contact in the external connector at an early stage.

  According to the present invention, data can be exchanged between the basic block and each additional block at high speed, and the occurrence of a communication failure due to a contact failure in the external connector can be detected at an early stage. It is possible to provide a PLC device that can be added via a cable that can be used.

1 is an external view of a PLC device to which the present invention is applied. It is a schematic internal block diagram of a basic block and an extension block. It is a detailed internal block diagram (one-way signal line part) of a basic block and an extension block. It is a detailed internal block diagram (bidirectional signal line part) of a basic block and an extension block. It is explanatory drawing which shows the flow of the data from an upstream block to a downstream block. It is explanatory drawing which shows the flow of the data from a downstream block to an upstream block. It is a schematic block diagram of the principal part for a cable check. It is a detailed block diagram of the principal part for a cable check. It is explanatory drawing which shows the procedure of a cable check process. It is a conceptual diagram of a cable check process. It is explanatory drawing which shows the flow of the data in a cable check process. It is explanatory drawing of the test pattern for a check. It is a flowchart which shows the cable check related process by the side of CPU unit. It is a flowchart which shows the function of a cable check means. It is a flowchart which shows the function of a cable check return means. It is an external view of the conventional PLC apparatus.

Explanation of symbols

1 Basic block 2, 3 Expansion block 10, 20, 30 Backplane 10A, 20A Interface circuit 10B, 20B Internal bus 11, 21, 31 Power supply unit 12 CPU unit 13, 22, 32 I / O unit 14, 23, 33 One-system block connection unit 15, 24, 34 Second-system block connection unit 41, 51 First-system extension cable 42, 52 Second-system extension cable 23a, 33a First-system upstream external connector 14b , 23b, 33b Downstream external connectors of the first system 24a, 34a Upstream external connectors of the second system 15b, 24b, 34b Downstream external connectors of the second system 101 One-way trunk line (on the backplane)
101a, 101b One-way branch line (on backplane)
102 One-way trunk line (on backplane)
102a, 102b One-way branch line (on backplane)
103 OR circuit 104 One-way branch line (on backplane)
104a, 104b One-way branch line (on backplane)
105 Bidirectional trunk line (on backplane)
105-1, 105-2 One-way branch line (on backplane)
105a, 105b Bidirectional branch line (on backplane)
106 OR circuit 107a, 107b Three-state buffer 107c Inverter element 141, 142 One-way branch line (in block connecting unit)
143,144 One-way branch line (inside block connection unit)
151,152 One-way branch line (in block connection unit)
153,154 One-way branch line (in block connection unit)
201 One-way trunk line (on backplane)
201a, 201b One-way branch line (on backplane)
202 One-way main line (on backplane)
202a, 202b One-way branch line (on backplane)
203 OR circuit 204 One-way branch line (on backplane)
205 Bidirectional trunk line (on backplane)
205-1, 205-2 One-way branch line (on backplane)
205a, 205b Bidirectional branch line (on backplane)
206 OR circuit 207a, 207b Three-state buffer 207c Inverter element 231, 232 One-way branch line (in inter-block connection unit)
233, 234 One-way branch line (in block connection unit)
241,242 One-way branch line (in block connection unit)
243, 244 One-way branch line (in block connection unit)
108 Internal register 108a Cable check start register 108b Cable check result register 109 Cable check means 208 Internal register 208b Cable check result register 209 Cable check means 210 Cable check return means 308 Internal register 308b Cable check result register 309 Cable check means 310 Cable check return Means CN Internal connector

Claims (2)

A PLC device in which a basic block and one or more extension blocks are connected via an extension cable,
The basic block is
A plurality of control units including a CPU unit and an I / O unit;
An internal bus connecting those control units,
Including a downstream external connector for leading the internal bus to the outside,
Expansion block is
A plurality of control units including I / O units;
An internal bus connecting those control units,
Including an upstream external connector for leading the internal bus to the outside, or an upstream external connector and a downstream external connector for leading the internal bus to the outside,
The basic block and the expansion block, and the expansion block and the expansion block are connected via an expansion cable that connects the external connectors.
In the basic block,
In response to the arrival of a predetermined check start command, a plurality of bit data having a predetermined test pattern is transferred to an extension unit located downstream via a group of signal lines that bisect the bus line in the extension cable. On the other hand, it is determined whether or not the multi-bit data having a predetermined test pattern has been normally returned from the extension unit located on the downstream side through the remaining group of signal lines, and the determination result is stored in the internal register. Cable check means designed to be stored in
In each of the expansion blocks,
In response to the arrival of a predetermined check start command, a plurality of bit data having a predetermined test pattern is transferred to an extension unit located downstream via a group of signal lines that bisect the bus line in the extension cable. On the other hand, it is determined whether or not the multi-bit data having a predetermined test pattern has been normally returned from the extension unit located on the downstream side through the remaining group of signal lines, and the determination result is stored in the internal register. Cable checking means designed to memorize,
In response to the arrival of a predetermined check start command, a plurality of test patterns having a predetermined test pattern from a basic block or an additional block located on the upstream side through a group of signal lines that bisect the bus line in the additional cable It is determined whether or not the bit data has been normally received. When the bit data has been normally received, a plurality of test patterns having a predetermined test pattern are transferred to the basic block or the additional block located upstream via the remaining group of signal lines. A PLC device, comprising: a cable check return means configured to return bit data. The basic block includes an interface circuit interposed between the internal bus and the downstream external connector,
The expansion block includes an interface circuit interposed between the internal bus and the upstream external connector, or between the internal bus and the upstream external connector and the downstream external connector,
Each of the external connectors includes a first system external connector and a second system external connector that are in parallel with each other,
Between the basic block and the extension block and between the extension block and the extension block, the second extension cable for connecting the first system extension cable and the second system external connector for connecting the first system external connectors to each other. It is connected in parallel via the system extension cable,
Each of the interface circuits includes a plurality of branch circuits that branch-connect each signal line constituting the internal bus to the first system external connector and the second system external connector, and each of the branch circuits is The signal that flows out is allowed to branch to the first system and the second system, while the signal that flows in is designed to allow merging by the logical sum from the first system and the second system,
As a result, the internal buses between the basic block and the extension block and between the extension block and the extension block are always connected through the extension cables of the first system and the second system that are parallel to each other. The PLC device according to claim 1.

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