JPH07134601A - Double bus control method - Google Patents

Abstract

PURPOSE:To provide a double bus control method which can ensure a fast control function of a programmable controller, etc., in a simple constitution and with high operability. CONSTITUTION:A common function unit 2 of a control system is provided with a flag register function 22a which designates the working one of both control function units 1A and 1B. Then the working control function unit designated based on contents of the function 22a transmits its own normal signal for each prescribed condition in an operation flow. If this normal signal does not reach the unit 2 for a prescribed time or longer, an abnormal state of the working control function unit is decided and the function 22a is inverted.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a control system using a general-purpose control device such as a programmable controller, and more particularly to a standby dual system control system suitable when control reliability is required. The present invention relates to a simple bus control method.

[0002]

2. Description of the Related Art For the control of various chemical plants, industrial systems such as machining or casting equipment, or public systems such as water and sewage treatment facilities, computers are the main elements of the control system. Programmable controllers are often used. In the above control, if the programmable controller, which is the main element, fails, for example, the overcurrent breaker trips or the power supply device fails for some reason, or the programmable controller is configured. If the printed circuit board fails, the function of the entire system will stop even if it is a minor failure. When the function of the entire system stops, for example, molten iron flows out in a casting facility, sludge overflows from a tank in a sewerage treatment facility, and a chemical plant stops in the middle of a chemical reaction, resulting in a large amount of damage. There is also the problem of suffering. As a countermeasure, recently, in a control system that places importance on reliability, two sets of control units with the same configuration are prepared, and a standby dual system in which one of them is normally operated and the other one is on standby There is a case where a so-called standby duplex operation, which is configured as described above, is executed. A control system of a standby dual system that executes the standby duplex operation has a configuration as shown in FIG. 5, for example.

In FIG. 5, I / O bus 31 of each of two programmable controllers 31A and 31B.
a and 31b are I to which various cables 33 connected to control actuators and sensors of this control system are connected.
It is connected to the / O module 34 via a bus controller 35. The bus controller 35 is controlled by a control circuit 40 provided inside. This bus control
An address multiplexer 41 connected to the address bus of the above-mentioned I / O buses 31a and 31b and a data multiplexer 42 connected to the data bus are provided inside the controller 35. The address multiplexer 41 and the data bus A multiplexer 42 connects to the I / 0 module 34. Further, the bus controller 35 is provided with a command control circuit 43 and a seek hand register 44. The command control circuit 43 described above calculates the logical product of the commands output from each of the two programmable controllers 31A and 31B in the I / O module 3.
It is output to 4. In addition, the seek hand register 44
Are two types of programmable controllers 31A and 31B
Among them, the programmable controller in operation has a function of temporarily recording the data being executed and transmitting the data to another waiting programmable controller. That is, in the above-described functional configuration, the two types of programmable controllers 31A and 31B have the same configuration and store the same program.

When the first programmable controller 31A of the two programmable controllers is operating, the control circuit 40 causes the address multiplexer 41, the data multiplexer 42, and the command control circuit 43 to operate. Each of the I / 0 modules 34 functions to connect to the first programmable controller 31A. In addition, the first programmable controller 31A
The predetermined programmable controller 31B writes predetermined information such as the data being executed to the seek hand register 44, and the second programmable controller 31B on standby reads the information written to the seek hand register 44 to obtain a predetermined data. -The data is recorded in the internal recording function, and the failure of the first programmable controller 31A is detected. When the first programmable controller 31A goes into an abnormal state during the above-described operation, the control circuit 40 that has detected the failure causes the address multiplexer 41, the data multiplexer 42, and the command control circuit 43 to receive the I / O module respectively. 34 functions to connect to the second programmable controller 31B. In addition, the first programmable controller 31A
The second programmable controller 31B, which has detected that an abnormal state has occurred, executes the control of this control system without interruption using the data recorded inside.
Also, the second programmable controller 31B sends predetermined information such as the data being executed to the seek hand register 44.
Write in.

[0005]

By the way, in the case of the operation function of the standby dual system as described above, the control circuit 40 for executing the switching operation and the shake hand register 44 are mutually programmable. -A flag that indicates whether the printer is normal or abnormal and a recording capacity that records the required capacity data are required. In addition, the control function of the programmable controller during operation is
It is necessary to write predetermined data into a predetermined address of the seek hand register 44 under the same condition as the external I / O function, and therefore control and processing and time for data transmission are required. Is. For that purpose, the bus controller 35
When the above-mentioned data writing process is executed at high speed, the data may be deteriorated due to noise. This has been an obstacle to shortening the time for one cycle of operation of the programmable controller. There is also a problem that the design condition of the control system is limited due to the data transmission function between the programmable controller and the seek hand register in operation. In addition, the operating programmable controller could not be easily switched when checking the replaced programmable controller. The present invention solves the above-mentioned problems (problems) of the prior art, and provides a dual-system bus control method with a simple structure that enables high-speed operation of a control function such as a programmable controller and has good operability. The purpose is to

[0006]

In order to solve the above-mentioned problems, in a dual system bus control method according to the present invention, two types of control function units having the same configuration are arranged in a standby dual system. In the bus control method in the system, a flag register function for designating an operating unit of the two control function units is provided in the common functional unit of this control system, and the operation control functional unit designated by the contents of the flag register function. When the self-normality signal output for each predetermined condition in the operation flow does not reach the common function unit for a predetermined time or longer, it is determined that this operation control function unit is abnormal and the flag register function is inverted. In this case, in the above dual system bus control method, each of the two control function units has a communication function, and the operation control function unit sends predetermined data to the standby control function unit by this communication function. When the operation control function unit is changed, the change control function unit may use this reception data to continue the control. Further, the flag register function described above can be manually reversible by a switch function. Further, the contents of the flag register function may be judged after the normal signal is output.

[0007]

Since the present invention operates by the above method, the flag register function is quickly reversed by the occurrence of an abnormality in the operation control function unit. Further, a predetermined control function unit or a normal control function unit can be operated by the flag register function. Further, since the data of the control function unit in operation is transmitted to the control function unit in standby by the communication function, the transmission time does not affect the operation of the control function unit. Since the communication function can be set appropriately according to the conditions of this system, there is a high degree of freedom in selecting its function performance.
Further, when the flag register function can be manually inverted by the switch function, the operation control function unit can be easily switched when necessary. further,
If the content of the flag register function is determined after the normal signal is output, even if the flag register function is reversed by a switch operation, the operating system can be reliably switched without the control system malfunctioning.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a dual system bus control method according to the present invention will be described with reference to the drawings. 1 and 2 show a configuration example of a control device for a control system to which the present invention is applied. FIG. 1 shows a functional configuration of the control device and FIG. 2 shows a comprehensive configuration. In FIGS. 1 and 2, 10 is a control device of a facility to which the present invention is applied, and the control device 10 is a first control function unit, for example, a programmable control unit, which is a control function unit having two identical configurations. LA (hereafter CPU
A stack) 1A, a second control function unit, for example, a programmable controller (hereinafter abbreviated as CPU stack) 1B, and the controller 10
And an input / output that is a common functional unit of this control device, which has an interface function with peripheral devices, actuators, and sensors provided in the facility to be controlled, and a management function of this control system. The connection function (hereinafter abbreviated as I / O stack) 2 and the like. I / O
The stack 2 includes various cables 3 required for signal transmission that connect between the element functions arranged inside the control device 10 and the element functions arranged outside the control device 10. For example, a terminal for connecting to a bus and other signal lines for connecting a sensor, an actuator, etc. is provided. In the control device 10, the power distribution line 17 is input to each of the above-mentioned stacks via the power switch 18 and the overcurrent breaker 19 and the power bus 17a in the control device.

First CPU stack 1A and second CPU
The stack 1B is composed of a power supply device 11, a CPU card 12, a communication card 13, an I / O stack (common function unit) connection card 14, and other necessary cards. The power supply busbar 17 a is input to the power supply device 11 via the overcurrent breaker 15. Each of the above
Each of the cards is a unit having a predetermined functional circuit, and each function has one card (unit) or a plurality of cards (unit) depending on the function size.
It is composed by. The power supply device 11 is a power supply bus 17
The voltage supplied from a is converted into a DC voltage suitable for the operation of each part in the CPU stack. CPU card 11
Is equipped with, for example, a microcomputer and a memory, a program as a predetermined programmable controller executed by the control device is recorded in the memory, and a function for recording data being processed is provided. I have it. The communication card 13 has a first CPU stack 1A and a second CPU.
A first CPU stack 1A and a second CPU (hereinafter, the communication function is referred to as a communication card) having a communication function for mutually transmitting predetermined data described later in detail between the stacks 1B. The stacks 1B are connected by, for example, an optical cable in accordance with the conditions such as the distance between them. I / O
The stack connection card 14 and the CPU card 12 are connected to C
It is connected to the bus in the PU stack by a signal line or the like. The I / O stack connection card 14 is used for the I / O stack 2
And a bus in the control device 10 and a signal line or the like. Further, the I / O stack connection card 14 removes, for example, noise by adjusting the signal shape of the input signal or the output signal according to the purpose and the necessary condition of the input signal or the output signal according to the condition of the control system. Alternatively, it may be provided with a function of transforming the signal waveform so as to conform to the allowable processing time.

The I / O stack 2 is composed of a power supply unit 21, a switching card 22, an I / O card 23, and other necessary cards, and the above-mentioned power supply busbar 17a is an overcurrent breaker. It is input to the power supply device 21 via 25.
Each of the above-mentioned cards is a unit having a predetermined functional circuit, and each function has one card (unit) or a plurality of cards (units) depending on the function size and the like. ). The power supply device 21 converts the voltage supplied from the power supply bus 17a into a DC voltage suitable for the operation of each part in the I / O stack 2. The changeover card 22 is internally provided with a flag register function 22a, the details of which will be described later, and the flag register function 22a is also connected to a flag register function operation switch 22b provided on an operation panel (not shown) of the controller 10. . Also, each C
The PU cards 1A and 1B are connected to each other by a bus, a signal line, or the like in the control device 10, and this bus has a flag register function 2
Depending on the contents of 2a, the connection to the first CPU stack 1A or the second CPU stack 1B is switched. The signal line also has a function of transmitting the contents of the flag register function 22a. In the I / O card 23,
A cable 3 including a predetermined signal line such as a bus is connected to each device outside the controller 10.

Next, the above-mentioned flag register function 22a
Explain the function of. The flag register function 22a is composed of a 2-stable flip-flop for displaying 1 and 0 or a corresponding function, and specifies a CPU stack to operate according to the displayed contents. For example, the flag register function 22a and each of the CPU stacks 1A and 1B are connected substantially as shown in FIG. In FIG. 4, reference numeral 22c is an inverter, and other symbols are those in FIG.
Is common with. That is, when the flag register function 22a is 0, 1 is input to the second CPU stack 1B,
CPU stack 1B is designated to operate. First
0 is input to the CPU stack 1A of the first CPU
Specifies that stack 1A is waiting. Further, according to the contents designated by the flag register function 22a, each predetermined bus is connected to the designated second CPU stack 1B. That is, when the second CPU stack 1B is designated to operate, each predetermined bus is connected to the second CPU stack 1B and the second CPU stack 1B operates. Therefore,
When the flag register function 22a is 1, the first C
The operation is specified in the PU stack 1A, 0 is input in the second CPU stack 1B, and the second CPU stack 1A is input.
B designates to wait. First CPU stack 1
When A is designated to operate, each predetermined bus is connected to the first CPU.
Connected to the stack 1A, the first CPU stack 1A operates.

When the power switch 18 of the control device 10 is operated to start up the control device, the flag register function 22a is set in a preset condition as an initial condition. That is, for example, the flag register function 22a outputs 1 to designate and operate the first CPU stack 1A. Therefore, the I / O stack connection card 14 of the first CPU stack 1A functions to take in the input signal transmitted to the buses connected to the I / O stack 2,
It functions to transmit predetermined signals to the / O stack 2 and / or output a signal to be transmitted to the outside of the control device 10 via the I / O stack 2.

Each CPU stack transmits a normal signal to the I / O stack 2 at preset timings according to the described program. Therefore, the I / O stack 2 constantly determines whether the two sets of CPU stacks are normal or abnormal. Therefore, when the I / O stack 2 determines that both the first CPU stack 1A and the second CPU stack 1B are normal, the flag register function 22a is maintained as it is, and the predetermined function is performed according to the preset condition. Run. I / O stack 2 is the first CP
When it is determined that the U stack 1A is normal and the second CPU stack 1B is abnormal, the flag register function 22a is maintained as it is, and a predetermined function such as outputting an alarm according to a preset condition is executed. The I / O stack 2 was operating, the first CPU stack 1A was abnormal, and the second CPU stack 1A
If it is determined that the CPU stack 1B is normal, the flag register function 22a is inverted to switch the operating CPU stack from the first CPU stack 1A to the second CPU stack 1B.

When it is necessary to check the replaced CPU stack or switch the operating CPU after repairing or replacing the abnormal stack, the operation of the control unit 10 is performed.
Switch operates the flag register function operation switch 22b. When the flag register function operation switch 22b is operated, the flag register function 22a is inverted. In that case, if necessary, the switch operation is not performed immediately, but is currently in operation or is the switching destination.
The CPU stack 1A or the second CPU stack 1B may be inverted when a predetermined condition is satisfied. Further, even when both of the two types of CPU stacks are abnormal, the flag register function operation switch 22b can be operated to operate any CPU stack.

In the I / O stack 2, the operating CPU
Under the condition that data is being transmitted to and from the stack, until the transmission is completed, the operation of the switching card such as inversion of the flag register function 22a is suspended and the signal is interrupted. It has a function to prevent reading and writing of abnormal signals. As will be described later in detail, the control device 10 has a flag register function 2 at a predetermined timing.
Since the contents of 2a are checked, the operating CPU stack is switched without fear of interrupting the control.

Next, the operation of the configuration example shown in FIGS. 1 and 2 will be described using the schematic flow chart shown in FIG. Figure 3
Is a flow showing the function in the first CPU stack 1A.
(A), a flow showing the operation in the second CPU stack 1B (B), a flow showing the operation in the I / O stack 2
(C) is divided and described. First CPU stack 1
Since the function in A and the function in the second CPU stack 1B are the same, in the description with FIG. 3, the flow (A) in which the first CPU stack 1A is the operating CPU stack will be mainly described. In FIG. 1, when the power switch 18 of the control device 10 is operated, a voltage is supplied from the in-device power bus 17a to the power devices 11 in the respective CPU stacks. CPU card 12, communication card 13, I / O stack connection card 14
And the like are supplied with a predetermined voltage to start a predetermined operation. Further, since the voltage is supplied to the power supply device 21 in the I / O stack 2 from the in-device power supply bus 17a, the I / O stack 2
A predetermined voltage is supplied to each of the cards, the switching card 22, the I / O card 23, etc. to start a predetermined operation. The flag register function 22a in the switching card 22 is set to a predetermined initial condition, for example, 1 as described above. Also,
Since various treatments (not shown) connected to the control device 10 and attached to the control system are subjected to predetermined treatment and power is supplied, the control device 10 connected by the I / O stack 2 and the cable 3 Each external function also starts a predetermined operation.

In FIG. 3A, when the first CPU stack 1A starts to operate, predetermined control initial processing is performed according to a program recorded in a memory function (not shown) provided in the CPU card 12. When the control initial process is completed, a predetermined normal signal indicating that the self CPU stack is normal is output to the I / O stack 2. After outputting the normal signal, the contents of the flag register function 22a transmitted from the switching card 22 of the I / O stack 2 are checked. When the flag register function 22a is 1 and indicates the operation of the self CPU stack, the communication card 13 is set to the transmission mode and the I / O stack connection card 14 is set to the I / O stack 2. The data signal transmitted by the bus connected to the switching card 22 is taken in and the CP
A predetermined series of processing is performed according to a control program recorded in a memory function (not shown) provided in the U-card 12, and the processing result is output by the I / O stack connection card 14 to the I / O stack card 14.
Output to the bus connected to the switching card 22 of the O-stack 2. Also, predetermined data of the processing result is output to the communication card 13. When the CPU card 12 executes the above processing and output operation, it outputs a predetermined normal signal indicating that the self CPU stack is normal to the I / O stack 2 through a predetermined signal line. Therefore, the processing operation described above is repeatedly executed. For example, 100 milliseconds is applied to this series of operations. Therefore, in this case, the normal signal is output every 100 milliseconds.

In the communication card 13, the communication card 1
The CPU card 1 has a latch function (not shown) provided in FIG.
The data sent from the second CPU stack 1 is temporarily recorded, and then the second CPU stack 1 is operated according to a predetermined protocol set in advance.
It is transmitted to the communication card 13 of B.

Switching card 2 for the above-mentioned I / O stack 2
As a result of checking the content of the flag register function 22a transmitted from the CPU 2, it is determined that the content of the flag register function 22a is 0 and the self CPU stack is in standby, the CPU card 12 executes the control program described above. The communication card 13 is set to the reception mode without executing the communication card.
The reception data recorded in the latch function (not shown) provided in the mode 13 is fetched and recorded in a predetermined address of the memory function (not shown). That is, the communication card 1 designated to wait
3 receives the data transmitted from the communication card 13 of the operating CPU stack according to a predetermined protocol and records it in a latch function (not shown). When the CPU card 12 executes the above processing and input operation, it outputs a predetermined normal signal to the I / O stack 2 indicating that its own CPU stack is normal. Therefore, the processing operation described above is repeatedly executed. The time required for repetitive execution is set to be the same as the output pitch of a normal signal in a series of operating states. Therefore, the normal signal is output, for example, every 100 milliseconds. By the time sequence described above, even if the flag register function 22a is inverted during execution of the control program, the operating stack can be safely switched without interruption of the control program.

When the I / O stack 2 starts to operate, as described above with reference to FIG.
The flag register function 22a provided in 1 is set to 1 to operate the first CPU stack 1A and put the second CPU stack 1B on standby. That is, each bus such as predetermined signal lines of the cable 3 connected to the I / O card 23 is connected to the I / O stack connection card 14 of the first CPU stack 1A. Function. After that, the normal signal input from the first CPU stack 1A and the second CPU stack 1B is confirmed, and for example, the normal signal input from the first CPU stack 1A is not input even after waiting a predetermined time from 100 milliseconds. Then, the flag register function 22a provided in the switching card 22 is set to 0 to make the first CPU stack 1A stand by and the second CPU stack 1B to operate. That is,
Further, each bus such as predetermined signal lines of the cable 3 connected to the I / O card 23 is connected to the I / O stack connection card 14 of the second CPU stack 1B. Function.

The flag register function operation switch 2
When a switching signal is input from 2b, a flag register function 22a provided in the switching card 22 is provided according to a predetermined condition.
Is reversed to switch the operation of the first CPU stack 1A and the second CPU stack 1B.

As described above, the first CPU stack 1A
Is operating, the overcurrent breaker 15 provided in the power input section of the first CPU stack 1A itself trips, the power supply device 11 fails, or the failure signal output function of the CPU card 12 or I When a failure occurs in the / O stack connection card 14 or the like, the normal signal is naturally not output. Also,
When the other functions of the CPU card 12, the communication card 13 or the like fails, the normal check signal provided in the CPU card 12 stops the output of the normal signal. Therefore,
As described above, the flag register function 22a of the I / O stack 2 is inverted.

The above description shows the basic method and configuration for realizing the technical idea of the present invention, and can be variously applied and modified. For example, the configurations shown in FIGS. 1 and 2 are examples of applying the present invention, and can be applied to other configuration systems as long as the above-described technical idea can be realized. In that case, the flow example shown in FIG. 3 may be modified in accordance with the circuit configuration. Also, the functions of each stack and cards may be set appropriately. For example, in order to switch the connection between the I / O card 23 of the I / O stack 2 and the I / O stack connection card 14 of the CPU stack, the switching of the I / O stack 2 is described in the above description of the embodiment. Although it has been described that buses are connected to the card 22 and the buses are switched under a predetermined condition, the switching card 22 is used for the switching.
Even if the switching gates are provided in the CPU stack, the I / O stack connection card 14 of the CPU stack may be provided with gates for performing input / output operations (signal interruption or transmission / reception execution). good. Further, the flag register function may of course have any configuration and method as long as it has the function described in the embodiment. Further, the configuration and sharing of the transmission signal processing function are performed by the system constituting the control unit such as the configuration of the bus connecting card in the I / O stack 2 other than the switching card 22. It is natural that the control device should function according to the conditions and the like based on an appropriate design concept of each stack, which is the configuration and function of the control device.

[0024]

Since the present invention is a method as described above,
It has the following excellent effects. With a simple configuration, it is possible to determine whether the abnormal control function unit (CPU stack) or the normal control function unit (CPU stack). With a simple structure, the abnormal control function unit (CPU stack) and the normal control function unit (CPU stack) can be replaced safely and quickly. Since the standby side control function unit (CPU stack) receives the data of the running side control function unit (CPU stack) being executed, the operation side control function unit (CPU stack)
When the stack becomes abnormal, the standby side control function unit (CPU stack) can promptly execute the function as the operating side without malfunctioning. Since the operating side control function unit (CPU stack) transmits data to the standby side control function unit (CPU stack) by the communication function, it is executed without affecting the transmission time in the control program execution cycle. The cycle time can be shortened. Since the operating control function unit (CPU stack) transmits the data to the standby control function unit (CPU stack) by the communication function, it is appropriate to handle the data depending on the conditions of the control system and the control device. -The data communication function can be configured, and the alteration of data due to noise can be prevented. If a normal signal is transmitted in each execution cycle, and non-reception of the normal signal within a predetermined time is determined to be an abnormality of the unit, it is possible to quickly and easily determine whether the unit is normal or abnormal. If the flag register function operation switch 22b is used at the time of outputting a normal signal and the content of the flag register function is judged after the normal signal is output, even if the flag register function is reversed by a switch operation, etc. Since it is possible to prevent the flag register function from being inverted between the determination of the content of the function and the execution of the control operation, it is possible to reliably switch the operating unit without causing the control system to malfunction. Even if both of the two types of control function units (CPU stacks) are abnormal, if the switching of the control function units (CPU stacks) operated by the switch operation can be executed, the abnormality content can be inspected. .

[Brief description of drawings]

FIG. 1 is a schematic block diagram showing a functional configuration example of a control device in a control system to which a dual system bus control method according to the present invention is applied.

FIG. 2 is a schematic block diagram showing an example of the overall configuration of a control device in a control system to which a dual system bus control method according to the present invention is applied.

3 is a schematic flowchart showing an example of an operation flow based on the present invention in the control system configuration example shown in FIG.

FIG. 4 is a connection diagram illustrating the operation of the flag register function shown in FIG.

FIG. 5 is a schematic block diagram illustrating an example of a conventional dual system bus control method.

[Explanation of symbols]

1A, 1B: CPU stack (control function unit) 2: I / O stack (common function unit) 3: Cable 10: Control device 11, 21: Power supply device 12: CPU card 13: Communication card ( Communication function) 14: I / O stack connection card (common function unit connection card) 22: Changeover card 22a: Flag register function 22b: Flag register function operation switch (switch function) 22c: Inverter 23 : I / O card

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Masashi Takeshita Inventor Masashi Takeshita, Toyohashi City, Aichi Prefecture 150 Motoyashiki, Shinko Electric Co., Ltd. Address Shinko Electric Co., Ltd. Toyohashi Works

Claims (4)

[Claims] 1. A bus control method in a control system in which two sets of control function units having the same structure are configured in a standby dual system, wherein a common function unit of the control system is one of the two sets of control function units. A flag register function that specifies the operation control function unit is provided, and the specification based on the contents of this flag register function is determined, and the operation control function unit that is connected to the bus and operates outputs a self-normality signal for each predetermined condition in the operation flow. If the operation control function unit does not reach the common function unit for a predetermined time or longer, it is determined that the operation control function unit is abnormal, the flag register function is inverted, and the operation control function unit is replaced to change the bus connection. A dual system bus control method characterized by the above. 2. The dual system bus controller according to claim 1.
In the above method, each of the two control function units is provided with a communication function, and the operation control function unit transmits predetermined data to the standby control function unit by the communication function, and when the operation control function unit is replaced, A dual system bus control method in which the new operation control functional unit that has been replaced continues to control using the received data. 3. A dual system bus control method wherein the flag register function according to claim 1 can be manually inverted by a switch function. 4. The dual system bus controller in which the normal signal output timing and the flag register function content determination timing in the control function unit according to claim 1 are determined after the normal signal is output. -Le method.