CN103728909A - Double-bus control mode multi-IO control device facing to high-speed chip mounter - Google Patents
Double-bus control mode multi-IO control device facing to high-speed chip mounter Download PDFInfo
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- CN103728909A CN103728909A CN201410027255.7A CN201410027255A CN103728909A CN 103728909 A CN103728909 A CN 103728909A CN 201410027255 A CN201410027255 A CN 201410027255A CN 103728909 A CN103728909 A CN 103728909A
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Abstract
The invention provides a double-bus control mode multi-IO control device facing to a high-speed chip mounter and relates to a control device. The multi-IO control device aims to solve the problem that a controller is not favorable for integration of multiple control ports at present. The multi-IO control device comprises a CPLD control module, a single-chip microcomputer module, a CAN bus communication module, a level conversion module and an ISA secondary bus. The CPLD control module is in communication with other devices of the ISA secondary bus through the level conversion module and the ISA secondary bus, the single-chip microcomputer module is in communication with other devices of a CAN bus through the CAN bus communication module, an interrupt/address multiplex port outside the single-chip microcomputer module is connected with an interrupt IO port of the CPLD control module, a first universal IO port of the single-chip microcomputer module is connected with an address IO port of the CPLD control module through a 7-bit special address parallel bus, and a second universal IO port of the single-chip microcomputer module is connected with a data IO port of the CPLD control module through a 16-bit special address parallel bus. The multi-IO control device serves as an industrial universal controller.
Description
Technical field
The present invention relates to a kind of control device, particularly a kind of many IO control device of the dual bus control model towards high speed placement system.
Background technology
The industrial general controller that the PLC of take is representative, although had, compared with this series products of ripe design proposal, to have volume large, and price is high, and controller function is single, is unfavorable for the integration of multi-control donsole, and the application in SMT field has certain limitation.
Summary of the invention
The object of the invention is to be unfavorable in order to solve current controller the problem of the integration of multi-control donsole, the invention provides a kind of many IO control device of the dual bus control model towards high speed placement system.
Many IO control device of the dual bus control model towards high speed placement system of the present invention, it comprises CPLD control module, one-chip computer module, CAN bus communication module, level switch module and ISA secondary bus;
CPLD control module is by level switch module and ISA secondary bus and other devices communicatings of ISA secondary bus;
One-chip computer module is by CAN bus communication module and other devices communicatings of CAN bus;
Outer interruption/address multiplex port of one-chip computer module is connected with the responsible interruption IO port of CPLD control module;
The first universal I/O port of one-chip computer module is connected with the responsible address IO port of CPLD control module by 7 specific address parallel buss;
The second universal I/O port of one-chip computer module is connected with the responsible data I/O port of CPLD control module by 16 exclusive data parallel buss.
It also comprises 32-bit number load module, first signal buffer circuit, 32-bit number power output module, secondary signal buffer circuit and 8 position digital signal output modules;
The digital signal output end of 32-bit number load module is connected with the digital signal input end of first signal buffer circuit, and the 24V digital signal output end of first signal buffer circuit is connected with the 24V digital signal input end of CPLD control module;
The digital signal output end of CPLD control module is connected with the digital signal input end of secondary signal buffer circuit;
The 24V digital signal output end of secondary signal buffer circuit is connected with the 24V digital signal input end of 32-bit number power output module;
8 position digital signal output terminals of one-chip computer module are connected with 8 position digital signal input ends of 8 position digital signal output modules.
It also comprises FLASH storage and power failure protection module;
Described FLASH storage and power failure protection module, for regularly writing the duty of one-chip computer module, also under the powering-off state in burst for one-chip computer module is powered, until power up normal power supply.
It also comprises logic power load module and driving power load module;
Logic power load module provides working power for CPLD control module, one-chip computer module, CAN bus communication module, level switch module, ISA secondary bus, first signal buffer circuit and secondary signal buffer circuit;
Driving power load module provides working power for 32-bit number load module, 32-bit number power output module and 8 position digital signal output modules.
Beneficial effect of the present invention: the present invention be take 32 bit wide scope 24V digital input modules as logic input, by take one-chip computer module 2 and CPLD control module 1, be main control module, by logical operation CPLD control module 1 and sequential operation one-chip computer module 2, realize the output of 24V digital logic signal and the power stage of totally 40.There is ISA secondary bus 5 and CAN bus communication module 3 simultaneously, can realize the data output of 5 pairs of presumptive addresss of ISA secondary bus and read in, also possess reading in and fan-out capability of CAN bus simultaneously, bus data can participate in control figure output and input simultaneously, the special-purpose many IO control system of SMT that realizes dual bus control model, is beneficial to the integration of multi-control donsole.
Accompanying drawing explanation
Fig. 1 is the principle schematic of many IO control device of the dual bus control model towards high speed placement system of the present invention.
Embodiment
Embodiment one: present embodiment is described in conjunction with Fig. 1, many IO control device of the dual bus control model towards high speed placement system described in present embodiment, it comprises CPLD control module 1, one-chip computer module 2, CAN bus communication module 3, level switch module 4 and ISA secondary bus 5;
CPLD control module 1 is by level switch module 4 and ISA secondary bus 5 and ISA secondary bus 5 other devices communicatings;
One-chip computer module 2 is by CAN bus communication module 3 and other devices communicatings of CAN bus;
Outer interruption/address multiplex port of one-chip computer module 2 is connected with the responsible interruption IO port of CPLD control module 1;
The first universal I/O port of one-chip computer module 2 is connected with the responsible address IO port of CPLD control module 1 by 7 specific address parallel buss;
The second universal I/O port of one-chip computer module 2 is connected with the responsible data I/O port of CPLD control module 1 by 16 exclusive data parallel buss.
Present embodiment forms total control module by CPLD control module 1 and one-chip computer module 2, CPLD control module 1 has very flexible and efficient and feature high-adaptability when processing complex logic function, the hardware circuit that does not need to change circuit board in the face of different logics needs only to need change CPLD control module 1 internal processes forms, this feature of present embodiment can complete all digital input and output logic control functions, rather than single hardware logic is controlled, simultaneously, connection present embodiment by CAN bus communication module 3 and ISA secondary bus 5 can be expanded with control panel or the drive plate with same-interface, complete more complicated logic function.In addition, CPLD control module 1 and one-chip computer module 2 have the active crystal oscillator of corresponding 10M and the passive crystal oscillator of 4M, therefore can also provide good sequential control function for present embodiment, by chip type selecting, can make it reach very high stability, the basic function that can fully complete the type of PLC control in the market IO control system, completes backward compatible ability.
The CPLD control module 1 of present embodiment is communicated by letter with 16 position datawire parallel interfaces by eight bit address lines mutually with one-chip computer module 2, wherein address parallel bus connects one-chip computer module 2 external interrupt mouths, can complete real-time response by interruption, by 8 bit address lines, can manage and reach 256 addresses or special command, and by external interrupt, undertaken, do not take one-chip computer module 2 self process.
For coordinating SMT system Real Time Control Function, present embodiment has added the control of dual bus, wherein ISA secondary bus 5 can realize fast parallel data communication in short distance, also can carry out by command address is set the order of correspondence self system of Upper system output.CAN bus communication module 3 can communicate in longer distance and other equipment, also can export and input the order of setting, ISA secondary bus 5 and CAN bus communication module 3 can read and operate present embodiment, make present embodiment can obtain a large amount of external datas, also the data of oneself can be exported to other has the system needing.The dirigibility of whole work system, intelligent and real-time have greatly been improved.Simultaneously, present embodiment just can be carried out the data in ISA secondary bus 5 and CAN bus communication module 3 alternately by coding, makes other systems of only having a bus to the uncontrollable bus with communicating by letter, to carry out reading in of data by present embodiment and writes out and order control.
In this enforcement, utilize the method for isa bus expansion ISA secondary bus 5:
Described step 1, PC104 embedded system is connected by isa bus with CPLD control module 1, and adopts active crystal oscillator as the clock signal of CPLD control module 1,
Step 2, PC104 embedded system is connected by isa bus with CPLD control module 1, CPLD control module 1 realizes the parsing of isa bus is expanded to secondary bus.
CPLD control module described in step 21 realizes the process that the parsing of isa bus is expanded to secondary bus and comprises and write data procedures, and write data process comprises the following steps:
Step 2 one, employing code translator carry out decoding to the address bus of isa bus and control bus, and export reading signal lines, write signal line, select two-level address bus signal line and select secondary data bus signal line,
Step 2 two, selecting to write data on two-level address bus signal line, using in the data bus of isa bus low eight as secondary bus address signal,
Step 2 three, employing latch latch the data on selection two-level address bus signal line, the trigger pip that adopts active crystal oscillator to latch as latch data, and gating peripherals,
Step 2 four, selecting write data bus data on secondary data bus signal line, PC104 embedded system is opened the write signal line in isa bus simultaneously, adopt latch to selecting the data on secondary data bus signal line to latch, then PC104 embedded system is closed the write signal line in isa bus.
The process that CPLD control module 1 realization described in step 2 expands secondary bus to the parsing of isa bus comprises reading data course, and described reading data course comprises the following steps:
Step 2 A, employing code translator carry out decoding to the address bus of isa bus and control bus, and export reading signal lines, write signal line, select two-level address bus signal line and select secondary data bus signal line,
Step 2 B, selecting to write data on two-level address bus signal line, using the low eight bit data in data as secondary bus address signal,
Step 2 C, employing latch latch the data on selection two-level address bus signal line, the trigger pip that adopts active crystal oscillator to latch as latch data, and gating peripherals,
The peripherals of step 2 D, gating is put into data on data bus, then PC104 embedded system is opened ISA reading signal lines, the data that peripherals is transmitted are imported in PC104 embedded system and are read by bus driver and isa bus, and then PC104 embedded system is closed ISA reading signal lines.Embodiment two: present embodiment is the further restriction to many IO control device of the dual bus control model towards high speed placement system described in embodiment one,
It also comprises 32-bit number load module 6, first signal buffer circuit 7,32-bit number power output module 8, secondary signal buffer circuit 9 and 8 position digital signal output modules 10;
The digital signal output end of 32-bit number load module 6 is connected with the digital signal input end of first signal buffer circuit 7, and the 24V digital signal output end of first signal buffer circuit 7 is connected with the 24V digital signal input end of CPLD control module 1;
The digital signal output end of CPLD control module 1 is connected with the digital signal input end of secondary signal buffer circuit 9;
The 24V digital signal output end of secondary signal buffer circuit 9 is connected with the 24V digital signal input end of 32-bit number power output module 8;
8 position digital signal output terminals of one-chip computer module 2 are connected with 8 position digital signal input ends of 8 position digital signal output modules 10.
The present embodiment setting nearly wide region 24V digital signal input of 32 is inputted as main, at input end, have to carry on optional and draw and pull down resistor, so the sensor signal of NPN and positive-negative-positive can directly access the input end of present embodiment and draw or drop-down without processing by intermediate transit points such as other connection terminals.Digital signal input is different with control chip interface voltage, so present embodiment employing signal isolation circuit carries out signal isolation to it, and external power source and control panel logic chip power supply are isolated completely, has guaranteed good security and the stability of signal.
Present embodiment has adopted and has aimed at the CPLD control module 1 that solves complex logic, therefore digital input and output also concentrate on the pin of CPLD control module 1, when this makes engineering practice, facing different logics requires directly by changing the program of CPLD control module 1, can directly input signal to be carried out exporting in real time after logic control, because CPLD can accomplish identical with actual logic circuit, little than PLC and singlechip control chip CPLD time delay, have higher stability, programming is simple.
Present embodiment has the ability of 32-bit number power stage, CPLD control module 1 low pressure digital output signal becomes 24V digital signal after secondary signal isolation, by Darlington transistor, amplify output again, can accomplish the pin electric current output of 0.5A, possess the ability of power drive completely.
In addition, one-chip computer module 2 has part ownership 8 bit timing devices and IO multiplexing pins by the external output signal of signal Isolation Amplifier Module, except being controlled 8 position digital signal outputs by one-chip computer module 2, one-chip computer module 2 can externally be exported clock signal accurately by timer, with external units such as Driving Stepping Motors, realize the functions such as accurately transmission.
Embodiment three: present embodiment is the further restriction to many IO control device of the dual bus control model towards high speed placement system described in embodiment one or two,
It also comprises FLASH storage and power failure protection module 11;
Described FLASH storage and power failure protection module 11, for regularly writing the duty of one-chip computer module 2, also for being one-chip computer module 2 power supplies under the powering-off state in burst, until power up normal power supply.
FLASH storage and power failure protection module 11 described in present embodiment are the flash chip of a 128KB; by SPI agreement; regularly chip being carried out to state writes; can guarantee that the control device described in present embodiment and other equipment in bus can inquire the information storing in flash chip in needs; simultaneously; this chip has special-purpose electric capacity protection; can under the powering-off state of burst, appoint for the power supply of chip short-term; the work state information of losing so that overhead control chip is therefrom read power-off after power up, normally works again.
Embodiment four: present embodiment is the further restriction to many IO control device of the dual bus control model towards high speed placement system described in embodiment two,
It also comprises logic power load module 12 and driving power load module 13;
Logic power load module 12 provides working power for CPLD control module 1, one-chip computer module 2, CAN bus communication module 3, level switch module 4, ISA secondary bus 5, first signal buffer circuit 7 and secondary signal buffer circuit 9;
Driving power load module 13 provides working power for 32-bit number load module 6,32-bit number power output module 8 and 8 position digital signal output modules 10.
The present embodiment to external world input and output acquiescence of signal adopts 24V signal; CPLD control module 1, one-chip computer module 2, CAN bus communication module 3, level switch module 4, first signal buffer circuit 7 and secondary signal buffer circuit 9 adopt 3.3V power voltage supply; 5 of ISA secondary bus adopt 5V power supply according to the rules; logic power load module 12 and driving power load module 13 all have power light with power supply input area, the function of reverse connecting protection and filtering.Outside is provided to the bent angle socket of 24V and 5V, the control device described in present embodiment carries 5V-3.3V level transferring chip, and the maximum electric current of supporting 3A guarantees the normal work of the control device described in present embodiment.
In actual applications, the present invention is the circuit board that a block size is about 10cm * 20cm, and the input and output of tipping row signal and power supply in by dedicated pins seat and contact pin, are connected on workbench.And inner with automatic electric-level conversion and power protection display module, external 5V logic power and 24V driving power get final product work, and control section has the burned socket of program, facilitates real-time debug, burned program.Four jiaos of circuit board have fixedly via hole, and ISA secondary bus 5 contact pins allow many plates stack work simultaneously, and communicate by letter mutually by ISA secondary bus 5.
The present invention has digital power/signal of nearly 32-bit number signal input and 40 and exports, and can realize sequential by timer and export.
The present invention can, by dual bus and other devices communicatings and Long-distance Control, can send order as main frame and also can be used as the relative logical operation of slave reception command execution in bus.
The present invention has failure data protection ability, has the data storage capacities of 128K.
Logic power load module 12 of the present invention is separated with the power supply signal of driving power load module 13, not altogether, has higher security, and powered operation, facilitates test and debugging separately.
The present invention can carry the flat conversion chip of large-current electric and power protection, only needs extraneous 24V and 5V power supply to get final product work.
Claims (4)
1. towards many IO control device of the dual bus control model of high speed placement system, it is characterized in that being, it comprises CPLD control module (1), one-chip computer module (2), CAN bus communication module (3), level switch module (4) and ISA secondary bus (5);
CPLD control module (1) is by level switch module (4) and ISA secondary bus (5) and other devices communicatings of ISA secondary bus (5);
One-chip computer module (2) is by CAN bus communication module (3) and other devices communicatings of CAN bus;
Outer interruption/address multiplex port of one-chip computer module (2) is connected with the responsible interruption IO port of CPLD control module (1);
The first universal I/O port of one-chip computer module (2) is connected with the responsible address IO port of CPLD control module (1) by 7 specific address parallel buss;
The second universal I/O port of one-chip computer module (2) is connected with the responsible data I/O port of CPLD control module (1) by 16 exclusive data parallel buss.
2. many IO control device of the dual bus control model towards high speed placement system according to claim 1, it is characterized in that, it also comprises 32-bit number load module (6), first signal buffer circuit (7), 32-bit number power output module (8), secondary signal buffer circuit (9) and 8 position digital signal output modules (10);
The digital signal output end of 32-bit number load module (6) is connected with the digital signal input end of first signal buffer circuit (7), and the 24V digital signal output end of first signal buffer circuit (7) is connected with the 24V digital signal input end of CPLD control module (1);
The digital signal output end of CPLD control module (1) is connected with the digital signal input end of secondary signal buffer circuit (9);
The 24V digital signal output end of secondary signal buffer circuit (9) is connected with the 24V digital signal input end of 32-bit number power output module (8);
8 position digital signal output terminals of one-chip computer module (2) are connected with 8 position digital signal input ends of 8 position digital signal output modules (10).
3. many IO control device of the dual bus control model towards high speed placement system according to claim 1 and 2, is characterized in that, it also comprises FLASH storage and power failure protection module (11);
Described FLASH storage and power failure protection module (11), for regularly writing the duty of one-chip computer module (2), also for being one-chip computer module (2) power supply under the powering-off state in burst, until power up normal power supply.
4. many IO control device of the dual bus control model towards high speed placement system according to claim 2, is characterized in that, it also comprises logic power load module (12) and driving power load module (13);
Logic power load module (12) is that CPLD control module (1), one-chip computer module (2), CAN bus communication module (3), level switch module (4), ISA secondary bus (5), first signal buffer circuit (7) and secondary signal buffer circuit (9) provide working power;
Driving power load module (13) is that 32-bit number load module (6), 32-bit number power output module (8) and 8 position digital signal output modules (10) provide working power.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201410027255.7A CN103728909A (en) | 2014-01-22 | 2014-01-22 | Double-bus control mode multi-IO control device facing to high-speed chip mounter |
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| CN201410027255.7A CN103728909A (en) | 2014-01-22 | 2014-01-22 | Double-bus control mode multi-IO control device facing to high-speed chip mounter |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN108241316A (en) * | 2017-01-06 | 2018-07-03 | 广东华志珹智能科技有限公司 | A kind of placement head driving and control integrated system |
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| CN2758901Y (en) * | 2004-04-27 | 2006-02-15 | 天津理工学院 | Microcomputer principle and CAN bus teaching experiment apparatus |
| CN201258206Y (en) * | 2008-08-08 | 2009-06-17 | 天津莱茵克拉电梯有限公司 | Elevator main controller |
| CN201569691U (en) * | 2009-09-28 | 2010-09-01 | 深圳市双合电脑系统股份有限公司 | Electric power quality monitoring and synchronous phasor monitoring device of power system |
| CN202083923U (en) * | 2011-05-21 | 2011-12-21 | 兰州海红通信设备有限责任公司 | Intelligent cabinet control unit |
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2014
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Patent Citations (5)
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| JPH07134601A (en) * | 1993-11-10 | 1995-05-23 | Shinko Electric Co Ltd | Double bus control method |
| CN2758901Y (en) * | 2004-04-27 | 2006-02-15 | 天津理工学院 | Microcomputer principle and CAN bus teaching experiment apparatus |
| CN201258206Y (en) * | 2008-08-08 | 2009-06-17 | 天津莱茵克拉电梯有限公司 | Elevator main controller |
| CN201569691U (en) * | 2009-09-28 | 2010-09-01 | 深圳市双合电脑系统股份有限公司 | Electric power quality monitoring and synchronous phasor monitoring device of power system |
| CN202083923U (en) * | 2011-05-21 | 2011-12-21 | 兰州海红通信设备有限责任公司 | Intelligent cabinet control unit |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN108241316A (en) * | 2017-01-06 | 2018-07-03 | 广东华志珹智能科技有限公司 | A kind of placement head driving and control integrated system |
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Application publication date: 20140416 |