JP2008072067A - Semiconductor device - Google Patents

Semiconductor device Download PDF

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JP2008072067A
JP2008072067A JP2006251875A JP2006251875A JP2008072067A JP 2008072067 A JP2008072067 A JP 2008072067A JP 2006251875 A JP2006251875 A JP 2006251875A JP 2006251875 A JP2006251875 A JP 2006251875A JP 2008072067 A JP2008072067 A JP 2008072067A
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semiconductor device
pad
interposer
semiconductor
semiconductor element
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Takeshi Murata
武志 村田
Hisamitsu Ishikawa
寿光 石川
Toshihiro Ushijima
利弘 牛島
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Toshiba Corp
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    • H01L2225/06503—Stacked arrangements of devices
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    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
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Abstract

<P>PROBLEM TO BE SOLVED: To shorten a length of bonding wires, reducing a dimension of a semiconductor device in the semiconductor device constructed to have a plurality of semiconductor components in a stack. <P>SOLUTION: A first semiconductor component is provided on a substrate for a semiconductor device which has connecting terminals provided on a top surface, and a rectangular opening is formed in a top surface of the first semiconductor component. Next, the semiconductor device is constructed, having: a rectangular second semiconductor component provided with an interposer in the opening, the interposer having first pads formed in each of adjoining regions of the four sides which define the opening in the top surface and second pads formed in the outer edge regions of the top surface making electrical connection with the first pads, and the second semiconductor component having third pads formed on each of the regions in the top surface which respectively adjoin the adjoining regions of the four sides; first wirings which electrically connect the first pads and the second pads; and second wirings which electrically connect the second pads and the connecting terminals. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

本発明は、半導体装置に関し、特に複数の半導体素子が積層されたマルチチップ型半導体装置に関する。   The present invention relates to a semiconductor device, and more particularly to a multichip semiconductor device in which a plurality of semiconductor elements are stacked.

半導体装置は、大容量・高機能・高速化の要求により複数の半導体素子を積層したＳｉＰ化が進んでいる。この場合、２辺以上にパッドが構成されている複数の半導体素子を積層し、これら半導体素子の電極から半導体装置用基板もしくはリードフレームにボンディングワイヤを介して電気的に接続するためは半導体素子間にスペーサを設け、このスペーサを介して前述のような電気的接続を行う方法がとられている。   Semiconductor devices are being made into SiPs in which a plurality of semiconductor elements are stacked due to demands for large capacity, high functionality, and high speed. In this case, a plurality of semiconductor elements having pads formed on two or more sides are stacked, and the semiconductor elements are electrically connected from the electrodes of these semiconductor elements to the semiconductor device substrate or the lead frame via bonding wires. A method is used in which a spacer is provided on the substrate and electrical connection as described above is performed through the spacer.

一方、１辺のみにパッドが構成されている複数の半導体素子を積層し、これら半導体素子の電極から半導体装置用基板もしくはリードフレームにボンディングワイヤを介して電気的に接続するためには、半導体素子の配置をオフセットすることが行われている。   On the other hand, in order to stack a plurality of semiconductor elements each having a pad on only one side and electrically connect the electrodes of these semiconductor elements to a substrate for a semiconductor device or a lead frame via bonding wires, Offsetting the placement has been done.

また、外形寸法の異なる半導体素子を積層することも一般的に実施されており、ＢＧＡ型の半導体装置のように半導体装置用基板を使用する半導体装置においては、下段側の半導体素子に比べてサイズが小さい半導体素子を積層する場合、下段側半導体素子の角にサイズの小さい半導体素子を配置して、この半導体素子の各辺のパッドから前記半導体装置用基板の電極に対してボンディングワイヤで接続することが可能である。   In addition, it is common practice to stack semiconductor elements having different external dimensions. In a semiconductor device using a semiconductor device substrate, such as a BGA type semiconductor device, the size is smaller than that of a lower-stage semiconductor element. When a semiconductor element having a small size is stacked, a semiconductor element having a small size is arranged at the corner of the lower semiconductor element, and the bonding pads connect the pads on each side of the semiconductor element to the electrodes of the semiconductor device substrate. It is possible.

しかしながら、このような態様では、前記半導体素子の配置に依存して、前記半導体装置用基板に近接した２辺のパッドから前記半導体装置用基板の電極までの配線距離は短くすることができる一方、前記半導体装置用基板から離隔した２辺のパッドから前記半導体装置用基板の電極までの配線距離が長くなり、かつ配線角度が大きくなるために、隣接する配線間において組立に必要な距離が確保できなくなるため、隣接する配線間の短絡および半導体素子と配線との接触等の技術的課題により、前記半導体素子のパッドから直接半導体装置用基板の電極にボンディングワイヤで電気的に接続することが困難である。   However, in such an embodiment, depending on the arrangement of the semiconductor elements, the wiring distance from the pads on the two sides close to the semiconductor device substrate to the electrodes of the semiconductor device substrate can be shortened, Since the wiring distance from the pads on the two sides separated from the semiconductor device substrate to the electrodes of the semiconductor device substrate is increased and the wiring angle is increased, the distance necessary for assembly can be secured between adjacent wirings. Therefore, due to technical problems such as short circuit between adjacent wires and contact between semiconductor elements and wires, it is difficult to electrically connect the pads of the semiconductor elements directly to the electrodes of the semiconductor device substrate with bonding wires. is there.

かかる問題に鑑みて、従来においては、インターポーザチップを用いて配線を中継していた（例えば、特許文献１参照）。すなわち、半導体装置用基板上に搭載された大型の半導体素子の上にインターポーザチップを搭載し、そのインターポーザチップの上に小型の半導体素子を搭載し、小型の半導体素子のパッドとインターポーザチップ上の内側領域に形成されたパッドとをワイヤボンディングし、さらにインターポーザチップの外周領域に形成されたパッドと半導体装置用基板上のパッドとをワイヤボンディングするものである。または、半導体装置用基板上に搭載された大型の半導体素子の上にインターポーザチップと小型の半導体素子を並べて配置し、小型の半導体素子の所定の辺側のパッドについてのみインターポーザチップを介して半導体装置用基板のパッドに接続していた。   In view of such a problem, conventionally, wiring has been relayed using an interposer chip (see, for example, Patent Document 1). That is, an interposer chip is mounted on a large semiconductor element mounted on a substrate for a semiconductor device, a small semiconductor element is mounted on the interposer chip, and a pad of the small semiconductor element and an inner side on the interposer chip The pad formed in the region is wire-bonded, and the pad formed in the outer peripheral region of the interposer chip and the pad on the semiconductor device substrate are wire-bonded. Alternatively, an interposer chip and a small semiconductor element are arranged side by side on a large semiconductor element mounted on a substrate for a semiconductor device, and only a pad on a predetermined side of the small semiconductor element is interposed via the interposer chip. It was connected to the pad on the circuit board.

しかしながら、インターポーザチップの上に半導体素子を搭載すると、インタポーザチップの厚み分だけ半導体装置の厚みが増し、半導体装置の小型化が図れないという問題があった。また、インターポーザチップと小型の半導体素子を並べて配置すると、インターポーザチップに隣接する小型の半導体素子の辺および大型の半導体素子の一辺に隣接する小型の半導体素子の辺においてはボンディングワイヤの長さが短くできるが、インターポーザチップおよび大型の半導体素子の辺に隣接しない小型の半導体素子の辺については配線距離を短くできないという問題があった。
特開２００４−２３５３５２ However, when a semiconductor element is mounted on the interposer chip, there is a problem that the thickness of the semiconductor device increases by the thickness of the interposer chip, and the semiconductor device cannot be reduced in size. Further, when the interposer chip and the small semiconductor element are arranged side by side, the length of the bonding wire is short on the side of the small semiconductor element adjacent to the interposer chip and the side of the small semiconductor element adjacent to one side of the large semiconductor element. However, there is a problem that the wiring distance cannot be shortened for the side of the small semiconductor element that is not adjacent to the side of the interposer chip and the large semiconductor element.
JP 2004-235352 A

本発明は、上記問題に鑑みてなされたものであり、複数の半導体素子を積層して構成された半導体装置において、半導体装置の大きさを抑えつつ、ボンディングワイヤの長さを短くすることを目的とする。   The present invention has been made in view of the above problems, and an object of the present invention is to reduce the length of a bonding wire while suppressing the size of a semiconductor device in a semiconductor device configured by stacking a plurality of semiconductor elements. And

上記課題を解決すべく、本発明の一態様は、
上面に接続端子が設けられた半導体装置用基板と、
前記半導体装置用基板上に設けられた第１の半導体素子と、
前記第１の半導体素子上に設けられ、上面に矩形状の開口部が形成され、前記上面の前記開口部を形成する４辺の隣接領域それぞれに第１のパッドが形成され、前記上面の外縁部に前記第１のパッドに電気的に接続された第２のパッドが形成されたインターポーザーと、
前記開口部内に設けられた矩形状の第２の半導体素子であって、前記４辺の隣接領域にそれぞれ隣接する上面領域上にそれぞれ第３のパッドが形成された第２の半導体素子と、
前記第１のパッドと前記第２のパッドとを電気的に接続する第１の配線と、
前記第２のパッドと前記接続端子とを接続する第２の配線と
を具備したことを特徴とする半導体装置に関する。 In order to solve the above problems, one embodiment of the present invention provides:
A substrate for a semiconductor device provided with a connection terminal on the upper surface;
A first semiconductor element provided on the semiconductor device substrate;
Provided on the first semiconductor element, a rectangular opening is formed on the upper surface, a first pad is formed on each of adjacent regions of the four sides forming the opening on the upper surface, and an outer edge of the upper surface An interposer in which a second pad electrically connected to the first pad is formed,
A second semiconductor element having a rectangular shape provided in the opening, wherein a third pad is formed on an upper surface area adjacent to the adjacent area of each of the four sides;
A first wiring that electrically connects the first pad and the second pad;
The present invention relates to a semiconductor device comprising: a second wiring that connects the second pad and the connection terminal.

また、本発明の一態様は、
上面に接続端子が設けられた半導体装置用基板と、
前記半導体装置用基板上に積層された複数の第１の半導体素子と、
前記複数の第１半導体素子の最上層の半導体素子上に設けられ、上面に矩形状の開口部が形成され、前記上面の前記開口部を形成する４辺の隣接領域それぞれに第１のパッドが形成され、前記上面の外縁部に前記第１のパッドに電気的に接続された第２のパッドが形成されたインターポーザーと、
前記開口部内に設けられた矩形状の第２の半導体素子であって、前記４辺の隣接領域にそれぞれ隣接する上面領域上にそれぞれ第３のパッドが形成された第２の半導体素子と、
前記第１のパッドと前記第２のパッドとを電気的に接続する第１の配線と、
前記第２のパッドと前記接続端子とを接続する第２の配線と、
を具備したことを特徴とする半導体装置に関する。 One embodiment of the present invention includes
A substrate for a semiconductor device provided with a connection terminal on the upper surface;
A plurality of first semiconductor elements stacked on the semiconductor device substrate;
Provided on the uppermost semiconductor element of the plurality of first semiconductor elements, a rectangular opening is formed on the upper surface, and a first pad is provided in each of the four adjacent areas forming the opening on the upper surface. An interposer formed and formed with a second pad electrically connected to the first pad on the outer edge of the upper surface;
A second semiconductor element having a rectangular shape provided in the opening, wherein a third pad is formed on an upper surface area adjacent to the adjacent area of each of the four sides;
A first wiring that electrically connects the first pad and the second pad;
A second wiring connecting the second pad and the connection terminal;
It is related with the semiconductor device characterized by comprising.

以上、本発明によれば、複数の半導体素子を積層して構成された半導体装置において、半導体装置の大きさを抑えつつ、ボンディングワイヤの長さを短くすることができる。   As described above, according to the present invention, in a semiconductor device configured by stacking a plurality of semiconductor elements, the length of the bonding wire can be shortened while suppressing the size of the semiconductor device.

以下、本発明のその他の特徴及び利点について発明を実施するための最良の形態に基づいて説明する。   Hereinafter, other features and advantages of the present invention will be described based on the best mode for carrying out the invention.

（第１の実施形態）
図１は、本発明の第１の実施形態における半導体装置の平面図であり、図２は、図１に示す半導体装置のＡ−Ａ線に沿って切った場合の断面図である。 (First embodiment)
FIG. 1 is a plan view of the semiconductor device according to the first embodiment of the present invention, and FIG. 2 is a cross-sectional view taken along the line AA of the semiconductor device shown in FIG.

図１及び２に示すように、半導体装置１０は所謂ＢＧＡ（Ball Grid Array）型のマルチチップパッケージ型半導体装置である。半導体装置は、半導体装置用基板１１上において、順次半導体素子１２，１３及び１４が接着材料１６により接着され、積層されてなる。さらに、半導体素子１４上には、接着材料１６を介して矩形状のインターポーザー１７が形成されている。また、インターポーザー１７の略中央には矩形状の開口部が形成され、この開口部内に接着材料１６を介して矩形状の小型の半導体素子１５が形成されている。開口部はインターポーザー１７の上面から下面にわたり貫通して形成されており、半導体素子１５は接着材料１６により半導体素子１４上に固定されている。また、インターポーザー１７の厚みと半導体素子１４の厚みは等しく、インターポーザー１７の上面と半導体素子１４の上面とはフラットに形成されている。なお、半導体素子１４の厚みはインターポーザー１７の厚み以下であれば良い。   As shown in FIGS. 1 and 2, the semiconductor device 10 is a so-called BGA (Ball Grid Array) type multi-chip package type semiconductor device. The semiconductor device is formed by sequentially laminating semiconductor elements 12, 13, and 14 with an adhesive material 16 on a semiconductor device substrate 11. Further, a rectangular interposer 17 is formed on the semiconductor element 14 via an adhesive material 16. In addition, a rectangular opening is formed in the approximate center of the interposer 17, and a rectangular small semiconductor element 15 is formed in the opening via an adhesive material 16. The opening is formed so as to penetrate from the upper surface to the lower surface of the interposer 17, and the semiconductor element 15 is fixed on the semiconductor element 14 with an adhesive material 16. Further, the thickness of the interposer 17 and the thickness of the semiconductor element 14 are equal, and the upper surface of the interposer 17 and the upper surface of the semiconductor element 14 are formed flat. Note that the thickness of the semiconductor element 14 may be equal to or less than the thickness of the interposer 17.

インターポーザー１７の上面の前記矩形状の開口部の周囲（開口部を形成する４辺それぞれの隣接領域）にはパッド１７Ａがそれぞれ形成されている。半導体素子１５の上面の４辺の外縁部（開口部の隣接領域に隣接する上面領域）には、パッド１５Ａがそれぞれ形成されている。パッド１７Ａとパッド１５Ａとはそれぞれボンディングワイヤである金属配線１８によって電気的に接続されている。また、インターポーザー１７の４つの外周辺（外縁部）のうち、２つの外周辺に隣接する上面上にはパッド１７Ｂが形成され、半導体装置用基板１１の上面上に形成されたパッド１１Ａと金属配線１８によって電気的に接続されている。さらに、半導体素子１４の上面のパッド１４Ａ及び半導体素子１２の上面のパッド（図示せず）と、半導体装置用基板１１上の上面のパッド１１Ａとが金属配線１８によって電気的に接続されている。なお、インターポーザー１７のパッド１７Ａとパッド１７Ｂは電気的に接続されている。また、半導体装置用基板１１の下面には半導体装置用基板１１の上面上に形成された接続端子であるパッド１１Ａと電気的に接続された外部端子が設けられている。   Pads 17 </ b> A are respectively formed around the rectangular opening on the upper surface of the interposer 17 (adjacent regions on each of the four sides forming the opening). Pads 15 </ b> A are respectively formed on the outer edges of the four sides of the upper surface of the semiconductor element 15 (upper surface region adjacent to the adjacent region of the opening). The pad 17A and the pad 15A are electrically connected to each other by a metal wiring 18 which is a bonding wire. Of the four outer peripheries (outer edge portions) of the interposer 17, pads 17B are formed on the upper surface adjacent to the two outer peripheries, and the pad 11A formed on the upper surface of the semiconductor device substrate 11 and the metal The wiring 18 is electrically connected. Further, the pad 14 A on the upper surface of the semiconductor element 14 and the pad (not shown) on the upper surface of the semiconductor element 12 are electrically connected to the pad 11 A on the upper surface of the substrate 11 for semiconductor device by the metal wiring 18. The pad 17A and the pad 17B of the interposer 17 are electrically connected. In addition, an external terminal electrically connected to a pad 11 </ b> A that is a connection terminal formed on the upper surface of the semiconductor device substrate 11 is provided on the lower surface of the semiconductor device substrate 11.

このように、本実施形態の半導体装置においては、特に最上層部にインターポーザー１７を設け、その略中央部に形成した開口部内に小型の半導体素子１５を形成し、この半導体素子１５と半導体装置用基板１１との電気的接続をインターポーザー１７を介して行っている。また、４辺に隣接する上面上のそれぞれにパッド１５Ａが形成された半導体素子１５に対して、開口部を形成する４辺の隣接領域にパッド１７Ａがそれぞれ形成されたインターポーザー１７を用いている。半導体素子１５の全てのパッドについて金属配線長を短くできる。したがって、半導体素子１５とインターポーザー１７との間の配線距離及びインターポーザー１７と半導体装置用基板１１との配線距離を十分に短くすることができ、半導体装置用基板から離隔した２辺のパッドから前記半導体装置用基板の電極までの配線距離が長くなり、かつ配線角度が大きくなることに起因した配線間の短絡や、半導体素子と配線との接触等の問題を生じることがない。   As described above, in the semiconductor device of this embodiment, the interposer 17 is provided in the uppermost layer portion, and the small semiconductor element 15 is formed in the opening formed in the substantially central portion thereof. Electrical connection with the circuit board 11 is performed via the interposer 17. Further, for the semiconductor element 15 in which the pad 15A is formed on each of the upper surfaces adjacent to the four sides, the interposer 17 in which the pads 17A are formed in the adjacent regions on the four sides forming the opening is used. . The metal wiring length can be shortened for all the pads of the semiconductor element 15. Therefore, the wiring distance between the semiconductor element 15 and the interposer 17 and the wiring distance between the interposer 17 and the semiconductor device substrate 11 can be sufficiently shortened from the pads on the two sides separated from the semiconductor device substrate. The wiring distance to the electrode of the semiconductor device substrate is increased and the wiring angle is increased, so that problems such as a short circuit between the wirings and contact between the semiconductor element and the wiring do not occur.

さらに、本態様においては、インターポーザー１７の略中央部に開口を設け、この開口部内に半導体素子１５を収納するようにしているので、半導体素子１５の厚さをインターポーザー１７の厚さで相殺することができ、半導体装置１０全体の厚さ増大による大型化を抑制することができる。   Further, in this embodiment, since an opening is provided in the substantially central portion of the interposer 17 and the semiconductor element 15 is accommodated in the opening, the thickness of the semiconductor element 15 is offset by the thickness of the interposer 17. Therefore, an increase in size due to an increase in the thickness of the entire semiconductor device 10 can be suppressed.

なお、半導体装置用基板１１は、ガラスエポキシやポリイミド等のフィルム上に銅あるいはその他の金属材料などから構成することができる。   In addition, the board | substrate 11 for semiconductor devices can be comprised from copper or another metal material etc. on films, such as glass epoxy and a polyimide.

また、金属配線１８は銅、アルミニウムなどの電気的良導体から構成することができる。さらに、各半導体素子はＳｉベースの半導体素子とすることができ、その具体的構成に関しては、半導体装置１０の用途などに応じて適宜に設定することができる。   Moreover, the metal wiring 18 can be comprised from electrical good conductors, such as copper and aluminum. Furthermore, each semiconductor element can be a Si-based semiconductor element, and a specific configuration thereof can be appropriately set according to the use of the semiconductor device 10 and the like.

なお、本例においては、４つの半導体素子を積層する場合について説明したが、半導体素子の積層数は、半導体装置１０に要求される特性や用途などに応じて適宜に設定することができる。   In this example, the case where four semiconductor elements are stacked has been described. However, the number of stacked semiconductor elements can be set as appropriate according to the characteristics and applications required of the semiconductor device 10.

また、インターポーザー１７内に形成された前記開口部は、所定の金型を用いたモールドにより当初から形成するようにすることもできるし、平板状のインターポーザーを形成した後、ルーターなどを用いて加工形成するようにすることもできる。   In addition, the opening formed in the interposer 17 can be formed from the beginning by molding using a predetermined mold, or after forming a flat interposer, a router or the like is used. It can also be processed and formed.

また、ＢＧＡ型の半導体装置に限らず、ＬＧＡ（Lead Grid Array）型の半導体装置においても用いることができる。   Further, the present invention can be used not only in a BGA type semiconductor device but also in an LGA (Lead Grid Array) type semiconductor device.

（第２の実施形態）
次に、本発明の第２の実施形態における半導体装置について説明する。本例においては、いわゆるＴＳＯＰ（Thin small outline package）型の半導体装置について説明する。 (Second Embodiment)
Next, a semiconductor device according to a second embodiment of the present invention will be described. In this example, a so-called TSOP (Thin Small Outline Package) type semiconductor device will be described.

図３は、上記ＴＳＯＰ型半導体装置の平面図であり、図４は、図３に示す半導体装置をＢ−Ｂ線に沿って切った場合の断面図である。   3 is a plan view of the TSOP type semiconductor device, and FIG. 4 is a cross-sectional view of the semiconductor device shown in FIG. 3 taken along the line BB.

図３及び４に示すように、ＴＳＯＰ型半導体装置２０は、リードフレーム２１上において、順次半導体素子２２及び２３が接着材料２６により接着され、積層されてなる。さらに、半導体素子２３上には、接着材料２６を介して矩形状のインターポーザー２７が形成されている。また、インターポーザー２７の略中央には矩形状の開口部が形成され、この開口部内に接着材料２６を介して小型の半導体素子２５が形成されている。前記開口部はインターポーザー２７の上面から下面にわたり貫通して形成されている。なお、半導体素子２５の厚みはインターポーザー２７の厚み以下であれば良い。   As shown in FIGS. 3 and 4, the TSOP type semiconductor device 20 is formed by sequentially laminating semiconductor elements 22 and 23 with an adhesive material 26 on a lead frame 21. Furthermore, a rectangular interposer 27 is formed on the semiconductor element 23 via an adhesive material 26. In addition, a rectangular opening is formed in the approximate center of the interposer 27, and a small semiconductor element 25 is formed in the opening via an adhesive material 26. The opening is formed so as to penetrate from the upper surface to the lower surface of the interposer 27. In addition, the thickness of the semiconductor element 25 should just be below the thickness of the interposer 27.

インターポーザー２７の前記開口部を形成する４辺それぞれの隣接領域にはパッド２７Ａがそれぞれ形成されている。半導体素子２５の上面の４辺の外縁部（開口部の隣接領域に隣接する上面領域）にはパッド２５Ａがそれぞれ形成されている。パッド２７とパッド１５とは、それぞれボンディングワイヤである金属配線２８によって電気的に接続されている。また、インターポーザー２７の４つの外周辺（外縁部）の内、２つの外周辺に隣接する上面にはパッド２７Ｂが形成され、リードフレーム２１に形成されたパッド２１Ａと金属配線２８によって電気的に接続されている。さらに、半導体素子２２に形成されたパッド２２Ａと、半導体素子２３に形成されたパッド２３Ａと、インターポーザー２７の１外縁部において外側に位置するパッド２７Ｂとは、金属配線２８によって電気的に接続されている。   Pads 27 </ b> A are formed in adjacent regions on each of the four sides forming the opening of the interposer 27. Pads 25 </ b> A are formed on the outer edges of the four sides of the upper surface of the semiconductor element 25 (upper surface region adjacent to the adjacent region of the opening). The pad 27 and the pad 15 are electrically connected to each other by a metal wiring 28 that is a bonding wire. A pad 27B is formed on the upper surface adjacent to the two outer peripheries (outer edges) of the interposer 27, and is electrically connected by the pads 21A and the metal wiring 28 formed on the lead frame 21. It is connected. Further, the pad 22 </ b> A formed on the semiconductor element 22, the pad 23 </ b> A formed on the semiconductor element 23, and the pad 27 </ b> B located outside at one outer edge portion of the interposer 27 are electrically connected by the metal wiring 28. ing.

なお、上記のようにして構成された積層体はモールド樹脂２９によって封止されている。   The laminated body configured as described above is sealed with a mold resin 29.

結果として、本例では、各半導体素子がインターポーザーを介してリードフレームと金属配線によって電気的に接続されることになり、配線構造を極めて簡略化した状態で複数の半導体素子を積層することができ、高機能化を図ることができる。   As a result, in this example, each semiconductor element is electrically connected to the lead frame and the metal wiring via the interposer, and a plurality of semiconductor elements can be stacked with the wiring structure extremely simplified. And high functionality can be achieved.

本例では、半導体素子２２及び２３の大きさが略同一で、半導体素子２４の大きさが前記半導体素子に比較して小さい場合について説明しているが、各半導体素子の大きさがそれぞれ異なる場合においても、その端部に形成したパッドを介して上述のようなインターポーザーに配線を集中させ、この配線をリードフレームに一括して電気的に接続するようにすれば、上記同様の高機能化を図ることができる。   In this example, the case where the sizes of the semiconductor elements 22 and 23 are substantially the same and the size of the semiconductor element 24 is smaller than that of the semiconductor element is described. However, the sizes of the semiconductor elements are different from each other. However, if the wiring is concentrated on the interposer as described above via the pad formed at the end, and the wiring is collectively connected to the lead frame, the same high functionality as described above can be achieved. Can be achieved.

また、このようなインターポーザーを介した一括の電気的接続を行うことにより、前記リードフレームには、各半導体素子からの電気的接続を実現するためのパッドが設けられた余分な引き出し部を形成する必要がない。したがって、ＴＳＯＰ型半導体装置の小型化を実現することができる。   In addition, by performing a batch electrical connection through such an interposer, the lead frame is formed with an extra lead portion provided with a pad for realizing electrical connection from each semiconductor element. There is no need to do. Therefore, it is possible to reduce the size of the TSOP type semiconductor device.

また、本態様においては、インターポーザー２７の略中央部に開口を設け、この開口部内に半導体素子２５を収納するようにしているので、半導体素子２５の厚さをインターポーザー２７の厚さで相殺することができ、ＴＳＯＰ型半導体装置２０全体の厚さ増大による大型化を抑制することができる。   Further, in this embodiment, an opening is provided in a substantially central portion of the interposer 27, and the semiconductor element 25 is accommodated in the opening. Therefore, the thickness of the semiconductor element 25 is offset by the thickness of the interposer 27. Therefore, an increase in size due to an increase in the thickness of the entire TSOP type semiconductor device 20 can be suppressed.

なお、リードフレーム１１は、銅や鉄合金などの金属の薄板を加工して形成することができる。   The lead frame 11 can be formed by processing a thin metal plate such as copper or iron alloy.

また、金属配線２８は銅、アルミニウムなどの電気的良導体から構成することができる。さらに、各半導体素子はＳｉベースの半導体素子とすることができ、その具体的構成に関しては、ＴＳＯＰ型の半導体装置２０の用途などに応じて適宜に設定することができる。   Moreover, the metal wiring 28 can be comprised from electrical good conductors, such as copper and aluminum. Furthermore, each semiconductor element can be a Si-based semiconductor element, and the specific configuration thereof can be set as appropriate according to the application of the TSOP type semiconductor device 20 or the like.

なお、本例においては、３つの半導体素子を積層する場合について説明したが、半導体素子の積層数は、ＴＳＯＰ型半導体装置２０に要求される特性や用途などに応じて適宜に設定することができる。   In this example, the case where three semiconductor elements are stacked has been described. However, the number of stacked semiconductor elements can be set as appropriate according to the characteristics and applications required of the TSOP type semiconductor device 20. .

また、インターポーザー２７内に形成された前記開口部は、所定の金型を用いたモール度により当初から形成するようにすることもできるし、平板状のインターポーザーを形成した後、ルーターなどを用いて加工形成するようにすることもできる。   In addition, the opening formed in the interposer 27 can be formed from the beginning according to the degree of molding using a predetermined mold, or after forming a flat interposer, a router or the like is formed. It can also be processed and formed.

（第３の実施形態）
本例は、上記第２の実施形態の変形例である。上記第２の実施形態では、各半導体素子間の電気的接合及び半導体素子とインターポーザーとの金属配線を介した電気的接合をＴＳＯＰ型半導体装置の短辺側で実施しているが、本例では、図５に示すように、各半導体素子間の電気的接合をＴＳＯＰ型半導体装置の長辺側で実施している。なお、上記第２の実施形態におけるＴＳＯＰ型半導体装置と同一あるいは類似の構成要素に関しては同じ参照符号を用いている。 (Third embodiment)
This example is a modification of the second embodiment. In the second embodiment, the electrical junction between the semiconductor elements and the electrical junction via the metal wiring between the semiconductor element and the interposer are performed on the short side of the TSOP type semiconductor device. Then, as shown in FIG. 5, the electrical connection between the semiconductor elements is performed on the long side of the TSOP type semiconductor device. Note that the same reference numerals are used for the same or similar components as those of the TSOP type semiconductor device in the second embodiment.

本例においても、各半導体素子がインターポーザーを介してリードフレームと金属配線によって電気的に接続されることになり、配線構造を極めて簡略化した状態で複数の半導体素子を積層することができ、高機能化を図ることができる。また、このようなインターポーザーを介した一括の電気的接続を行うことにより、前記リードフレームには、各半導体素子からの電気的接続を実現するためのパッドが設けられた余分な引き出し部を形成する必要がない。したがって、ＴＳＯＰ型半導体装置の小型化を実現することができる。   Also in this example, each semiconductor element is electrically connected by a lead frame and metal wiring through an interposer, and a plurality of semiconductor elements can be stacked with the wiring structure extremely simplified. High functionality can be achieved. In addition, by performing a batch electrical connection through such an interposer, the lead frame is formed with an extra lead portion provided with a pad for realizing electrical connection from each semiconductor element. There is no need to do. Therefore, the TSOP type semiconductor device can be reduced in size.

また、インターポーザー２７の略中央部に開口を設け、この開口部内に半導体素子２５を収納するようにしているので、半導体素子２５の厚さをインターポーザー２７の厚さで相殺することができ、ＴＳＯＰ型半導体装置２０全体の厚さ増大による大型化を抑制することができる。   In addition, since an opening is provided in the substantially central portion of the interposer 27 and the semiconductor element 25 is accommodated in the opening, the thickness of the semiconductor element 25 can be offset by the thickness of the interposer 27. An increase in size due to an increase in the thickness of the entire TSOP type semiconductor device 20 can be suppressed.

なお、その他の特徴に関しては、上記第２の実施の形態と同じである。   Other features are the same as those in the second embodiment.

（第４の実施形態）
本例は、上記第３の実施形態の変形例である。上記第３の実施形態では、インターポーザー２７の略中央部に開口を設け、この開口部内に小型の半導体素子を収納するようにしていたが、本例ではインターポーザー２７は開口部を有しない一様な層とし、前記小型の半導体素子を設けることなく、略同一の半導体素子２２及び２３のみを積層してＴＳＯＰ型の半導体装置を構成している。 (Fourth embodiment)
This example is a modification of the third embodiment. In the third embodiment, an opening is provided in a substantially central portion of the interposer 27, and a small semiconductor element is accommodated in the opening. However, in this example, the interposer 27 does not have an opening. The TSOP type semiconductor device is configured by stacking substantially the same semiconductor elements 22 and 23 without providing the small semiconductor elements.

本例においても、図６に示すように、各半導体素子間の電気的接合をＴＳＯＰ型半導体装置の長辺側で実施し、各半導体素子がインターポーザーを介してリードフレームと金属配線によって電気的に接続されることになり、配線構造を極めて簡略化した状態で複数の半導体素子を積層することができ、高機能化を図ることができる。   Also in this example, as shown in FIG. 6, electrical connection between the semiconductor elements is performed on the long side of the TSOP type semiconductor device, and each semiconductor element is electrically connected by a lead frame and metal wiring via an interposer. Thus, a plurality of semiconductor elements can be stacked with the wiring structure extremely simplified, and high functionality can be achieved.

また、このようなインターポーザーを介した一括の電気的接続を行うことにより、前記リードフレームには、各半導体素子からの電気的接続を実現するためのパッドが設けられた余分な引き出し部を形成する必要がない。したがって、ＴＳＯＰ型半導体装置の小型化を実現することができる。   In addition, by performing a batch electrical connection through such an interposer, the lead frame is formed with an extra lead portion provided with a pad for realizing electrical connection from each semiconductor element. There is no need to do. Therefore, it is possible to reduce the size of the TSOP type semiconductor device.

なお、上記第２の実施形態におけるＴＳＯＰ型半導体装置と同一あるいは類似の構成要素に関しては同じ参照符号を用いている。   Note that the same reference numerals are used for the same or similar components as those of the TSOP type semiconductor device in the second embodiment.

また、本例の他の特徴に関しては、上記第２及び第３の実施の形態と同じである。   The other features of this example are the same as those in the second and third embodiments.

以上、本発明を上記具体例に基づいて詳細に説明したが、本発明は上記具体例に限定されるものではなく、本発明の範疇を逸脱しない限りにおいてあらゆる変形や変更が可能である。   While the present invention has been described in detail based on the above specific examples, the present invention is not limited to the above specific examples, and various modifications and changes can be made without departing from the scope of the present invention.

本発明の第１の実施形態における半導体装置の平面図である。1 is a plan view of a semiconductor device according to a first embodiment of the present invention. 図１に示す半導体装置のＡ−Ａ線に沿って切った場合の断面図である。 本発明の磁気抵抗効果素子の一例を示す構成図である。It is sectional drawing at the time of cutting along the AA line of the semiconductor device shown in FIG. It is a block diagram which shows an example of the magnetoresistive effect element of this invention. 本発明の第２の実施形態における半導体装置の平面図である。It is a top view of the semiconductor device in the 2nd Embodiment of this invention. 図３に示す半導体装置のＢ−Ｂ線に沿って切った場合の断面図である。 本発明の磁気抵抗効果素子の一例を示す構成図である。It is sectional drawing at the time of cutting along the BB line of the semiconductor device shown in FIG. It is a block diagram which shows an example of the magnetoresistive effect element of this invention. 本発明の第３の実施形態における半導体装置の平面図である。It is a top view of the semiconductor device in a 3rd embodiment of the present invention. 本発明の第４の実施形態における半導体装置の平面図である。It is a top view of the semiconductor device in the 4th Embodiment of this invention.

符号の説明Explanation of symbols

１０ ＢＧＡ（Ball Grid Array）型の半導体装置
１１ 半導体装置用基板
１２，１３，１４，１５ 半導体素子
１６ 接着材料
１７ インターポーザー
１８ 金属配線
２０ ＴＳＯＰ型の半導体装置
２１ リードフレーム
２２，２３，２５ 半導体素子
２６ 接着材料
２７ インターポーザー
２８ 金属配線 DESCRIPTION OF SYMBOLS 10 BGA (Ball Grid Array) type semiconductor device 11 Semiconductor device substrate 12, 13, 14, 15 Semiconductor element 16 Adhesive material 17 Interposer 18 Metal wiring 20 TSOP type semiconductor device 21 Lead frame 22, 23, 25 Semiconductor element 26 Adhesive material 27 Interposer 28 Metal wiring

Claims (5)

上面に接続端子が設けられた半導体装置用基板と、
前記半導体装置用基板上に設けられた第１の半導体素子と、
前記第１の半導体素子上に設けられ、上面に矩形状の開口部が形成され、前記上面の前記開口部を形成する４辺の隣接領域それぞれに第１のパッドが形成され、前記上面の外縁部に前記第１のパッドに電気的に接続された第２のパッドが形成されたインターポーザーと、
前記開口部内に設けられた矩形状の第２の半導体素子であって、前記４辺の隣接領域にそれぞれ隣接する上面領域上にそれぞれ第３のパッドが形成された第２の半導体素子と、
前記第１のパッドと前記第２のパッドとを電気的に接続する第１の配線と、
前記第２のパッドと前記接続端子とを接続する第２の配線と
を具備したことを特徴とする半導体装置。 A substrate for a semiconductor device provided with a connection terminal on the upper surface;
A first semiconductor element provided on the semiconductor device substrate;
Provided on the first semiconductor element, a rectangular opening is formed on the upper surface, a first pad is formed on each of adjacent regions of the four sides forming the opening on the upper surface, and an outer edge of the upper surface An interposer in which a second pad electrically connected to the first pad is formed,
A second semiconductor element having a rectangular shape provided in the opening, wherein a third pad is formed on an upper surface area adjacent to the adjacent area of each of the four sides;
A first wiring that electrically connects the first pad and the second pad;
A semiconductor device comprising: a second wiring that connects the second pad and the connection terminal. 上面に接続端子が設けられた半導体装置用基板と、
前記半導体装置用基板上に積層された複数の第１の半導体素子と、
前記複数の第１半導体素子の最上層の半導体素子上に設けられ、上面に矩形状の開口部が形成され、前記上面の前記開口部を形成する４辺の隣接領域それぞれに第１のパッドが形成され、前記上面の外縁部に前記第１のパッドに電気的に接続された第２のパッドが形成されたインターポーザーと、
前記開口部内に設けられた矩形状の第２の半導体素子であって、前記４辺の隣接領域にそれぞれ隣接する上面領域上にそれぞれ第３のパッドが形成された第２の半導体素子と、
前記第１のパッドと前記第２のパッドとを電気的に接続する第１の配線と、
前記第２のパッドと前記接続端子とを接続する第２の配線と
を具備したことを特徴とする半導体装置。 A substrate for a semiconductor device provided with a connection terminal on the upper surface;
A plurality of first semiconductor elements stacked on the semiconductor device substrate;
Provided on the uppermost semiconductor element of the plurality of first semiconductor elements, a rectangular opening is formed on the upper surface, and a first pad is provided in each of the four adjacent areas forming the opening on the upper surface. An interposer formed and formed with a second pad electrically connected to the first pad on the outer edge of the upper surface;
A second semiconductor element having a rectangular shape provided in the opening, wherein a third pad is formed on an upper surface area adjacent to the adjacent area of each of the four sides;
A first wiring that electrically connects the first pad and the second pad;
A semiconductor device comprising: a second wiring that connects the second pad and the connection terminal. 前記第２の半導体素子の厚みは前記インターポーザーの厚みと等しいことを特徴とする請求項１または２記載の半導体装置。   3. The semiconductor device according to claim 1, wherein the thickness of the second semiconductor element is equal to the thickness of the interposer. 前記半導体装置はＢＧＡ（Ball Grid Array）型、ＬＧＡ（Lead Grid Array）型またはＴＳＯＰ（Thin small outline package）型であることを特徴とする請求項１乃至３記載の半導体装置。   4. The semiconductor device according to claim 1, wherein the semiconductor device is a BGA (Ball Grid Array) type, an LGA (Lead Grid Array) type, or a TSOP (Thin small outline package) type. 前記複数の半導体素子の配線を前記インターポーザーに集約し、前記インターポーザーに集約された前記配線から前記接続端子に対して一括した電気的接続を行うことを特徴とする、請求項１乃至４に記載の半導体装置。   The wirings of the plurality of semiconductor elements are aggregated in the interposer, and electrical connection is collectively performed from the wirings aggregated in the interposer to the connection terminals. The semiconductor device described.
JP2006251875A 2006-09-15 2006-09-15 Semiconductor device Withdrawn JP2008072067A (en)

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