JP2008060289A - Semiconductor package - Google Patents

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JP2008060289A
JP2008060289A JP2006234838A JP2006234838A JP2008060289A JP 2008060289 A JP2008060289 A JP 2008060289A JP 2006234838 A JP2006234838 A JP 2006234838A JP 2006234838 A JP2006234838 A JP 2006234838A JP 2008060289 A JP2008060289 A JP 2008060289A
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substrate
semiconductor package
sealing
barrier
chip
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Kazuo Matsuura
一雄 松浦
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Hitachi Ltd
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Hitachi Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124—Aluminium (Al) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/141—Analog devices
    • H01L2924/1423—Monolithic Microwave Integrated Circuit [MMIC]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding

Abstract

<P>PROBLEM TO BE SOLVED: To provide a sealing package for surely positioning a ceramic board and a sealing member and improving a productivity and stabilizing a performance in the semiconductor package using the ceramic board. <P>SOLUTION: In the semiconductor package, the sealing member such as a cap 3, a wall 2a or the like is fitted on the board 1a loading an IC chip through a joining member, and the inside is sealed hermetically in a hollow. In the semiconductor package, an indentation is formed for aligning the sealing member at a site fitting the sealing member on the board 1a. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

本発明は半導体パッケージに関し、特にレーダ装置等に用いられる高周波回路パッケージに関する。   The present invention relates to a semiconductor package, and more particularly to a high-frequency circuit package used for a radar device or the like.

従来、平坦なセラミック基板にＩＣチップを実装し、封止対象とする部分を覆う封止部材（ウォール，キャップ等）を、接合部材（ＡｕＳｎ，はんだ等）を用いて取り付け、内部を中空に気密封止してなる半導体パッケージがある。   Conventionally, an IC chip is mounted on a flat ceramic substrate, and a sealing member (wall, cap, etc.) that covers a portion to be sealed is attached using a joining member (AuSn, solder, etc.), and the inside is hollow. There is a semiconductor package that is hermetically sealed.

特開２００６−１３５５９５号公報JP 2006-135595 A

セラミック基板と封止部材を接合するとき、ＡｕＳｎ，はんだ等の接合部材のぬれ性の観点から接合面に圧力を加える必要がある。そこで、封止部材自体の荷重が小さく、接合面への加重が不足する場合は、おもり等で加重をかけてリフロー炉に入れる。このとき、上記従来技術ではセラミック基板と封止部材との接合面とが双方とも平坦であるため、セラミック基板と封止部材との相対位置が炉内の搬送ベルトの振動等でずれることがある。このようなずれが生じた場合、以下（１）乃至（４）に示す悪影響の少なくともいずれかが生じる可能性がある。以下（１）乃至（４）のいずれかが発生した製品については、通常不良品とされる。従って上記従来技術では製品の歩留まりはセラミック基板と封止部材との相対位置のずれが発生する確率に支配され、歩留まりの向上が難しいという問題がある。
（１）セラミック基板と封止部材との間の接合部材に隙間が生じることがあり、十分な気密性が確保できない場合がある。気密性が確保できないと、パッケージ内部へ水蒸気が進入し、ＩＣチップの配線のマイグレーション等による劣化や、結露によるＩＣチップの性能劣化，Ａｕ線の腐食等が生じることになる。
（２）セラミック基板と封止部材とのずれが防止できない場合、ＩＣチップ上にゲル等を封入して封止する必要が生じる。しかしながら、封止するＩＣチップが高周波ＩＣチップの場合、ＩＣチップ上を空間として電波伝搬経路の一部とする場合が多い。このようなゲルは比誘電率が空気に比べて高く、誘電損失が大きいため、ＩＣチップ上にゲル等を充填すると、ＩＣチップ上が空間である場合に比べてＩＣチップ上を伝播する電波の波長が短くなり、ＩＣチップ上の回路のインピーダンス整合がとれなくなる。またゲル中を高周波が伝播するので伝送損失が高くなる。従って高周波特性が劣化する。
（３）高周波ＩＣのパッケージではＩＣ周辺の部材も高周波回路の一部を構成する。特に周波数が高い高周波ＩＣを用いるパッケージでは、セラミック基板と封止部材との間のずれにより、パッケージ内部の空間長が周波数に応じた波長より長くなる場合がある。この場合、電波がパッケージ内部で共振し、高周波ＩＣの性能を低下させる場合がある。
（４）高周波ＩＣでは、パッケージ外部からの信号（ノイズ及び干渉信号）により、性能劣化，誤動作を引き起こす可能性があるため、電磁気的なシールドが必要である。しかし、セラミック基板と封止部材との相対位置がずれると、隙間が生じて電磁気的なシールドの効果が得られない可能性がある。 When bonding the ceramic substrate and the sealing member, it is necessary to apply pressure to the bonding surface from the viewpoint of the wettability of the bonding member such as AuSn or solder. Therefore, when the load of the sealing member itself is small and the load on the joint surface is insufficient, the load is applied with a weight or the like and put into the reflow furnace. At this time, in the above-described prior art, since the joint surfaces of the ceramic substrate and the sealing member are both flat, the relative position of the ceramic substrate and the sealing member may be shifted due to vibration of the conveyance belt in the furnace or the like. . When such a shift occurs, at least one of the adverse effects shown in (1) to (4) below may occur. A product in which any one of (1) to (4) below is generated is usually a defective product. Therefore, in the above-described prior art, the yield of products is governed by the probability that a relative position shift between the ceramic substrate and the sealing member occurs, and there is a problem that it is difficult to improve the yield.
(1) A gap may occur in the bonding member between the ceramic substrate and the sealing member, and sufficient airtightness may not be ensured. If airtightness cannot be ensured, water vapor enters the inside of the package, resulting in degradation due to migration of IC chip wiring, IC chip performance degradation due to condensation, Au wire corrosion, and the like.
(2) When the displacement between the ceramic substrate and the sealing member cannot be prevented, it is necessary to encapsulate the IC chip on the IC chip for sealing. However, when the IC chip to be sealed is a high frequency IC chip, the IC chip is often used as a part of a radio wave propagation path with a space on the IC chip. Since such a gel has a higher relative dielectric constant than air and has a larger dielectric loss, filling the IC chip with gel or the like reduces the amount of radio waves propagating on the IC chip compared to when the IC chip is a space. The wavelength becomes shorter, and impedance matching of the circuit on the IC chip cannot be achieved. Moreover, since high frequency propagates in the gel, transmission loss increases. Accordingly, the high frequency characteristics are deteriorated.
(3) In a high frequency IC package, members around the IC also constitute a part of the high frequency circuit. In particular, in a package using a high-frequency IC having a high frequency, the space length inside the package may be longer than the wavelength corresponding to the frequency due to the deviation between the ceramic substrate and the sealing member. In this case, the radio wave may resonate inside the package, which may reduce the performance of the high frequency IC.
(4) In a high-frequency IC, an electromagnetic shield is necessary because a signal (noise and interference signal) from the outside of the package may cause performance degradation and malfunction. However, if the relative position of the ceramic substrate and the sealing member is deviated, there is a possibility that a gap is generated and the electromagnetic shielding effect cannot be obtained.

以上の課題に鑑み、本発明ではセラミック基板と封止部材との位置関係が、これらの部材の接合工程においてずれないような半導体パッケージの構造を提供することを目的とする。   In view of the above problems, an object of the present invention is to provide a semiconductor package structure in which the positional relationship between a ceramic substrate and a sealing member does not shift in the bonding process of these members.

ＩＣチップを搭載した基板上に、接合部材を介してキャップ，ウォール等の封止部材を取り付け、内部を中空に気密封止してなる半導体パッケージにおいて、基板上の封止部材を取り付ける部位に封止部材の位置合わせのための段差又は突起を設ける。   In a semiconductor package in which a sealing member such as a cap or a wall is attached to a substrate on which an IC chip is mounted via a joining member, and the inside is hermetically sealed in a hollow state, the sealing member on the substrate is sealed at a portion to which the sealing member is attached. A step or protrusion is provided for positioning the stop member.

より好ましくは、ＩＣチップと、前記ＩＣチップを搭載する基板と、前記基板に接合され、前記ＩＣチップの周囲を囲う封止障壁と、前記障壁に取り付けられ、前記基板と前記障壁とにより形成された開口部を塞ぐ封止蓋とを備えた半導体パッケージにおいて、前記基板上の前記封止障壁を取り付ける部位に、前記封止障壁の位置合わせのための段差又は突起を設ける。   More preferably, an IC chip, a substrate on which the IC chip is mounted, a sealing barrier bonded to the substrate and surrounding the IC chip, and attached to the barrier, and formed by the substrate and the barrier. In a semiconductor package including a sealing lid for closing the opening, a step or a protrusion for positioning the sealing barrier is provided on a portion where the sealing barrier is attached on the substrate.

接合工程において、セラミック基板と封止部材との相対位置がずれることを防止できる。これにより、不良品の発生率を低減し、生産上の歩留まりを向上させることができる。   In the joining step, the relative position between the ceramic substrate and the sealing member can be prevented from shifting. Thereby, the incidence rate of defective products can be reduced and the production yield can be improved.

以下、図を用いて本発明の実施例を説明する。   Embodiments of the present invention will be described below with reference to the drawings.

図１、図２に本発明の第一の実施例に係る半導体パッケージを示す。図１は、分解斜視図を示し、図２はＡ−Ａ′断面図を示している。   1 and 2 show a semiconductor package according to a first embodiment of the present invention. FIG. 1 is an exploded perspective view, and FIG. 2 is a cross-sectional view taken along line AA ′.

本実施例の半導体パッケージは、配線パターン８が形成されたセラミック基板１ａと、当該セラミック基板に搭載されるＩＣチップ４と、当該配線パターン及びＩＣチップが設けられた領域を囲うウォール２ａと、当該ウォール２ａの開口部を塞ぐリッド３とを備える。このウォール２ａ及びリッド３により、ＩＣチップ４を含めた高周波回路が封止される。セラミック基板１ａの内部には内部配線パターンが形成されている。ＩＣチップ４や他の回路構成部品は、当該内部配線パターンを介して接続端子１０に電気的に接続される。接続端子１０は半導体パッケージを外部の回路と接続するための端子である。本実施例の構造は車載用レーダに用いられる高周波回路パッケージに好適であり、種々のギガヘルツ帯（２４ＧＨｚ，７６ＧＨｚ，８０ＧＨｚなど）の高周波回路に適用することができる。   The semiconductor package of this example includes a ceramic substrate 1a on which a wiring pattern 8 is formed, an IC chip 4 mounted on the ceramic substrate, a wall 2a surrounding a region where the wiring pattern and the IC chip are provided, And a lid 3 for closing the opening of the wall 2a. The wall 2 a and the lid 3 seal the high frequency circuit including the IC chip 4. An internal wiring pattern is formed inside the ceramic substrate 1a. The IC chip 4 and other circuit components are electrically connected to the connection terminal 10 via the internal wiring pattern. The connection terminal 10 is a terminal for connecting the semiconductor package to an external circuit. The structure of the present embodiment is suitable for a high-frequency circuit package used for an on-vehicle radar, and can be applied to various gigahertz band (24 GHz, 76 GHz, 80 GHz, etc.) high-frequency circuits.

セラミック基板１ａのウォール２ａが取り付けられる位置にはウォール２ａの外形に合わせた段差５を設ける。すなわち、ＩＣチップ４や配線パターン８などが設けられた封止対象領域の周囲に段差５を設ける。従って、段差５の内側に配線パターン８が形成され、ＩＣチップ４の厚みにあわせたキャビティ６が設けられた構造となる。これにより、ウォール２ａをセラミック基板１ａにはんだ付けする際に、ウォール２ａとセラミック基板
１ａとの相対的な位置がずれることを防止できる。 A step 5 corresponding to the outer shape of the wall 2a is provided at a position where the wall 2a of the ceramic substrate 1a is attached. That is, the step 5 is provided around the region to be sealed where the IC chip 4 and the wiring pattern 8 are provided. Accordingly, the wiring pattern 8 is formed inside the step 5 and the cavity 6 is provided in accordance with the thickness of the IC chip 4. Thereby, when the wall 2a is soldered to the ceramic substrate 1a, it is possible to prevent the relative position between the wall 2a and the ceramic substrate 1a from shifting.

本実施例では、セラミック基板１ａを多層基板とし、封止対象領域の外側の層数を１層分、多くして段差を形成している。当該構成により、接合用のはんだが封止対象領域の外側にはみ出すことを抑止できる。なお、段差の高さは必ずしも１層分である必要はない。しかしながら、１層分若しくは２層，３層分などのように、多層基板の各層の厚さの倍数とすることで、段差の形成がより容易になる。   In this embodiment, the ceramic substrate 1a is a multilayer substrate, and the number of layers outside the region to be sealed is increased by one layer to form a step. With this configuration, it is possible to prevent the bonding solder from protruding outside the sealing target region. Note that the height of the step is not necessarily one layer. However, it is easier to form a step by setting the multiple of the thickness of each layer of the multilayer substrate, such as one layer, two layers, or three layers.

以下、図１，図２に示す半導体パッケージの製造工程の例を説明する。   Hereinafter, an example of a manufacturing process of the semiconductor package shown in FIGS. 1 and 2 will be described.

まず、セラミック基板１ａにプリフォームのＡｕＳｎ材を乗せその上にウォール２ａを載せる。このとき、セラミック基板１ａに形成された段差５がウォール２ａの位置合わせとなる。なお位置合わせに用いるセラミック基板１ａの段差５の幅の精度は例えば±５０μｍ程度である。また、ウォール２ａの外形精度は、エッチングで成形する場合、例えば±１０μｍ程度である。   First, a preformed AuSn material is placed on the ceramic substrate 1a, and the wall 2a is placed thereon. At this time, the step 5 formed on the ceramic substrate 1a is aligned with the wall 2a. The accuracy of the width of the step 5 of the ceramic substrate 1a used for alignment is, for example, about ± 50 μm. In addition, the external accuracy of the wall 2a is, for example, about ± 10 μm when it is formed by etching.

次に、これをＨ２還元炉で３００℃以上の温度でリフローを行い、接合する。この接合では、予めウォール２ａもしくはセラミック基板１ａの接合面に接合部材をリフロー炉に通して融着し、セラミック基板１ａとウォール２ａを組み合わせて再度リフロー炉に通して接合する方法がある。あるいは、どちらかの部材に接合材を融着させず、セラミック基板１ａとウォール２ａの接合面の間に接合部材（ＡｕＳｎあるいははんだ等）を挟んでリフロー炉に通し、一度に接合する方法もある。 Next, this is reflowed and bonded at a temperature of 300 ° C. or higher in an H 2 reduction furnace. In this joining, there is a method in which a joining member is passed through a reflow furnace in advance on the joining surface of the wall 2a or the ceramic substrate 1a, and the ceramic substrate 1a and the wall 2a are combined and joined again through the reflow furnace. Alternatively, there is a method in which a bonding material (AuSn, solder, or the like) is sandwiched between the bonding surfaces of the ceramic substrate 1a and the wall 2a and passed through a reflow furnace without bonding the bonding material to either member and bonded at once. .

続いて、ＩＣチップ４をダイボンド材でセラミック基板１ａへ接合し、ＩＣチップ４とセラミック基板１ａ間をＡｕワイヤもしくはＡｌワイヤでボンディング結線を行う。   Subsequently, the IC chip 4 is bonded to the ceramic substrate 1a with a die bonding material, and bonding connection is performed between the IC chip 4 and the ceramic substrate 1a with an Au wire or an Al wire.

次にＩＣチップ４などの部品を実装する。ＩＣチップ４はダイボンド材でセラミック基板１ａへ接合される。ＩＣチップ４は、高周波ＩＣチップであり、裏面の接合面をＧＮＤとしたマイクロストリップ線路で構成されたものである。当該ＩＣチップ４のマイクロストリップ線路をセラミック基板１ａ上のマイクロストリップ線路と結線するためには、
ＩＣチップ４のＧＮＤである裏面とセラミック基板１ａのＧＮＤとを導通させる必要がある。そこでＩＣチップ４の実装には導電性のＡｇペースト接着剤を用いる。恒温層でＡｇペーストを硬化させた後、Ａｕワイヤでボンディングしてセラミック基板１ａとＩＣチップ４を結線する。 Next, components such as the IC chip 4 are mounted. The IC chip 4 is bonded to the ceramic substrate 1a with a die bond material. The IC chip 4 is a high-frequency IC chip, and is composed of a microstrip line whose back-side joining surface is GND. In order to connect the microstrip line of the IC chip 4 to the microstrip line on the ceramic substrate 1a,
It is necessary to electrically connect the back surface which is the GND of the IC chip 4 and the GND of the ceramic substrate 1a. Therefore, a conductive Ag paste adhesive is used for mounting the IC chip 4. After the Ag paste is cured in the constant temperature layer, the ceramic substrate 1a and the IC chip 4 are connected by bonding with an Au wire.

この後、Ｎ２ （窒素）雰囲気でリッド３をウォール２ａの上に載せリッド３とウォール２ａの接合面をレーザで溶接し、気密封止する。なお、使用する封止部材のウォール
２ａおよびリッド３は金属材料で、導電性を有しており、外部からのＩＣへ影響をおよぼす信号をシールドすることが可能である。 Thereafter, the lid 3 is placed on the wall 2a in an N 2 (nitrogen) atmosphere, and the joint surface between the lid 3 and the wall 2a is welded with a laser to be hermetically sealed. The wall 2a and the lid 3 of the sealing member to be used are metallic materials and have conductivity, and can shield signals that affect the IC from the outside.

本実施例では、封止部材をウォール２ａとリッド３の二部材の構成とする。そして、
ＩＣチップ４等を実装する前にセラミック基板１ａにウォール２ａを接合し、ＩＣチップ４を実装後にウォール２ａへリッド３を接合する。ここでウォール２ａへのリッド３の接合では、ＩＣチップ４等の温度上昇が少ない、シーム溶接やレーザ溶接のような局部の温度上昇の接合方法を用いる。 In this embodiment, the sealing member has a two-member configuration of the wall 2 a and the lid 3. And
Before mounting the IC chip 4 or the like, the wall 2a is bonded to the ceramic substrate 1a, and after mounting the IC chip 4, the lid 3 is bonded to the wall 2a. Here, in joining of the lid 3 to the wall 2a, a joining method of local temperature rise such as seam welding or laser welding, in which the temperature rise of the IC chip 4 or the like is small, is used.

本実施例のような高周波回路パッケージでは、セラミック基板１ａに実装されるＩＣチップ４や他の回路構成部材がリフロー炉での加熱温度に耐えられない場合がある。   In the high-frequency circuit package as in this embodiment, the IC chip 4 and other circuit components mounted on the ceramic substrate 1a may not be able to withstand the heating temperature in the reflow furnace.

ここで、封止部材をウォール２ａとリッド３の二部材に分けずに、キャップ状の部材とし、この部材をリフローによってセラミック基板１ａに接合部材で接合しようとすると、セラミック基板１ａおよびＩＣチップ４を含む半導体パッケージ全体をリフロー炉に通す必要が生じるため、この方法は適用できない。   Here, the sealing member is not divided into the two members of the wall 2a and the lid 3, but is made into a cap-like member, and when this member is joined to the ceramic substrate 1a by reflow, the ceramic substrate 1a and the IC chip 4 are joined. This method cannot be applied because it is necessary to pass the entire semiconductor package including the substrate through a reflow furnace.

また、リフロー時に用いられる水素等のガスがＩＣチップ４に影響をおよぼす場合がある。例えばＩＣチップ４は、動作する周波数が高い場合、ＧａＡｓなどの化合物を基板として作られることが多い。このＩＣチップ４のＦＦＴ層に水素が付着すると性能が劣化する場合がある。   In addition, a gas such as hydrogen used at the time of reflow may affect the IC chip 4. For example, when the operating frequency is high, the IC chip 4 is often made using a compound such as GaAs as a substrate. When hydrogen adheres to the FFT layer of the IC chip 4, the performance may be deteriorated.

このように、封止部材のずれによる気密封止の低下をなくし、生産上の歩留まり向上を目的とするとともに、特に高周波ＩＣの性能低下を防ぐとともに位置合わせの工数を小さくし、生産性をあげることができる。さらに、封止部材の内側もしくは外側、あるいは全体を導電性の材料とすることで、高周波ＩＣを封止する場合、シールド効果を得ることができる。   In this way, the purpose of eliminating the deterioration of the hermetic sealing due to the displacement of the sealing member and improving the production yield, in particular, preventing the performance deterioration of the high frequency IC and reducing the alignment man-hours and increasing the productivity. be able to. Furthermore, when a high frequency IC is sealed, a shielding effect can be obtained by using a conductive material inside or outside of the sealing member.

図３，図４を用いて、本発明の第２の実施形態について説明する。図３は、分解斜視図を示し、図４はＡ−Ａ′断面図を示している。   A second embodiment of the present invention will be described with reference to FIGS. FIG. 3 is an exploded perspective view, and FIG. 4 is a cross-sectional view taken along line AA ′.

本実施例は、ウォール２ｂのセラミック基板１ｂと接合する面に突起２ｂ′を設け、セラミック基板１ｂにはウォール２ｂに設けた突起２ｂ′に合うように窪み５ｂを設けた点で、実施例１と異なる。当該構成によれば、実施例１のように封止対象領域の全周囲について段差５を設ける必要が無く、実施例１よりもセラミック基板１ｂの形状を単純にすることができる。ここでは窪み５ｂはセラミック基板１ｂの層構成に合わせて１層分としている。なお、セラミック基板１ｂ及びウォール２ｂは形状が実施例１と異なっているが、その材質や電気的特性は同様である。従って、特に説明しない構成及び効果については、実施例１と同様である。   In this embodiment, the protrusion 2b 'is provided on the surface of the wall 2b to be joined to the ceramic substrate 1b, and the depression 5b is provided in the ceramic substrate 1b so as to match the protrusion 2b' provided on the wall 2b. And different. According to the said structure, it is not necessary to provide the level | step difference 5 about the perimeter of the sealing object area | region like Example 1, and the shape of the ceramic substrate 1b can be simplified rather than Example 1. FIG. Here, the dent 5b is one layer according to the layer structure of the ceramic substrate 1b. The ceramic substrate 1b and the wall 2b are different in shape from those of the first embodiment, but the materials and electrical characteristics thereof are the same. Therefore, configurations and effects that are not particularly described are the same as those in the first embodiment.

ここで突起２ｂ′及び窪み５ｂは少なくとも２ヶ所以上設ける。これにより、セラミック基板１ｂとウォール２ｂの位置が一意に決まるからである。ウォール２ｂに向きがある場合は、誤組立防止のため２ヶ所の突起５ｂの形状を異なるようにすることもできる。例えば、ウォール２ｂが単純な正方形状である場合にはウォール２ｂを１８０度回転させて組み立てても問題は生じない。しかしながら、ウォール２ｂの機械的形状若しくは物理的な性質が回転対称でない場合は、上述のように複数の突起５ｂの形状を相互に異ならせることにより、向きを誤って組み立てることを防止できるという利点がある。   Here, at least two protrusions 2b 'and recesses 5b are provided. This is because the positions of the ceramic substrate 1b and the wall 2b are uniquely determined. When the wall 2b is oriented, the shape of the two protrusions 5b can be made different to prevent erroneous assembly. For example, when the wall 2b is a simple square, there is no problem even if the wall 2b is rotated 180 degrees and assembled. However, when the mechanical shape or physical property of the wall 2b is not rotationally symmetric, there is an advantage that it is possible to prevent incorrect assembly by changing the shapes of the plurality of protrusions 5b as described above. is there.

なお、本実施例にかかる半導体回路パッケージの組立手順は、実施例１と基本的に同じである。   The assembly procedure of the semiconductor circuit package according to the present embodiment is basically the same as that of the first embodiment.

図５，図６を用いて、本発明の第３の実施形態について説明する。図５は、分解斜視図を示し、図６はＡ−Ａ′断面図を示している。   A third embodiment of the present invention will be described with reference to FIGS. FIG. 5 shows an exploded perspective view, and FIG. 6 shows an AA ′ cross-sectional view.

本実施例は、セラミック基板１ｃのうち、封止対象領域の内側をかさ上げすることによって段差５を形成している。この点で、封止対象領域の外側をかさ上げして段差５を形成する実施例１と異なる。   In this embodiment, the step 5 is formed by raising the inside of the sealing target region of the ceramic substrate 1c. This is different from the first embodiment in which the step 5 is formed by raising the outside of the region to be sealed.

なお、セラミック基板１ｃ及びウォール２ｃは形状が実施例１と異なっているが、その材質や電気的特性は同様である。従って、特に説明しない構成及び効果については、実施例１と同様である。   The shape of the ceramic substrate 1c and the wall 2c is different from that of the first embodiment, but the material and electrical characteristics are the same. Therefore, configurations and effects that are not particularly described are the same as those in the first embodiment.

図７，図８を用いて、本発明の第４の実施形態について説明する。図７は、分解斜視図を示し、図８はＡ−Ａ′断面図を示している。   A fourth embodiment of the present invention will be described with reference to FIGS. FIG. 7 shows an exploded perspective view, and FIG. 8 shows a cross-sectional view along AA ′.

本実施例は、本発明を送信回路と受信回路とを備えたレーダ装置に適用した例であり、送信及び受信の各機能を実現する高周波ＩＣチップを複数個実装したパッケージに適用した実施形態である。ここでは、高周波ＩＣチップを複数個実装するパッケージとしてレーダ用のＩＣチップ構成を例に説明する。セラミック基板１ｄには高周波ＩＣチップが実装される。本実施例では、セラミック基板１ｄに実装される高周波ＩＣチップとして、発振器ＭＭＩＣ（Monolithic Microwave Integrated Circuit）４ａ，ミキサＭＭＩＣ４ｂ、及び電力増幅器ＭＭＩＣ４ｃを想定する。   The present embodiment is an example in which the present invention is applied to a radar apparatus having a transmission circuit and a reception circuit, and is an embodiment in which the present invention is applied to a package in which a plurality of high-frequency IC chips that realize each function of transmission and reception are mounted. is there. Here, a radar IC chip configuration will be described as an example of a package for mounting a plurality of high-frequency IC chips. A high frequency IC chip is mounted on the ceramic substrate 1d. In the present embodiment, an oscillator MMIC (Monolithic Microwave Integrated Circuit) 4a, a mixer MMIC 4b, and a power amplifier MMIC 4c are assumed as high-frequency IC chips mounted on the ceramic substrate 1d.

発振器ＭＭＩＣ４ａの発振信号は、二分岐してミキサＭＭＩＣ４ｂと電力増幅器MMIC4cにそれぞれ入力される。電力増幅器ＭＭＩＣ４ｃは入力された信号を増幅し、伝送線路
８ｂへ信号を送る。伝送線路８ｂの裏面は送信用のアンテナと接続されており、電力増幅器ＭＭＩＣ４ｃで増幅された送信信号は送信用のアンテナから送信される。送信用のアンテナから送信された信号はレーダの被検知物で反射される。 The oscillation signal of the oscillator MMIC 4a is branched into two and input to the mixer MMIC 4b and the power amplifier MMIC 4c. The power amplifier MMIC 4c amplifies the input signal and sends the signal to the transmission line 8b. The back surface of the transmission line 8b is connected to a transmission antenna, and the transmission signal amplified by the power amplifier MMIC 4c is transmitted from the transmission antenna. The signal transmitted from the transmitting antenna is reflected by the radar object.

一方、伝送線路８ａの裏面は受信用のアンテナと接続されている。被検知物で反射された反射信号は受信用のアンテナにより受信される。ミキサＭＭＩＣ４ｂは、伝送線路８ａを介して入力されるレーダの被検知物で反射される反射信号と発振器ＭＭＩＣ４ａからの発振信号を混合し、ＩＦ信号（中間周波数信号）を生成する。ＩＦ信号を処理することで、被検知物までの距離等が計測される。   On the other hand, the back surface of the transmission line 8a is connected to a receiving antenna. The reflected signal reflected by the object to be detected is received by the receiving antenna. The mixer MMIC 4b mixes the reflected signal reflected by the radar detection object input via the transmission line 8a and the oscillation signal from the oscillator MMIC 4a to generate an IF signal (intermediate frequency signal). By processing the IF signal, the distance to the object to be detected is measured.

ウォール２ｄは、ＭＭＩＣ４ａ〜４ｃを二つの空間に分離する仕切りを備える。二つの空間のうち一方には、発振器ＭＭＩＣ４ａと電力増幅ＭＭＩＣ４ｃとが収容される。他方の空間にはミキサＭＭＩＣ４ｂが収容される。仕切り７ａには窓７ｂが二空間を繋ぐ伝送線路上に設けられる。窓７ｂの幅は発振器ＭＭＩＣ４ａが発振する周波数の電波が伝送線路以外を通過できないように、遮断周波数が発振器ＭＭＩＣ４ａで発振する周波数以上となるような幅としている。このとき、ウォール２ｄの位置ずれがあると、窓７ｂとその下の伝送路の相対位置が変わり、伝送路の特性インピーダンスが変化する。伝送線路の特性インピーダンスが変化すると、伝送線路の特性インピーダンスが変化した部分で伝送する信号の一部が反射するため、伝送特性が劣化し、レーダ性能が低下する。そのため、セラミック基板１に窪みを設け、ウォール２ｄの位置合わせを行い、ずれを防止する。   The wall 2d includes a partition that separates the MMICs 4a to 4c into two spaces. An oscillator MMIC 4a and a power amplification MMIC 4c are accommodated in one of the two spaces. The mixer MMIC 4b is accommodated in the other space. The partition 7a is provided with a window 7b on the transmission line connecting the two spaces. The width of the window 7b is set such that the cut-off frequency is equal to or higher than the frequency oscillated by the oscillator MMIC 4a so that the radio wave having the frequency oscillated by the oscillator MMIC 4a cannot pass through other than the transmission line. At this time, if the wall 2d is misaligned, the relative position of the window 7b and the transmission line below it changes, and the characteristic impedance of the transmission line changes. When the characteristic impedance of the transmission line changes, a part of the signal to be transmitted is reflected at the portion where the characteristic impedance of the transmission line changes, so that the transmission characteristic deteriorates and the radar performance deteriorates. Therefore, a recess is provided in the ceramic substrate 1 to align the wall 2d to prevent deviation.

なお、実施例１乃至３では、一般的な高周波回路パッケージとして本発明の実施形態を説明したが、実施例１乃至３で説明したセラミック基板（１ａ，１ｂ，１ｃ）及びウォール（２ａ，２ｂ，２ｃ）の形状を実施例４のような送信回路と受信回路を備えたレーダ装置に適用してもよい。その場合、実施例１乃至３における複数のＩＣパッケージとして、発振器ＭＭＩＣ４ａ，ミキサＭＭＩＣ４ｂ、及び電力増幅器ＭＭＩＣ４ｃを採用し、封止領域内の配線パターン８を伝送線路８ａ，８ｂとして用いる。   In Examples 1 to 3, the embodiment of the present invention has been described as a general high-frequency circuit package. However, the ceramic substrates (1a, 1b, 1c) and walls (2a, 2b, The shape of 2c) may be applied to a radar apparatus including a transmission circuit and a reception circuit as in the fourth embodiment. In that case, the oscillator MMIC 4a, the mixer MMIC 4b, and the power amplifier MMIC 4c are employed as the plurality of IC packages in the first to third embodiments, and the wiring pattern 8 in the sealing region is used as the transmission lines 8a and 8b.

実施例１の分解斜視図。1 is an exploded perspective view of Example 1. FIG. 実施例１の断面図。1 is a cross-sectional view of Example 1. FIG. 実施例２の部品毎に分解した斜視図。The perspective view which decomposed | disassembled for every component of Example 2. FIG. 実施例２の断面図。Sectional drawing of Example 2. FIG. 実施例３の部品毎に分解した斜視図。The perspective view which decomposed | disassembled for every component of Example 3. FIG. 実施例３の断面図。Sectional drawing of Example 3. FIG. 実施例４の部品毎に分解した斜視図。The perspective view which decomposed | disassembled for every component of Example 4. FIG. 実施例４の断面図。Sectional drawing of Example 4. FIG.

符号の説明Explanation of symbols

１ａ，１ｂ，１ｃ，１ｄ…セラミック基板、２ａ，２ｂ，２ｃ，２ｄ…ウォール、２ｂ′…突起、２ｃ′…切り欠き、３…リッド、４…ＩＣチップ、４ａ…発振器ＭＭＩＣ、
４ｂ…ミキサＭＭＩＣ、４ｃ…電力増幅器ＭＭＩＣ、５…段差、５ｂ…窪み、６…キャビティ、７ａ…仕切り、７ｂ…窓、８…配線パターン、８ａ，８ｂ…伝送線路、９…内部配線パターン、１０…接続端子。

DESCRIPTION OF SYMBOLS 1a, 1b, 1c, 1d ... Ceramic substrate, 2a, 2b, 2c, 2d ... Wall, 2b '... Projection, 2c' ... Notch, 3 ... Lid, 4 ... IC chip, 4a ... Oscillator MMIC,
4b: mixer MMIC, 4c: power amplifier MMIC, 5 ... step, 5b ... depression, 6 ... cavity, 7a ... partition, 7b ... window, 8 ... wiring pattern, 8a, 8b ... transmission line, 9 ... internal wiring pattern, 10 …Connecting terminal.

Claims (16)

ＩＣチップと、
前記ＩＣチップを搭載する基板と、
前記基板に接合され、前記ＩＣチップの周囲を囲う封止障壁と、
前記障壁に取り付けられ、前記基板と前記障壁とにより形成された開口部を塞ぐ封止蓋とを備え、
前記基板上の前記封止障壁を取り付ける部位に、前記封止障壁の位置合わせのための段差を設けた半導体パッケージ。 IC chip,
A substrate on which the IC chip is mounted;
A sealing barrier bonded to the substrate and surrounding the IC chip;
A sealing lid attached to the barrier and closing an opening formed by the substrate and the barrier;
The semiconductor package which provided the level | step difference for the alignment of the said sealing barrier in the site | part which attaches the said sealing barrier on the said board | substrate. 請求項１において、
前記封止障壁及び前記封止蓋の内側もしくは外側、あるいは全体を導電性の材料としたことを特徴とする半導体パッケージ。 In claim 1,
A semiconductor package characterized in that the inside or outside of the sealing barrier and the sealing lid, or the whole is made of a conductive material. 請求項１において、
前記基板はセラミック多層基板であることを特徴とする半導体パッケージ。 In claim 1,
A semiconductor package, wherein the substrate is a ceramic multilayer substrate. 請求項１において、
前記封止障壁を取り付ける部位の外側が内側よりも高いことを特徴とする半導体パッケージ。 In claim 1,
The semiconductor package characterized in that the outside of the portion to which the sealing barrier is attached is higher than the inside. 請求項１において、
前記封止障壁を取り付ける部位の外側が内側よりも低いことを特徴とする半導体パッケージ。 In claim 1,
The semiconductor package characterized in that the outside of the portion to which the sealing barrier is attached is lower than the inside. ＩＣチップと、
前記ＩＣチップを搭載する基板と、
前記基板に接合され、前記ＩＣチップの周囲を囲う封止障壁と、
前記障壁に取り付けられ、前記基板と前記障壁とにより形成された開口部を塞ぐ封止蓋とを備え、
前記封止障壁は、前記基板と対向する側の面に位置合わせのための突起を有し、前記基板は、前記封止障壁の突起と嵌合する窪みを備えた半導体パッケージ。 IC chip,
A substrate on which the IC chip is mounted;
A sealing barrier bonded to the substrate and surrounding the IC chip;
A sealing lid attached to the barrier and closing an opening formed by the substrate and the barrier;
The sealing barrier has a protrusion for alignment on a surface facing the substrate, and the substrate has a recess that fits into the protrusion of the sealing barrier. 請求項６において、
対となる前記封止障壁の突起及び前記基板の窪みを複数備えたことを特徴とする半導体パッケージ。 In claim 6,
A semiconductor package comprising a plurality of pairs of protrusions of the sealing barrier and depressions of the substrate. 請求項７において、
前記複数の突起及び窪みは、その対ごとに形状が異なることを特徴とする半導体パッケージ。 In claim 7,
The plurality of protrusions and depressions have different shapes for each pair. 発振器ＩＣと、
電力増幅器ＩＣと、
ミキサＩＣと、
これらのＩＣを搭載する基板と、
前記基板に接合され、前記ＩＣの周囲を囲う封止障壁と、
前記障壁に取り付けられ、前記基板と前記障壁とにより形成された開口部を塞ぐ封止蓋とを備え、
前記基板は、前記封止障壁を取り付ける部位に、前記封止障壁の位置合わせのための段差を備えた半導体パッケージ。 An oscillator IC;
A power amplifier IC;
A mixer IC;
A substrate on which these ICs are mounted;
A sealing barrier bonded to the substrate and surrounding the IC;
A sealing lid attached to the barrier and closing an opening formed by the substrate and the barrier;
The substrate is a semiconductor package provided with a step for positioning the sealing barrier at a portion to which the sealing barrier is attached. 請求項９において、
前記封止障壁は、当該封止障壁により囲まれる領域内を２以上の領域に分割する仕切り壁を備えたことを特徴とする半導体パッケージ。 In claim 9,
The semiconductor package according to claim 1, wherein the sealing barrier includes a partition wall that divides a region surrounded by the sealing barrier into two or more regions. 請求項１０において
前記２以上の領域のうち、第一の領域に前記発振器ＩＣと前記電力増幅ＩＣを収容し、第二の領域に前記ミキサＩＣを収容したことを特徴とする半導体パッケージ。 11. The semiconductor package according to claim 10, wherein the oscillator IC and the power amplifier IC are accommodated in a first area, and the mixer IC is accommodated in a second area of the two or more areas. 請求項１１において、
前記発振器ＩＣと前記ミキサＩＣとを接続する伝送線路を備え、
前記封止障壁の仕切り壁は、前記伝送線路を通すための窓部を備えることを特徴とする半導体パッケージ。 In claim 11,
A transmission line for connecting the oscillator IC and the mixer IC;
The partition wall of the sealing barrier includes a window portion through which the transmission line passes. 請求項９において、
前記封止障壁及び前記封止蓋の内側もしくは外側、あるいは全体を導電性の材料としたことを特徴とする半導体パッケージ。 In claim 9,
A semiconductor package characterized in that the inside or outside of the sealing barrier and the sealing lid, or the whole is made of a conductive material. 請求項９において、
前記基板はセラミック多層基板であることを特徴とする半導体パッケージ。 In claim 9,
A semiconductor package, wherein the substrate is a ceramic multilayer substrate. 請求項９において、
前記封止障壁を取り付ける部位の外側が内側よりも高いことを特徴とする半導体パッケージ。 In claim 9,
The semiconductor package characterized in that the outside of the portion to which the sealing barrier is attached is higher than the inside. 請求項９において、
前記封止障壁を取り付ける部位の外側が内側よりも低いことを特徴とする半導体パッケージ。
In claim 9,
The semiconductor package characterized in that the outside of the portion to which the sealing barrier is attached is lower than the inside.
JP2006234838A 2006-08-31 2006-08-31 Semiconductor package Pending JP2008060289A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9125311B2 (en) 2011-09-26 2015-09-01 Nec Corporation Hollow sealing structure

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9125311B2 (en) 2011-09-26 2015-09-01 Nec Corporation Hollow sealing structure

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