JP2008059032A - Circuit verification method and circuit verification apparatus for semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To display a verification index which can be recognized in RTL descriptions by extracting the subset of RTL descriptions corresponding to the subset of a net list by using the subset of the net list which has been verified by formal verification. <P>SOLUTION: A circuit verification method for a semiconductor integrated circuit includes: an RTL introduction step S10 of introducing RTL descriptions with which a logic circuit is designed; a net list conversion step S20 of converting the RTL descriptions into a net list; a property introduction step S30 of introducing a property showing the operating specifications of the logic circuit; a formal verification execution step S40 of executing formal verification to the net list by using property; and a subset extraction step S50 of extracting the subset of RTL descriptions corresponding to the subset of the verified net list in the RTL descriptions by using the subset of the verified net list. Thus, it is possible to provide quantitative verification progress in the RTL descriptions. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a circuit verification method and a circuit verification apparatus for a semiconductor integrated circuit.

  In circuit verification using a test vector for a semiconductor integrated circuit, coverage is used as an index of how much verification should be performed. As an example of the coverage calculation method, the number of lines executed in the simulation among all the description lines of the register transfer level (RTL) description is measured. This is called line coverage.

  As another circuit verification method, there is a formal verification method for proving whether logic is mathematically established. The formal verification method does not have a verification index such as line coverage, and it cannot be confirmed how much verification has been performed. Therefore, formal verification coverage was devised. The coverage of conventional formal verification is described below.

  FIG. 15 is a flowchart showing the flow of a conventional method for deriving coverage for formal verification.

  In FIG. 15, N10 is a step of introducing a design circuit, N20 is a step of introducing a property indicating an operation specification, N30 is a step of performing formal verification using the property, and N40 is a circuit verification by a verified subset of property verification. This is a step of deriving the coverage which is the progress of the above. N50 is a step of returning to step N20 when the coverage derived in step N40 does not satisfy the termination criterion.

By having such steps, coverage can be derived as a verification index even in formal verification, and feedback can be provided in the form of adding the coverage result to the formal verification property. As a result, efficient formal verification is realized (see Patent Document 1).
US 2003-659804

  In recent semiconductor integrated circuits, the scale has increased remarkably, and a verification index for formal verification is indispensable. Therefore, the concept of coverage is essential. The conventional formal verification coverage described with reference to FIG. 15 indicates the progress of verification in the netlist, and does not represent the extent to which verification is performed in the RTL description as in line coverage. Therefore, the coverage of conventional formal verification is not a sufficient index for RTL designers and RTL verifiers.

  The present invention was created in view of such circumstances, and a verification index that can be grasped in the RTL description is obtained even in formal verification so that it is an effective verification index for RTL designers and RTL verifiers. An object of the present invention is to provide a circuit verification method and a circuit verification apparatus.

(1) A circuit verification method according to the present invention includes:
An RTL introduction process for introducing an RTL description for designing a logic circuit of a semiconductor integrated circuit;
A netlist conversion step of converting the RTL description into a netlist;
A property introduction step for introducing a property indicating an operation specification of the logic circuit;
A formal verification performing step of performing formal verification on the netlist using the properties;
A subset extracting step of extracting a subset of the RTL description corresponding to the verified subset of the netlist in the RTL description using the subset of the netlist verified in the formal verification performing step.

  According to this configuration, when formal verification is performed on a semiconductor integrated circuit, a subset of the netlist verified by the formal verification is used in the subset extraction step, and the subset of the netlist is converted into the subset in the RTL description. By extracting a subset of the corresponding RTL description, it is possible to indicate verification indexes that can be grasped in the RTL description.

(2) A circuit verification method according to the present invention includes:
An RTL introduction process for introducing an RTL description for designing a logic circuit of a semiconductor integrated circuit;
A netlist conversion step of converting the RTL description into a netlist;
A property introduction step for introducing a property indicating an operation specification of the logic circuit;
A formal verification performing step of performing formal verification on the netlist using the properties;
A subset extracting step of extracting, in the RTL description, a subset of the RTL description corresponding to the verified subset of the netlist using the subset of the netlist verified in the formal verification performing step;
A component deriving step of deriving a component that is a component of the logic circuit verified by the formal verification from the subset of the RTL description extracted by the subset extracting step.

  According to this configuration, when formal verification is performed on a semiconductor integrated circuit, a verification index can be indicated using a component in the RTL description by deriving a verified component in the component deriving step. become. In addition, the component which is a component of a logic circuit is addition, subtraction, multiplication, division, a selector, etc., for example.

(3) The circuit verification method according to the present invention includes:
Logical simulation coverage introduction process for introducing coverage results by logical simulation;
An RTL introduction process for introducing an RTL description for designing a logic circuit of a semiconductor integrated circuit;
A netlist conversion step of converting the RTL description into a netlist;
A property introduction step for introducing a property indicating an operation specification of the logic circuit;
A formal verification performing step of performing formal verification on the netlist using the properties;
A subset extracting step of extracting, in the RTL description, a subset of the RTL description corresponding to the verified subset of the netlist using the subset of the netlist verified in the formal verification performing step;
A coverage merge step of merging the subset of the RTL description extracted in the subset extraction step and the coverage result by the logic simulation introduced in the logic simulation coverage introduction step.

  According to this configuration, when formal verification is performed on a semiconductor integrated circuit, a subset of the RTL description extracted in the subset extraction step and the logic simulation introduced in the logic simulation coverage introduction step in the coverage merge step By merging (integrating) the coverage results obtained by the above, it becomes possible to show the verification index of the circuit verification using the conventional test vector and the verification index of the formal verification in an integrated form.

(4) The circuit verification method according to the present invention includes:
Logical simulation coverage introduction process for introducing coverage results by logical simulation;
An RTL introduction process for introducing an RTL description for designing a logic circuit of a semiconductor integrated circuit;
A netlist conversion step of converting the RTL description into a netlist;
A property introduction step for introducing a property indicating an operation specification of the logic circuit;
A formal verification performing step of performing formal verification on the netlist using the properties;
A subset extracting step of extracting, in the RTL description, a subset of the RTL description corresponding to the verified subset of the netlist using the subset of the netlist verified in the formal verification performing step;
A component derivation step for deriving a component that is a component of the logic circuit verified in the formal verification from the subset of the RTL description extracted in the subset extraction step;
A component merging step of merging the component derived in the component derivation step and the coverage result of the logic simulation introduced in the logic simulation coverage introduction step.

  According to this configuration, when the formal verification is performed on the semiconductor integrated circuit, in the component merge process, the component derived in the component derivation process and the coverage result by the logic simulation introduced in the logic simulation coverage introduction process By merging, it is possible to show the verification index for circuit verification and formal verification using a conventional test vector in an integrated form using components in the RTL description.

  Furthermore, in the circuit verification method referred to the above component, there is an aspect in which an arithmetic unit or a selector is included as the component. In this case, it is possible to indicate the verification index using an arithmetic unit or selector in the RTL description.

  Further, in any one of the above circuit verification methods, the subset of the netlist verified in the formal verification execution step includes an FF extraction step of extracting a flip-flop in the netlist used in the formal verification; And a subset extracting step of extracting a subset of the RTL description corresponding to the verified subset of the netlist using the flip-flop. In this case, since a subset of the verified netlist is extracted using a flip-flop (hereinafter referred to as FF) in the subset extraction step, the subset can be extracted using the RTL description describing the FF in the subset extraction step.

  Further, in the circuit verification method referred to the flip-flop, the subset indicating the RTL description includes the RTL description describing the FF and the RTL description describing a combinational circuit. In this case, when the verification index in the RTL description is indicated, the verification index of the entire RTL description is provided by including both the FF description and the combinational circuit description.

  Further, in the circuit verification method referring to the combinational circuit, there is an aspect in which the RTL description describing the combinational circuit includes information on the number of logical stages from the RTL description describing the FF. In this case, when the verification index in the RTL description is indicated, the information about the execution probability of the code proportional to the number of logical stages can be provided by adding information about the depth of the logical stages to the combinational circuit.

  Also, in any one of the above circuit verification methods, the subset extracting step has a mode in which a path route information of a code is derived from the RTL description, and a subset of the RTL description is extracted using the path route information. . In this case, when extracting a subset of the RTL description, it is possible to provide a verification index in the RTL description in detail by using the path route information of the code.

  In the circuit verification method mentioned in the coverage merge step, the coverage merge step has a mode in which a subset of the RTL description and a coverage result by the logic simulation are merged in units of modules in the RTL description. In this case, it is possible to provide verification progress in module units by merging coverage results in module units.

  Further, in the circuit verification method mentioned in the coverage merge step, the coverage merge step has a mode in which the component and the coverage result by the logic simulation are merged in units of code in the RTL description. In this case, it is possible to provide verification progress in code units by merging coverage results in code units.

  In the circuit verification method mentioned in the component merging step, the component merging step has a mode in which a subset of the RTL description and a coverage result by the logic simulation are merged in units of modules in the RTL description. In this case, by merging coverage results in module units, it is possible to provide verification progress using components in the RTL description in module units.

  Further, in the circuit verification method mentioned in the component merging step, the component merging step has a mode in which the component and the coverage result by the logic simulation are merged for each component type in the RTL description. In this case, it is possible to provide verification progress for each component type by merging coverage results in units of component types.

Further, the circuit verification apparatus according to the present invention includes:
An RTL introduction part for introducing an RTL description for designing a logic circuit of a semiconductor integrated circuit;
A netlist converter for converting the RTL description into a netlist;
A property introduction unit for introducing a property indicating an operation specification of the logic circuit;
A formal verification performing unit that performs formal verification on the netlist using the properties;
A subset for extracting a subset of the RTL description corresponding to the subset of the netlist verified by the formal verification execution unit in the RTL description using the subset of the netlist verified by the formal verification execution unit. An extractor;
And a coverage display unit for displaying the progress of circuit verification based on the subset of the RTL description extracted by the subset extraction unit.

  According to this configuration, it is possible to provide a verification index that can be grasped in the RTL description by the coverage display unit that displays the progress of the circuit verification when the formal verification is performed on the semiconductor integrated circuit.

  As described above, according to the present invention, the subset of the RTL description corresponding to the subset of the netlist is extracted in the subset extraction step by using the subset of the netlist verified by the formal verification, thereby obtaining the RTL description. It becomes possible to show the verification index which can be grasped in.

  Further, by deriving a verified component in the component deriving step, it is possible to indicate a verification index using a component in the RTL description.

  Further, by merging with the coverage result by the logic simulation, it becomes possible to show the verification index of the circuit verification using the conventional test vector and the verification index of the formal verification in an integrated form.

  Embodiments of a circuit verification method for a semiconductor integrated circuit according to the present invention will be specifically described below with reference to the drawings.

(Embodiment 1)
FIG. 1 is a flowchart showing a processing procedure of an LSI circuit verification method according to the first embodiment of the present invention. In FIG. 1, S10 is an RTL introduction process, a step of introducing a designed RTL description, S20 is a netlist conversion process, a step of converting the RTL description into a netlist, and S30 is a property introduction process, and the operation specifications S40 is a formal verification execution step, and a formal verification is performed on the net list using the property. S50 is a subset extraction step, and a subset of the verified net list is introduced. A step of extracting a subset of the RTL description using S, step S60 is a step of grasping the progress of circuit verification based on the subset of the RTL description extracted in step S50, and step S70 is a step of whether the verification progress grasped in step S60 satisfies the termination criterion This is the step to confirm. The netlist subset indicates a part of the netlist of the semiconductor integrated circuit to be verified, and the RTL description subset indicates the RTL description representing the semiconductor integrated circuit to be verified. Some of them are shown.

  The operation of the circuit verification method of the first embodiment having the above steps will be described below.

  First, in step S10, the designed RTL description is introduced. This RTL description is a verification target itself for performing formal verification. As the RTL description, a known design language such as Verilog-HDL or VHDL is generally used, but is not limited to this.

  Next, in step S20, the RTL description is converted into a netlist.

  Thereafter, in step S30, a property indicating the operation specification is introduced. The property in the present embodiment is “the output q is always 0 when the input signal x and the input signal y are equal”. The property is not limited to this.

  In step S40 of the formal verification execution process, formal verification is performed on the netlist using the properties introduced in step S30. As a formal verification method, as shown in FIG. 2, a logic circuit, which is a combinational circuit network having FF as a vertex, is applied to a mathematical circuit such as OBDD (Ordered Binary Decision Diagram), and the design circuit shown in the upper diagram of FIG. And the following figure can be used to investigate whether the expected values (determined by properties) are equivalent. The formal verification method is not limited to this.

  In step S50, a subset of the RTL description corresponding to the subset of the netlist verified in the formal verification is extracted. Here, the steps of FIG. 3 are performed to extract a subset of the RTL description. S51 is a step of extracting FFs in the netlist used in the formal verification. S52 is a step of extracting a corresponding subset of the RTL description using the FF extracted in step S51.

  FIG. 4 shows the logic cone that was the subject of formal verification. Of the plurality of logic cones, FF2, FF3, and FF5 are FFs extracted in step S51. Here, the logic cone targeted in the formal verification indicates a logic cone subjected to the mathematical solution, and can be easily known by outputting from the formal verification tool. In FIG. 4, PI indicates a primary input and PO indicates a primary output.

  Next, a subset of the RTL description is extracted in step S52. In this embodiment, the verified subset of the netlist is equal to the FF extracted in step S51, and is only FF2, FF3, and FF5. Note that the method of extracting a subset of the RTL description corresponding to the verified subset of the netlist is not limited to this.

  FIG. 5 shows a part of the RTL description in the present embodiment. In the present embodiment, only the outputs FF2, FF3, and FF5 are set as verified subsets of the netlist. In FIG. 5, Expression 1, Expression 2, and Expression 3 represent the description of the FF part in the output q of the FF 3, and are RTL descriptions verified in formal verification. As described above, a subset of the RTL description corresponding to the subset of the netlist verified in the formal verification is extracted based on the FF in the netlist.

  In the present embodiment, the subset of the RTL description includes the FF description and the combinational circuit description. Also, the logic stage number information from the subset output q of the RTL description is owned. As a result, in the combinational circuit description, the possibility of executing the code can be inferred from the logic depth from the FF.

  FIG. 6 is a subset of the RTL description in the present embodiment. Note that the number of logical stages is not necessarily owned as a subset expression method.

  It is also possible to derive code path route information from the RTL description and extract a subset of the RTL description using the path route information. For example, the RTL description code that is always executed between the RTL description codes describing FF2 and FF3 in FIG. 4 can be a subset of the verified RTL description.

  Next, in step S60 of FIG. 1, the progress of circuit verification is grasped by a subset of the RTL description. In this embodiment, as shown in FIG. 6, verified RTL descriptions are expressed as a subset. That is, it is possible to grasp code information that is not implemented.

  Finally, in step S70 of FIG. 1, it is confirmed whether the verification progress satisfies the end criterion. For example, when the verification end criterion is that all the codes in the RTL description are verified, the termination criterion is not satisfied unless all the codes are verified. Therefore, a new property is added, formal verification is performed, and the process is repeated until the end criterion is satisfied.

  According to the present embodiment, when formal verification is performed on a semiconductor integrated circuit, the RTL corresponding to the subset of the netlist is used in the RTL description by using the subset of the netlist verified by the formal verification. By extracting a subset of the description, it is possible to indicate verification indexes that can be grasped in the RTL description.

  In addition, since a subset of the verified netlist is extracted using the FF, the subset of the RTL description can be extracted using the RTL description describing the FF as a clue. In addition, a subset of the RTL description can be extracted in detail by using the code path information.

  Furthermore, by adding the logic stage number information to the subset of the RTL description, it becomes possible to grasp information relating to code execution ease.

(Embodiment 2)
FIG. 7 is a flowchart showing a processing procedure of the LSI circuit verification method according to the second embodiment of the present invention. In FIG. 7, the same step numbers as in FIG. 1 of the first embodiment indicate the same processing contents. The steps specific to this embodiment are as follows. S53 is a step of deriving verified components from the subset of the RTL description extracted in step S50, and S61 is a step of grasping the progress of circuit verification by the components derived in step S53. The component indicates a logic component of the semiconductor integrated circuit to be verified. Since other steps are the same as those in the first embodiment, the description thereof will be omitted.

  The present embodiment is different from the first embodiment in that the component verified in step S53 is derived and the component is used instead of the subset in the subsequent verification progress grasp.

  FIG. 8 is an example of a subset of verified RTL descriptions in the present embodiment. Here, four arithmetic operations such as multiplication and subtraction, or selector descriptions are used as components. The component is not limited to this.

  FIG. 9 is an example showing verified components. It is possible to grasp a verified component among all the components and use it as a verification index.

  According to this embodiment, when formal verification is performed on a semiconductor integrated circuit, it is possible to indicate a verification index using a component in the RTL description.

(Embodiment 3)
FIG. 10 is a flowchart showing a processing procedure of the LSI circuit verification method according to the third embodiment of the present invention. 10, the same step numbers as those in FIG. 1 of the first embodiment indicate the same processing contents. The steps specific to this embodiment are as follows. S5 is a step of introducing the coverage result by the logic simulation, S54 is a step of merging the subset of the RTL description and the coverage result by the logic simulation, and S62 is a step of grasping the progress of the circuit verification by the merged coverage result. Since other steps are the same as those in the first embodiment, the description thereof will be omitted.

  Compared with the first embodiment, the present embodiment is different from the first embodiment in that step S5 for introducing the coverage result by the logic simulation and step S54 for merging the subset of the RTL description and the coverage result by the logic simulation are added. Different.

  FIG. 11 shows a module to be verified and its RTL description for the current merge. Module A has five RTL descriptions (a) to (e), and module B has four RTL descriptions (f) to (i).

  The upper diagram of FIG. 12 shows test vector coverage results and a subset by formal verification. The lower diagram of FIG. 12 shows an example of the merge result. Here, the RTL description that has been verified by the test vector or formal verification is the verified RTL description after the merge. It shows what was merged in module units and what was merged in code units. The merging method is not limited to this.

  In the present embodiment, merging is performed using a subset by formal verification, but components may be used as in the second embodiment.

  The upper diagram of FIG. 13 shows the test vector coverage results and components by formal verification. The lower diagram of FIG. 13 shows an example of the merge result. A merged module unit and a component type merged are shown. The merging method is not limited to this.

  According to the present embodiment, it is possible to integrate verification indexes for circuit verification and formal verification using a conventional test vector.

(Embodiment 4)
FIG. 14 is a schematic configuration diagram showing a configuration of an LSI circuit verification apparatus according to the fourth embodiment of the present invention. In this configuration, the central processing unit 1 includes a netlist unit that converts an RTL description into a netlist, a formal verification execution unit that performs formal verification on the netlist using properties, and a formal verification execution unit. Responsible for a subset extractor that extracts a subset of the RTL description corresponding to the verified subset of the netlist. Further, the input device 3 is used to store the RTL description designed for the semiconductor integrated circuit and the properties indicating the operation specifications in the hard disk 2. The stored data is taken into the central processing unit 1 through the interface between the central processing unit 1 and the hard disk 2. Furthermore, the central processing unit 1 instructs the external output unit 4 to output the progress of circuit verification based on the subset of the RTL description extracted by the subset extraction unit, and is output.

  According to this configuration, when formal verification is performed on a semiconductor integrated circuit, it is possible to visually recognize verification indexes that can be grasped by the RTL by displaying the progress of circuit verification.

  The circuit verification method of the present invention is a method capable of grasping the progress of verification in formal verification, and is useful as a circuit verification method for semiconductor integrated circuits.

7 is a flowchart showing a processing procedure of a circuit verification method for a semiconductor integrated circuit according to the first embodiment of the present invention. Explanatory drawing of the formal verification method in Embodiment 1 of this invention The flowchart which shows the procedure of the extraction process of the subset of Embodiment 1 of this invention. Explanatory drawing of the logic cone which is the object of formal verification in Embodiment 1 of the present invention Part of the RTL description as a target in Embodiment 1 of the present invention Exemplary diagram of a subset of the RTL description extracted in the first embodiment of the present invention 8 is a flowchart showing a processing procedure of a circuit verification method for a semiconductor integrated circuit according to the second embodiment of the present invention. FIG. 6 is an exemplary diagram of a subset of the RTL description used in the second embodiment of the present invention. Exemplary diagram of components derived in the second embodiment of the present invention The flowchart which shows the process sequence of the circuit verification method of the semiconductor integrated circuit in Embodiment 3 of this invention. Example of module used in embodiment 3 of the present invention and RTL description for it FIG. 10 is an exemplary diagram of a subset of RTL descriptions merged in the third embodiment of the present invention. Exemplary diagram of components merged in Embodiment 3 of the present invention Schematic configuration diagram of a circuit verification device for a semiconductor integrated circuit according to a fourth embodiment of the present invention. The flowchart which shows the procedure of the process of the conventional verification method

Explanation of symbols

S5 Logic simulation coverage introduction step S10 RTL introduction step S20 Netlist conversion step S30 Property introduction step S40 Formal verification execution step S50 Subset extraction step S51 FF extraction step S52 Subset extraction step S53 Component derivation step S54 Coverage merge step S60 Circuit verification by subset Step S61 Step of grasping the progress of circuit verification by the component S62 Step of grasping the progress of the circuit verification by the merged coverage result S70 Step of confirming whether the grasped verification progress satisfies the end criterion

Claims (14)

A circuit verification method for verifying a logic circuit of a semiconductor integrated circuit,
An RTL introduction process for introducing a register transfer level description designed for the logic circuit;
A netlist conversion step of converting the register transfer level description into a netlist;
A property introduction step for introducing a property indicating an operation specification of the logic circuit;
A formal verification performing step of performing formal verification on the netlist using the properties;
A subset extracting step of extracting a subset of the RTL description corresponding to the verified subset of the netlist in the register transfer level description using the subset of the netlist verified in the formal verification performing step. Circuit verification method.   The component deriving step according to claim 1, further comprising a component deriving step of deriving a component that is a component of the logic circuit verified by the formal verification from the subset of the register transfer level description extracted by the subset extracting step. Circuit verification method. A circuit verification method for verifying a logic circuit of a semiconductor integrated circuit,
Logical simulation coverage introduction process for introducing coverage results by logical simulation;
An RTL introduction process for introducing a register transfer level description designed for the logic circuit;
A netlist conversion step of converting the register transfer level description into a netlist;
A property introduction step for introducing a property indicating an operation specification of the logic circuit;
A formal verification performing step of performing formal verification on the netlist using the properties;
A subset extracting step of extracting, in the register transfer level description, a subset of the RTL description corresponding to the verified subset of the netlist using the subset of the netlist verified in the formal verification performing step;
A circuit verification method comprising: a coverage merge step of merging a subset of the register transfer level description extracted in the subset extraction step and a coverage result by the logic simulation introduced in the logic simulation coverage introduction step. A component derivation step for deriving a component that is a component of the logic circuit verified by the formal verification from the subset of the register transfer level description extracted by the subset extraction step;
The circuit verification method according to claim 3, further comprising: a component merge step of merging the component derived in the component derivation step and a coverage result obtained by the logic simulation introduced in the logic simulation coverage introduction step.   The circuit verification method according to claim 2, wherein the component includes an arithmetic unit or a selector. The subset of the netlist verified in the formal verification execution step is
FF extraction step of extracting flip-flops in the netlist used in the formal verification;
6. The circuit verification method according to claim 1, wherein the circuit verification method is obtained by a subset extraction step of extracting a subset of an RTL description corresponding to the verified subset of the netlist using the flip-flop.   The circuit verification method according to claim 6, wherein the subset indicating the register transfer level description includes the register transfer level description describing the flip-flop and the register transfer level description describing a combinational circuit.   The circuit verification method according to claim 7, wherein the register transfer level description describing the combinational circuit includes information on the number of logical stages from the register transfer level description describing the flip-flop.   9. The subset extracting step derives code path route information from the register transfer level description, and extracts a subset of the register transfer level description using the path route information. The circuit verification method as described.   The circuit verification method according to claim 3, wherein the coverage merging step merges the subset of the register transfer level description and the coverage result by the logic simulation in module units in the register transfer level description.   The circuit verification method according to claim 3, wherein the coverage merging step merges the component and the coverage result by the logic simulation in a code unit in the register transfer level description.   5. The circuit verification method according to claim 4, wherein the component merging step merges the subset of the register transfer level description and the coverage result by the logic simulation in module units in the register transfer level description.   The circuit verification method according to claim 4, wherein the component merging step merges the component and the coverage result by the logic simulation for each component type in the register transfer level description. A circuit verification apparatus for verifying a logic circuit of a semiconductor integrated circuit,
An RTL introduction unit for introducing a register transfer level description designed for the logic circuit;
A netlist converter for converting the register transfer level description into a netlist;
A property introduction unit for introducing a property indicating an operation specification of the logic circuit;
A formal verification performing unit that performs formal verification on the netlist using the properties;
Extracting a subset of the RTL description corresponding to the subset of the netlist verified by the formal verification execution unit in the register transfer level description using the subset of the netlist verified by the formal verification execution unit A subset extractor,
A circuit verification apparatus comprising: a coverage display unit configured to display a progress of circuit verification using a subset of the register transfer level description extracted by the subset extraction unit.

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