JP2014067353A - Rtl optimization method, device and program - Google Patents

Abstract

PROBLEM TO BE SOLVED: To optimize a description of an if-else branch in an RTL source.SOLUTION: An if-else extraction part 11 of an RTL optimization device 1 extracts an if-else branch from an RTL source 21, and a data generation part 13 generates information about the if-else branch having the number of paragraphs that is equal to or higher than a threshold determined by a threshold determination part 12. A correction method determination part 14 determines a correction method on the basis of the number of bits of a signal, presence or absence of the same name signal and presence or absence of AND connection in a condition for an if-else sentence, and a correction part 15 corrects the RTL source 21 in accordance with the determined correction method and outputs a corrected RTL 27.

Description

  The present invention relates to processing for optimizing RTL (Register Transfer Level) description, which is one of hardware description languages (HDL).

  The RTL, which is one of the hardware descriptions, defines a structure inside the hardware and describes a function from register to register based on a clock operation. At the hardware logic circuit design stage, it is necessary not only to check the grammar conventions of the description of the RTL source, but also to check whether the logic circuit based on the description is configured to operate more appropriately.

  With regard to if-else describing a branch in an RTL source, it is recognized that the timing is deteriorated when the if-else statement is deeply nested when the nest stage is deep. Therefore, in the conventional method of RTL check, an if-else statement having a certain number of stages or more is targeted for warning. The operator manually corrects whether or not the if-else branch for which warning has been made is necessary or how to correct it based on his own rule of thumb.

  Further, as a conventional technique for RTL correction, a technique for automatically changing an if-else sentence in an RTL source to a case sentence is known.

Japanese Patent Laid-Open No. 10-187781

  In the above conventional method, the if-else statement in the RTL source is corrected to the case statement. However, if the if-else statement is simply transformed into the case statement, there is a problem that the logic circuit becomes redundant.

  34 and 35 are diagrams for explaining the problem of correction by the conventional method. FIG. 34A is a diagram showing an example of the original (before correction) RTL source, and FIG. 34B is a diagram showing an example of the RTL source after correction by the conventional method. 35A shows a circuit configuration example using the original RTL source in FIG. 34A, and FIG. 35B shows a circuit configuration example using the modified RTL source in FIG. 34B. It is.

  The if-else statement described in the 7th to 11th lines of the RTL source shown in FIG. 34A is transformed into the case statement described in the 7th to 14th lines of the RTL source shown in FIG. Is done. In terms of the circuit configuration, as shown in FIG. 35A, a configuration in which three stages of 1-bit (bit) input selectors are connected in series is shown in FIG. It is transformed into a bit AND configuration. That is, in the original RTL source, the signal selection condition is one condition, but in the corrected RTL source, since the signal selection condition is two conditions, two comparison circuits are required. The circuit configuration with the corrected RTL source is generally determined as addition of redundant determination logic.

  Since the automatic transformation of the if-else statement into the case statement by the conventional method does not optimize the circuit configuration, the operator manually handles the if-else statement in consideration of the number of stages at which the circuit configuration is optimal. The problem that had to be fixed could not be solved.

  An object of the present invention is to provide a processing method, apparatus, and program for optimizing the description of a branch by an if-else statement included in an RTL source.

  The RTL optimization method disclosed as one aspect of the present invention is a method in which a computer 1) if-else statements having a number of stages of an if-else statement equal to or greater than the number of stages indicated by a preset threshold from an RTL source describing a target circuit Else branches are extracted, and 2) a plurality of if-else branch correction methods are set in advance in association with the conditions of the if-else statement, and based on the conditions that constitute the extracted if-else branches. One of the plurality of correction methods is determined, and 3) a process of correcting the extracted if-else branch extracted from the RTL source based on the determined correction method is executed.

  According to the disclosed RTL optimization method, an if-else branch having a large number of nesting stages can be automatically changed to an optimal description, and the load of RTL correction work can be reduced in logic circuit design.

It is a figure which shows the block structural example in one Example of the disclosed RTL optimization apparatus. It is a figure which shows the example of a data structure of the log memory | storage part in one Example. It is a figure which shows the example of a data structure of the correction object memory | storage part in one Example. It is a figure which shows the example of the setting table used for the threshold value determination in one Example. It is a figure which shows the example of an outline processing flow of the RTL optimization apparatus in one Example. It is a figure which shows the example of a more detailed process flow of the process of step S3. It is a figure which shows the example of a more detailed process flow of the process of step S4. It is a figure which shows the more detailed process flow example of a process of step S33. It is explanatory drawing of the block division | segmentation in the case of correction by the 1st correction method. It is a figure which shows the specific example of the block division | segmentation in the case of correction by the 1st correction method. It is a figure which shows the specific example of the block division | segmentation in the case of correction by the 1st correction method. It is a figure which shows the example of the RTL source containing the correction object by a 1st correction method. It is explanatory drawing of the correction by a 1st correction method. It is explanatory drawing of the correction by a 1st correction method. It is explanatory drawing of the correction by a 1st correction method. It is explanatory drawing of the correction by a 1st correction method. It is a figure which shows the circuit structure of the RTL source before correction by the 1st correction method. It is a figure which shows the circuit structure of the corrected RTL source after correction by the 1st correction method. It is explanatory drawing of the block division | segmentation in the case of correction by the 2nd correction method. It is a figure which shows the example of the RTL source containing the correction object by the 2nd correction method. It is explanatory drawing of the correction by a 2nd correction method. It is explanatory drawing of the correction by a 2nd correction method. It is explanatory drawing of the correction by a 2nd correction method. It is explanatory drawing of the correction by a 2nd correction method. It is a figure which shows the circuit structure of the RTL source before correction by the 2nd correction method. It is a figure which shows the circuit structure of the corrected RTL source after correction by the 2nd correction method. It is a figure which shows the example of the RTL source containing the correction object by the 3rd correction method. It is explanatory drawing of the correction by the 3rd correction method. It is explanatory drawing of the correction by the 3rd correction method. It is explanatory drawing of the correction by the 3rd correction method. It is a figure which shows the circuit structure of the RTL source before correction by the 3rd correction method. It is a figure which shows the circuit structure of the corrected RTL source after correction by the 3rd correction method. It is a figure which shows the hardware structural example of a RTL optimization apparatus. It is explanatory drawing of the problem of correction by a conventional method. It is explanatory drawing of the problem of correction by a conventional method.

  Hereinafter, an RTL optimization device disclosed as one aspect of the present invention will be described.

  FIG. 1 is a diagram illustrating a block configuration example in an embodiment of the disclosed RTL optimization device.

  The RTL optimization device 1 stores an if-else extraction unit 11, a threshold determination unit 12, a data generation unit 13, a correction method determination unit 14, a correction unit 15, and various types of data used or generated by these processing units. A part.

  The if-else extraction unit 11 performs branching by an if-else statement (hereinafter referred to as “if-else branch” or simply “if-else”) from the RTL source 21 in which the target circuit is described in RTL (Register Transfer Level). All are extracted, and information (log information) regarding the extracted if-else branch is stored in the log storage unit 22. The extraction of the if-else branch is performed by a parsing process using a known RTL style checker. The log information related to the if-else is, for example, the position (line) of the if-else statement, the number of stages, the name of a file including the if-else statement, and the like.

  The threshold determination unit 12 determines a threshold th (the number of stages of if-else) for determining whether or not if-else is a correction target, and stores the threshold th in the threshold holding unit 24.

  For example, a fixed value, an arbitrary value given by the user, a value based on information on the target circuit (for example, operating frequency), or the like can be used as the threshold th that is a means for determining if-else to be corrected. The threshold determination unit 12 sets the threshold th based on the designation 23 of the determination unit.

  The determination means specification 23 is information for specifying the threshold th used as the determination means. The RTL optimization apparatus 1 holds the initial setting as an initial setting, or is given to the threshold determination section 12 before the data generation section 13 starts processing. .

  The data generation unit 13 determines whether the if-else branch stored in the log storage unit 22 has a number of stages exceeding the threshold th determined by the threshold determination unit 12, and if- The else branch is set as a correction target, and information regarding the corresponding if-else (correction target information) is stored in the correction target storage unit 25.

The correction method determination unit 14 holds a plurality of correction methods in advance, determines a correction method to be executed for the if-else branch stored in the correction target storage unit 25, and holds the determined correction method 26. The modification method determination unit 14 classifies the if-else branch based on the contents of the conditions of the if-else statement to be configured (number of signal bits, presence / absence of the same name signal in each condition, presence / absence of AND configuration, etc.) Determine how to fix. The following are examples of conditions for classification of correction methods.
(1) Whether the condition of the if-else statement is composed of only a 1-bit signal.
(2) Does the same name signal exist in all conditions?
(3) Are all conditions configured with AND?
(4) Is there any other signal in the condition?

  As a correction method, for example, the following method is prepared.

[First correction method]
The first correction method is selected when the signal set in the condition of the if-else statement is a 1-bit signal and a signal with the same name does not exist in each condition.

  In the first correction method, the if-else statement is divided into blocks so that the number of branch stages is within a predetermined number (threshold value), and the if-else branch of each block is configured in the structure of the if-else statement. Then, the configuration is modified so that the if-else branch of each block is within a predetermined number of stages.

  With this modification, in the logic circuit corresponding to the if-else branch of the original RTL source 21, when the selector circuit is connected in series beyond the appropriate number of stages, the number of stages to which the selector circuit is connected in series is constant. It is possible to realize a configuration in which the number of connections is limited to a few and the connections are partially connected in parallel.

[Second modification method]
The second correction method is selected when it does not correspond to the first correction method or the third correction method described later. For example, if the signal set in the condition of the if-else statement is a plurality of bits, a signal having the same name exists in each condition, and the condition is composed of AND, the second correction method is selected.

  In the second correction method, the if-else sentence is classified by the signal name and signal value set in the condition, and the first correction method is performed for each group of if-else sentences grouped by the signal and signal value used for classification. To correct the if-else branch.

  With this modification, it is possible to realize a configuration in which selector circuits corresponding to input signals summarized by signal names and signal values are connected in series within an appropriate number of stages and partially connected in parallel.

[Third Modification Method]
The third correction method is selected when the signal set in the condition of the if-else statement is a multi-bit signal and there is no other signal in each condition.

  In the third correction method, the case is transformed into a case branch having the condition of each stage of the if-else branch as an element.

  With this modification, in the logic circuit based on the if-else branch of the original RTL source 21, the configuration in which the selector circuits are connected in series exceeding the appropriate number can be realized by an alternative circuit.

  The correction unit 15 corrects the correction target if-else branch included in the RTL source 21 according to the correction method 26 determined, and outputs a corrected RTL source 27.

  FIG. 2 is a diagram illustrating a data configuration example of the log storage unit 22.

In the log storage unit 22, for each of the n if-else statements extracted from the RTL source 21, an identification number (n), the number of stages (a _n−1 ), a file name (F _n−1 ), a line number ( L _n−1 ) is stored. “Identification number” is the data identification number, “Number of stages” is the number of nested stages of the if-else statement, “File name” is the name of the file containing the if-else statement, and “Line number” is in the file (RTL source) This is the line number in which the if-else statement is described.

  FIG. 3 is a diagram illustrating a data configuration example of the correction target storage unit 25.

The correction target storage unit 25 stores the identification number (m) and the number of stages (m) for each of m (m ≦ n) if-else statements that are extracted from the log storage unit 22 as the correction target when the number of stages exceeds the threshold th. a _m-1 ), a file name (F _m-1 ), and data including a line number (L _m-1 ) are stored. “Identification number” is the data identification number, “Number of stages” is the number of nested stages of the if-else statement, “File name” is the name of the file containing the if-else statement, and “Line number” is in the file (RTL source) This is the line number in which the if-else statement is described.

  FIG. 4 is a diagram illustrating an example of a setting table used for threshold value determination.

  The setting table is a data table indicating the correspondence between the operating frequency (MHz) of the target circuit and the threshold value.

  When the determination means designation 23 is “setting based on the operating frequency of the target circuit”, the threshold value determination unit 12 acquires information indicating the operating frequency (f) of the target circuit, and from the setting table illustrated in FIG. A threshold th corresponding to the obtained operating frequency is determined.

  The RTL optimizing device 1 having the above configuration eliminates the serial connection exceeding the appropriate number of stages and solves the problem that the output timing difference may vary between the first and last selector circuits. It is possible to realize a circuit configuration capable of eliminating variations in output timing difference by equalization.

  FIG. 5 is a diagram illustrating an example of an outline processing flow of the RTL optimization device 1.

  In the RTL optimizing device 1, the if-else extraction unit 11 acquires the RTL source 21 of the target circuit (step S1), extracts all if-else sentences from the RTL source 21, and information on the extracted if-else sentence (Log information) is stored in the log storage unit 22 (step S2). The information shown in FIG. 2 is stored in the log storage unit 22 by the process of step S2.

  The data generation unit 13 uses the threshold th stored in the threshold holding unit 24 to extract, from the log information stored in the log storage unit 22, an if-else statement whose number of stages exceeds the threshold th as a processing target, Information (correction target information) related to the if-else sentence to be treated is stored in the correction target storage unit 25 (step S3). The information shown in FIG. 3 is stored in the correction target storage unit 25 by the process of step S3.

  If the determination means designation 23 is given from the outside, it is assumed that the threshold th is determined by the threshold determining unit 12 and stored in the threshold holding unit 24 before the process of step S3.

  The correction method determination unit 14 determines a correction method for the if-else sentence stored in the correction target storage unit 25, and stores the determined correction method 26 in association with the if-else sentence (step S4). The modification unit 15 transforms the if-else statement to be modified of the RTL source 21 according to the determined modification method 26, and outputs a modified RTL source 27 (step S5).

  FIG. 6 is a diagram showing a more detailed processing flow example of the processing in step S3.

The data generation unit 13 acquires log information stored in the log storage unit 22 (step S21), and acquires a threshold th using the threshold th recorded in the threshold holding unit 24 (step S22). Data generator 13, a counter i is set to 0 (step S23), i th the if-else the number _{a n} of (0 ≦ i ≦ n-1 ), or number _{a i} is equal to or less than the threshold value th Is determined (step S24). If the number of stages a _i ≦ threshold th is not satisfied (N in step S24), the data generation unit 13 stores the if-else information in the correction target storage unit 25 (step S25), and proceeds to step S26, where the number of stages a _{If i} ≦ threshold th (Y in step S24), the process directly proceeds to step S26.

  In step S26, the data generation unit 13 determines whether i = n−1. If i = n−1 (N in step S26), i = i + 1 is set (step S27), and the process returns to step S24. If i = n−1 (Y in step S26), the process is terminated.

  With the processing shown in FIG. 6, it is determined that the m number of if-else elements included in the RTL source 21 are equal to or greater than the threshold th and are to be corrected.

  FIG. 7 is a diagram showing a more detailed processing flow example of the processing in step S4.

  The correction method determination unit 14 acquires the correction target information from the correction target storage unit 25 (step S31), sets the counter i to 0 (step S32), and the i-th (0 ≦ i ≦ m−1) if. -Else correction method is selected (step S33). Details of the processing in step S33 will be described later with reference to FIG.

  Thereafter, the correction method determination unit 14 determines whether i = m−1 (step S34). If i = m−1 is not satisfied (N in step S34), the correction method determination unit 14 determines that i = i + 1. (Step S35), the process returns to Step S33, and if i = m−1 (Y in Step S34), the process ends.

  FIG. 8 is a diagram showing a more detailed processing flow example of the processing in step S33.

  The correction method determination unit 14 extracts the i-th (0 ≦ i ≦ m−1) if-else statement of the correction target information (step S341), and the signal set as the condition is a 1-bit (bit) signal. It is determined whether or not there is (step S342). If the signal is a 1-bit signal (Y in step S342), the correction method determination unit 14 further determines whether there is a signal with the same name in the condition (step S343). If there is no signal with the same name in the condition (N in Step S343), the correction method determination unit 14 determines the correction method of the if-else as “first correction method” (Step S344), and ends the processing (Step S344). The process proceeds to S34).

  If it is determined in step S343 that there is a signal with the same name in the condition (Y in step S343), the correction method determination unit 14 further determines whether the condition is configured by AND (step S345). If the condition is composed of AND (Y in step S345), the correction method determination unit 14 determines that the if-else correction method is the “second correction method” (step S346), and ends the process. If the condition is not composed of AND (N in step S345), the process returns to step S344, and the correction method of the if-else statement is determined as the “first correction method”.

  If the signal set in the condition is not a 1-bit signal in the determination in step S342 (N in step S342), the correction method determination unit 14 further determines whether there is another signal in the condition (step S347). . If there is another signal in the condition (Y in step S347), the modification method of the if-else statement is determined to be “third modification method” (step S348), the process is terminated, and another signal is included in the condition. If there is not (N of step S347), it will return to step S343.

  The correcting unit 15 corrects the if-else of the RTL source 21 to be corrected according to the determined correction method. The if-else correction process by each correction method will be described in more detail below.

[Correction by the first correction method]
(1) Preprocessing (block division processing)
The correction unit 15 performs the following processes S151 to S152 as preprocessing (block division processing) for correction.

  Process S151: The number L of blocks to be divided by the if-else statement is calculated.

Processing S152: calculating the number _{P L} of if-else statements stored in each block.

  Here, as the division of the number of stages, the correction unit 15 performs either of the following two processes.

First division method: Divide stage number a _i by 2. At this time, since the number of stages a _i −1 is divided by 2, L = 2. Further, P ₀ is a value obtained by rounding up the decimal point of (a _i −1) / 2, and P ₁ = (a _i −1) −P ₀ . _{That, (a i -1) P 0} = (a i -1) when the even / _{2, and} the _P 0 _{= P} 1 +1 when is an odd number _{(a i -1) (P 0} = P It may be ₁ -1).

Second division method: (a _i -1) is divided by a threshold th-1. At this time, the number of blocks L is a value obtained by rounding up the decimals of (a _i −1) / (th−1).

As shown in FIG. 9, the if-else statement with the number of stages a _i is decomposed into L blocks named A _L-1 so as to be less than the threshold th, and the number of if-else statements included therein Is P _L-1 (<th), the number of stages in all if-else statements increases in order to insert an else term into each divided block. Therefore, when the number of stages is divided by the threshold th, the number of stages in the if-else statement of each block may eventually exceed the threshold th, and therefore the stage number (a _i −1) is divided by the threshold th−1. I will do it. By suppressing the number of stages of the if-else statement of each block to the threshold value th-1, it is possible to prevent the threshold value th from being exceeded. Further, 1 subtracted from the stage number a _i is obtained by excluding the else term.

Hereinafter, a specific example of the pretreatment (calculation of the P _L). The first division method can be regarded as an example of the second division method when P _L ≦ th−1, and can be described in the same procedure. Therefore, a specific example of the second division method will be described.

FIG. 10A is a diagram illustrating an example of division when an if-else statement with a _i = 7 and th = 4. In this case, L = (a _i −1) / (th−1) = (7-1) / (4-1) = 6/3 = 2, and P ₀ = (a _i −1) / L = (7-1) / 2 = 6/2 = 3. Therefore, P ₀ = 3 and P ₁ = 3.

FIG. 10B is a diagram illustrating an example of division when an if-else statement with a _i = 6 and th = 4. In this case, L = (a _i −1) / (th−1) = (6-1) / (4-1) = 5/3 <2, and P ₀ = (a _i −1) / L = (6-1) / 2 = 5/2 <3. Therefore, P ₀ = 2 and P ₁ = 3. When P _{i of} each block is different, the blocks may be arranged in order from the last block and assigned so that the top block has the minimum number of stages.

FIG. 11A is a diagram illustrating an example of division when an if-else statement with a _i = 13 and th = 5. In this case, L = (a _i −1) / (th−1) = (13-1) / (5-1) = 12/4 = 3, and P ₀ = (a _i −1) / L = (13-1) / 3 = 12/3 = 4. Therefore, P ₀ = 4, P ₁ = 4, and P ₂ = 4.

FIG. 11B is a diagram illustrating an example of division when an if-else statement with a _i = 12 and th = 5. In this case, L = (a _i -1) / (th-1) = (12-1) / (5-1) = 11/4 <3, and P ₀ = (a _i -1) / L = (12-1) / 3 = 11/3 <4. Therefore, P ₀ = 3, P ₁ = 4, and P ₂ = 4.

(2) This process (correction process)
Next, as this processing (correction processing), the correction unit 15 performs the following processing S153 to S156 as processing for transforming the description of the correction target of the RTL source 21 according to the RTL grammar rules.

Processing S153: the number of blocks obtained by dividing calculated in preprocessing L, to generate a plurality of blocks according to the number of stages P _L number of if-else statements in each block, performing a description of each block.

  In accordance with the grammatical rules of the RTL source 21, the structure of “if () begin to end” is described in the first block, and the structure of “else begin to end” is described in the last block. When there are other blocks, the structure of “else if () begin to end” is described in each block. At this time, the element (conditional expression) in each if () is empty.

  FIG. 12 is a diagram illustrating an example of the RTL source 21 including a correction target according to the first correction method.

  In the RTL source 21 shown in FIG. 12, the if-else in the seventh line to the 27th line is a correction target. Then, if each stage of the if-else statement is divided into elements to be classified as the first block (lines 7 to 15) and elements to be classified as the last block (lines 16 to 27) by preprocessing. To do.

  Here, since the number of stages of the if-else statement for each block is known, as shown in FIG. 13, “if (), which is the start description of if-else, is displayed in the first line (seventh line) of the first block. “begin” and “end” as the end description are described in the last line (line 20). Similarly, “else begin” is described in the first line (the 21st line) of the last block, and “end” is described in the last line (the 34th line).

Process S154: The logic of the conditional expression to be inserted into if () at the head of each block is extracted. More specifically, on the j-th block, ΣP _i (i = 0 to j−1) +1 P _j from the first if-else statement based on the elements in each stage of the if-else statement. The conditional expression of the if-else statement is extracted and ORed and inserted into () of “if () begin”. This process is executed for all blocks.

  As shown in FIG. 14, the conditional expressions (A_IN == 1′b1) and (B_IN == 1 ′) extracted from the if-else statements in the seventh, tenth, and thirteenth lines of the RTL source 21 shown in FIG. b1) and the condition of (C_IN == 1′b1) ORed together are described in () of “if () begin” in the seventh row.

  Process S155: An if-else statement is inserted into each block. More specifically, all if-else statements whose conditions are extracted in the process of S154 are inserted into the j-th block. This process is executed for all blocks.

  As shown in FIG. 15, the 7th to 15th if-else statements of the RTL source 21 shown in FIG. 12 are described in the 8th to 16th lines of the first block, and the ifs of the 16th to 27th lines of the RTL source 21 -The else statement is described in the 22nd to 30th lines of the final block.

  Process S156: The description of the else term extracted from the RTL source 21 is inserted into each block.

  As shown in FIG. 16, the else terms of the 25th to 26th lines of the RTL source 21 shown in FIG. 12 are described in the 17th to 19th lines of the first block and the 31st to 33rd lines of the last block, respectively.

  FIG. 17 is a diagram showing a circuit configuration of the RTL source 21 before correction by the first correction method, and FIG. 18 is a diagram showing a circuit configuration of the corrected RTL source 27 after correction by the first correction method. is there. In FIG. 17 and FIG. 18, circuit components are simply shown for comparison.

  According to the RTL source 21 before correction, as shown in FIG. 17, six selector circuits are connected in series, and the signal 3′b110 input to the selector F passes by the output signal Y_OUT [2: 0]. The number of selectors is six. On the other hand, the signal 3′b011 input to the selector C has three stages of selectors that pass by the output signal Y_OUT [2: 0].

  On the other hand, according to the modified RTL source 27, as shown in FIG. 18, the number of selector circuits increases by one, but the signal 3′b110 input to the selector F by connecting the selector circuits in parallel is output. The number of selectors passing by the signal Y_OUT [2: 0] is four stages, and the signal 3′b011 input to the selector C is also four stages of selectors passing by the output signal Y_OUT [2: 0].

  Therefore, the original RTL source 21 has a configuration in which the variation in the output timing difference is large, but in the modified RTL source 27 output by the RTL optimization device 1, the variation in the output timing difference is eliminated. I understand.

[Correction by the second correction method]
(1) Preprocessing (block division processing)
The correction unit 15 performs the following processes S161 to S162 as preprocessing for correction (block division processing). The preprocessing for correction by the second correction method is substantially the same as the preprocessing for correction by the first correction method. Let a _i be the number of stages in the target if-else statement.

  Process S161: The number L of blocks to be divided by the if-else statement is calculated.

Based on the number of bits of the signal appearing in all conditional statements, the block number L is determined according to the following rules.
“Rule: When the number of bits is N, the number of blocks to be divided is L = ^2N .”
Processing S162: calculating the number _{P L} of if-else statements stored in each block.

The stage number P ₁ is calculated by performing case classification based on the signal value of each conditional expression used in the calculation of the block number L and counting the corresponding if-else statements.

For example, signals appearing in all conditional statements of an if-else statement are extracted, and the number of blocks L in which the if-else statement is stored is determined as follows.
• If the conditional statement signal is 1 bit, the number of blocks L = 2 at maximum.
• If the conditional statement signal is 2 bits, the number of blocks L = 4 at maximum.
-If the conditional statement signal is 3 bits, the number of blocks L = 8 at maximum.
• If the conditional statement signal is N bits, the number of blocks L = 2 ^{N at} maximum.

  Further, division is performed for each value of the extracted signal. Thereby, it is determined in which block the if-else statement of the original RTL source 21 is inserted.

  FIG. 19 is a diagram for explaining block division in the case of correction by the second correction method.

FIG. 19A shows an example of block division when the conditional statement signal is 1 bit. In this case, the number of storage blocks of the if-else statement is maximum = 2, and the number of stages of the if-else statement storage blocks A ₀ and A ₁ are P ₀ = 2 and P ₁ = 4, respectively. = 1.

FIG. 19B shows an example of block division when the conditional statement signal is 2 bits. In this case, the maximum number of if-else statement storage blocks is 4, and the if-else statement storage blocks A ₀ , A ₁ , A ₂ , and A ₃ have the number of stages P ₀ = 1 and P ₁ = 2, respectively. , P ₂ = 3, P ₃ = 4, and the number of stages in the else term = 1.

(2) This process (correction process)
Next, the correction unit 15 performs this processing (correction processing).

FIG. 20 is a diagram illustrating an example of the RTL source 21 including a correction target by the second correction method. In the RTL source 21 shown in FIG. 20, the if-else in the 7th to 24th lines is a correction target. It is assumed that the number of divisions L = 2, the number of stages P ₀ = 2 and P ₁ = 3 by preprocessing.

  Process S163: The signal value of the signal with the same name that appears in all conditions of the if-else statement is searched, and the condition of the if-else statement is classified into a signal with the same name, a signal value, and an inverted value. The if-else statement of the RTL source 21 in FIG. 20 is divided into two elements (namely, based on a signal having the same name and a signal value, here (A_IN == 1′b0) and (A_IN == 1′b1)). 7th to 12th lines) and 3 elements (13th to 21st lines).

  As the subsequent processing, in accordance with the grammatical rules of the RTL source 21, the elements of the conditional expressions classified in each block are inserted to correct the if-else statement. This correction is substantially the same process as the correction processes S153 to S156 according to the first correction method.

  Process S164: Similar to process S153, the structure of “if () begin to end” is described in the first block, and the structure of “else begin to end” is described in the last block.

  As shown in FIG. 21, “if () begin” in the first row (seventh row) of the first block, “end” in the last row (17th row), and “end” in the first row (18th row) of the last block. “else begin” and “end” in the last line (line 31), respectively.

  Process S165: Similarly to process S154, the logic of the conditional expression to be inserted into if () at the head of each block is extracted.

  As shown in FIG. 22, the conditional expression (A_IN == 1′b0) extracted from the RTL source 21 shown in FIG. 20 as one of the combination of the signal of the same name and the signal value used in the calculation of the number L of blocks is shown in the seventh row. “If () begin” in ().

  In process S166, as in process S155, conditions other than the described conditions are described in parentheses in the if-else statement.

  As shown in FIG. 23, the conditions of the if-else statement in the seventh to eighth lines of the RTL source 21 shown in FIG. 20 ((A_IN == 1′b0) && (B_IN == 1′b0) && (C_IN == 1'b1)) and a condition obtained by ANDing a signal other than the signal already extracted from the signal value (A_IN == 1'b0) and the signal value ((B_IN == 1'b0) && (C_IN == 1'b1) If-else statement in which) is set is described in the 8th to 13th lines of the top block. Similarly, based on the conditional expression of the if-else statement in the 10th to 12th lines of the RTL source 21 shown in FIG. 20, the condition ((B_IN == 1′b1) && (C_IN == 1′b0)) is changed. The set if-else statement is described in the 11th to 13th lines of the top block. Further, similarly, the if-else statement is changed to the 19th to 21st lines of the final block based on the conditions of the 13th to 15th lines, the 16th to 18th lines, and the 19th to 21st lines of the RTL source 21 of FIG. Described in lines 22 to 24 and lines 25 to 27, respectively.

  Process S167: As in process S156, as shown in FIG. 24, the else term in the 22nd to 23rd lines of the RTL source 21 shown in FIG. 20 is replaced with the 14th to 15th lines of the first block and the 28th to 29th of the last block. Each line is described.

  FIG. 25 is a diagram showing a circuit configuration of the RTL source 21 before correction by the second correction method, and FIG. 26 is a diagram showing a circuit configuration of the RTL source 27 corrected by the second correction method. In FIGS. 25 and 26, circuit components are simply shown for comparison.

  According to the RTL source 21 before correction, as shown in FIG. 25, five selectors having a 3-bit signal input are connected in series. The signal 3′b111 input to the selector E has five stages of selectors that pass by the output signal Y_OUT [2: 0], while the signal 3′b010 input to the selector B has the output signal Y_OUT [2: 0] is two stages.

  On the other hand, according to the corrected RTL source 27, as shown in FIG. 26, the configuration is changed to a 5-stage selector having a 2-bit signal input and a selector having a 1-bit signal input. . Although the number of selectors increases by one, the selectors are connected in parallel, and the signal 3′b111 input to the selector E has four stages of selectors that pass by the output signal Y_OUT [2: 0], and the speed It can be seen that is improved.

[Modification by the third modification method]
Next, as the main process (correction process), the correction unit 15 performs the following processes S171 to S174 as a process of transforming the correction target if-else branch of the RTL source 21 into a case branch in accordance with the RTL grammar rules.

  FIG. 27 is a diagram illustrating a description example of the RTL source 21 including a correction target by the third correction method. In the RTL source 21 shown in FIG. 27, the if-else in the 7th to 24th lines is a correction target.

  Process S171: The signal name “SEL_IN” is extracted from the condition of the if-else statement.

Process S172: The number of stages a _i of the target if-else statement is acquired from the signal name of the extracted conditional statement.

  Process S173: In accordance with the RTL grammar rules, instead of describing if-else, a case () statement that is a start description constituting case () and an endcase that is an end description are described.

  As shown in FIG. 28, “case ()” is described in the first line (seventh line), “endcase” is described in the last line (14th line), and the signal name extracted in () of “case ()”. “SEL_IN” is described.

  Process S174: The condition of the exceptional if-else statement of the original RTL source 21 is rewritten to “signal value of conditional expression: operation process” which is a condition of the case statement.

  As shown in FIG. 29, the conditions of the 7th to 8th lines, the 10th to 11th lines, the 13th to 14th lines, the 16th to 17th lines, and the 19th to 20th lines of the RTL source 21 shown in FIG. Describe each in ~ 12 lines. For example, “SEL_IN == 4′b0000” and “Y_OUT = 3′b000” of the if statement in the seventh to eighth lines are extracted, and “4′b0000: Y_OUT = 3′b000” is set as the corresponding condition of the case statement. Describe in 8 lines. The same applies to other if statements.

  Process S175: The else term of the if-else statement is rewritten to the default term of the case statement.

  As shown in FIG. 30, based on the condition of the else term (Y_OUT = 3′b101) in the 22nd to 23rd lines of the RTL source 21 shown in FIG. 27, the condition of the default term “default: Y_OUT = 3′b101”. Is described on line 13.

  FIG. 31 is a diagram showing a circuit configuration of the RTL source 21 before correction by the third correction method, and FIG. 32 is a diagram showing a circuit configuration of the RTL source 27 corrected by the third correction method. 31 and 32, circuit components are simply shown for comparison.

  According to the RTL source 21 before correction, as shown in FIG. 31, five 3-bit output selectors having four-bit signal inputs are connected in series, and the time for the signal to pass through the selector becomes longer, so the speed is improved. There is room for.

  On the other hand, according to the corrected RTL source 27, as shown in FIG. 32, the configuration of the 4-bit selector signal is changed into a 4-bit signal input match comparison circuit and a 3-bit AND circuit. It can be seen that since the AND circuit has six stages, but is connected in parallel, the speed of the transit time to the output signal Y_OUT [2: 0] is improved.

  The RTL optimization apparatus 1 described above can be implemented as dedicated hardware including the processing unit illustrated in FIG.

  Also, the RTL optimizing apparatus 1 includes a CPU 101, a memory 102, a storage device (hard disk) 103, an input device (keyboard, mouse, etc.) 104, an output device (display, printer, etc.) 105, and communication control as shown in FIG. The unit 106 or the like can be implemented as the computer 100 connected via an internal network or the like.

  Furthermore, the RTL optimization device 1 can be implemented as a program that can be executed by the computer 100. In this case, a program that realizes the function of the processing unit of the RTL optimization apparatus 1 shown in FIG. 1 is installed and executed on the computer 100.

  That is, the computer 100 is caused to read an execution program that causes the computer to execute the functions of the if-else extraction unit 11, the threshold determination unit 12, the data generation unit 13, the correction method determination unit 14, and the correction unit 15 illustrated in FIG. By executing it, the RTL optimizing device 1 can be realized.

In this case, the CPU 101 of the computer 100, for example,
The above execution program and input information (RTL source 21) are stored in the hard disk 103 as a file.
An execution program is activated from the input device 104, and the activated execution program is loaded into the memory 102. The RTL source 21 and the determination means designation 23 are read from the hard disk 103 to the memory 102 as necessary, and the process proceeds. During processing, processing results (log information, correction target information, determined correction method, etc.) are stored in the memory 102 and the hard disk 103.
-Display the corrected RTL source 27 on the display 105 and output it in a file format.
The process is executed according to the procedure.

  The execution program is not only a recording medium such as a CD-ROM, CD-RW, DVD-R, DVD-RAM, DVD-RW, or flexible disk, but also other storage devices provided at the end of the communication line. It may be stored in a computer hard disk or the like.

  Note that the elements constituting the RTL optimization device 1 may be realized in any combination. A plurality of components may be realized as one member, and one component may be configured from a plurality of members. The RTL optimizing apparatus 1 is not limited to the above-described embodiment, and various improvements and changes may naturally be made without departing from the gist of the present invention.

  As described above, according to the disclosed RTL optimizing apparatus 1, the description of the branch by the if-else statement of the RTL source 21 is automatically corrected so as to be more optimal in terms of the logic circuit configuration, and the corrected RTL Source 27 can be output. Therefore, the number of work steps for improving the configuration related to the branching of the logic circuit can be greatly reduced, and the variation in correction caused by manual work can be eliminated. Therefore, the efficiency of logic circuit design can be realized.

DESCRIPTION OF SYMBOLS 1 RTL optimization apparatus 11 if-else extraction part 12 Threshold value determination part 13 Data generation part 14 Correction method determination part 15 Correction part 21 RTL source 22 Log storage part 23 Specification of determination means 24 Threshold holding part 25 Correction object storage part 26 Determination Modified 27 Modified RTL source

Claims (8)

A method for optimizing a hardware description language RTL, comprising:
Computer
From the RTL source describing the target circuit, extract an if-else branch composed of the number of stages of an if-else statement equal to or greater than the number of stages indicated by a preset threshold value;
A plurality of correction methods for the if-else branch are set in advance in association with the conditions of the if-else statement, and one of the plurality of correction methods is determined based on the extracted conditions that constitute the if-else branch. Decide
An RTL optimization method comprising: executing a process of correcting the if-else branch extracted from the RTL source based on the determined correction method. The correction method is set in association with the number of signal bits, presence / absence of a signal with the same name, and presence / absence of an AND condition, which are included in a condition of an if-else statement constituting the if-else branch. The RTL optimization method according to claim 1. If the number of signal bits in the condition of the if-else statement constituting the if-else branch is 1 bit and there is no signal of the same name in each of the conditions, the first correction method is one of the correction methods. Is determined,
In the first modification method, when modifying the extracted if-else branch, the if-else statement of each stage constituting the if-else branch is divided into blocks within a preset number of stages,
The RTL optimization method according to claim 2, wherein an if-else branch configured by an if-else statement divided for each block is set in the if-else branch. The correction is made when the number of signal bits of the condition of the if-else statement constituting the if-else branch is 1 bit, a signal having the same name exists in each of the conditions, and all of the conditions are configured by AND conditions. A second correction method is determined as one of the methods,
In the second correction method, when the extracted if-else branch is corrected, the if-else statement of each stage constituting the if-else branch is changed to the same name signal of the condition of the if-else statement and the 4. The RTL optimization method according to claim 3, wherein classification is performed based on signal values of signals having the same name, and correction is performed by the first correction method for each group of the classified if-else statements. . If the number of signal bits of the condition of the if-else statement constituting the if-else branch is a plurality of bits and no other signal exists in each of the conditions, a third correction method is one of the correction methods. Is determined,
In the third correction method, each if-else statement constituting the extracted if-else branch is used as an element indicating a signal value of a condition and an operation process, and the else statement constituting the extracted if-else branch is initialized. The RTL optimization method according to claim 2, wherein the branch is changed to a branch by a case statement as a condition. The RTL according to any one of claims 1 to 5, wherein the threshold is at least an arbitrary fixed value or a value determined in advance based on an operating frequency of the target circuit. Optimization method. In order to optimize the hardware description language RTL,
From the RTL source describing the target circuit, extract an if-else branch composed of the number of stages of an if-else statement equal to or greater than the number of stages indicated by a preset threshold value;
A plurality of correction methods for the if-else branch are set in advance in association with the conditions of the if-else statement, and one of the plurality of correction methods is determined based on the extracted conditions that constitute the if-else branch. Decide
An RTL optimization program for executing a process of correcting the if-else branch extracted from the RTL source based on a determined correction method. To optimize the hardware description language RTL,
An extraction unit that extracts, from an RTL source describing the target circuit, an if-else branch composed of the number of stages of an if-else statement that is equal to or greater than the number of stages indicated by a preset threshold;
A plurality of correction methods for the if-else branch are set in advance in association with the conditions of the if-else statement, and one of the plurality of correction methods is determined based on the extracted conditions that constitute the if-else branch. A correction method determination unit for determining one;
An RTL optimizing apparatus comprising: a correcting unit that corrects the if-else branch extracted from the RTL source based on the determined correcting method.

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