CN117521566A - Logic circuit design method and logic circuit design device - Google Patents

Abstract

Embodiments of the present disclosure relate to a logic circuit design method and a logic circuit design apparatus. A method of designing a semiconductor device. It may include interpreting constraints defining delay values according to timing constraints by inputting data defining a logic circuit and timing constraint data defining timing constraints associated with the logic circuit, calculating the delay values that may be applied to each path in the logic circuit, and verifying the logic circuit by detecting the delay values as logic verification violations.

Description

Logic circuit design method and logic circuit design device

Cross Reference to Related Applications

The present application claims the benefit of U.S. provisional patent application No. 63/395,191, filed on 8.4 of 2022. The entire disclosure of U.S. patent application Ser. No. 63/395,191 is incorporated herein by reference.

Technical Field

The present invention relates to a design method, a design system, and a storage medium for a semiconductor device, and more particularly, to a design method for a logic circuit formed in a semiconductor device, a design system for executing the design method, and a storage medium storing a program for implementing the design method.

Background

When designing a logic circuit that performs a desired operation, the operation is described in a hardware description language (e.g., RTL (register transfer level)), a timing constraint of the logic circuit generated based on the RTL description is described in, for example, SDC (Synopsys design constraint), and the logic circuit is generated using the described circuit data SDC and the described timing constraint.

The disclosed techniques are listed below.

[ patent document 1] U.S. patent publication 2016/0055271.

Disclosure of Invention

In designing semiconductor devices, the timing constraints of the SDC descriptions are verified to see if they are valid in the logic circuits generated based on the RTL descriptions. Based on the generated logic circuit, an RTL description is generated, for example, by performing an actual operation. For example, the verification is performed by performing actual load logic verification using a netlist of a logic circuit generated based on the RTL description, an SDF (standard delay format) defining a delay time associated with the netlist, or the like. Since netlists, SDFs, etc. are required, verification is performed at a timing close to the final step of the design method. Therefore, even if a defect is found through verification, there are many steps for correcting the defect, and there is a problem that correction is not easy.

Other objects and novel features will become apparent from the description of the specification and drawings.

The method of designing a semiconductor device according to an embodiment includes: an interpretation step of interpreting a constraint defining a delay value according to a timing constraint by inputting data defining a logic circuit and timing constraint data defining a timing constraint related to the logic circuit; a calculation step of calculating a delay value that can be given to each path in the logic circuit; and a verification step of detecting the delay value calculated in the calculation step as a logical verification violation.

Drawings

Fig. 1 is a flowchart illustrating an outline of a method for designing a semiconductor device according to embodiment 1.

Fig. 2 is a diagram for explaining an example of a defect of a timing constraint.

Fig. 3 is a waveform diagram showing waveforms when the logic simulator is implemented using the delay data generated in step s7_1 and the netlist corresponding to the logic circuit LGC1 according to the first embodiment.

Fig. 4 is a flowchart for explaining generation of delay information according to embodiment 1.

Fig. 5 is a diagram for describing an example of the design method according to embodiment 1.

Fig. 6 is a diagram for describing an example of the design method according to embodiment 1.

Fig. 7 is a diagram for describing an example of the design method according to embodiment 1.

Fig. 8 is a diagram for describing an example of a design method according to embodiment 1.

Fig. 9 is a diagram for describing an example of a design method according to embodiment 1.

Fig. 10 is a diagram for describing an example of the design method according to embodiment 1.

Fig. 11 is a diagram for describing an example of the design method according to embodiment 1.

Fig. 12 is a diagram for describing a design method according to embodiment 2.

Fig. 13 is a diagram for describing a design method according to embodiments 1 and 2.

Fig. 14 is a block diagram illustrating the configuration of the design system according to embodiment 1.

Detailed Description

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. In all the drawings for describing the embodiments, the same parts are denoted by the same reference numerals in principle, and repeated descriptions thereof will be omitted.

Example 1

(configuration of design System)

First, a configuration of a design system for designing a semiconductor device will be described with reference to the drawings. Fig. 14 is a block diagram illustrating the configuration of the design system according to embodiment 1.

In fig. 14, reference numeral 1000 denotes a design system. The design system 1000 includes a computer 1001 such as a computer, a display device 1002 connected to the computer 1001, an input device 1003 connected to the computer 1001, and a storage device 1004 connected to the computer 1001.

The computer 1001 operates according to a program stored in the storage device 1004. During this operation, data and the like are input to the computer 1001 and processed by the input device 1003 and the storage device 1004. The computer 1001 displays the processing results through, for example, a display device 1002 and stores the results in a storage device 1004.

In the storage device 1004, various design programs for designing a semiconductor device are stored as programs. Here, a case where the design program is stored in the storage device 1004 will be described, but the present invention is not limited thereto. For example, the computer 1001 may be connected to a network (not shown), and may acquire and execute a design program via the network. In this specification, both the storage device 1004 and the network are regarded as a storage medium storing a design program.

(outline of design method of semiconductor device)

Next, an outline of a method for designing a semiconductor device will be described with reference to the drawings. Fig. 1 is a flowchart illustrating an outline of a method for designing a semiconductor device according to embodiment 1. The flow illustrated in fig. 1 is implemented by the computer 1001 executing various design programs in the design system 1000 (fig. 14).

First, in step S0, a user designs specifications of a logic circuit to perform a desired operation.

Based on the specifications designed in step S0, the user designs an RTL description for defining (generating) the logic circuit in step S1. This is achieved, for example, by the user creating an RTL description defining logic circuits in the computer 1001 using the input device 1003 shown in fig. 14. In this way, the RTL description defining the logic circuit is prepared as the data DF1.

In step S2, the user designs the timing for the logic circuit. The design in step S2 generates timing constraints for the logic circuit. This provides timing constraint data DF2 for the logic circuit.

In step S3, the computer 1001 synthesizes a logic circuit using data (RTL description) DF1 and data (timing constraint) DF2. The synthesis in step S3 generates a netlist defining a logic circuit, and the generated netlist is prepared as data DF3.

In step S4, the computer 1001 performs a test facilitation technique (DFT: design for testability). Thus, data for facilitating the test is generated, the generated data is inserted into a data (netlist) DF3, and a netlist for facilitating the test is generated. The generated netlist is prepared as data DF5. Further, the computer 1001 generates a constraint (hereinafter, also referred to as DFT constraint) based on the data generated by the test facilitation technique, and prepares the constraint as the data DF4.

The computer 1001 selects gates (logic cells) of a library using data DF5 of the netlist, arranges the selected gates, and connects the gates. Thus, a netlist including the arranged gates and the wires connecting the gates is prepared as data DF7. In addition, the computer 1001 generates data of delay data related to a netlist prepared as the data DF7, and prepares the data as the data DF6.

That is, in step S5, the computer 1001 selects and arranges a plurality of gates specified by the netlist of the data DF5 from gate libraries prepared in advance. In addition, computer 1001 connects selected gates based on the netlist of data DF5. Thus, a netlist corresponding to the netlist of the data DF5 and a netlist arranged to the routing gate are prepared as the data DF7. The computer 1001 prepares the delay value between gates connected by a wire as the delay information as the data DF6, for example. In a first embodiment, DF6 is in the form of an SDF.

In step S6, signature-off (sign-off) is performed, and the design of the semiconductor device is completed. Note that in step S6, the computer 1001 may perform the timing verification STA using the data DF7 and the data DF4.

By performing the process shown in fig. 1, DF6, DF7, etc. desired to manufacture a device having desired logic circuits can be prepared.

(comparative example)

Next, referring to fig. 1, it will be verified whether the timing constraint described in the SDC is appropriate by the actual load logic verification. The actual load logic verification is performed at a timing near the final step of the design method. In fig. 1, after the signing is performed (step S6), actual load logic verification is performed in step S8 indicated by a broken line. This is because, in the actual load logic verification, the actual operation of the logic circuit is performed by using the data DF7 of the netlist that has been laid out and routed and the data DF6 of the delay information about the delay value between the gates connected by the wires. That is, unless these DF6 and DF7 are prepared, it is difficult to perform reference (datum) load logic verification, and as shown in fig. 1, actual load logic verification is performed in the vicinity of the last step of the design process.

If the actual load logic verification performed in step S8 finds a failure, the user returns to, for example, step S1 or S2 to check the design of the RTL and the design of the timing constraints. After the inspection, S6 is performed again from step S3, so that a large number of steps need to be performed, and a large number of correction steps are required when a defect is found.

In addition, actual load logic verification is problematic in terms of performance and is difficult to implement for large scale logic circuits.

(logical verification Using timing constraints)

In the first embodiment, step S7 is performed in designing the apparatus, instead of step S6 indicated by the broken line in fig. 1.

Step S7 according to the first embodiment includes steps s7_1 and s7_2. In step s7_1, the computer 101 (fig. 14) generates delay information on the constraint according to the timing constraint described in the SDC as the data DF2 and the logic circuit described as the RTL of the data DF1 or the logic circuit of the netlist as the data DF3. The computer 101 prepares the generated delay information as data s7_df. Thereafter, in step s7_2, the computer 101 performs logic simulation using the delay information prepared for the data s7_df to simulate the logic circuit of the RTL description or the logic circuit of the netlist. In this way, the same verification as the actual load logic verification is performed at step S7.

In the logic simulation in step s7_2, when a defect is found, the user returns to, for example, step S1 or S2 to check the design of RTL and the design of timing constraints. Therefore, it is not necessary to perform steps S3 to S6 again (for example, to correct a defect), and the number of correction steps can be prevented from increasing. For example, in step s7_1, when delay information is generated using a logic circuit described by the SDC as the data DF2 and the RTL as the data DF1, the timing constraint can be verified without performing logic synthesis in step S3.

Next, an example will be described in which defects are found by performing logic simulation using the generated delay information and the existence of defects in the timing constraint described in SDC is verified.

(examples of defects of timing constraints)

Fig. 2 is a diagram for explaining an example of a defect of a timing constraint. The configuration of the logic circuit according to the exemplary embodiment is defined by a netlist (or RTL) corresponding to the logic circuit, but for convenience of explanation, the configuration of the logic circuit defined by the netlist will be described. In fig. 2, LGC1 indicates an exemplary logic circuit, and DS1 indicates a timing constraint (timing constraint described in SDC) related to the logic circuit LGC 1.

As shown in fig. 2, the logic circuit LGC1 includes two flip-flop circuits (hereinafter also referred to as FF circuits) FF1, FF2, and a selector SL. The output of the FF circuit FF1 is connected to one input terminal of the selector SL through a wire, and the output terminal of the selector SL is connected to the input terminal of the FF circuit FF2 through a wire. The output terminal of the FF circuit FF2 is connected to the other input terminal of the selector SL through a wire and is output as an output Dout.

The output terminal of the selector SL is connected to the input terminal of the FF circuit FF2 through a wire. The selector SL operates according to a selection signal SEL to supply a signal supplied to one input terminal or the other of the FF circuit FF2 to the FF circuit.

As shown in fig. 2, FF circuits FF1 and FF2 capture data and supply the captured data in synchronization with one common clock signal CLK. That is, the FF circuit FF1 receives the data Din in synchronization with a change (e.g., a rising edge) of the clock signal CLK and supplies it as a signal U1 to one of the selectors SL. The FF circuit FF2 also receives and outputs a signal output from the selector SL in synchronization with the rising edge of the clock signal CLK.

The timing constraint DS1 for the logic circuit LGC1 is described by two description statements SD1_1 and SD1_2, as shown in fig. 2. Here, the description statement SD1_1 indicates that one cycle of the clock signal CLK is 10 (ns), and the description statement SD1_2 indicates that there is a multi-cycle path of two cycles between the FF circuit FF1 and the FF circuit FF2. That is, the timing constraint DS1 illustrated in fig. 2 designates that the logic circuit LGC1 transfers data from the FF circuit FF1 to the FF circuit FF2 within two cycles (20 (ns)) of the clock signal CLK.

Fig. 3 is a waveform diagram showing waveforms when the logic simulator is implemented using the delay data generated in step s7_1 and the netlist corresponding to the logic circuit LGC1 according to the first embodiment. Fig. 3 shows a state when the selection signal SEL changes every two cycles from time t1 to time t2, and after time t2, the selection signal SEL changes once every cycle.

As can be seen from fig. 3, between time t1 and time t2, an output Dout according to the input Din and the selection signal SEL is output from the logic circuit LGC 1. On the other hand, after time t2, output Dout is undefined. In fig. 3, the times from the times t1, t2 to the times t1_d and t2_d are times determined by the delay data generated in step s7_1 illustrated in fig. 1. Even after time t2_d, when the output Dout is uncertain, generation of an uncertain FAI (diagonal line) is detected by logic simulation. As a result, the timing constraint DS1 shown in fig. 2 was found to have a defect.

< generation of delay information >

Next, generation of delay information described in step s7_1 of fig. 1 will be described in more detail with reference to the accompanying drawings. Fig. 4 is a flowchart for explaining generation of delay information according to embodiment 1.

As shown on the left side of fig. 4, in step s7_1, the computer 1001 receives DF2 associated with the timing constraints described by the SDC. Further, in step s7_1, data DF1 or data DF3 of the netlist related to the logic circuit described in RTL is input to the computer 1001. Here, although the data DF1 or the data DF3 is input to the computer 1001 in step s7_1, two pieces of data (DF 1, DF 3) may be mixed and input to the computer 1001.

In step s7_1, the computer 1001 sequentially executes steps s7_1_0, s7_1_1, and s7_1_2, and stores delay information generated by executing these steps as data s7_df in the storage device 1004 (fig. 14).

In step s7_1_0, the computer 1001 interprets the timing constraint described in SDC (data DF 2). Next, in step s7_1_1, the computer 1001 executes step s7_ck and step s7_ex for generating information necessary for calculating the delay value. In step s7_ck, the computer 1001 analyzes a clock signal used in a logic circuit defined by the data DF1 or the data DF3. In step s7_ex, the computer 1001 analyzes the abnormal constraint based on the timing constraint (data DF 3) described in the SDC. Examples of the abnormal constraint will be described later, and thus a description thereof will be omitted.

Thereafter, in step s7_1_2, the computer 1001 calculates a maximum delay value that can be assigned to each path. Here, the path means a path connecting at least two gates in a logic circuit defined by the data DF1 or the data DF3. Details of this step s7_1_2 are shown on the right side of fig. 4. Next, steps s7_rt0 to s7_rt5 executed by the computer 1001 in step s7_1_2 will be described.

< description of step s7_1_2 where the maximum delay value that can be given to each path is calculated)

Here, a case where the computer 1001 calculates the maximum delay by inputting the data DF1 related to the timing constraint and the data DF3 of the netlist will be described with reference to fig. 4. Instead of the data DF3 of the netlist, the data DF1 described in RTL will be described in the second embodiment, and thus will not be described here.

In step s7_1_2, the computer 1001 executes steps in order from step s7_rt0 to rt_5. Here, since the first step s7_rt0 is a step performed by the computer 1001 when inputting the data DF described in RTL, the first step s7_rt0 will be described later in embodiment 2.

In step s7_rt1, the computer 1001 extracts a clock signal, i.e., data DF3, used in a path connecting at least two gates in the logic circuit defined by the netlist. Since the logic circuit generally includes a plurality of paths, in step s7_rt1, the computer 1001 extracts a clock signal to be used for each path.

The computer 1001 lists all combinations of the transmission side clock signal and the reception side clock signal of the clock signal extracted in step s7_rt1 in step s7_rt2. That is, when data propagates through a path connecting two gates, a clock signal used at a gate side transmitting the data is used as a transmission side clock signal, and a clock signal used at a gate side receiving the data is used as a reception side clock signal. In step s7_rt2, the computer 1001 lists a combination of all paths using the transmission side clock signal and the reception side clock as settings.

Next, in step s7_rt3, the computer 1001 calculates a delay value that needs to be satisfied at minimum so that data can be transmitted and received in each combination of the transmission-side clock signal and the reception-side clock signal. Hereinafter, this delay is also referred to as the required time.

In step s7_rt4, the computer 1001 calculates the minimum value from all the request times calculated in step s7_rt3. For paths where no exception constraint is applied, computer 1001 sets "0" to a minimum value.

In step s7_rt5, the computer 1001 calculates a maximum delay value (maximum delay value) that can be assigned (assigned) to a path connecting gates constituting a logic circuit. The computer 1001 sets the maximum delay value calculated in step s7_rt5 as delay information.

< calculation example of maximum delay value >

Next, an example of calculating the maximum delay value by performing steps s7_rt1 to s7_rt5 will be described with reference to the accompanying drawings. Fig. 5 to 11 are diagrams for describing an example of the design method according to embodiment 1. Here, an example will be described in which a netlist is used in designing a logic circuit, but for convenience of explanation, schematic configurations of circuits defined by the netlist are shown in fig. 5 to 11.

First, the configuration of the logic circuit LGC2 designed in the first embodiment and the timing constraint DS2 related to the logic circuit LGC2 will be described with reference to fig. 5.

The logic circuit LGC2 includes an FF4 from the FF circuit FF1, an AND circuit AND, AND an OR circuit OR. The clock signal CLK is supplied from the FF circuit FF1 to each clock terminal of the FF4. Taking the FF circuit FF1 as an example, the FF circuit FF1 receives data and outputs data in synchronization with a change in the clock signal CLK. The FF circuits FF2 to FF4 are identical to FF1 in the FF circuit.

In the logic circuit LGC2, the outputs of the FF circuits FF1 AND FF2 are input to an AND circuit AND, the output of the AND circuit AND the output of the FF circuit FF3 are input to an OR circuit OR, AND the output of the OR circuit OR is input to the FF circuit FF4.

As shown in fig. 5, three description statements ds2_1 to ds2_3 are described in the timing constraint DS2 related to the logic circuit LGC2.

Here, the descriptive statement ds2_1 indicates that one period of the clock signal CLK is 10 (ns). The description statement SD2_2 indicates that there is a multi-cycle path of three cycles between the FF circuits FF1 and FF4. That is, in the timing constraint DS2 shown in fig. 3, the specified logic circuit LGC2 transfers data from the FF circuit FF1 to the FF circuit FF4 in three cycles (30 (ns)) of the clock signal CLK. The description statement SD2_3 indicates that there is a multi-cycle path of two cycles between the FF circuit FF2 and the FF circuit FF4. That is, in the logic circuit LGC2, it is prescribed that the data transfer from the FF circuit FF2 to the FF circuit FF4 does not exceed two cycles (20 (ns)) of the clock signal CLK.

In the timing constraint DS2, the exception constraint corresponds to the description statements ds2_2 and ds2_3. That is, in the example of the timing constraint DS2, the abnormal constraint is a portion where paths of multiple cycles exist, and the abnormal constraint is applied to a path connecting the FF circuit FF1 and the FF circuit FF4 and a path connecting the FF circuit FF2 and the FF circuit FF4.

Using the logic circuit LGC2 and the timing constraint DS2 illustrated in fig. 5, the computer 1001 performs steps s7_rt1 to s7_rt5 illustrated in fig. 4.

Fig. 6 is a diagram for explaining steps s7_rt1 and s7_rt2. In step s7_rt1, the clock signal used in each path is extracted. In the logic circuit LGC2, as indicated by reference numeral rt_lgc2 in fig. 6, there are three paths. That is, the logic circuit LGC2 has a path (FF) connecting the FF2→ff4 circuit FF1 and the FF circuit FF4, a path (FF) connecting the FF3→ff4 circuit FF2 and the FF circuit FF1→ff4, and a path connecting the FF circuit FF3 and the FF circuit FF4. Since the clock signal used in the FF circuit FF1 from the FF circuit FF4 is only the clock signal CLK, only the clock signal CLK is extracted by performing step s7_rt1.

By executing step s7_rt2, all combinations of the transmission side clock signal and the reception side clock signal are enumerated. In fig. 6, referring to FF1→ff4, data propagates from FF circuit FF1 to FF circuit FF4. Thus, FF circuit FF1 corresponds to the transmission side gate and FF4 of the FF circuit corresponds to the reception side gate. In the logic circuit LGC2, only the clock signal CLK is used, and therefore, in the path (FF 1→ff 4), the combination of the transmission side clock signal and the reception side clock signal becomes the clock signal clk→clk. Since the other paths are the same as the paths (FF 1→ff 4), by performing step ST7 RT2, only the combinations of the clock signals clk→clk are listed, as indicated by reference numeral clk_lgc2 in fig. 6. In the following drawings, the clock signal CLK supplied to the FF circuit is omitted.

Next, the request time is calculated by executing step s7_rt3. Fig. 7 is a diagram for explaining this step s7_rt3.

In fig. 7, a multi-cycle path (FF 1→ff 4) as an abnormality constraint is applied, which is represented by the code MCP3, and a multi-cycle path (FF 2→ff 4) as an abnormality constraint is applied, which is represented by the code MCP 2. Further, a path (FF 3→ff 4) to which the abnormality constraint is not applied is denoted by reference numeral SCP in fig. 7.

As shown in fig. 6, for each of the paths MCP2 and MCP3, the combination of the transmission side clock signal and the reception side transmission clock signal is one signal (clock signal CLK). Thus, in the clock signal CLK, the delay required to reference and allow paths MCP2 and MCP3 to be transmitted is calculated based on the timing constraint DS2, as indicated by the code ds2_an.

First, in the path MCP3, since the multicycle is three cycles, as shown in ds2_an, the delay of the path MCP3 is calculated as (10 (ns) +10 (ns) ×2) ×90% =27 (ns). In this calculation, the worst case of the timing of the clock signal CLK variation is considered and multiplied by 90%. It should be noted that 90% is an example and is not limited to this value. Similarly, in the path MCP2, since the multicycle is two cycles, the delay for the path MCP2 is calculated as (10 (ns) +10 (ns) ×2) ×90% =27 (ns). Here, the reason for multiplying by 90% is the same as that for the path MCP 3.

By executing step s7_rt4, the minimum value is calculated from all delay values (required time). Fig. 8 and 9 are diagrams for explaining step s7_rt4.

In fig. 8, since the state of the logic circuit LGC2 shown on the left side of the arrow CH1 is the same as the state of the logic circuit LGC2 shown in fig. 7, the description thereof will be omitted. In step s7_rt4, when the path to which the abnormality constraint is applied and the route to which the abnormality constraint is not applied are merged or branched, a delay value is also set for the route to which the abnormality constraint is not applied. In the logic circuit LGC2 shown on the left side of fig. 8, the path SCP corresponds to a path to which no abnormal constraint is applied. Thus, in logic circuit LGC2, path SCP and path MCP2 are combined in OR circuit OR. Thus, a delay is also set in the path SCP. Here, the delay set in the path SCP is 1 cycle (10 (ns)) ×90% =9 (ns). Here, 90% is a value determined in consideration of the worst case of the variation timing of the clock signal CLK. Thus, as shown on the right side of the arrow CH1 in fig. 8, the delay added to each of the paths SCP, MCP2, and MCP3 is calculated.

Next, the computer 1001 executes the processing illustrated in fig. 9. In fig. 9, the state of the logic circuit LGC2 shown on the left side of the arrow CH1 is similar to the state of the logic circuit LGC2 shown on the right side of the arrow CH1 in fig. 8. In contrast, fig. 9 clearly shows that the path connecting the OR circuit OR and the FF circuit FF4 is the common path cm_s. That is, it indicates that the path (common path cm_s) connecting the OR circuit OR and the FF circuit FF4 is commonly used in the path SCP given no abnormal constraint and the paths (MCP 2, MCP 3) given abnormal constraint.

The computer 1001 subtracts the delay value 9 (ns) of the path SCP without abnormal constraint from the time of the common path cm_s. The computer 1001 sets the delay value of the subtracted path SCP to the delay value of the common path cm_s. Further, the computer 1001 subtracts the delay value set in the common path cm_s from the delay values of the paths MCP2, MCP3 to which the abnormality constraint is added. By this subtraction, the delay value of the path MCP2 becomes 18 (ns), and the delay value of the path MCP3 becomes 9 (ns). The delay values 18 (ns) and 9 (ns) calculated by the subtraction are minimum values of the request time (required time) of the paths MCP2, MCP3 to which the abnormality constraint is added. In addition, the delay of the path SCP without additional anomaly constraint is 0 (ns). In fig. 9, the state of the logic circuit LGC2 at this time is shown on the right side of an arrow CH1 of the logic circuit LGC2.

Next, as illustrated in fig. 4, the computer 1001 performs step s7_rt5. The processing performed in step s7_rt5 is shown in fig. 10 and 11.

In fig. 10, the state of the logic circuit LGC2 shown on the left side of the arrow CH1 is similar to the state shown on the right side of the arrow CH1 in fig. 9. In contrast, fig. 10 clearly shows that the path connecting the AND circuit AND the OR circuit OR is the common path cm_m. That is, paths MCP2 AND MCP3 to which an abnormality constraint is added are combined in the AND circuit AND, AND a path connecting the AND circuit AND the OR circuit OR is shared by two paths to which an abnormality constraint is added, indicating that the paths are the common path cm_m.

When paths to which an abnormality constraint is added are merged or branched at gates (AND circuits AND in the example of fig. 10), the computer 1001 sets paths overlapping between the paths as a common path cm_m, AND sets a minimum value (1 cycle×90% =9 (ns) in the example of fig. 10) as a delay value of the common path cm_m. Thereafter, the computer 1001 subtracts the delay value of the common path cm_m from the paths MCP2, MCP3 to which the abnormality constraint calculated in step s7_rt4 is added, and recalculates the delay value of the paths MCP2, MCP 3. With this recalculation, the delay of the path MCP2 becomes 0 (ns), and the delay of the path MCP3 becomes 9 (ns).

Therefore, in fig. 10, as shown on the right side of the arrow CH1, a delay value assigned to each of a path connecting the FF circuit FF1 AND the AND circuit AND, a path connecting the FF circuit FF2 AND the AND circuit AND, a path connecting the AND circuit AND the OR circuit OR, a path connecting the FF circuit FF3 AND the OR circuit OR, AND a path connecting the OR circuit OR AND the FF circuit FF4 is calculated. In the embodiment illustrated in fig. 10, a delay value 9 (FF 1) is assigned to a path connecting the FF circuit ns AND the AND circuit AND, AND a delay value 9 (ns), a delay value 0 (ns), AND a path connecting the AND circuit AND the OR circuit OR are assigned to a path connecting the FF circuit FF2 AND the AND circuit AND. Delay value 9 (ns) is assigned to a path connecting FF circuit FF3 and OR circuit OR, and delay value 0 (ns) is assigned to a path connecting OR circuit OR and FF circuit FF4.

Therefore, in the logic circuit LGC2, the maximum delay that can be allocated between the logic units (the FF circuit, the AND circuit, AND the OR circuit in fig. 10) is calculated. It should be noted that since a logical unit may be considered a node when viewed in a netlist, for example, it may be considered to calculate the maximum delay value that may be allocated between nodes.

Next, the computer 1001 executes the processing illustrated in fig. 11. In fig. 11, the state of the logic circuit LGC2 shown on the left side of the arrow CH1 is the same as that shown on the right side of the arrow CH1 in fig. 10, and thus will not be described again. The computer 1001 outputs, as delay information, a maximum delay value excluding a delay value 0 (ns) among the maximum delay values allocated between logic units. In fig. 11, a computer 1001 describes the maximum delay value in the SDF and outputs the maximum delay value. This is illustrated on the right side of arrow CH 1.

In other words, in fig. 11, ds_sdf indicates delay data, wherein the calculated maximum delay data is described by SDF. In the delay information ds_sdf, the description sentence ds_d1 indicates that the delay value of the path connecting the output terminal (Q) of the FF circuit FF1 AND the input terminal (a) of the AND circuit AND is 9 (ns), the description sentence ds_d2 indicates that the delay value of the path connecting the output terminal (Y) of the AND circuit AND the input terminal (a) of the OR circuit OR is 9 (ns), AND the description sentence ds_d3 indicates that the delay value of the path connecting the output terminal (Y) of the OR circuit OR AND the input terminal (DATA) of the FF circuit FF4 is 9 (ns).

As shown below the arrow CH2 in fig. 11, the delay data ds_sdf output from the computer 1001 is input to the logic simulator. The computer 1001 performs logic simulation by using the delay information ds_sdf as data for determining that the delay information ds_sdf is a logic verification violation. That is, in the logic simulation, when there is a delay exceeding the delay information ds_sdf, the logic simulator determines that the delay is violated.

Example 2

Next, description will be made with reference to the drawings, inputting data DF1 of RTL description of the definition logic circuit of data DF3 in place of the netlist to step s7_1 shown in fig. 4. Fig. 12 is a diagram for describing a design method according to embodiment 2. Here, the same logic circuit LGC2 as that described in the first embodiment is designed.

When the data DF1 described by RTL is input to step s7_1, the computer 1001 first executes step s7_rt0 in step s7_1_2.

In step s7_rt0, the computer 1001 sets a path corresponding to the constraint as a node. Thereafter, the computer 1001 performs the above steps s7_rt1 to s7_rt5.

In fig. 12, ds_rtl1 above arrow CH3 indicates an RTL description defining the logic circuit LGC2. In the second embodiment, in step s7_rt0, the computer 1001 converts the described operator RTL (e.g., &, |, etc.) into a logic unit (e.g., AND circuit AND, OR circuit OR, etc.) used in the netlist description, AND assigns an output signal of the FF circuit to a wire (wire). Further, the computer 1001 divides each operator into assignments, and deletes the description sentence (FF 4< = (FF 1& FF 2) |ff 3) existing in the original RTL description. Thus, as shown below arrow CH3, RTL description ds_rtl1 generates RTL description ds_rtl2. In the RTL description ds_rtl2, the/added of the beginning of the description sentence indicates that the description sentence of the description sentence is added in the original RTL. In addition, in the RTL description ds_rtl2, the description statement/removed FF4< = (FF 1& FF 2) |ff3/indicates removal from the original RTL. In addition, regardless of the descriptive text of the RTL, it can be deleted by a procedure, operation, or the like in various tools related to design support.

Thereafter, the computer 1001 performs steps s7_rt1 to s7_rt5 to calculate the delay value in the same manner as in the first embodiment. The calculated delay value is applied to the wire to be applied using known techniques. Thus, in fig. 12, a delay is given between logic cells (logic circuits indicated by reference sign LGC 2). Thereafter, a delay value (9 (ns)) assigned between the logic units is input as delay information to the logic simulator.

According to the second embodiment, even if a logic circuit is defined in the RTL description, the timing constraint can be efficiently verified.

Fig. 13 is a diagram for describing a design method according to embodiments 1 and 2. With reference to fig. 13, the outline of the first embodiment and the second embodiment will be described below. That is, in step S1, a description defining the configuration of the logic circuit to be designed (RTL creation) is created, and in step S2, a description defining the timing constraint (SDC creation) is created. Thereafter, in step s7_1, the computer 1001 executes a program to extract a clock signal related to an abnormal constraint based on the created timing constraint, calculate a request time (required time) from the extracted clock signal and the abnormal constraint, and generate delay information from the calculated request time. With the generated delay information as a restriction of verification, the computer 1001 performs logic verification in step s7_2.

Although the invention made by the present inventors has been described in detail based on the embodiments, it goes without saying that the invention is not limited to the above-described embodiments and various modifications can be made without departing from the gist thereof.

Claims (8)

1. A method of designing a semiconductor device, comprising:

(a) Interpreting a constraint defining a delay value according to a timing constraint by inputting data defining a logic circuit and timing constraint data defining a timing constraint associated with the logic circuit;

(b) Calculating the delay value that can be applied to each path in the logic circuit; and

(c) The logic circuit is verified by detecting the delay value as a logic verification violation.

2. The method of claim 1, wherein the (b) calculating comprises:

(b1) Extracting, in each of the paths, an output side clock for output data used on the output side and an input side clock for input data used on the input side;

(b2) Enumerating all combinations of the output side clock and the input side clock;

(b3) Extracting clock paths involving the output side and the input side; and

(b4) A minimum delay value is calculated that allows data to be transferred between the output side clock and the input side clock.

3. The method of claim 2, wherein the (c) verification comprises functional verification by hardware and software.

4. A method according to claim 3,

wherein the data defining the logic circuit is described in RTL, and

wherein the timing constraint data is described in terms of SDC.

5. A method according to claim 3,

wherein the data defining the logic circuit is described in a netlist and

wherein the timing constraint data is described in terms of SDC.

6. A logic circuit design apparatus, comprising:

a computer;

an input device connected to the computer; and

a display device connected to the computer,

wherein the computer is configured to perform the following:

(a) Interpreting a constraint defining a delay value according to a timing constraint by inputting data defining a logic circuit and timing constraint data defining a timing constraint associated with the logic circuit;

(b) Calculating the delay value that can be applied to each path in the logic circuit; and

(c) The logic circuit is verified by detecting the delay value detection as a logic verification violation.

7. The apparatus of claim 6, wherein the (b) calculating comprises:

(b1) Extracting, in each of the paths, an output side clock for the output data used on the output side and an input side clock for the input data used on the input side;

(b2) Enumerating all combinations of the output side clock and the input side clock;

(b3) Extracting clock paths involving the output side and the input side; and

(b4) A minimum delay value is calculated that allows data to be transferred between the output side clock and the input side clock.

8. The method of claim 7, wherein the (c) verification comprises functional verification by hardware and software.