JP3908192B2 - Logic circuit failure diagnosis apparatus, failure diagnosis method and program thereof - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a failure diagnosis device for a logic circuit, a failure diagnosis method, and a program thereof, and more particularly, a failure diagnosis device for a logic circuit that estimates a failure location of a logic circuit based on fail information obtained from a test result of the logic circuit, The present invention relates to a failure diagnosis method and a program thereof.
[0002]
[Prior art]
In recent years, with the advancement of semiconductor element miniaturization technology, the size of semiconductor devices composed of such semiconductor elements has also increased. Therefore, the efficiency of failure analysis as well as logic verification at the time of design and test efficiency improvement of manufactured semiconductor devices has been increased. There is also a need to make it easier.
[0003]
Conventionally, when designing a logic circuit in a semiconductor device, a logic simulation device has been used as a tool for verifying the logic operation and timing. On the other hand, as a tool applied at the time of failure analysis of a manufactured semiconductor device, for example, fault diagnosis There is a device.
[0004]
This type of logic circuit fault diagnosis is performed by installing a logic circuit fault diagnosis program in a computer having a general configuration and executing it according to each command input as a method for estimating the fault location of the logic circuit. Do.
[0005]
One example is described in the conventional example of Japanese Patent Application No. 2001-383335. Referring to FIG. 14, which shows a flowchart of schematic processing in this conventional logic circuit failure diagnosis, first, in step S31, using a failure simulator, a function or logic simulation is performed assuming a failure in the logic circuit. The simulation result is compared with the expected value, and a failure dictionary is created in which the assumed failure location is associated with the test vector that detected the failure. In step S32, fail information is obtained from the actual test result of the logic circuit. (See Patent Document 1).
[0006]
Next, in step S33, the failure dictionary is searched corresponding to the fail pin and the fail vector of the fail information to obtain the assumed failure location. In step S34, priority is given to the plurality of assumed failure candidates obtained. Estimate the failure location by ranking.
[0007]
In addition, as another method for identifying a failure location of a conventional logic circuit, for example, using an electron beam tester, the failure location is estimated from an upper layer of the logic circuit, an internal signal at the layer boundary is observed, and the failure location is identified as a logic circuit. There is also a method of narrowing down to the lower hierarchy in order.
[0008]
Further, as another conventional logic circuit failure diagnosis method, there is a method of estimating a failure location at the gate level by dividing the logic circuit into a latch and a combinational circuit as described in Japanese Patent Application Laid-Open No. 8-146093. Yes (see Patent Document 2).
[0009]
In this method, combinational circuits that can propagate faults to fault output are dynamically extracted, the logic state and path of fault propagation are estimated for each combinational circuit, and the fault location is estimated by going back to the input method. is doing.
[0010]
Here, the logic state of the combinational circuit is not only the logic value of one signal line, but all nodes in the circuit, that is, signal lines, gates, gate terminals, and input / output terminals are 0/1 / X (Don't Care). ) / Z (high impedance) / U (undefined).
[0011]
On the other hand, the method in the above-mentioned Japanese Patent Application No. 2001-383335 “Logic Circuit Fault Location Estimation Method and Logic Circuit Fault Location Estimation Program” converts the logic circuit into a decision graph and converts each node corresponding to the test pattern. While comparing the expected value with the estimated value, the failure location is estimated at the functional level.
[0012]
[Patent Document 1]
Japanese Patent Application No. 2001-383335 (paragraph “0003”, FIGS. 1 and 5).
[0013]
[Patent Document 2]
JP-A-8-146093 (paragraphs “0013”, “0016”, “0017”, FIGS. 1 and 2).
[0014]
[Problems to be solved by the invention]
As described above, in the logic circuit fault diagnosis method using the conventional fault simulator, it is necessary to create a fault dictionary in advance, but since the creation of the fault dictionary requires a lot of fault simulation time, the logic circuit becomes large-scale. There is a problem that the more it takes, the calculation time becomes enormous, and the file of the failure dictionary becomes very large.
[0015]
In addition, failure models used in failure simulation are generally single stuck-at faults, so multiple failures such as bridge failures may not match the actual ones.If the failure simulation model is expanded to multiple failures, failure simulation There is a problem that it is not practical in terms of processing time.
[0016]
Furthermore, the conventional failure location estimation method of the logic circuit using the electron beam tester is an effective means for narrowing down the failure location while sequentially observing the failure location from the upper hierarchy to the lower hierarchy of the logic circuit. When the scale is increased and a multilayer wiring structure is formed, there is a problem that the potential of the lower layer wiring cannot be observed.
[0017]
Furthermore, in the case of the conventional fault diagnosis method at the gate level, it is an effective means because the fault location can be estimated for each combinational circuit. Processing time becomes a problem.
[0018]
An object of the present invention is made in view of the above-mentioned problems, and calculates an expected value in a short time at a functional level for a large-scale, multi-layered logic circuit. It is to estimate the location.
[0019]
[Means for Solving the Problems]
Therefore, the present invention provides a state transition table created for each fail estimation circuit block having a fail estimation output port extracted by a fail extraction device from description information in which the structure or operation of a logic circuit is described in the design language in units of circuit blocks. Based on the above, an input node, an operation node composed of operators, a selection node that selects one output value from a set of a plurality of input values, and an output node are connected to each of these nodes, and the data flow display on the display means Then, a decision graph for determining the operation for each node is created, and the failure propagation path estimation using the decision graph is performed while assuming the data system failure and the control system failure separately. It has the function of estimating the fault location of the system and the control system.
[0020]
Another feature of the present invention is a logic circuit fault diagnosis device that estimates a fault location of the logic circuit based on fail information acquired from a test result of the logic circuit. The input device and the logic circuit are configured in a design language. A fail extraction device that extracts a fail estimation circuit block having a fail output port and a fail estimation output port based on description information functionally described in units of blocks, the fail information, and fail propagation estimation information, and the fail estimation based on the description information A state transition table having a plurality of states is created in accordance with the processing order of the circuit block. Based on the state transition table, one output value is obtained from a set of input nodes, operation nodes composed of operators, and a plurality of input values. The selected node and output node to be selected are connected to each node, and the data flow is displayed to display all conditions. A conversion device for creating a decision graph for determining an operation for the operation, an expected value calculation device for calculating an expected value of the logic circuit, a failure location estimation device for estimating a failure location of the logic circuit, and each of the devices It is provided with the memory | storage device which memorize | stores information, and the output device which displays the output data of the said failure location estimation apparatus.
[0021]
The design language is a language describing the structure or operation of the logic circuit.
[0022]
Further, the conversion device divides the processing of the logic circuit into a plurality of transition states, and creates a state transition table including items of a current state, a state transition condition, a next state, and an operation, and the state Set the process to read the input port, state variable or numeric value described in the transition table as an input node, set the operator process as an operation node, and write the output port, the state variable or the numeric value as an output node Setting, creating a control part that calculates a state by connecting the input node and the operation node as a data flow, giving the result of the created state as a binary value of TRUE / FALSE, and the input node and Create a data part that calculates an output value by connecting the operation node as the data flow, and depending on the result of the state, And means for setting the selected nodes for from among the obtained set to select output to the output node of the output value of the one corresponding to the state of the TRUE.
[0023]
Furthermore, the expected value calculation device calculates an output value of the input node, the operation node, the selection node, and the output node each time a state changes based on the decision graph, and calculates a node name and a calculation. Expected node value acquisition means for creating a node table composed of a set of values, and output value extraction means for extracting the output value of the logic circuit from the node table.
[0024]
Further, the expected node value acquisition means in the expected value calculation device reads the test pattern or the previous output pattern, sets the input node, and sets all input values and outputs the input pattern. Operation node extraction means for extracting operation nodes whose values are not set, operation node setting means for calculating output values based on input values for the extracted operation nodes, and setting of all operation nodes are completed If not completed, return to the operation node extraction means, if completed, proceed to the next means operation node determination means, selection node setting means for calculating the output value of the selected node, Output node setting means for calculating an output value of the output node, and input pattern reading means for the next state if there is a next state and the next state is not the first transition state Come, whether there is the next state, or if the first transition state next state, and a state determining means to end the process.
[0025]
Further, the output value extracting means in the expected value calculating device outputs the output value of the logic circuit by means for extracting the output value of the output port in the final state for each test pattern from the node table created by the node expected value acquiring means. Has a function to extract a value.
[0026]
The logic circuit failure diagnosis method of the present invention is characterized in that in the logic circuit failure diagnosis method for estimating the failure location of the logic circuit based on fail information obtained from the test result of the logic circuit, the logic circuit is expressed in a design language. A fail extraction step of extracting a fail estimation circuit block having a fail output port and a fail estimation output port from the description information described in units of circuit blocks, the fail information and the fail propagation estimation information, and the fail estimation by the description information. Creates a state transition table with multiple states according to the processing order of the circuit block, and selects one output value from a set of input nodes, operator nodes composed of operators, and multiple input values based on the state transition table The selected node and output node to be connected to each node and the data flow display A conversion step of creating a decision diagram for determining the operation to all conditions Te, the expected value calculation step of calculating an expected value of the logic circuit is to have a failure location estimating step of estimating the fault location.
[0027]
The design language is a language describing the structure or operation of a logic circuit.
[0028]
Further, the conversion step divides the processing of the logic circuit into a plurality of transition states, creates a state transition table composed of items of a current state, a state transition condition, a next state, and an operation, and the state Set the process to read the input port, state variable or numeric value described in the transition table as an input node, set the operator process as an operation node, and write the output port, the state variable or the numeric value as an output node Setting, creating a control part for calculating the state by connecting the input node and the operation node as a data flow, giving the result of the state as a binary value of TRUE / FALSE, and the input node And a data part for calculating an output value by connecting the operation node as a data flow, and in the result of the state, given From within the set, and a step of setting a selected node for selectively outputting to an output node of the output value of the one corresponding to the TRUE state.
[0029]
Furthermore, the expected value calculation step calculates output values of the input node, the operation node, the selection node, and the output node each time the state transitions using the decision graph, and the node name and A node expected value acquisition step of creating a node table composed of sets of calculated values; and an output value extraction step of extracting an output value of the logic circuit from the node table.
[0030]
The expected node value acquisition step in the expected value calculation step reads the test pattern or the previous output pattern, sets the input node, sets the input node, sets all input values, and outputs Operation node extraction process for extracting operation nodes whose values are not set, operation node setting process for calculating output values based on input values for the extracted operation nodes, and setting of all operation nodes are completed If it is not completed, return to the operation node extraction step, if it is completed, the operation node determination step to go to the next step, the selection node setting step to calculate the output value of the selection node, To the output node setting step for calculating the output value of the output node, and to the input pattern reading step of the next state if there is a next state and the next state is not the first transition state Come, whether there is the next state, or if the first transition state next state, and a state determining step of the process ends.
[0031]
The output value extraction step in the expected value calculation processing step includes a step of extracting the output value of the output port in the final state for each test pattern from the node table created in the node expected value acquisition step. Extract the output value.
[0032]
Further, the failure location estimation step includes a failure mode selection step of estimating a failure location while separately assuming a control system failure and a data system failure, and a fail output port and a node corresponding to the fail estimation output port. Based on the fail vector, the node estimation process for estimating the fail propagation path by estimating the failure of each node in the input direction by estimating the output of each node and comparing the expected value, and the failure location estimation of the node information of this fail propagation path An estimation information registration step for registering as information, an end determination step for repeating these processes until all combinations that may propagate a failure to the output port are calculated, and a failure candidate for outputting the failure location estimation information as a list An output step.
[0033]
Furthermore, in the node estimation step in the failure location estimation step, when the output of each node is estimated, if the value of the node is multi-bit, only the value of the estimable bit is estimated.
[0034]
The logic circuit failure diagnosis method program of the present invention is a logic circuit failure diagnosis method for estimating a failure location of the logic circuit based on fail information obtained from a test result of the logic circuit. A fail extraction step of extracting a fail estimation circuit block having a fail output port and a fail estimation output port from the description information described in units of circuit blocks, the fail information and the fail propagation estimation information, and the fail estimation by the description information. Creates a state transition table with multiple states according to the processing order of the circuit block, and selects one output value from a set of input nodes, operator nodes composed of operators, and multiple input values based on the state transition table The selected nodes and output nodes to be connected are connected to the respective nodes, and the data flow Causing a computer to execute a conversion step for generating a decision graph for displaying and determining an operation for all conditions, an expected value calculation step for calculating an expected value of the logic circuit, and a failure location estimation step for estimating a failure location It is in.
[0035]
The design language is a language describing the structure or operation of a logic circuit.
[0036]
Further, the conversion step divides the processing of the logic circuit into a plurality of transition states, creates a state transition table composed of items of a current state, a state transition condition, a next state, and an operation, and the state Set the process to read the input port, state variable or numeric value described in the transition table as an input node, set the operator process as an operation node, and write the output port, the state variable or the numeric value as an output node Setting, creating a control part for calculating the state by connecting the input node and the operation node as a data flow, giving the result of the state as a binary value of TRUE / FALSE, and the input node And a data part for calculating an output value by connecting the operation node as a data flow, and in the result of the state, given And a program for the in the set to execute a step of setting a selected node for selectively outputting to an output node of the output value of the one corresponding to the TRUE state to the computer.
[0037]
Furthermore, the expected value calculation step calculates output values of the input node, the operation node, the selection node, and the output node each time the state transitions using the decision graph, and the node name and A program for causing a computer to execute an expected node value acquisition step for creating a node table composed of a set of calculated values and an output value extraction step for extracting an output value of the logic circuit from the node table.
[0038]
The expected node value acquisition step in the expected value calculation step reads the test pattern or the previous output pattern, sets the input node, sets the input node, sets all input values, and outputs Operation node extraction process for extracting operation nodes whose values are not set, operation node setting process for calculating output values based on input values for the extracted operation nodes, and setting of all operation nodes are completed If it is not completed, return to the operation node extraction step, if it is completed, the operation node determination step to go to the next step, the selection node setting step to calculate the output value of the selection node, To the output node setting step for calculating the output value of the output node, and to the input pattern reading step of the next state if there is a next state and the next state is not the first transition state Come, whether there is the next state, or if the first transition state next state, a program for executing a state determination process to terminate the process on the computer.
[0039]
Further, the output value extraction step in the expected value calculation processing step is a step of extracting the output value of the output port in the final state for each test pattern from the node table created in the node expected value acquisition step. A program for causing a computer to execute a process of extracting an output value.
[0040]
Furthermore, the failure location estimation step includes a failure mode selection step for estimating a failure location while separately assuming a control system failure and a data system failure, and a node corresponding to the fail output port and the failure estimation output port. As a starting point, the node estimation process for estimating the fail propagation path by estimating the fail propagation path of each node in the input direction by estimating the output of each node and comparing the expected value based on the fail vector, and the information on the node of this fail propagation path An estimation information registration step registered as estimation information, an end determination step that repeats these processes until all combinations that may propagate a failure to the output port are calculated, and a failure that outputs a list of the failure location estimation information A program for causing a computer to execute a candidate output step.
[0041]
In the node estimation step in the failure location estimation step, when estimating the output of each node, if the value of the node is multi-bit, the computer executes a step of estimating only the value of the estimable bit. It is a program for.
[0042]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described in detail with reference to the drawings.
[0043]
FIG. 1 is a block diagram showing a system configuration of a logic circuit fault diagnosis apparatus that estimates a fault location of a logic circuit based on fail information acquired from a test result of the logic circuit as an embodiment of the present invention. Referring to FIG. 1, an input device 1 such as a keyboard, a fail extraction device 2 that extracts a fail estimation circuit block, a conversion device 3 that converts a logic circuit into a decision graph, and an expected value calculation device that calculates an expected value of the logic circuit 4, a failure location estimation device 5 that estimates a failure location of a logic circuit, a storage device 6 that includes a hard disk, a memory, and the like and stores information, and an output device 7 such as a display device and a printing device. is there.
[0044]
The fail extraction device 2 extracts a fail estimation circuit block having a fail output port and a fail estimation output port based on description information, fail information, and fail propagation estimation information in which a logic circuit is functionally described in a circuit block unit in a design language.
[0045]
The conversion device 3 creates a state transition table having a plurality of states according to the processing order of the fail estimation circuit block based on the description information, and based on the created state transition table, an operation node composed of input nodes and operators, Based on the selection node and output node for selecting one output value from a set of a plurality of input values, and the connection of these nodes, a decision graph is created to display data flow and determine the operation for all conditions.
[0046]
The expected value calculation device 4 uses the decision graph to calculate the output values of the input node, the operation node, the selection node, and the output node each time the state transitions, and is configured with a set of a node name and a calculated value The expected value of the logic circuit is calculated by the expected node value acquisition means 41 that creates the node table and the output value extraction means 42 that extracts the output value of the logic circuit from the node table.
[0047]
The failure location estimation device 5 uses a failure mode selection means 51 for estimating a failure location while separately assuming a control system failure and a data system failure, and a failure output port and a node corresponding to the failure estimation output port as a starting point. Based on the vector, the node estimation means 52 for estimating the fail propagation path by performing the fail estimation of each node by the output estimation and the expected value comparison of each node in the input direction, and the node information of the fail propagation path as the fault location estimation information The estimated information registration means 53 to be registered, the end determination means 54 that repeats these processes until all combinations that may propagate a failure to the output port are calculated, and the failure candidate output that outputs the failure location estimation information as a list The fault location is estimated by means 55. Thereby, it is possible to estimate the failure location of the data system and the control system.
[0048]
A design language is a language that describes the structure or operation of a logic circuit. A fault location can be estimated for a logic circuit described in a hardware description language such as Verilog-HDL or VHDL, C language, or the like.
[0049]
Although not shown, the conversion device 3 divides the processing of the logic circuit into a plurality of transition states, creates a state transition table composed of the current state, state transition condition, next state and operation, and state transition Set the process to read the input port, state variable or value described in the table as the input node, set the operator process as the operation node, and set the output port, state variable or value write process as the output node. The control part for calculating the state is created by connecting the input node and the operation node as a data flow, the result of the state is given as a binary value of TRUE / FALSE, and the input node and the operation node are used as the data flow. Create a data part that calculates the output value by connecting, and in the result of the state described above, one corresponding to the TRUE state from the given set Select the force values, to create a decision graph and means for setting the selected node for selectively outputting the value to the output node. Thereby, a decision graph required for failure location estimation can be created.
[0050]
The expected node value acquisition means 41 in the expected value calculation device 4 reads the test pattern or the output pattern of the previous state, and sets the input node, and all input values are set. An operation node extracting unit (not shown) for extracting an operation node whose output value is not set, and an operation node setting unit (not shown) for calculating an output value based on the input value for the extracted operation node It is determined whether or not the setting of all operation nodes has been completed, and if not completed, the process returns to the operation node extraction unit, and if completed, the operation node determination unit (not shown) that goes to the next unit is selected. Selection node setting means (not shown) for calculating the output value of the node, output node setting means (not shown) for calculating the output value of the output node, and there is a next state and the next state is not the first transition state. If there is no next state or if the next state is the first transition state, the output value of each node is calculated by the state determination means (not shown) that terminates the process. Thus, it is possible to create a node table composed of pairs of node names and calculated values.
[0051]
The output value extraction means 42 in the expected value calculation device 4 is a means (not shown) for extracting the output value of the output port in the final state for each test pattern from the node table created by the node expected value acquisition means 41. The output value of the logic circuit is extracted. Thereby, an expected value required for failure diagnosis can be calculated.
[0052]
When estimating the output of each node, the node estimation means 52 in the failure location estimation apparatus 5 estimates only the value of an estimable bit if the value of the node is multi-bit. Thus, fail estimation can be performed without estimating all bit values.
[0053]
When the failure location estimation unit 54 of the failure location estimation device 5 determines that the failure location estimation between the control system failure and the data system failure has been completed and the fail propagation input port is extracted, the failure extraction device 2 described above A circuit block whose fail propagation input port is an output port is extracted, and a fault location is estimated for the circuit block.
[0054]
If there is no fail propagation input port, the failure location output means 55 outputs failure location estimation information to the output device 7.
[0055]
Next, the conversion apparatus 3 in this Embodiment is demonstrated, referring FIG.2, FIG.3 and FIG.4.
[0056]
FIG. 2 is a Verilog-HDL description of the counter circuit, and FIG. 3 is a state transition table of the counter circuit shown in FIG. FIG. 4 is a determination graph of the counter circuit.
[0057]
The counter circuit of the present embodiment is a circuit that counts up when a change in the clock signal clk is detected and outputs a count to the signal out.
[0058]
First, a state transition table is created according to the processing order of Verilog-HDL description.
[0059]
As the first transition state, the event block determination process for the always block is assigned to the state ST0. Here, the change of the signal clk is expressed as @clk. Next, the process described in the always block is assigned to the state ST1.
[0060]
Further, in the state ST1, a process of assigning the evaluation of the expression on the right side in the non-blocking assignment expression (out <= 4′b0000, out <= out + 1′b1) to the temporary register: _reg is assigned.
[0061]
Next, a process of assigning the value held in the temporary register: _reg to the signal: out on the left side of the non-blocking assignment expression is assigned to the state ST2.
[0062]
In the state ST0, when the process is completed, the process proceeds to the state ST1 as the next state. In the state ST1, when the process is completed, the process proceeds to the state ST2 as the next state. In the state ST2, when the process is completed, the process proceeds to the state ST0 as the next state.
[0063]
Next, creation of a decision graph with reference to the state transition table will be described.
[0064]
The input port clk is set as an input node. The state variable STATE and state numbers ST0, ST1, and ST2 are set as input nodes. Also, variables and constants clk, out, and “1111” in the conditional expression are set as input nodes.
[0065]
On the right side of the assignment expression, variables and constants “0000”, out, “1”, and _reg used in the evaluation of the expression are set as input nodes. An event node “_event” for judging a change in signal is set as an input node.
[0066]
The output port out and the state variable STATE are set as output nodes. _Reg and out, which are variables assigned on the left side of the assignment expression, are set as output nodes.
[0067]
As operators used in the state transition table, an equal sign (=), addition (+), negation (!) And a logical operator and (&) are set as operation nodes.
[0068]
State_a, _reg_a, and out_a corresponding to the output nodes out, state, and _reg are set as selection nodes.
[0069]
Next, the link of each node will be described.
[0070]
The input node STATE that is the state variable and the input nodes ST0, ST1, and ST2 that are the state numbers are linked by the operation node “=”.
[0071]
The output node STATE is linked as the output destination of the selected node STATE_a. The selection node state_a is linked to the input nodes ST0, ST1, and ST2 that are state numbers as output values.
[0072]
In the state ST0, since the next state when the condition temp is true is the state ST1, as the state result corresponding to the output value ST1 of the selected node STATE_a, “equals linked to the input node ST0“ = ”” and “clk” And the equal sign “=” linked to _event is linked to the operation node “&”, and the selected node STATE_a is linked as the output destination of the operation node “&”.
[0073]
Since the next state after the state ST1 is the state ST2, the equal sign “=” linked to the input node ST1 is linked to the selected node STATE_a as a result of the state corresponding to the output value ST2 of the selected node STATE_a.
[0074]
Since the next state after the state ST2 is the state ST0, the equal sign “=” linked to the input node ST2 is linked to the selected node STATE_a as a state result corresponding to the output value ST0 of the selected node STATE_a.
[0075]
The selection node_reg_a is linked to the output node_reg as an output destination. Here, as a state result corresponding to one of the output values “0000”, “operation node“ = ”linked to input node ST1” and “operation node linked to input node out and“ 1111 ”“ = "" Is linked with the operation node "&", and the operation node "&" is linked with the selection node_reg_a.
[0076]
Further, the input node out and “1” are linked by the operation node “+”, and the operation node “+” is linked to _reg_a as the other output value.
[0077]
As a state result corresponding to the output out + “1”, “the operation node“ = ”” that links the input node “out” and “1111” is linked to the operation node “!” (Negative), and the operation nodes “!” And “input” The operation node “=” linked to the node ST1 is linked by the operation node “&”, and the operation node “&” is linked to the selected node_reg_a.
[0078]
The input node_reg is linked with the selection node out_a as an output value. The selection node out_a is linked to the output node out as an output destination. Here, as a result of the state corresponding to the output value _reg, the equal sign “=” linked to the input node ST2 is linked to the selected node out_a.
[0079]
Thus, the decision graph shown in FIG. 4 is created.
[0080]
Next, the expected node value acquisition unit 41 in the present embodiment will be described with reference to FIGS. 4, 5, and 6.
[0081]
FIG. 5 is a flowchart showing a processing order in the node expected value acquisition means 41, and FIG. 6 is a node table of the decision graph shown in FIG.
[0082]
It is assumed that “0110” is set to out and “p” (rising) is input to clk by the test pattern.
[0083]
First, in the input pattern reading means, the input node I3 is set to “0110” from the test pattern, and “p” is set to the input node I1. Further, since this circuit starts processing from the state ST0, “ST0” is set to the input node I2 (processing step S11).
[0084]
In the operation node extracting means, X1, X2, X3, X4, X5 and X7 are extracted as operation nodes for which all input values are set and output values are not set (processing step S12).
[0085]
The operation node setting means calculates the output value of each operation node extracted by the operation node extraction means (processing step S13). Since the input nodes of X1 are clk and _event, X1 is set to “1” if the output value of clk has changed, and “0” if it has not changed.
[0086]
Here, since the output value of clk is “p” (rising) and the value is changing, X1 is set to “1”. Since STATE == “ST0”, X2 is set to “1”, X3 is set to “0”, and X4 is set to “0”. Since out == “0110”, X5 is set to “0” and X7 is set to “0111”.
[0087]
In the operation node determination means, it is determined whether or not all the operation nodes have been set. Since the settings of the operation nodes X6, X8, X9, and X10 are not completed, the process returns to the operation node extraction unit (processing step S14).
[0088]
In the operation node extracting means, X6, X8, and X9 are extracted as operation nodes for which all input values are set and output values are not set (processing step S12).
[0089]
In the operation node setting means, since X5 == “0”, X6 is set to “1”. Since X1 == “1” and X2 == “1”, X8 is set to “1”. Since X3 == “0” and X5 == “0”, X9 is set to “0” (processing step S13).
[0090]
In the operation node determination means, it is determined whether or not all the operation nodes have been set. Since the setting of the operation node X10 has not been completed, the process returns to the operation node extraction unit (processing step S14).
[0091]
In the operation node extracting means, X10 is extracted as an operation node in which all input values are set and the output value is not set (processing step S12).
[0092]
In the operation node setting means, since X6 == “1” and X3 == “0”, X10 is set to “0” (processing step S13).
[0093]
In the operation node determination means, it is determined whether or not all the operation nodes have been set. Since all the operation nodes have been set, the process proceeds to the next processing means (processing step S14).
[0094]
The selection node setting means sets selection nodes A1, A2 and A3 (processing step S15). In the selection node A1, since the 0th condition X4 == “0”, the first condition X8 == “1”, and the second condition X3 == “0”, the first condition whose value is “1” A1 is set to “1” corresponding to the condition X8.
[0095]
In the selected node A2, since the 0th condition X10 == “0”, the first condition X9 == “0”, and there is no condition whose value is “1”, this means that no value is output to O2. , A2 is set to “−1”.
[0096]
In the selection node A3, since the 0th condition X4 == “0” and there is no condition whose value is “1”, A3 is set to “−1”.
[0097]
The output node setting means sets the output nodes O1, O2, and O3 (processing step S16). In the output node O1, since the selection node A1 == “1”, “ST1” which is the first input value of the selection node A1 is set. In the output node O2, no value is set because the value is not output when the selection node A2 = “− 1”. In the output node O3, no value is set because the value is not output when the selection node A3 == “− 1”.
[0098]
With the above processing, the node table of the first state no1 is created.
[0099]
Next, the state determination means goes to the input pattern reading means because there is a next state and the next state is not the first transition state ST0 (processing step S17).
[0100]
Next, in the input pattern reading means in the next state, since the output node O1 == “ST1” in the state no1, the input node I2 corresponding to the output node O1 is set to “ST1” in the state no2 (processing step) S11).
[0101]
Since the output node O2 in the state no1 is not set, the corresponding input node I4 is not set in the state no2. Since the output node O3 in the state no1 is not set, in the state no2, the corresponding input node I3 does not set a new value, and sets the value “0110” of the input node I3 in the state no1.
[0102]
That is, in state no2, “0110” is set to the input node I3. In the state no2, the input node I1 sets the value “p” in the state no1 because there is no corresponding output node.
[0103]
By repeating the operation node extraction means (processing step S12), the operation node setting means (processing step S13), and the operation node determination means (processing step S14) until the setting of all the operation nodes is completed,
X1 == “1”
X2 == “0”
X3 == “1”
X4 == “0”
x5 == “0”
X6 == “1”
X7 == “0111”
X8 == “0”
X9 == “0”
X10 == “1”
Is set.
[0104]
The selection node setting means sets selection nodes A1, A2 and A3 (processing step S15). In the selection node A1,
0th condition X4 == “0”
First condition X8 == “0”
Second condition X3 == “1”
Therefore, A1 is set to “2” corresponding to the second condition X3 whose value is “1”.
[0105]
In the selection node A2,
0th condition X10 == “1”
First condition X9 == “0”
And A2 is set to “0” corresponding to the 0th condition X10 whose value is “1”.
[0106]
In selection node A3,
0th condition X4 == “0”
Since there is no condition that the value is “1”, A3 is set to “−1”.
[0107]
The output node setting means sets the output nodes O1, O2, and O3 (processing step S16).
[0108]
In the output node O1, since the selection node A1 == “2”, the second input value “ST2” of the selection node A1 is set.
[0109]
In the output node O2, since the selection node A2 == “0”, the X7 value “0111” which is the 0th input value of the selection node A2 is set.
[0110]
In the output node O3, no value is set because the value is not output when the selection node A3 == “− 1”.
[0111]
With the above processing, a node table in the state no2 is created.
[0112]
Next, the state determination means goes to the input pattern reading means because there is a next state and the next state is not the first transition state ST0 (processing step S17).
[0113]
Next, in the input pattern reading means in the next state, since the output node O1 = “ST2” in the state no2, the input node I2 corresponding to the output node O1 is set to “ST2” in the state no3.
[0114]
Since the output node O2 == “0111” in the state no2, the corresponding input node I4 is set to “0111” in the state no3. Since the output node O3 in the state no2 is not set, the corresponding input node I3 does not set a new value in the state no3, and sets the value “0110” of the input node I3 in the state no2.
[0115]
That is, in the state no3, “0110” is set to the input node I3. In the state no3, the input node I1 sets the value “p” in the previous state no2 because there is no corresponding output node.
[0116]
By repeating the operation node extraction means (processing step S12), the operation node setting means (processing step S13), and the operation node determination means (processing step S14) until the setting of all the operation nodes is completed,
X1 == “1”
X2 == “0”
X3 == “0”
X4 == “1”
x5 == “0”
X6 == “1”
X7 == “0111”
X8 == “0”
X9 == “0”
X10 == “0”
Is set.
[0117]
The selection node setting means sets selection nodes A1, A2 and A3 (processing step S15).
[0118]
In the selection node A1,
0th condition X4 == “1”
First condition X8 == “0”
Second condition X3 == “0”
Therefore, A1 is set to “0” corresponding to the 0th condition X4 whose value is “1”.
[0119]
In the selection node A2,
0th condition X10 == “0”
First condition X9 == “0”
Since there is no condition that the value is “1”, A2 is set to “−1”.
[0120]
In the selection node A3, A2 is set to “0” corresponding to the 0th condition X4 where the 0th condition X4 == “1” and the value is “1”.
[0121]
The output node setting means sets the output nodes O1, O2, and O3 (processing step S16).
[0122]
In the output node O1, since the selection node A1 == “0”, the “0” input value “ST0” of the selection node A1 is set.
[0123]
In the output node O2, since the value is not output when the selection node A2 = "-1", the value "0111" in the previous state no2 is set.
[0124]
In the output node O3, since the selection node A3 == “0”, the value “0111” of I4 which is the 0th input value of the selection node A3 is set.
[0125]
With the above processing, a node table in the state no3 is created.
[0126]
Next, since the next state is the first transition state ST0, the state determination means ends the processing (processing step S17).
[0127]
Through the above processing, a node table corresponding to one test pattern is created. Here, when a plurality of test patterns are used, a node table is created for each test pattern by repeating the above processing.
[0128]
Next, the output value extraction means 42 in the present embodiment will be described with reference to FIGS.
[0129]
Since the node of the decision graph corresponding to the output port out of the counter circuit is the output node O3, in the test pattern described as an example in the present embodiment, the value “0111” of the output node O3 in the final state no3 is output. Extracted as output value of port out.
[0130]
Here, when using a plurality of test patterns, the output value of the logic circuit can be extracted by extracting the output value of the output port in the final state for each test pattern.
[0131]
Next, the failure diagnosis apparatus in the present embodiment will be described with reference to FIG. 4 and FIGS.
[0132]
FIG. 7 is an example of a test result of the counter circuit, and FIG. 8 is a node table of a decision graph obtained by the expected value calculation device. 9 and 10 show node estimation results obtained by the node estimation means for a data system failure, and FIGS. 11 and 12 show node estimations obtained by the node estimation means for a control system failure. It is a result.
[0133]
As shown in FIG. 7, in the test pattern V1, since the output value of out is “1000” and the expected value is “1000”, the test is passed. In the test pattern V2 that is continuous with the test pattern V1, the output value of out is “0000” and the expected value is “1001”.
[0134]
The node table in the test pattern V2 shown in FIG. 8 is created by the node expected value acquisition unit of the expected value calculation apparatus for the test patterns V1 and V2.
[0135]
First, the failure search of the data system is selected by the failure mode selection means.
[0136]
From the test pattern, clk is “p”, and clk does not exist in the read node. Therefore, in each transition state, the node I1 is set to “p”.
[0137]
Here, each node of I2, “ST0”, “ST1”, “ST2”, X2, X3, X4, X6, X8, X9, X10, A1, A2, A3, O1 converts the design language into a decision graph. Therefore, it is not extracted as a failure candidate.
[0138]
The node estimation means 52 first estimates the control system on the assumption that no fault exists in the control system. The output value of each node is determined from the normal output nodes O1 and O2.
[0139]
Since the transition state is “0” when the test pattern V2 ends, O1 is set to “ST0”.
[0140]
From the output value of O1, the output value of A1 becomes “0”, X4 is “1”, I2 is “ST2”, X3 is “0”, and X8 is “0”. X1 or X2 is estimated to be “0” from the value of X8.
[0141]
Assume that X1 is “0”. Since I1 is “p” and the signal is changing, X1 is “1”, but a contradiction occurs. Therefore, it is assumed that X1 == “1” and X2 == “0”. In this case, no contradiction occurs.
[0142]
A2 takes one of the values “−1”, “0”, and “1”. Assuming that A2 == “1”, X9 == “1” is estimated, but X3 == “0”, which is contradictory.
[0143]
Assuming that A2 == “0”, X10 == “1” is estimated, but X3 == “0”, which is contradictory.
[0144]
Assuming A2 == “− 1”, X9 == “0”, X10 == “0”, X5 == “x” (may be 0 or 1), X6 == “x”, I3 == “ xxxx ”, X7 ==“ xxxx ”, O2 ==“ xxxx ”, and no contradiction occurs.
[0145]
Next, each node is estimated from the fail output port. From the test result, fail output port O3 == “0000”. Since X4 == “1”, A3 == “0” is estimated, and I4 == “0000” is estimated. O3 and I4 are registered as failure location estimation information.
[0146]
Thus, the node table in the state no1 is created.
[0147]
Since I2 == “ST2” in the state no1, O1 is set to “ST2”, and the state no2 is estimated. Since O1 == “ST2”, A1 == “2”, X3 == “1”, I2 == “ST1”, X4 == “0”, and X8 == “0” are determined.
[0148]
In the same manner as in the state no1, X1 == “1” and X2 == “0” are determined. A3 == “− 1”, O3 == “xxxx”, and I4 == “xxxx” are determined.
[0149]
Next, each node is estimated from the fail output port. From the value of I4 in the state no1, fail estimation output port O2 == “0000”. A2 takes one of the values “−1”, “0”, and “1”.
[0150]
Assuming that A2 == “− 1”, since X9 == “0”, X5 == “0”. Since X10 == “0”, X6 == “0” and X5 == “1”. A2 is not "-1" because X5 contradicts.
[0151]
Assuming that A2 == “0”, X9 == “0”, X5 == “0”, X10 == “1”, and X6 == “1”. Accordingly, from O2 == “0000” and A2 == “0”, X7 == “0000” and I3 == “1111”. I3 == “1111” to X5 == “0” are contradictory.
[0152]
Since there is no input pattern that satisfies the output pattern, O2, X7, and I3 are registered as failure location estimation information. The node table shown in FIG. 9 is obtained.
[0153]
On the other hand, assuming that A2 == “1”, X9 == “1”, X5 == “1”, I3 == “1111”, X10 == “0”, and X6 == “0”. O2 is registered as failure location estimation information.
[0154]
Thus, the node table in the state no2 is created.
[0155]
Since I2 == “ST1” in the state no2, O1 is set to “ST1”, and the state no3 is estimated. Since O1 == “ST1”, X8 == “1”, X1 == “1”, X2 == “1”, X3 == “0”, X4 == “0”, I2 == “ST0” "Is decided.
[0156]
A3 == “− 1”, O3 == “xxxx”, and I4 == “xxxx” are determined. X9 == “0”, X10 == “0”, A2 == “− 1”, and O2 == “xxxx” are determined. X5 = "x" and X6 == "x" are determined. Since the value of I3 is not updated in states no2 and no3, I3 is registered as failure location estimation information.
[0157]
Thus, the node table in the state no3 is created. The node table shown in FIG. 10 is obtained.
[0158]
Since the failure location estimation of the data system is completed by the termination determination means, the failure candidate output means outputs a list of O3 and I4 in the transition state ST2, O2, X7 and I3 in the transition state ST1, and I3 in the transition state ST0.
[0159]
Next, failure estimation of the control system is selected by the failure mode selection means, and failure estimation of the control system is performed by the node estimation means 52.
[0160]
From the test pattern, clk is “p”, and clk does not exist in the read node. Therefore, in each transition state, the node I1 is set to “p”.
[0161]
Here, each node of I2, “ST0”, “ST1”, “ST2”, X2, X3, X4, X6, X8, X9, X10, A1, A2, A3, O1 converts the design language into a decision graph. Therefore, it is not extracted as a failure candidate.
[0162]
First, the data system is estimated on the assumption that no failure exists in the data system. The output value of each node is determined from the normal output nodes O1 and O2. Since the transition state is “0” when the test pattern V2 ends, O1 is set to “ST0”.
[0163]
From the output value of O1, the output value of A1 becomes “0”, X4 is “1”, I2 is “ST2”, X3 is “0”, and X8 is “0”. X1 or X2 is estimated to be “0” from the value of X8. Assume that X1 is “0”.
[0164]
Since I1 is “p” and the signal is changing, X1 is “1”, but a contradiction occurs. Therefore, it is assumed that X1 == “1” and X2 == “0”. In this case, no contradiction occurs.
[0165]
A2 takes one of the values “−1”, “0”, and “1”. Assuming that A2 == “1”, X9 == “1” is estimated, but X3 == “0”, which is contradictory.
[0166]
Assuming that A2 == “0”, X10 == “1” is estimated, but X3 == “0”, which is contradictory.
[0167]
Assuming A2 == “− 1”, X9 == “0”, X10 == “0”, X5 == “x”, X6 == “x”, I3 == “xxxx”, X7 == “ xxxx ″, O2 == “xxxx”, and no contradiction occurs.
[0168]
Next, each node is estimated from the fail output port. From the test result, fail output port O3 == “0000”. Since X4 == “1” and X4 and A3 are not fault candidates, A3 == “0”, and I4 == “0000” is estimated. O3 and I4 are registered as failure location estimation information.
[0169]
Thus, the node table in the state no1 is created.
[0170]
Since I2 == “ST2” in the state no1, O1 is set to “ST2”, and the state no2 is estimated. Since O1 == “ST2”, A1 == “2”, X3 == “1”, I2 == “ST1”, X4 == “0”, and X8 == “0” are determined.
[0171]
In the same manner as in the state no1, X1 == “1” and X2 == “0” are determined. A3 == “− 1”, O3 == “xxxx”, and I4 == “xxxx” are determined.
[0172]
Next, each node is estimated from the fail output port. From the value of I4 in the state no1, fail estimation output port O2 == “0000”. A2 takes one of the values “−1”, “0”, and “1”.
[0173]
Assuming that A2 == “− 1”, the nodes of the control system are X9 == “0” and X10 == “0”. When the route is traced back from X9 == “0”, X5 == “0”.
[0174]
When estimated in the output direction of another route from X5, X6 == “1”, X10 == “1”, and X9 == “0” and X10 == “0” are not satisfied at the same time.
[0175]
On the other hand, when the route is traced back from X10 == “0”, X6 == “0” and X5 == “1”. When estimated in the output direction of another route from X5, X9 == “1”, and X9 == “0” and X10 == “0” are not satisfied at the same time. That is, A2 == “− 1” is not satisfied.
[0176]
Assuming that A2 == “0”, the nodes of the data system are X7 == “0000” and I3 == “1111”.
[0177]
The nodes of the control system are X9 == “0”, X10 == “1”, X6 == “1”, and X5 == “0”. Since I3 == “1111” and X5 == “0” contradict each other and there is no input pattern that satisfies the output pattern, O2 and X5 are registered as failure location estimation information. The node table shown in FIG. 11 is obtained.
[0178]
On the other hand, assuming that A2 == “1”, the input of O2 is the node “0000”, and the data system nodes are established without contradiction.
[0179]
The nodes of the control system are X9 == “1”, X10 == “0”, X6 == “0”, X5 == “1”, and I3 == “1111”. O2 and I3 are registered as failure location estimation information.
[0180]
Thus, the node table in the state no2 is created.
[0181]
Since I2 == “ST1” in the state no2, O1 is set to “ST1”, and the state no3 is estimated.
[0182]
Since O1 == “ST1”, X8 == “1”, X1 == “1”, X2 == “1”, X3 == “0”, X4 == “0”, I2 == “ST0” "Is decided. A3 == “− 1”, O3 == “xxxx”, and I4 == “xxxx” are determined.
[0183]
X9 == “0”, X10 == “0”, A2 == “− 1”, and O2 == “xxxx” are determined. X5 = "x" and X6 == "x" are determined.
[0184]
Since the value of I3 is not updated in states no2 and no3, I3 is registered as failure location estimation information.
[0185]
Thus, the node table in the state no3 is created. The node table shown in FIG. 12 is obtained.
[0186]
Since the failure location estimation of the control system is completed by the termination determination means, the failure candidate output means outputs O3 and I4 in the transition state ST2, O2, I3 and X5 in the transition state ST1, and I3 in the transition state ST0 as a list. .
[0187]
The above processing is performed for each test pattern, the failure location is estimated for each test pattern, and the failure location estimation for the counter circuit is completed.
[0188]
Next, the fail extraction device 2 extracts the fail estimation circuit block having the fail estimation output port “out” based on the fail propagation estimation information of the counter circuit, and estimates the failure location. If there is no estimation circuit block having the fail estimation output port “out”, all the processes are terminated.
[0189]
In addition, when estimating the output of each node, the node estimation means in the failure location estimation apparatus 5 may estimate only the value of an estimable bit if the value of the node is multi-bit.
[0190]
FIG. 13 is a flowchart showing the processing procedure of the logic circuit failure diagnosis method of the present invention.
[0191]
Referring to FIG. 13, in the failure diagnosis method for a logic circuit, as processing step 1, fail output port and fail estimation are performed based on description information, fail information and fail propagation estimation information in which the logic circuit is described in units of circuit blocks in a design language. A fail extraction step S21 for extracting a fail estimation circuit block having an output port;
[0192]
Also, as processing step 2, a state transition table having a plurality of states is created from the description information according to the processing order of the fail estimation circuit block, and an operation node composed of input nodes and operators based on the state transition table, There is a conversion step S22 for creating a decision graph for displaying data flow and determining the operation for all conditions by selecting nodes for selecting one output value from a set of a plurality of input values and the connection between each output node and each node.
[0193]
Further, as processing step 3, an expected value calculation step S23 for calculating an expected value using a decision graph is provided.
[0194]
The expected value calculation step S23 includes the following two steps (not shown). That is, a node expected value acquisition step of calculating an output value of an input node, an operation node, a selection node, and an output node each time a state transitions and creating a node table composed of a set of a node name and a calculated value; And an output value extracting step of extracting an output value of the logic circuit from the node table.
[0195]
Furthermore, as processing step 4, there is a failure location estimation step S24 for estimating a failure location. The failure location estimation step S24 includes a failure mode selection step (not shown) for estimating a failure location while separately assuming a data system failure and a control system failure, a fail output port, and a node corresponding to the fail estimation output port. As a starting point, a node estimation step (not shown) for estimating a fail propagation path by performing fail estimation of each node in the input direction by output estimation and expected value comparison of each node based on the fail vector, and a node of this fail propagation path End determination that repeats these processes until calculation of all combinations that may cause a failure to propagate to the output port, and step S25 including an estimation information registration step (not shown) for registering information as failure location estimation information Step S26 and a failure candidate output step S27 for outputting the above-described failure location estimation information as a list.
[0196]
Although not shown, the conversion step S22 includes the following steps. That is, as the processing step 1, the process of the logic circuit is divided into a plurality of transition states, and a step of creating a state transition table composed of the current state, the state transition condition, the next state and the operation is included.
[0197]
As processing step 2, a process for reading an input port, state variable or value described in the state transition table is set as an input node, an operator process is set as an operation node, and an output port, state variable or value is written. A processing part is set as an output node, a control part for calculating a state is created by connecting an input node and an operation node as a data flow, a result of the state is given as a binary value of TRUE / FALSE, and an input node A data part for calculating an output value is created by connecting the operation node as a data flow, and in the result of the state, one output value corresponding to a TRUE state is selected from a given set, A step of setting a selection node for selectively outputting the value to the output node.
[0198]
In the conversion step S22, a decision graph is created by these processing steps 1 and 2.
[0199]
In addition, the node expected value acquisition step in the expected value calculation step S23 includes the following steps although not shown. That is, as processing step 1, there is an input pattern reading step for reading a test pattern or an output pattern in the previous state and setting an input node.
[0200]
The processing step 2 includes an operation node extraction step for extracting operation nodes in which all input values are set and output values are not set.
[0201]
The processing step 3 includes an operation node setting step for calculating an output value based on the input value for the extracted operation node.
[0202]
As processing step 4, it is determined whether or not the setting of all operation nodes has been completed, and if not completed, the process returns to the operation node extraction process, and if completed, the operation node determination process goes to the next process.
[0203]
The processing step 5 includes a selection node setting step for calculating the output value of the selected node, and the processing step 6 includes an output node setting step for calculating the output value of the output node.
[0204]
As processing step 7, if there is a next state and the next state is not the first transition state, the process proceeds to the input pattern reading process of the next state, and if there is no next state or the next state is the first transition state, the processing is performed. It has the state determination process to complete | finish.
[0205]
In the node expected value acquisition step, the output values of each node are calculated by the above-described processing steps 1 to 7, and a node table composed of pairs of node names and calculated values is created.
[0206]
The output value extracting step in the expected value calculating step S23 is a step of extracting the output value of the logic circuit in the final state for each test pattern from the node table created in the node expected value acquiring step. Extract.
[0207]
Further, the node estimation step in the failure location estimation step S24 estimates only the value of an estimable bit when the output of each node is estimated and the node value is multi-bit.
[0208]
In the present invention, each processing of the processing procedures S21 to S24 is realized by executing a program by a computer that constitutes a failure diagnosis device for a logic circuit. The computer reads the program from a computer-readable recording medium (for example, a magnetic disk, an optical disk, a semiconductor memory, or any other recording medium) that records the program, and loads the program into a main circuit memory fault diagnosis device. The present invention can be implemented by executing the above. Alternatively, the program may be downloaded from a server or the like provided with a recording medium recording the program to the computer of the logic circuit failure diagnosis apparatus via a communication line. By using a recording medium in this way, program management becomes easy.
[0209]
In the present invention, as a design language, not only Verilog-HDL described in the present embodiment, but also a hardware description language such as VHDL, a language describing the structure or operation of a logic circuit, such as C language, may be used.
[0210]
【The invention's effect】
As described above, the logic circuit failure diagnosis apparatus, the failure diagnosis method, and the program thereof according to the present invention extract the fail estimation circuit block from the design language describing the structure or operation of the logic circuit, and extract the fail estimation circuit. By creating a decision graph for each block and estimating the failure propagation path using the decision graph while separately assuming the data system failure and the control system failure, the failure location of the data system and the control system at the functional level Therefore, for a logic circuit with a large scale and multi-layered wiring, there is an effect that it contributes to the improvement of the efficiency of calculation of expected values and estimation of failure locations.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a system configuration of a failure diagnosis apparatus for a logic circuit according to the present invention.
FIG. 2 is a Verilog-HDL description example of a logic circuit.
FIG. 3 is a state transition table in one embodiment of the present invention.
FIG. 4 is a decision graph according to an embodiment of the present invention.
FIG. 5 is a flowchart showing a processing order in an expected node value acquisition unit of the present invention.
FIG. 6 is a node table according to an embodiment of the present invention.
FIG. 7 is a test result in one embodiment of the present invention.
FIG. 8 is another example node table according to the embodiment of the present invention;
FIG. 9 shows a node estimation result when a data system failure is assumed in the embodiment of the present invention.
FIG. 10 is a node estimation result in the case of assuming another example of a data system failure in the embodiment of the present invention.
FIG. 11 is a node estimation result when a control system failure is assumed in the embodiment of the present invention.
FIG. 12 is a node estimation result when another example control system failure is assumed in the embodiment of the present invention;
FIG. 13 is a flowchart showing a processing procedure of a logic circuit failure diagnosis method of the present invention.
FIG. 14 is a flowchart showing an outline process of a conventional failure location estimation method for a logic circuit.
[Explanation of symbols]
1 Input device
2 Fail extraction device
3 Conversion device
4 Expected value calculation device
5 Failure location estimation device
6 Storage device
7 Output device
41 Node expected value acquisition means
42 Output value extraction means
51 Failure mode selection means
52 Node estimation means
53 Estimated information registration means
54 End determination means
55 Failure candidate output means

Claims (25)

Based on the state transition table created for each fail estimation circuit block having a fail estimation output port extracted from the description information in which the structure or operation of the logic circuit is described in units of circuit blocks in the design language, the input node, An operation node composed of operators, a selection node that selects one output value from a set of a plurality of input values, and an output node are connected to each of these nodes. Create a decision graph that determines the operation and perform failure propagation path estimation using the decision graph while separately assuming a data system failure and a control system failure. A logic circuit fault diagnosis device having a function of estimating a location. In a failure diagnosis device for a logic circuit that estimates a failure location of the logic circuit based on fail information obtained from a test result of the logic circuit, description information in which the input device and the logic circuit are described in units of circuit blocks in a design language A fail extraction device that extracts a fail estimation circuit block having a fail output port and a fail estimation output port based on the fail information and the fail propagation estimation information, and a plurality of processing steps of the fail estimation circuit block based on the description information. A state transition table having a state is created, and based on the state transition table, an input node, an operation node composed of operators, a selection node that selects one output value from a set of a plurality of input values, and an output node; Connect the nodes and display the data flow to determine the operation for all conditions A conversion device for creating a decision graph, an expected value calculation device for calculating an expected value of the logic circuit, a failure location estimation device for estimating a failure location of the logic circuit, and a memory for storing information on each of the devices A logic circuit fault diagnosis device comprising: a device; and an output device that displays output data of the fault location estimation device. 3. The logic circuit fault diagnosis apparatus according to claim 2, wherein the design language is a language describing a structure or an operation of the logic circuit. The conversion device divides the processing of the logic circuit into a plurality of transition states and creates a state transition table including items of a current state, a state transition condition, a next state, and an operation, and the state transition table The process for reading the input port, state variable, or numeric value described in is set as an input node, the operator process is set as the operation node, and the process for writing the output port, the state variable, or the numeric value is set as the output node. A control part for calculating a state by connecting the input node and the operation node as a data flow, giving a result of the state as a binary value of TRUE / FALSE, and the input node and the operation Create a data part that calculates the output value by connecting nodes as the data flow, given the result of the state, given Trouble diagnosis device for the logic circuit according to claim 2, further comprising a means for setting the selected nodes to select the output from the set to the output node of the output value of the one corresponding to the state of the TRUE. The expected value calculation device calculates an output value of the input node, the operation node, the selection node, and the output node each time a state transitions based on the decision graph, and sets a combination of a node name and a calculated value. 3. The logic circuit fault diagnosis device according to claim 2, further comprising: an expected node value acquisition unit that creates a node table configured by: and an output value extraction unit that extracts an output value of the logic circuit from the node table. The expected node value acquisition means in the expected value calculation device reads the test pattern or the previous output pattern, sets the input node, input pattern reading means for setting the input node, all input values are set, and the output value is Operation node extraction means for extracting unset operation nodes, operation node setting means for calculating output values based on input values for the extracted operation nodes, and whether all operation nodes have been set If not completed, the process returns to the operation node extraction means, and if completed, the operation node determination means proceeds to the next means, the selection node setting means for calculating the output value of the selected node, and the output Output node setting means for calculating the output value of the node, and if there is a next state and the next state is not the first transition state, go to the input pattern reading means of the next state, Or the absence, or if the first transition state next state, the trouble diagnosis device for the logic circuit of claim 5, further comprising a state determining means to end the process. The output value extraction means in the expected value calculation device is configured to extract the output value of the logic circuit from the node table created by the node expected value acquisition means by means of extracting the output value of the output port in the final state for each test pattern. 6. The logic circuit fault diagnosis apparatus according to claim 5, which has a function of extracting. The failure location estimating device is based on failure mode selection means for estimating a failure location while separately assuming a control system failure and a data system failure, and a node corresponding to the fail output port and the fail estimation output port. Node estimation means for estimating fail propagation path by performing fail estimation of each node in the input direction by output estimation and expected value comparison of each node based on the fail vector, and information on the node of this fail propagation path as failure location estimation information The estimated information registering means to be registered, the end judging means for repeating these processes until all combinations that may propagate a failure to the output port are calculated, and the failure candidate output means for outputting the failure location estimated information as a list The logic circuit fault diagnosis device according to claim 2, comprising: 3. The node estimation means in the fault location estimation device has a function of estimating only the value of an estimable bit when the value of the node is multi-bit when estimating the output of each node. Logic circuit fault diagnosis device. In a logic circuit failure diagnosis method for estimating a failure location of the logic circuit based on fail information acquired from a test result of the logic circuit, description information in which the logic circuit is functionally described in a circuit block unit in a design language, the fail information And a fail extraction step for extracting a fail estimation circuit block having a fail output port and a fail estimation output port based on the fail propagation estimation information, and a state transition having a plurality of states according to the processing order of the fail estimation circuit block based on the description information Create a table, based on the state transition table, an input node, an operation node composed of operators, a selection node that selects one output value from a set of a plurality of input values, and an output node and the connection of each node And a decision graph that determines the behavior for all conditions by displaying the data flow. A conversion step of creating, the expected value calculation step of calculating an expected value of the logic circuit, a fault diagnosis method of a logic circuit and having a failure location estimating step of estimating the fault location. 11. The logic circuit failure diagnosis method according to claim 10, wherein the design language is a language describing a structure or an operation of the logic circuit. The converting step divides the processing of the logic circuit into a plurality of transition states, and creates a state transition table including items of a current state, a state transition condition, a next state, and an operation;
Set the process to read the input port, state variable or numeric value described in the state transition table as an input node, set the operator process as an operation node, and output the process to write the output port, the state variable or the numeric value A control part that calculates a state by setting the node as a node and connecting the input node and the operation node as a data flow, giving the result of the state as a binary value of TRUE / FALSE, and A data part for calculating an output value is created by connecting an input node and the operation node as a data flow, and in the result of the state, one output value corresponding to the TRUE state is obtained from a given set. 11. A logic circuit fault diagnosis according to claim 10, further comprising the step of setting a selection node for selective output to the output node. Method. The expected value calculation step calculates the output value of the input node, the operation node, the selection node, and the output node each time the state transitions using the decision graph, and calculates the node name and the calculated value. The logic circuit fault diagnosis method according to claim 10, further comprising: an expected node value acquisition step of creating a node table composed of sets; and an output value extraction step of extracting an output value of the logic circuit from the node table. The expected node value acquisition step in the expected value calculation step reads the test pattern or the previous output pattern, sets the input node, sets the input node, sets all input values, and outputs the output value. An operation node extraction process for extracting an unset operation node;
An operation node setting step for calculating an output value based on an input value for the extracted operation node;
It is determined whether or not all the operation nodes have been set, and if not completed, the process returns to the operation node extraction process, and if completed, the operation node determination process goes to the next process;
A selection node setting step for calculating an output value of the selection node; an output node setting step for calculating an output value of the output node;
A state in which the next state exists and if the next state is not the first transition state, the process proceeds to the input pattern reading process of the next state, and if there is no next state or the next state is the first transition state, the process is terminated. 14. The logic circuit failure diagnosis method according to claim 13, further comprising a determination step. The output value extraction step in the expected value calculation processing step is a step of extracting the output value of the output port in the final state for each test pattern from the node table created in the node expected value acquisition step. 14. The logic circuit failure diagnosis method according to claim 13, wherein the logic circuit failure is extracted. The failure location estimation step includes a failure mode selection step of estimating a failure location while separately assuming a control system failure and a data system failure, and
A node that estimates a fail propagation path by performing fail estimation of each node in an input direction by output estimation and expected value comparison of each node based on a fail vector, starting from a node corresponding to the fail output port and the fail estimation output port An estimation process;
An estimation information registration step of registering information on the nodes of the fail propagation path as failure location estimation information,
11. The method according to claim 10, further comprising: an end determination step that repeats these processes until all combinations that may propagate a failure to an output port are calculated, and a failure candidate output step that outputs a list of the failure location estimation information. Logic circuit failure diagnosis method. 17. The logic circuit according to claim 16, wherein the node estimation step in the fault location estimation step estimates only a value of an estimable bit when the output of each node is estimated and the value of the node is multi-bit. Fault diagnosis method. In a logic circuit failure diagnosis method for estimating a failure location of the logic circuit based on fail information acquired from a test result of the logic circuit, description information in which the logic circuit is functionally described in a circuit block unit in a design language, the fail information And a fail extraction step for extracting a fail estimation circuit block having a fail output port and a fail estimation output port based on the fail propagation estimation information, and a state transition having a plurality of states according to the processing order of the fail estimation circuit block based on the description information Create a table, based on the state transition table, an input node, an operation node composed of operators, a selection node that selects one output value from a set of multiple input values, and an output node and the connection of each node And a decision graph that determines the behavior for all conditions by displaying the data flow. And the conversion process to create,
A program for causing a computer to execute an expected value calculation step for calculating an expected value of the logic circuit and a failure location estimation step for estimating a failure location. The program according to claim 18, wherein the design language is a language describing a structure or an operation of a logic circuit. The converting step divides the processing of the logic circuit into a plurality of transition states, and creates a state transition table including items of a current state, a state transition condition, a next state, and an operation;
Set the process to read the input port, state variable or numeric value described in the state transition table as an input node, set the operator process as an operation node, and output the process to write the output port, the state variable or the numeric value A control part that calculates a state by setting the node as a node and connecting the input node and the operation node as a data flow, giving the result of the state as a binary value of TRUE / FALSE, and A data part for calculating an output value is created by connecting an input node and the operation node as a data flow, and in the result of the state, one output value corresponding to the TRUE state is obtained from a given set. 19. The program according to claim 18, further comprising the step of setting a selection node for selective output to the output node. The expected value calculation step calculates the output value of the input node, the operation node, the selection node, and the output node each time the state transitions using the decision graph, and calculates the node name and the calculated value. The program according to claim 18, further comprising: a node expected value acquisition step of creating a node table composed of sets; and an output value extraction step of extracting an output value of the logic circuit from the node table. The expected node value acquisition step in the expected value calculation step reads the test pattern or the previous output pattern, sets the input node, sets the input node, sets all input values, and outputs the output value. Operation node extraction step for extracting unset operation nodes, operation node setting step for calculating output values based on input values for the extracted operation nodes, and whether all operation nodes have been set If it is not completed, the process returns to the operation node extraction process, and if it is completed, the operation node determination process that goes to the next process, the selection node setting process that calculates the output value of the selected node, and the output An output node setting step for calculating an output value of the node, and if there is a next state and the next state is not the first transition state, the process proceeds to the input pattern reading step of the next state, Or the absence, or if the first transition state next state, according to claim 21 of a program and a state determining step of the process ends. The output value extraction step in the expected value calculation processing step is a step of extracting the output value of the output port in the final state for each test pattern from the node table created in the node expected value acquisition step. The program according to claim 21, wherein the program is extracted. The failure location estimation step starts from a failure mode selection step that estimates a failure location while separately assuming a control system failure and a data system failure, and a node corresponding to the fail output port and the fail estimation output port. Based on the fail vector, the node estimation process for estimating the fail propagation path by performing the fail estimation of each node in the input direction by estimating the output of each node and comparing the expected value, and the node information of this fail propagation path as the fault location estimation information An estimation information registration step to register, an end determination step that repeats these processes until all combinations that may propagate a failure to the output port are calculated, and a failure candidate output step that outputs a list of the failure location estimation information The program according to claim 18, comprising: 25. The program according to claim 24, wherein in the node estimation step in the failure location estimation step, when the output of each node is estimated, if the value of the node is multi-bit, only the value of the estimable bit is estimated.

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