JP3957507B2 - Device for converting logic circuit into decision graph, conversion method, and recording medium recording conversion program - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention records a conversion device, a conversion method, and a conversion program for a logic circuit decision graph suitable for conversion to a logic circuit decision graph described in a hardware description language when estimating a failure location at a function level. In particular, an apparatus, a conversion method, and a conversion method for converting a logic circuit into a decision graph that can be converted into a decision graph in a short time for a logic circuit having a large scale and multilayer wiring The present invention relates to a computer-readable recording medium on which a program is recorded.
[0002]
[Prior art]
The method of converting to a decision graph in failure location estimation is a method of converting a logic circuit described in a hardware description language into a decision graph in a system that estimates a failure location of a logic circuit at a functional level.
[0003]
In the conventional failure location estimation method, as shown in FIG. 19, a failure dictionary is created in advance using a failure simulator (step S101), the LSI is actually tested to obtain fail information (step S102), and the test result The failure dictionary is searched from the failure information (step S103), and the failure location is estimated (step S104).
[0004]
The fault simulator performs functional simulation or logic simulation assuming a fault in the LSI, collates the result with an expected value, and creates a fault dictionary that associates the assumed fault location with the test vector that detected the fault. create. Then, the failure dictionary is searched from the fail information obtained as a result of actually testing the LSI, the assumed failure location is obtained, and prioritization is performed from a plurality of assumed failures obtained using a plurality of fail information and path information. The failure location is estimated.
[0005]
As another failure location estimation method, there is a method in which the above-described procedure is performed hierarchically and internal observation is performed with an electron beam tester. In this method, the failure location is estimated in the order described above from the upper level, the inside is observed using an electron beam tester at the boundary of the level, and the failure location is narrowed down to the lower level. .
[0006]
Still another failure location estimation method is disclosed in JP-A-8-146093. This method is a method of estimating a failure location at the gate level. A combinational circuit that may propagate a fault to a fault output is dynamically extracted, and a logic state and a path through which the fault propagates are estimated for each combinational circuit. . The logic state is not only the logical value of one signal line, but all nodes in the circuit, that is, signal lines, gates, gate terminals and input / output terminals are 0, 1, X (Don't Care), Z ( It is a state having a logical value such as high impedance) or U (undefined).
[0007]
[Problems to be solved by the invention]
However, in the fault location estimation method using the fault simulator, it is necessary to create a fault dictionary in advance. However, since the creation of the fault dictionary requires a lot of fault simulation time, it is necessary to increase the scale of the LSI. There is a problem that the calculation time becomes enormous and the failure dictionary file becomes very large. In addition, failure models used in failure simulation are generally single stuck-at faults, so multiple failures such as bridge failures may not match the actual ones. If the failure simulation model is expanded to multiple failures, the processing time of failure simulation There is also a problem that this is not practical.
[0008]
The combined use of hierarchical failure simulation and an electron beam tester is effective because it narrows down the estimated locations while observing them sequentially. However, when the LSI becomes large-scale and becomes multi-layer wiring, the lower layer potential is observed. There is a problem that it becomes impossible.
[0009]
Although the failure location estimation method at the gate level is an effective method because the failure location can be estimated at the gate level, it cannot be said that the accuracy for a large-scale LSI is sufficient because of the estimation processing in units of gates. There is a problem that the time becomes longer.
[0010]
The present invention has been made in view of the above-mentioned problems, and its main purpose is to estimate a failure point at a functional level in a short time for a logic circuit that is increased in scale and multilayer wiring. An object of the present invention is to provide a device for converting a logic circuit described in a hardware description language into a decision graph, a conversion method, and a recording medium on which a conversion program is recorded.
[0011]
[Means for Solving the Problems]
According to the present invention, there is provided an apparatus for converting a logic circuit into a decision graph, wherein the logic circuit described in a hardware description language is converted into a decision graph. And a state transition table creating means for creating a state transition table including a state number, a determination condition, a next state number, and an operation content according to the processing order of the logic circuit, an input port, a state variable, The state number, variables and constants in the conditional expression, and variables and constants used in the evaluation of the expression on the right side of the assignment expression are set as read nodes, and assigned to the output port, state variable, and left side of the assignment expression Is set as a write node, and the operator used in the hardware description language is an operation node. Set by selecting one value corresponding to the true state from the given set and setting an allocation decision node corresponding to each write node for assigning the selected value to the write node. By linking the read node and the operation node as a data flow on the basis of the state transition table and the node setting means for setting the nodes of the graph, the output value and 2 of true / false corresponding to the output value are obtained. A node link that links each node by calculating a state result given by a value, linking the set of the output value and the state result to an assignment decision node, and linking the assignment decision node to a write node Means And the decision graph is a function level decision graph. It is characterized by that.
[0012]
The state transition table creating means includes a process statement of a hardware description language VHDL (VHSIC HDL: very high speed integrated circuit hardware description language) or a hardware description language as the loop process in the logic circuit described in the hardware description language. When a always-block of verilog-HDL (verilog-hardware description language) is included, a state transition table composed of the first and second states can be created. In this case, in the first state, An event generation determination process is assigned, and when the event occurs, a transition is made to the second state. In the second state, a process described in the process statement or always block is assigned, and the process statement or always block is assigned. When the processing described in It is possible to transition to the 1 state.
[0013]
In addition, the state transition table creation unit is configured to include a state including the third state and the fourth state when an initial block of the hardware description language verilog-HDL is included in the logic circuit described in the hardware description language. A transition table can be created. In this case, in the third state, an event occurrence determination process is assigned, and when the event occurs, the state transitions to the second state, and in the fourth state, the initial state. All processes can be completed by allocating the process described in the block and ending the process described in the initial block.
[0014]
Further, the state transition table creating means includes a logic statement described in the hardware description language including a while statement of a hardware description language VHDL or a hardware description language verilog-HDL as the loop processing. A state transition table composed of the fifth to seventh states can be created. In this case, in the fifth state, a loop condition is assigned and evaluation is performed with a binary value of true / false. If it is false, the process transitions to the seventh state. In the sixth state, the loop condition is assigned a process when the loop condition is true and the loop condition is assigned. If true is true, the sixth state is maintained. If false, the state transitions to the seventh state. In the seventh state, the sixth state is maintained. It can transition to state.
[0015]
Still further, the state transition table creating means includes a sequential signal assignment statement of the hardware description language VHDL or a procedural nonblocking assignment of the hardware description language verilog-HDL as the timing control in the logic circuit described in the hardware description language. When a sentence is included, a state transition table composed of the eighth and ninth states can be created. In this case, in the eighth state, the right side of the sequential signal assignment expression or the procedural nonblocking assignment expression After the evaluation of the expression is substituted into a temporary register, the state transits to the ninth state. In the ninth state, the value of the temporary register is changed to the left side of the sequential signal assignment expression or the procedural nonblocking assignment expression. Can be substituted into the signal.
[0016]
The state transition table creating means includes a logic circuit described in the hardware description language including a wait for statement in the hardware description language VHDL or a # statement in the hardware description language verilog-HDL as the timing control. If the waiting time indicated by the wait for statement or # statement is converted into the number of clock cycles before the state transition table including the fifth to seventh states is created, the number of clock cycles is determined. It may be converted into a conditional while statement, and the logic circuit described in the hardware description language includes a wait description statement in the hardware description language VHDL or a wait statement in the hardware description language verilog-HDL as the timing control. The fifth to seventh states. Before creating the state transition table may be converted into a while statement that the determination condition conditions the wait the until statement or wait statement.
[0017]
A method for converting a logic circuit into a decision graph according to the present invention is a method for converting a logic circuit described in a hardware description language into a decision graph. And a process of creating a state transition table including a state number, a determination condition, a next state number, and an operation content according to the processing order of the logic circuit, and an input port, a state variable, a state number, and a condition. Variables and constants in expressions, and variables and constants used in expression evaluation on the right side of assignment expressions are set as read nodes, and output ports, state variables, and variables assigned on the left side of assignment expressions are set as write nodes. And set the operator used in the hardware description language as the operation node. Setting a decision graph node by selecting one value corresponding to the true state from the set and setting an assignment decision node corresponding to each write node to assign the selected value to the write node And, based on the state transition table, link the read node and the operation node as a data flow to calculate an output value and a state result given as a true / false binary value corresponding to the output value. Linking the set of the output value and the state result to an allocation decision node, and linking the allocation decision node to a write node, thereby linking the nodes. And the decision graph is a function level decision graph. It is characterized by that.
[0018]
The step of creating the state transition table includes a process statement of the hardware description language VHDL or an always block of the hardware description language verilog-HDL as the loop processing in the logic circuit described in the hardware description language. In some cases, the method may include a step of creating a state transition table including a first state and a second state. In the first state, an event occurrence determination process is assigned, and when the event occurs, the second state is assigned. In the second state, the process described in the process statement or always block is assigned, and when the process described in the process statement or always block ends, the process transits to the first state. Can do.
[0019]
The state transition table is generated from the third and fourth states when the logic circuit described in the hardware description language includes an initial block of the hardware description language verilog-HDL. A state transition table can be created, and in the third state, an event occurrence determination process is assigned, and when the event occurs, the state transitions to the second state, and in the fourth state, All processes can be completed by assigning the process described in the initial block and ending the process described in the initial block.
[0020]
Further, in the step of creating the state transition table, when the logic circuit described in the hardware description language includes a while statement of the hardware description language VHDL or the hardware description language verilog-HDL as the loop processing In the fifth state, a loop condition is assigned and evaluated with a binary value of true / false, and if it is true, the state transition table comprising the fifth to seventh states can be created. Transition to the sixth state. If false, transition to the seventh state. In the sixth state, a process when the loop condition is true and a loop condition are assigned. If the loop condition is true, the sixth state is maintained. If the loop condition is false, the state transitions to the seventh state. In the seventh state, It can transition to the fifth state.
[0021]
Furthermore, the step of creating the state transition table includes a sequential signal assignment statement of the hardware description language VHDL or a procedural procedure of the hardware description language verilog-HDL as the timing control in the logic circuit described in the hardware description language. When a non-blocking assignment statement is included, the method may include a step of creating a state transition table including the eighth and ninth states. In the eighth state, a sequential signal assignment expression or a procedural non-blocking assignment expression After the evaluation of the expression on the right side in FIG. 9 is assigned to a temporary register, the state is shifted to the ninth state. In the ninth state, the value of the temporary register is changed to a sequential signal assignment expression or a procedural non-blocking assignment expression. Can be substituted into the signal on the left side of.
[0022]
The step of creating the state transition table includes a wait for statement in the hardware description language VHDL or a # statement in the hardware description language verilog-HDL as the timing control in the logic circuit described in the hardware description language. The waiting time indicated by the wait for statement or # statement is converted into the number of clock cycles before the step of creating the state transition table consisting of the fifth to seventh states. The logic circuit described in the hardware description language can be converted into a while statement using the number as a determination condition, and the wait description statement of the hardware description language VHDL or the hardware description language verilog- If an HDL wait statement is included, Before 5 to the step of creating a state transition table of the seventh state, may have a step of converting the while statement that the determination condition conditions the wait the until statement or wait statement.
[0023]
A computer-readable recording medium on which a conversion program for converting a logic circuit into a decision graph according to the present invention is recorded is a program for converting a logic circuit described in a hardware description language into a decision graph. In a recorded computer-readable recording medium, a state number and a process in each state are assigned for loop processing or timing control, and the state number, determination condition, next state number, and operation contents are included according to the processing order of the logic circuit The procedure for creating the transition table, input port, state variable, state number, variable and constant in the conditional expression, and the variable and constant used in the expression evaluation on the right side of the assignment expression are set as the read node, and the output port , State variables, and variables assigned on the left side of an assignment expression Set as the operation node, set the operator used in the hardware description language as the operation node, select one value corresponding to the true state from the given set, and write this selected value By setting an assignment decision node corresponding to each writing node to be assigned to the node, a procedure for setting a node of the decision graph, and based on the state transition table, the read node and the operation node are used as a data flow. By linking, the output value and the state result given by the true / false binary value corresponding to the output value are calculated, the set of the output value and the state result is linked to the assignment decision node, and the assignment is performed. Linking a decision node to a writing node to link each node together. It is executed by the data The decision graph is a decision graph of function level It is characterized by that.
[0024]
The procedure for creating the state transition table includes a process statement in the hardware description language VHDL or an always block in the hardware description language verilog-HDL as the loop processing in the logic circuit described in the hardware description language. In this case, a procedure for creating a state transition table composed of a first state and a second state may be included. In the first state, an event occurrence determination process is assigned, and when the event occurs, the second state is assigned. In the second state, the process described in the process statement or always block is assigned, and when the process described in the process statement or always block ends, the process transits to the first state. Can do.
[0025]
Further, the procedure for creating the state transition table includes the third and fourth states when the initial circuit of the hardware description language verilog-HDL is included in the logic circuit described in the hardware description language. A procedure for creating a state transition table can be included. In the third state, an event occurrence determination process is assigned, and when the event occurs, the state transitions to the second state. In the fourth state, All processes can be completed by assigning a process described in the initial block and ending the process described in the initial block.
[0026]
Further, the procedure for creating the state transition table is performed when the logic circuit described in the hardware description language includes a while statement of the hardware description language VHDL or hardware description language verilog-HDL as the loop processing. , And a procedure for creating a state transition table composed of fifth to seventh states. In the fifth state, a loop condition is assigned and evaluated with a binary value of true / false. Transition to the sixth state, and if false, transition to the seventh state. In the sixth state, a process and a loop condition are assigned when the loop condition is true, and the loop is executed after the process is true. If the condition is true, the sixth state is maintained. If the condition is false, the state transitions to the seventh state. In the seventh state, It can transition serial to the fifth state.
[0027]
Furthermore, the procedure for creating the state transition table includes a sequential signal assignment statement of the hardware description language VHDL or a procedural non-blocking of the hardware description language verilog-HDL as the timing control in the logic circuit described in the hardware description language. In the case where an assignment statement is included, a procedure for creating a state transition table composed of the eighth and ninth states can be included. In the eighth state, in the sequential signal assignment expression or the procedural non-blocking assignment expression After the evaluation of the expression on the right side is assigned to a temporary register, the state transitions to the ninth state. In the ninth state, the value of the temporary register is changed to a sequential signal assignment expression or a procedural non-blocking assignment expression. It can be assigned to the signal on the left side.
[0028]
The procedure for creating the state transition table includes a wait description statement in the hardware description language VHDL or a # statement in the hardware description language verilog-HDL as the timing control in the logic circuit described in the hardware description language. The waiting time indicated by the wait for statement or the # statement is converted into the number of clock cycles before the procedure for creating the state transition table comprising the fifth to seventh states. The logic circuit described in the hardware description language can have a procedure for converting into a while statement using the number as a determination condition, and the wait description statement of the hardware description language VHDL or the hardware description language verilog- If an HDL wait statement is included, Before 5 to steps to create a state transition table of the seventh state, it is possible to have a procedure for converting the while statement that the determination condition conditions the wait the until statement or wait statement.
[0029]
At the input / output ports and latches of the logic circuit, compare the estimated state value estimated based on the decision graph created in the present invention with the test result in the tester and the expected value obtained from the function simulation to estimate the fail propagation path Thus, the failure can be estimated. Also, compared with failure estimation at the gate level, the number of basic elements is reduced, so the number of estimation processes is reduced and the estimation process time is shortened.
[0030]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, a conversion device, a conversion method, and a computer-readable recording medium on which a conversion program for a logic circuit according to an embodiment of the present invention is recorded will be described in detail with reference to the accompanying drawings. FIG. 1 is a block diagram showing the configuration of a conversion apparatus for converting to a decision graph in estimating a fault location of a logic circuit according to an embodiment of the present invention.
[0031]
In this embodiment, an input device 1 such as a keyboard, a data processing device 2 that converts a logic circuit described in a hardware description language into a decision graph, a storage device 3 that stores information including a hard disk or a memory, and a display An output device 4 such as a device or a printing device is provided.
[0032]
The data processing device 2 is provided with preprocessing means for assigning the number of states and processing in each state with respect to loop processing or timing control. Further, the data processing device 2 is provided with post-processing means for creating a state transition table composed of a state number, a determination condition, a next state number, and operation contents according to the processing order of the logic circuit. A state transition table creating means 11 is composed of the pre-processing means and the post-processing means. Further, the data processing device 2 is provided with node setting means 12 for setting nodes of the decision graph and node link means 13 for linking the nodes.
[0033]
The node setting unit 12 sets the input port, the state variable, the state number, the variable and constant in the conditional expression, and the variable and constant used in the expression evaluation on the right side of the assignment expression as a read node. Further, the node setting unit 12 sets the output port, the state variable, and the variable assigned on the left side of the assignment expression as a write node. Further, the node setting means 12 sets an operator used in the hardware description language as an operation node, and selects one value corresponding to a true state from a given set. An assignment decision node corresponding to each write node for assigning the selected value to the write node is set.
[0034]
The node link unit 13 links the read node and the operation node as a data flow based on the state transition table created by the state transition table creation unit 1, thereby obtaining an output value and a true / false (true / false) corresponding to the output value. The state result given by the binary value of false is calculated, the set of the output value and the state result is linked to the assignment decision node, and the assignment decision node is linked to the write node.
[0035]
The storage device 3 includes a circuit configuration storage unit (not shown) that stores a logic circuit decision graph and its configuration.
[0036]
Next, the operation of the conversion apparatus of the present embodiment configured as described above, that is, the conversion method to the decision graph in the estimation of the failure location of the logic circuit will be described. FIG. 2 is a flowchart showing the operation of the conversion device into the decision graph in the estimation of the failure location of the logic circuit according to the embodiment of the present invention.
[0037]
First, the state transition table creating unit 11 assigns the number of states and the processing in each state with respect to loop processing or timing control as a previous process. Thereafter, the state transition table creating unit 11 creates a state transition table composed of the state number, the determination condition, the next state number, and the contents of the operation as a subsequent process in accordance with the processing order of the logic circuit (step S11).
[0038]
Next, the node setting unit 12 sets a node of the decision graph (step S12). Specifically, the node setting unit 12 sets the input port, the state variable, the state number, the variable and constant in the conditional expression, and the variable and constant used in the expression evaluation on the right side of the assignment expression as a read node. . The node setting unit 12 also sets the output port, the state variable, and the variable assigned on the left side of the assignment expression as a write node. The node setting means 12 further sets an operator used in the hardware description language as an operation node, selects one value corresponding to the true state from the given set, and selects the selected value. An assignment determination node corresponding to each write node for assigning to the write node is set.
[0039]
Next, the node link means 13 links the nodes (step S13). Specifically, the node link unit 13 supports the output value and the output value by linking the read node and the operation node as a data flow based on the state transition table created by the state transition table creating unit 11. The state result given by the binary value of true / false is calculated. The node link means 13 links the set of the output value and the state result to the allocation determination node, and links the allocation determination node to the writing node.
[0040]
Next, a method for converting to a decision graph in estimating the fault location of the counter circuit expressed in the hardware description language verilog-HDL will be described. This counter circuit is assumed to be a circuit that counts up when the clock signal clk becomes “1” and outputs a count to the signal out. FIG. 3 is a diagram showing a counter circuit expressed in hardware description language verilog-HDL, FIG. 4 is a state transition table of the counter circuit, and FIG. 5 is a decision graph of the counter circuit.
[0041]
First, the operation of the state transition table creation unit 11 will be described.
[0042]
In the present embodiment, as shown in FIG. 3, an always block and a non-blocking assignment statement are described. For this reason, as shown in FIG. 4, the state transition table creating means 11 is assigned the process described in the state ST0 to which the event occurrence determination process of the always block is assigned, and in the non-blocking substitution expression. State ST1 in which processing for assigning the evaluation of the expression on the right side to the temporary register is assigned, and state ST2 in which processing for assigning the value held in the temporary register in state ST1 to the signal on the left side of the non-blocking assignment expression is assigned A state transition table showing these three states is created.
[0043]
When the process in the state ST0 is completed, the state transitions to the state ST1 as the next state. When the process in the state ST1 is completed, the state transitions to the state ST2 as the next state. When the process in the state ST2 is completed, the state ST0 is the next state. Transition to.
[0044]
Next, the operation of the node setting unit 12 will be described.
[0045]
The node setting unit 12 sets clk and ci as input ports as read nodes. The state variable STATE and state numbers ST0, ST1, and ST2 are also set as read nodes. Furthermore, variables and constants ckl, “1”, out, and “1111” in the conditional expression are also set as read nodes. Furthermore, “0000”, out, ci, and reg, which are variables and constants used in the evaluation of the expression on the right side of the assignment expression, are also set as read nodes.
[0046]
The node setting unit 12 sets the output port out as a write node. The state variable STATE is also set as a write node, and reg and out, which are variables assigned on the left side of the assignment formula, are also set as write nodes.
[0047]
Further, the node setting unit 12 sets the equal sign “=”, the addition “+”, the negation “!”, And the logical operator and “∩” as the operation nodes as operators used in the state transition table.
[0048]
Furthermore, the node setting unit 12 sets STATE_a, reg_a, and out_a corresponding to the write nodes out, STATE, and reg as allocation decision nodes.
[0049]
Next, the operation of the node link means 13 will be described using the operation corresponding to the state number ST2 as an example.
[0050]
The node link means 13 links the read node STATE that is a state variable and the read node ST2 that is a state number with an equal sign “=” that is an operation node. The node link means 13 links the read node reg and the assignment determination node reg_a as an output value, and links the assignment determination node reg_a and the write node reg as an output destination. Here, as a state result corresponding to the output value reg, the equal sign “=” linked to the read node ST2 is linked to the assignment determination node reg_a.
[0051]
The node link means 13 links the write node STATE and the assignment determination node STATE_a as the output destination. The node link means 13 links the assignment determination node STATE_a and the read nodes ST0, ST1, and ST2 that are state numbers as output values. Here, since the next state after the state ST2 is the state ST0, as a state result corresponding to the output value ST0 of the assignment determination node STATE_a, the equal sign “=” linked to the read node ST2 is linked to the assignment determination node STATE_a. .
[0052]
By linking the nodes in state ST0 and state 1 of the state transition table in the same manner, the decision graph shown in FIG. 5 is created.
[0053]
Next, as a loop process, the state transition table creating unit 11 when the hardware description language verilog-HDL data includes an alwayss block or the hardware description language VHDL data includes a process statement. An operation example will be described with reference to FIGS. FIG. 6 is a diagram showing an example of a verilog-HDL always block and a VHDL process statement, and FIG. 7 is a state transition table created by the state transition table creating unit 11.
[0054]
When an always block or process statement as shown in FIG. 6 is included, the value of the signal y is substituted into the signal x when the signal clock is changed.
[0055]
In the verilog-HDL always block and the VHDL process statement, the state transition table has two states. In the state ST0, it is assumed that “change in signal clock” is assigned as an event occurrence determination process, and when the signal clock changes, the state transitions to the state ST1 as the next state. In the state ST1, an assignment expression x = y is assigned as a process described in an always block or a process statement, and when the process ends, the state ST0 is transitioned to.
[0056]
Next, an operation example of the state transition table creating unit 11 when an initial block is included in data of the hardware description language verilog-HDL will be described with reference to FIGS. FIG. 8 is a diagram illustrating an example of a verilog-HDL initial block, and FIG. 9 is a state transition table created by the state transition table creating unit 11.
[0057]
When an initial block as shown in FIG. 8 is included, when the reset signal changes to 1, 0 is substituted for the value of the signal a.
[0058]
In the veritilog-HDL initilla block statement, the state transition table has two states. In the state ST0, it is assumed that “change of the signal reset to 1” is assigned as the event occurrence determination process, and when the signal reset changes to 1, the state transitions to the state ST1 as the next state. In the state ST1, an assignment expression a = 0 is assigned as the process described in the initial block, and all processes are terminated when the process in the state ST1 is completed.
[0059]
Next, see FIG. 10, FIG. 11 and FIG. 12 for the conversion to a decision graph by the conversion device when the while statement is included in the data of the hardware description language verilog-HDL or the data of the hardware description language VHDL. To explain. FIG. 10 is a diagram showing examples of the verilog-HDL and VHDL while statements, FIG. 11 is a state transition table created by the state transition table creating unit 11, and FIG. 12 is a decision graph finally created. is there.
[0060]
When the “while” statement as shown in FIG. 10 is included, the value of “b−a” is substituted into the signal b while “a <b” is established for the signal a and the signal b.
[0061]
The state transition table created by the state transition table creating unit 11 is composed of three states. In state 0ST, a loop condition “a <b” is assigned, and if “a <b” is true, the state transits to state ST1 as the next state. On the other hand, if it is false, it changes to state ST2 as the next state. In the state ST1, the process “b = ba” is performed as a process when the loop condition is true. Next, the loop condition “a <b” is determined. If the next state is true, the state ST1 is maintained. If the state is false, the state transitions to the state ST2. In state ST2, it is assumed that transition to state ST0 is made as the next state.
[0062]
The node setting unit 12 sets STATE, ST0, ST1, ST2, a, and b, which are variables used in the evaluation of the expression on the right side of the assignment expression, as state nodes, state numbers, conditional expressions, and readout nodes. To do. Further, STATE and b, which are variables substituted on the left side of the assignment expression, and state variables are set as write nodes. Furthermore, as operators used in the state transition table, an equal sign “=”, negation “!”, Subtraction “−”, inequality sign “<”, and logical operators and “∩” and or “∪” are operated. Set as a node. Furthermore, STATE_a and b_a corresponding to the write nodes STATE and b are set as assignment determination nodes.
[0063]
The node link means 13 links the read node STATE that is a state variable and the read node ST1 that is a state number with an equal sign “=” that is an operation node at a location corresponding to the state ST1 in the state transition table. The allocation decision node b_a is linked to the write node b as an output destination. Since the calculated value of “b−a” is the output value of the allocation decision node b_a, the read nodes a and b are linked with the subtraction “−” that is the operation node. The subtraction “−” that is the operation node is linked as an output value to the assignment determination node b_a. Here, as a state result corresponding to the calculated value of “b−a” that is the output value, the equal sign “=” linked to the read node ST1 is linked to the assignment determination node b_a.
[0064]
The node link means 13 links the write node STATE as the output destination of the assignment determination node STATE_a. The assignment determination node STATE_a is linked to the read nodes ST0, ST1, and ST2 which are state numbers as output values. Here, in the state ST0 or the state ST1, when the loop condition “a <b” is true, the next state is the state 1. As a result of the state corresponding to the output value ST1 of the assignment determination node STATE_a, “a <b” and “STATE = ST0”, or “a <b” and “STATE = ST1” are connected by a data flow, and the assignment determination node STATE_a Linked with.
[0065]
Similarly, for the state ST0 and the state ST2, the decision graph shown in FIG. 12 is created by linking the nodes. Here, “∪” in the figure means the logical operator or.
[0066]
Next, as timing control, state transition when hardware description language verilog-HDL data includes a procedural non-blocking assignment statement or hardware description language VHDL data includes a sequential signal assignment statement An example of the operation of the table creating means 11 will be described with reference to FIGS. FIG. 13 is a diagram showing an example of a verilog-HDL procedural non-blocking assignment statement and a VHDL sequential signal assignment statement, and FIG. 14 is a state transition table created by the state transition table creation means 11.
[0067]
When a procedural non-blocking statement or sequential signal assignment statement as shown in FIG. 13 is included, the value of the signal ct is held in a temporary register, and then whether or not ct is equal to “1111”. Thus, “0000” or “ct + 1” is substituted into ct. Then, the value of ct temporarily held in the register is substituted for the signal count.
[0068]
In the verilog-HDL procedural non-blocking assignment statement and the VHDL sequential signal assignment statement, the state transition table has two states. In the state ST0, the evaluation ct of the expression on the right side in the verilog-HDL procedural non-blocking assignment statement and the VHDL sequential signal assignment statement is assigned to the temporary register reg. Next, a value of “0000” or “ct + 1” is substituted into ct depending on whether or not ct is equal to “1111”. And it changes to state ST1 as the next state. In the state ST1, the temporary register reg value in the state ST0 is assigned to count.
[0069]
Next, as timing control, when the hardware description language verilog-HDL data includes a # statement or the hardware description language VHDL data includes a wait for statement, state transition table creation means The operation of converting these sentences into a while sentence will be described with reference to FIGS. 15 and 16.
[0070]
The # statement shown in FIG. 15 and the wait for statement shown in FIG. 16 describe an operation for stopping the execution of the process for a time of 100 nsec. Also, the while statement shown in FIGS. 15 and 16 shows the conversion result to the when statement when the clock interval is 10 nsec. If the while loop is processed for the number of 10 clock cycles, the execution of the process is stopped for 100 nsec in time, and an operation equivalent to a # statement or a wait for statement is obtained.
[0071]
After converting the # sentence or the wait for sentence into a while sentence in this way, the processing is performed by the state transition table creating unit 11, the node setting unit 12, and the node link unit 13, thereby converting the while sentence into a decision graph. be able to.
[0072]
Next, as a timing control, when the wait statement is included in the data of the hardware description language verilog-HDL, or when the wait until statement is included in the data of the hardware description language VHDL, the state transition table creating unit The operation of converting these sentences into a while sentence will be described with reference to FIGS. 17 and 18.
[0073]
The wait statement shown in FIG. 17 and the wait until statement shown in FIG. 18 describe an operation for stopping the execution of the process until the value of the signal c becomes equal to “1”. Moreover, the while sentence shown in FIG.17 and FIG.18 has shown the conversion result to a while sentence. If the while loop is processed during the period until the value of the signal c becomes equal to “1”, the execution of the process is stopped until the value of the signal c becomes equal to “1”, and a wait statement or a wait until statement Equivalent operation is obtained.
[0074]
In this way, after converting the wait statement or wait until statement to the while statement, the processing is performed by the state transition table creating unit 11, the node setting unit 12, and the node link unit 13, thereby converting the while statement into a decision graph. be able to.
[0075]
The state estimation values obtained by estimating the states of the input / output ports and the latches of the logic circuit using the decision graph created by these embodiments, the test results in the tester, and the expected values obtained by the function simulation And the failure propagation path at the functional level can be estimated by estimating the fail propagation path.
[0076]
Each process performed by the state transition table creating unit 11, the node setting unit 12, and the node link unit 13 is executed by a computer constituting a device that converts a logic circuit described in a hardware description language into a decision graph, for example. Can be realized. A main storage unit that reads the program from a computer-readable recording medium on which the program is recorded, such as a magnetic disk, an optical disk, and a semiconductor memory, into a computer of a device that converts a logic circuit described in a hardware description language into a decision graph The present invention can be implemented by loading and executing the program. Further, the program may be downloaded from a server or the like provided with a recording medium recording the program to a computer of a device that converts a logic circuit described in a hardware description language into a decision graph via a communication line. By using the recording medium in this way, management of the program becomes easy.
[0077]
【The invention's effect】
As described above in detail, according to the present invention, a logic circuit can be appropriately converted into a decision graph. Then, in the input / output ports and latches of the logic circuit, the state estimated value estimated based on the decision graph created in the present invention is compared with the expected value obtained by the function simulation, the failure propagation path is estimated, and the failure Estimation can be performed. That is, it is possible to estimate a location where a failure occurs at the function level. Therefore, it is not necessary to create a failure dictionary by failure simulation, and the failure location can be estimated in a short time. In addition, since the number of basic elements is reduced compared to failure estimation at the gate level, the number of estimation processes is reduced, and the estimation process time can be shortened.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of a conversion device to a decision graph in estimation of a failure location of a logic circuit according to an embodiment of the present invention.
FIG. 2 is a flowchart showing an operation of the conversion device into the decision graph in the estimation of the failure location of the logic circuit according to the embodiment of the present invention.
FIG. 3 is a diagram illustrating a counter circuit expressed in hardware description language verilog-HDL.
4 is a state transition table of the counter circuit shown in FIG. 3. FIG.
FIG. 5 is a determination graph of the counter circuit shown in FIG. 3;
FIG. 6 is a diagram illustrating examples of a verilog-HDL always block and a VHDL process statement;
7 is a state transition table created by state transition table creating means 11. FIG.
FIG. 8 is a diagram illustrating an example of an initial block of verilog-HDL.
FIG. 9 is a state transition table created by the state transition table creating unit 11;
FIG. 10 is a diagram illustrating examples of “while” statements of verilog-HDL and VHDL.
FIG. 11 is a state transition table created by the state transition table creating unit 11;
FIG. 12 is a decision graph finally created.
FIG. 13 is a diagram illustrating an example of a verilog-HDL procedural non-blocking assignment statement and a VHDL sequential signal assignment statement;
FIG. 14 is a state transition table created by the state transition table creating unit 11;
FIG. 15 is a diagram illustrating a relationship between a # sentence and a while sentence.
FIG. 16 is a diagram illustrating a relationship between a wait for sentence and a while sentence.
FIG. 17 is a diagram illustrating a relationship between a wait sentence and a while sentence.
FIG. 18 is a diagram illustrating a relationship between a wait until sentence and a while sentence.
FIG. 19 is a flowchart showing a method of converting to a decision graph in conventional failure location estimation.
[Explanation of symbols]
1: Input device
2: Data processing device
3; Storage device
4; Output device
11: State transition table creation means
12: Node setting means
13: Node link means

Claims (21)

In a device for converting a logic circuit described in a hardware description language into a decision graph, the number of states and processes in each state are assigned to loop processing or timing control according to the processing order of the logic circuits. State transition table creation means for creating a state transition table including the state number, determination condition, next state number and operation content, input port, state variable, state number, variable and constant in conditional expression, and right side of assignment expression Set the variables and constants used in the evaluation of expressions in the above as read nodes, set the output ports, state variables, and variables assigned on the left side of the assignment expression as write nodes, and use them in the hardware description language Set the operator that is being used as the operation node and set it to true from the given set A node setting means for setting a node of a decision graph by setting an assignment determination node corresponding to each write node for selecting one corresponding value and assigning the selected value to the write node; and the state transition table Based on the above, the readout node and the operation node are linked as a data flow to calculate an output value and a state result given by a true / false binary value corresponding to the output value, and the output value link the pair of the said state results in assignment decision node, by linking to the node writes the allocation decision node, and the node linking means for linking between nodes, have a, the decision graph determining the functional level An apparatus for converting a logic circuit into a decision graph, characterized by being a graph.   The state transition table creation means is configured when the logic circuit described in the hardware description language includes a process statement of the hardware description language VHDL or an always block of the hardware description language verilog-HDL as the loop processing. , Creating a state transition table composed of first and second states, assigning event occurrence determination processing in the first state, transitioning to the second state when the event occurs, In the state, the process described in the process statement or always block is assigned, and when the process described in the process statement or always block ends, the process transits to the first state. An apparatus for converting the described logic circuit into a decision graph.   The state transition table creating means includes a state transition table composed of third and fourth states when the logic circuit described in the hardware description language includes a hardware description language verilog-HDL initial block. In the third state, an event occurrence determination process is assigned, and when the event occurs, the process transits to the second state. In the fourth state, the process described in the initial block is performed. 2. The apparatus for converting a logic circuit into a decision graph according to claim 1, wherein all the processes are terminated by the allocation and the termination of the processes described in the initial block.   When the logic circuit described in the hardware description language includes a while statement of the hardware description language VHDL or the hardware description language verilog-HDL as the loop processing, To the seventh state, and in the fifth state, a loop condition is assigned and evaluation is performed with a binary value of true / false. If true, the state transitions to the sixth state. If the loop condition is true after the process when the loop condition is true, the process proceeds to the seventh state. In the sixth state, the process and the loop condition are assigned when the loop condition is true. If it is false, the state transitions to the seventh state, and in the seventh state, the state transitions to the fifth state. Converter into the decision graph of the logic circuit according to any one of claims 1 to 3.   The state transition table creating means includes a sequential signal assignment statement of the hardware description language VHDL or a procedural non-blocking assignment statement of the hardware description language verilog-HDL as the timing control in the logic circuit described in the hardware description language. A state transition table composed of the eighth and ninth states is created, and in the eighth state, the right-side expression in the sequential signal assignment expression or the procedural nonblocking assignment expression is evaluated as a temporary register. To the ninth state, and in the ninth state, the value of the temporary register is substituted into the signal on the left side of the sequential signal substitution expression or the procedural non-blocking substitution expression. A conversion device for converting a logic circuit to a decision graph according to any one of claims 1 to 4 .   In the case where the state transition table creation unit includes a wait for statement in the hardware description language VHDL or a # statement in the hardware description language verilog-HDL as the timing control in the logic circuit described in the hardware description language In addition, before creating the state transition table composed of the fifth to seventh states, the waiting time indicated by the wait for statement or # statement is converted into the number of clock cycles, and the number of clock cycles is set as a determination condition. 5. The apparatus for converting a logic circuit into a decision graph according to claim 4, wherein the logic circuit is converted into a while statement.   The state transition table creation means includes a logic unit described in the hardware description language including a hardware description language VHDL wait until statement or a hardware description language verilog-HDL wait statement as the timing control. In addition, before creating the state transition table including the fifth to seventh states, the state transition table is converted into a while statement using the condition of the wait until statement or the wait statement as a determination condition. For converting a logic circuit into a decision graph. In a method for converting a logic circuit described in a hardware description language into a decision graph, the number of states and processes in each state are assigned to loop processing or timing control according to the processing order of the logic circuits. A step of creating a state transition table including a state number, a judgment condition, a next state number, and an operation content, and an input port, a state variable, a state number, a variable and a constant in a conditional expression, and an expression evaluation on the right side of an assignment expression The variables and constants used in the above are set as read nodes, the output ports, state variables, and variables assigned on the left side of the assignment expression are set as write nodes, and the operations used in the hardware description language Set the child as the operation node and select one value corresponding to the true state from the given set. And setting an assignment decision node corresponding to each write node for assigning the selected value to the write node, setting a node of the decision graph, and based on the state transition table, the read node and the By linking the operation node as a data flow, an output value and a state result given as a binary value of true / false corresponding to the output value are calculated, and a set of the output value and the state result is assigned and determined. link to the node, by linking to the assignment decision node write node, possess a step of linking between nodes, a logic circuit, wherein the decision graph is a decision graph for functional level How to convert to a decision graph.   The step of creating the state transition table includes a process statement of the hardware description language VHDL or an always block of the hardware description language verilog-HDL as the loop processing in the logic circuit described in the hardware description language. A step of creating a state transition table composed of first and second states, and in the first state, an event occurrence determination process is assigned, and when the event occurs, the state transitions to the second state. In the second state, the process described in the process statement or always block is assigned, and when the process described in the process statement or always block ends, the process transits to the first state. The method for converting a logic circuit into a decision graph according to claim 8.   The step of creating the state transition table includes a state composed of a third state and a fourth state when an initial block of a hardware description language verilog-HDL is included in the logic circuit described in the hardware description language. A transition table is created. In the third state, an event occurrence determination process is assigned, and when the event occurs, the process transits to the second state, and in the fourth state, in the initial block. 9. The method of converting a logic circuit into a decision graph according to claim 8, wherein the process described in the above is allotted and all the processes are terminated when the process described in the initial block ends.   The step of creating the state transition table is performed when the logic circuit described in the hardware description language includes a while statement of the hardware description language VHDL or the hardware description language verilog-HDL as the loop processing. A step of creating a state transition table composed of fifth to seventh states. In the fifth state, a loop condition is assigned and evaluated with a binary value of true / false. If it is false, it transits to the seventh state, and in the sixth state, the process and loop condition are assigned when the loop condition is true, and the loop condition is true after the process when true. If so, the sixth state is maintained. If false, the state transitions to the seventh state. In the seventh state, the state transitions to the fifth state. Method of converting the decision graph of the logic circuit according to any one of claims 8 to 10, characterized in that transfer.   The step of creating the state transition table includes a sequential signal assignment statement of the hardware description language VHDL or a procedural non-blocking assignment statement of the hardware description language verilog-HDL as the timing control in the logic circuit described in the hardware description language. Is included, a step of creating a state transition table composed of the eighth and ninth states is included, and in the eighth state, the right-hand side expression in the sequential signal assignment expression or the procedural nonblocking assignment expression After the evaluation is assigned to a temporary register, the state is shifted to the ninth state. In the ninth state, the value of the temporary register is transferred to the signal on the left side of the sequential signal assignment expression or the procedural nonblocking assignment expression. 12. The logic circuit according to claim 8, wherein the logic circuit is substituted. Conversion method to the constant graph.   The step of creating the state transition table includes a wait for statement in the hardware description language VHDL or a # statement in the hardware description language verilog-HDL as the timing control in the logic circuit described in the hardware description language. In this case, before the step of creating the state transition table including the fifth to seventh states, the waiting time indicated by the wait for statement or the # statement is converted into the clock cycle number, and the clock cycle number is calculated. 12. The method for converting a logic circuit into a decision graph according to claim 11, further comprising the step of converting into a while sentence as a determination condition.   The step of creating the state transition table includes a wait description statement of the hardware description language VHDL-HDL or a wait description statement of the hardware description language VHDL as the timing control in the logic circuit described in the hardware description language. In this case, before the step of creating the state transition table including the fifth to seventh states, the method includes a step of converting into a while statement using the condition of the wait until statement or the wait statement as a determination condition. The method for converting a logic circuit to a decision graph according to claim 11. A computer-readable recording medium storing a logic circuit conversion program for converting a logic circuit described in a hardware description language into a decision graph, the number of states and processing in each state relating to loop processing or timing control Allocation, a procedure for creating a state transition table including a state number, a determination condition, a next state number and an operation content according to the processing order of the logic circuit, and input ports, state variables, state numbers, variables and constants in a conditional expression, And the variables and constants used in the expression evaluation on the right side of the assignment expression are set as read nodes, the output port, the state variable, and the variable assigned on the left side of the assignment expression are set as write nodes, and the hardware Set the operator used in the description language as the operation node and give it A node of the decision graph is set by selecting one value corresponding to the true state from the set and setting an assignment decision node corresponding to each write node for assigning the selected value to the write node. By linking the readout node and the operation node as a data flow based on the procedure and the state transition table, an output value and a state result given as a binary value of true / false corresponding to the output value are obtained. Calculating, linking the set of the output value and the state result to an allocation decision node, and linking the allocation decision node to a write node, thereby linking the nodes to each other. it is, to determine the graph of the logic circuit, wherein the decision graph is a decision graph for functional level A computer-readable recording medium conversion program.   The procedure for creating the state transition table includes a process statement in the hardware description language VHDL or an always block in the hardware description language verilog-HDL as the loop processing in the logic circuit described in the hardware description language. A procedure for creating a state transition table composed of a first state and a second state, and in the first state, an event generation determination process is assigned, and when the event occurs, the state transitions to the second state. In the second state, the process described in the process statement or always block is assigned, and when the process described in the process statement or always block ends, the process transits to the first state. The conversion program of the logic circuit according to claim 15 to a decision graph A computer-readable recording medium beam.   The procedure for creating the state transition table is the state transition consisting of the third and fourth states when the logic circuit described in the hardware description language includes an initial block of the hardware description language verilog-HDL. A procedure for creating a table. In the third state, an event occurrence determination process is assigned, and when the event occurs, the process transits to the second state, and in the fourth state, the initial block contains 16. The computer-readable recording program for converting a logic circuit into a decision graph according to claim 15, wherein the described process is assigned and all the processes are terminated when the process described in the initial block is terminated. Possible recording media.   The procedure for creating the state transition table is performed when the logic circuit described in the hardware description language includes a while statement of hardware description language VHDL or hardware description language verilog-HDL as the loop processing. A procedure for creating a state transition table composed of 5 to 7 states. In the fifth state, a loop condition is assigned and evaluation is performed with a binary value of true / false. If it is false, the process transits to the seventh state. In the sixth state, the process and loop condition are assigned when the loop condition is true, and the loop condition is true after the process when true. If there is, the sixth state is maintained. If it is false, the state transitions to the seventh state. In the seventh state, the state transitions to the fifth state. Logic computer readable recording medium conversion program to decision graph according to any one of claims 15 to 17, characterized in that.   The procedure for creating the state transition table includes a sequential signal assignment statement of the hardware description language VHDL or a procedural non-blocking assignment statement of the hardware description language verilog-HDL as the timing control in the logic circuit described in the hardware description language. If it is included, it has a procedure for creating a state transition table consisting of the eighth and ninth states, and in the eighth state, the evaluation of the right-hand side expression in the sequential signal substitution expression or the procedural non-blocking substitution expression Is assigned to a temporary register and then the state is shifted to the ninth state. In the ninth state, the value of the temporary register is assigned to the signal on the left side of the sequential signal assignment expression or the procedural nonblocking assignment expression. The logic circuit according to any one of claims 15 to 18, wherein A computer-readable recording medium conversion program to the constant graph.   In the procedure for creating the state transition table, the logic circuit described in the hardware description language includes a wait for statement of the hardware description language VHDL or a # statement of the hardware description language verilog-HDL as the timing control. In this case, before the procedure for creating the state transition table including the fifth to seventh states, the waiting time indicated by the wait for statement or the # statement is converted into the number of clock cycles, and the number of clock cycles is calculated. 19. The computer-readable recording medium recording a conversion program for converting a logic circuit into a decision graph according to claim 18, further comprising a procedure for converting into a while sentence as a determination condition.   The procedure for creating the state transition table includes a hardware description language VHDL wait until statement or a hardware description language verilog-HDL wait statement as the timing control in the logic circuit described in the hardware description language. In this case, before the procedure for creating the state transition table composed of the fifth to seventh states, there is a procedure for converting into a while statement using the condition of the wait until statement or the wait statement as a determination condition. 19. A computer-readable recording medium on which the conversion program for converting a logic circuit into a decision graph according to claim 18 is recorded.

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