JP5440094B2 - Circuit design apparatus and method - Google Patents

Description

  The present invention relates to a circuit design apparatus and method for creating a tree using flip-flops and realizing a multi-clock environment in a pseudo manner. In particular, the present invention relates to a delay constraint problem, a test problem, and a hazard check problem. Related to improvement.

  As a design method for an LSI (Large Scale Integration) circuit, there is a design method that introduces a clock-equivalent signal called a definer, creates a tree using flip-flops, and realizes a multi-clock environment in a pseudo manner. Such a refiner design method is used when a plurality of clocks cannot be introduced due to physical limitations or the like, as in the case where two clock meshes cannot be installed. Multiple clocks can be introduced more easily than the so-called CTS (Clock Tree Synthesis) used.

  In addition, when designing an LSI circuit, there is a problem of variations in clock delay, as disclosed in Patent Document 1. The design of a refiner that artificially realizes a multi-clock environment with a tree structure of such flip-flops has the effect of suppressing variations in the arrival time of the refiner signal to the flip-flops by distributing the signals using the flip-flops. is there.

Japanese Patent Laid-Open No. 11-284077

  However, in such a refiner design, there are a mix of a refiner tree flip-flop that distributes the refiner in one unit, a frequency-dividing flip-flop driven by the definer, and a normal flip-flop that is not related to the definer. Become. This causes a problem that processing such as delay constraint, asynchronous design, and testing becomes complicated as described below.

  That is, first, all the flip-flops to be frequency-divided must be manually given multicycle path restrictions. Conventionally, naming rules were given at the time of RTL creation, and restrictions were given based on the names, but in this method, human error such as omission of compliance with naming rules at the time of RTL creation and omission at the time of delay constraint creation occurred frequently, Causes a large design reversion.

  Further, since the frequency-divided flip-flop cannot directly input an external clock, it is necessary to make the frequency-divided flip-flop not to be scanned or to incorporate a bypass logic. The former leads to a decrease in detection rate, and the latter leads to a circuit amount overhead.

  Furthermore, it is necessary for the designer to always be aware of the asynchronous path where the refiner tree flip-flop and the normal flip-flop cross each other, and check whether the circuit as intended in the logic synthesis is synthesized. However, in the case of a refiner design, since there are relatively many such asynchronous paths, it is very difficult to list and check all of them in an exhaustive manner. Therefore, check leakage is likely to occur, and if a circuit that causes a hazard is passed to the subsequent process as it is, the actual machine may malfunction due to glitch noise.

  In view of the above-described problems, the present invention provides a circuit design that can improve the delay constraint problem, the test problem, and the hazard check problem in the circuit design using the clock divided by the flip-flop by the definer design. It is an object to provide a design apparatus and method.

  In order to solve the above-described problems, the present invention provides a circuit design apparatus that creates a tree using flip-flops and artificially realizes a multi-clock environment using clocks divided by the flip-flops. Referring to the refiner signal information, the flip-flop in the netlist is classified into a refiner tree flip-flop, a frequency-dividing flip-flop, and a normal flip-flop.

The present invention relates to a circuit design method for a circuit design device that creates a tree using flip-flops and realizes a pseudo-multiple clock environment using clocks divided by the flip-flops. means, with reference to the netlist and definer signal information, the flip-flops in the netlist, the definer tree flip-flop, and the division of the flip-flop, and wherein the classified into normal flip-flop To do.

  According to the present invention, when designing a circuit using a clock frequency-divided by a flip-flop by a definator design, the flip-flop in the netlist is divided into a refiner tree flip-flop, a frequency-dividing flip-flop, It is classified into other normal flip-flops, and based on the classified flip-flop information, delay constraints are generated, scan paths are inserted, and hazard check target flip-flops are extracted. As a result, the delay constraint problem, the test problem, and the hazard check problem can be improved.

1 is a block diagram illustrating an overall system configuration of a circuit design device according to a first exemplary embodiment of the present invention. It is explanatory drawing of the example of description of RTL containing the refiner description in the 1st Embodiment of this invention. It is a block diagram used for description of the circuit which can synthesize | combine RTL of a refiner description in the 1st Embodiment of this invention. It is a block diagram which shows the specific example of the net list in the 1st Embodiment of this invention. It is a flowchart used for description of the classification process of the flip-flop in the 1st Embodiment of this invention. It is explanatory drawing of the refiner signal information in the 1st Embodiment of this invention. It is explanatory drawing of the FF category list | wrist in the 1st Embodiment of this invention. It is explanatory drawing of the delay constraint in the 1st Embodiment of this invention. It is a block diagram which shows the specific example of the scanned net list in the 1st Embodiment of this invention. It is a block diagram which shows the specific example of the optimized net list in the 1st Embodiment of this invention. It is explanatory drawing of the specific example of the hazard report in the 1st Embodiment of this invention.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. Referring to FIG. 1, the overall system according to the embodiment of the present invention includes a data processing device 1 and a storage device 2.

  The data processing apparatus 1 includes a synthesis unit 11, a trace unit 12, a delay constraint generation unit 13, a scan circuit generation unit 14, an optimization unit 15, and a hazard check unit 16.

  The synthesizer 11 reads an RTL (Register transfer level) 21 described in a hardware description language (HDL) such as Verilog or VHDL, and converts it into a netlist 22. At this time, optimization based on various constraints is performed in a later process, and therefore, particularly powerful logic optimization is not performed here. Of course, optimization may be performed at this time.

  The trace unit 12 traces the inside of the net list 22 with reference to the net list 22 and the refiner signal information 23, and outputs the FF categorized list 24. The FF categorization list 24 is a table in which the flip-flops in the netlist 22 are classified into a refiner tree flip-flop, a frequency division flip-flop, and other normal flip-flops. The flip-flop classification process at this time is as follows.

  The trace unit 12 first extracts a terminal to be the source of the definator signal from the input terminals in the netlist 22 based on the definator signal information 23, and traces in the fan-out direction from the source terminal. When reaching the flip-flop, the flip-flop is added to the FF categorization list 24 as a refiner tree flip-flop. Then, the trace unit 12 acquires the first-stage flip-flop directly connected to the output of the gating cell that drives the division ratio, and is directly connected to the gating cell that drives this division ratio. The flip-flop is added to the FF categorization list 24 as a frequency-dividing flip-flop. Further, the trace unit 12 removes the refiner tree flip-flops and the frequency-divided flip-flops that have already been added to the FF categorization list 24 from all the flip-flop groups, and the remaining flip-flops are normally flip-flops to obtain FFs. Add to categorized list 24.

  The delay constraint generation unit 13 generates delay constraint information 25 for a circuit in which a definer is incorporated, based on information in the FF categorization list 24. The delay constraint generation unit 13 sets a multicycle having the entire set of frequency-divided flip-flops as the start point and the end point.

  The scan circuit generation unit 14 receives the FF categorized list 24 and the net list 22 and outputs a scanned net list 26 in which scans of different systems are inserted by the frequency-divided flip-flops and other flip-flops. Here, two systems of scan paths of frequency-divided flip-flops and other flip-flops are inserted. The scan connection order in the frequency-divided flip-flops and the scan connection order in flip-flops other than the frequency-divided flip-flops are arbitrary.

  The optimization unit 15 receives the delay constraint information 25 and the scanned netlist 26, performs logical optimization on the netlist, and creates a circuit that satisfies the delay constraint and the circuit design constraint. The optimized net list 27 is output.

  The hazard check unit 16 inputs the FF categorized list 24 and the optimized netlist 27, extracts a flip-flop targeted for the hazard check from the FF categorized list 24, and then checks whether there is a hazard for the optimized netlist 27. A check is made to see if there is any, and the result is output as a hazard report 28.

  On the other hand, the storage device 2 includes the RTL 21, the net list 22, the definator signal information 23, the FF categorized list 24, the delay constraint information 25, the scanned net list 26, the optimized net list 27, and the hazard. And a report 28.

  The RTL 21 is a digital circuit described in a hardware description language such as verilog or VHDL.

  The netlist 22 is obtained by converting the RTL 21 into a gate description using logic elements by the synthesis unit 11. At this time, logic optimization is not performed. Specifically, the net list 22 is expressed by, for example, Gate-Verilog.

  The definator signal information 23 is the name of the definator signal in the netlist 22. Matches one of the input ports present in the netlist 22.

  In the FF categorized list 24, the trace unit 12 uses all types of flip-flops in the net list 22 based on the net list 22 and the refiner signal information 23 as a definitive tree flip-flop, a frequency-dividing flip-flop, and a normal flip-flop. A table classified into Specifically, the FF categorization list 24 holds a list of names of flip-flops belonging to each category.

  The delay constraint information 25 holds a delay constraint for designing a refiner. The delay constraint is described by standard SDC (Synopsys Design Constraints), for example.

  The scanned netlist 26 is a circuit in which the netlist 22 is scanned by the scan circuit generation unit 14. Specifically, it has two paths, a frequency-dividing flip-flop and other flip-flops. Dividing the scan path in this way facilitates the test for the frequency-divided flip-flop.

  The optimized netlist 27 is obtained by logically optimizing the scanned netlist so that the optimization unit 15 satisfies the delay constraint information 25. By this logic optimization, logic optimization is performed in a divided clock cycle between frequency-divided flip-flops and in a normal one cycle cycle between other flip-flops.

  The hazard report 28 is a result of the hazard check unit 16 listing the hazard check target flip-flops from the FF categorized list 24 for the optimized netlist 27 and performing a hazard check on each of them.

  Next, the operation of the first embodiment of the present invention will be described. First, the designer creates the RTL 21. The RTL 21 is described in a hardware description language such as Verilog or VHDL. It is assumed that the RTL 21 includes a description of a refiner as shown in FIG.

  FIG. 2 shows an example of description in Verilog. In FIG. 2, when “XXCLK2G” as a clock signal and “XXDEF1G” as a definitive signal are input to the terminals, the definitive signal is in an enabled state. Only the circuit description is such that the clock signal is transmitted to each flip-flop. As a result, the clock signal can be divided at an arbitrary period. The synthesis unit 11 performs logic synthesis on the RTL 21 and outputs a net list 22.

  FIG. 3 shows an example of a circuit that can be obtained by logically synthesizing such an RTL having a refiner description. In FIG. 3, Rx is a frequency-dividing flip-flop, and Gx is an integrated gating cell. As shown in FIG. 3, in the netlist 22, the periphery of the refiner is realized by an integrated gating cell Gx. The integrated gating cell Gx is generally composed of a latch and an AND gate, and takes the role of transmitting the clock signal only when the enable signal is true by taking the AND logic of the enable signal and the clock signal. Bear. As shown in FIG. 3, the frequency-dividing flip-flop Rx is always connected to the integrated gating cell Gx. In addition, a multi-cycle path is formed between the flip-flops Rx driven by the refiner signal.

  FIG. 4 shows a specific example of the net list 22. In FIG. 4, R1 to RB are flip-flops, and G1 to G5 are integrated gating cells. The refiner signal is distributed by flip-flops R1, R2, and R3 to flip-flops R4, R5, R6, and R7 that are driven by the refiner. Usually, the refiner signal is distributed in this way in a tree of flip-flops in order to meet the design rules of the electrical circuit. For example, the flip-flop R4 is a flip-flop driven by the integrated gating cell G1.

  In FIG. 4, flip-flops R8, R9, RA, and RB are flip-flops that are unrelated to the definer. Of these flip-flops, the flip-flop RA is driven by the integrated gating cell G5, but this is not driven by a definator signal, but occurs as a result of normal clock gating. doing.

  Next, a description will be given of a process in which the trace unit 12 classifies flip-flops by using the netlist 22 and the definator signal information 23 as inputs.

  FIG. 5 is a flowchart showing a process in which the trace unit 12 classifies flip-flops. In FIG. 5, the trace unit 12 first extracts a terminal to be the source of the definator signal from the input terminals in the netlist 22 based on the definator signal information 23 (step S1), and extracts the terminal from the source terminal. Trace in the fan-out direction (step S2) and determine whether or not the flip-flop has been reached (step S3). Then, when reaching the flip-flop, the trace unit 12 adds the flip-flop as a refiner tree FF to the FF categorization list 24 (step S4). The trace in the fan-out direction is performed until reaching the gating cell (step S5), and when reaching the gating cell, the tracing unit 12 ends the tracing.

  By performing such tracing, the trace unit 12 can extract only the gating cell that drives the frequency-dividing flip-flop. The trace unit 12 adds the gating cell that drives the frequency-divided flip-flop to the FF categorization list 24 (step S6). Then, the trace unit 12 takes out the gating cells added to the FF categorization list 24 one by one, and acquires the first-stage flip-flop directly connected to the output of the gating cell that drives the division ratio. Then, the flip-flop is added to the FF categorization list 24 as a frequency-dividing flip-flop (step S8). This is based on a refiner design rule that the frequency-divided flip-flop is always connected as the first-stage flip-flop of the gating cell (see FIG. 3).

  Next, the trace unit 12 acquires all flip-flops in the netlist 22 (step S9), and from all the flip-flops, the refiner tree flip-flops and the frequency-divided FFs that have already been added to the FF categorization list 24. Is removed, and the rest is normally flip-flopped and added to the FF categorization list 24 (step S10). Then, the trace unit 12 outputs the FF categorization list 24 when these processes are completed.

  For example, it is assumed that the netlist 22 is configured as shown in FIG. 4 and the refiner signal information 23 is defined as shown in FIG. FIG. 6 shows that the terminal name of the refiner signal is “DEF”. The flip-flop categorization process in this case will be described.

  The trace unit 12 first traces the circuit in the fan-out direction from the terminal “DEF” described in the definator signal information 23 until it reaches the integrated gating cell, and the flip-flop that has passed during the trace is Final tree flip-flop. In FIG. 4, when tracing from the terminal “DEF” in the fan-out direction, the trace first reaches the flip-flop R1, then the flip-flop R2, and the flip-flop R3. Since the integrated gating cells G1, G2, and G3, G4 exist, the trace ends there, and the flip-flops R1, R2, R3 are registered in the FF categorization list 24 as the definitive tree flip-flops. (Steps S1 to S5).

  Next, the trace unit 12 traces the one-stage flip-flop from the integrated gating cells G1, G2, G3, and G4 acquired in the trace in the fan-out direction, and uses the acquired one as a frequency-dividing flip-flop. , Registered in the FF categorization list 24. Specifically, flip-flops R4, R5, R6, and R7 correspond to frequency-divided flip-flops (steps S6 to S7).

  Finally, the trace unit 12 starts from a whole set of flip-flops (flip-flops R1 to RB), a refiner tree flip-flop (flip-flops R1, R2, and R3), and a frequency-dividing flip-flop (flip-flops R4, R5, and R6). , R7) is extracted to extract a normal flip-flop and register it in the FF categorization list 24. Specifically, the flip-flops R8, R9, RA, and RB are normal flip-flops (steps S8 to S11).

  FIG. 7 shows the FF categorization list 24 after the tracing is finished. In this example, flip-flops R1, R2, and R3 are listed as definitive tree flip-flops, flip-flops R4, R5, R6, and R7 are listed as frequency division ratio flip-flops, and flip-flops R8, R9, RA, and RB are listed.

  Next, a process in which the delay constraint generating unit 13 inputs the FF categorized list 24 and generates the delay constraint information 25 will be described.

  Since the delay constraint has a period that is a constant multiple of the clock only between the frequency-divided flip-flops, the FF categorized list 24 is used to set the start point as a set of all frequency-divided flip-flops and the end point is also the frequency-divided flip-flop. A set of groups may be used. If this is described, for example, in the format of Synopsys Design Constraints, it is as shown in FIG. Although the method of specifying in a lump in this way is simple, it tries to constrain the path that does not actually exist, so if such specification is redundant or not allowed, referring to the netlist 22, There is also a method for deleting paths that do not actually exist.

  Next, a process in which the scan circuit generating unit 14 inputs the net list 22 and the FF categorized list 24 to generate the scanned net list 26 will be described.

  The scan path needs to be divided into two systems by a frequency-dividing flip-flop and other flip-flops. This is because the clock of the frequency-dividing flip-flop is distributed via the definer tree flip-flop and cannot be directly operated by an external tester.

  Therefore, the scan circuit generation unit 14 refers to the FF categorization list 24 and constructs a scan path composed of a refiner tree flip-flop and a normal flip-flop, and a scan path composed only of a frequency division flip-flop. .

  FIG. 9 shows a specific example of the scanned netlist 26 constructed in this way. In FIG. 9, a scan path SCAN1 is a scan path composed of a refiner tree flip-flop and a normal flip-flop, and a scan path SCAN2 is a scan path composed only of a frequency division flip-flop. From FIG. 9, another system scan is performed with the frequency-divided flip-flops (flip-flops R4, R5, R6, and R7) and the other flip-flops (flip-flops R1, R2, R3, R8, R9, RA, and RB). You can see that there is a route.

  Next, the optimization unit 15 inputs the delay constraint information 25 and the scanned netlist 26 and generates an optimized netlist 27. As for the logic optimization method here, this conversion method is described in “BoolDozer: Logic synthesis for ASICs, IBM Journal of R & D, February 6 1996 AJ Sullivan et al.”. As a result, the frequency-dividing flip-flops are optimized so that the delay constraint (clock cycle) is correctly driven with a constant multiplied between the flip-flops.

  Finally, the hazard check unit 16 inputs the optimized net list 27 and the FF categorized list 24 and outputs a hazard report 28. Here, it is assumed that the FF categorized list 24 is as shown in FIG. 7 and the optimized netlist 27 is as shown in FIG.

  There is a possibility that a static hazard occurs in a circuit in which a 1T path and an asynchronous path (here, a multi-cycle path) are mixed and enter an end-point flip-flop of the asynchronous path. When this idea is applied to a frequency-divided circuit, among the frequency-divided flip-flops (flip-flops R4, R5, R6, R7), the frequency-divided flip-flop and the normal flip-flop (or the refiner tree) are input to the input. A path in which flip-flops are mixed becomes a flip-flop to be subjected to a hazard check.

  Referring now to FIG. 6, flip-flops R4, R5, R6, and R7 are frequency-dividing flip-flops. Looking at the connection in FIG. 10 for each of these, the inputs of the flip-flop R4 are flip-flops RA and RB, both of which are normal flip-flops and are not checked flip-flops. . Next, only the flip-flop RB is input to the flip-flop R5, which is also a non-checked flip-flop. Next, the inputs of the flip-flop R6 are flip-flops R4 and R8, which are a flip-flop in which a normal flip-flop and a frequency-divided flip-flop are mixed, and this flip-flop R6 is one of the flip-flops subject to hazard check It is. Next, the inputs of the flip-flop R7 are flip-flops R4 and R5, both of which are frequency-divided flip-flops FF, so that they are not checked flip-flops. Therefore, the flip-flop R6 is the only flip-flop to perform the hazard check.

  Therefore, the hazard check unit 16 performs a hazard check only on the flip-flop R6 and outputs a hazard report 28. As the hazard check method, for example, the method described in Japanese Patent Application No. 2008-304099 can be used. If there is no problem with the flip-flop R6 as a result of the hazard check, as shown in FIG. 11, a hazard report indicating that there is no problem with the hazard check is output.

  As described above, in the embodiment of the present invention, when the circuit design using the clock divided by the flip-flop by the definer design is performed, the flip-flop in the netlist 22 is It is classified into a refiner tree flip-flop, a frequency-dividing flip-flop, and other normal flip-flops. Thus, by classifying the flip-flops, the delay constraint problem, the test problem, and the hazard check problem can be improved as follows.

  In other words, in the embodiment of the present invention, the delay constraint is generated by using the entire set of flip-flops classified as the frequency-divided flip-flops based on the information of the classified flip-flops as the start point and the end point. Sometimes it is not necessary to manually give delay constraints to the frequency-divided flip-flops, and the man-hours for the designer can be reduced, and the design can be prevented from being backtracked due to human error.

  In addition, based on the information of the classified flip-flops, a scan path netlist is generated by inserting a separate scan path between the frequency-divided flip-flops and other flip-flops. Since a full scan can be performed including the frequency-divided flip-flop, the detection rate is improved.

  Also, based on the information of the classified flip-flops, the flip-flops that are subject to the hazard check are extracted, and the presence or absence of the hazard is checked, so that the flip-flops that should be checked for hazards are automatically extracted. There is no need to manually extract the flip-flops to be checked, leading to a reduction in man-hours. In addition, since checking is performed comprehensively, there is no check omission due to human error, and as a result, malfunction due to static hazard in an actual machine can be prevented.

  The present invention is not limited to the above-described embodiments, and various modifications and applications can be made without departing from the gist of the present invention.

1: Data processing device 2: Storage device 11: Synthesis unit 12: Trace unit 13: Delay constraint generation unit 14: Scan circuit generation unit 15: Optimization unit 16: Hazard check unit 21: RTL
22: Net list 23: Definer signal information 24: Categorized list 25: Delay constraint information 26: Scanned net list 27: Optimized net list 28: Hazard report

Claims (10)

In a circuit design apparatus that creates a tree using flip-flops and realizes an environment of a plurality of clocks in a pseudo manner using clocks divided by the flip-flops,
A means for classifying the flip-flops in the netlist into a definitive tree flip-flop, a frequency-dividing flip-flop, and a normal flip-flop with reference to the netlist and the definitive signal information; Circuit design equipment. The means for classifying the flip-flops is:
Based on the definator signal information, tracing from the terminal to be the source of the definator signal in the fan-out direction, and when the flip-flop is reached, means for adding the flip-flop to the list as a definitive tree flip-flop;
The flip-flop directly connected to the output of the gating cell that drives the division ratio is obtained, and the flip-flop that is directly connected to the gating cell that drives the division ratio is used as the division flip-flop. Means to add to,
Means for removing the refiner tree flip-flops and the frequency-dividing flip-flops already added to the list from all the flip-flop groups, and adding the remaining flip-flops to the list by performing normal flip-flops; The circuit design device according to claim 1 , comprising:   3. The apparatus according to claim 1, further comprising means for generating a delay constraint using a set of flip-flops classified as the frequency-divided flip-flop as a start point and an end point based on information on the classified flip-flops. The circuit design device described in 1.   And a means for generating a scanned netlist by inserting scan paths of different systems between the frequency-divided flip-flop and the other flip-flops based on the classified flip-flop information. The circuit design device according to any one of claims 1 to 3.   5. The circuit design according to claim 1, further comprising means for extracting a hazard check target flip-flop and checking whether there is a hazard or not based on the classified flip-flop information. apparatus. A circuit design method for a circuit design device that creates a tree using flip-flops and realizes an environment of a plurality of clocks in a pseudo manner using clocks divided by the flip-flops ,
The classification means of the circuit design device refers to the netlist and the refiner signal information, and converts the flip-flops in the netlist into a refiner tree flip-flop, a frequency-dividing flip-flop, and a normal flip-flop. A circuit design method characterized by classification. Classification means of the circuit design device for classifying the flip-flops,
Based on the definator signal information, trace in the fanout direction from the terminal that should be the source of the definator signal, and when it reaches the flip-flop, add the flip-flop to the list as a definator tree flip-flop,
The flip-flop directly connected to the output of the gating cell that drives the division ratio is obtained, and the flip-flop that is directly connected to the gating cell that drives the division ratio is used as the division flip-flop. Add to
The refiner tree flip-flop and the frequency-divided flip-flop that have already been added to the list are removed from all the flip-flop groups, and the remaining flip-flops are added to the list as normal flip-flops. The circuit design method according to claim 6. Furthermore, delay constraint generator of the circuit design apparatus based on the information of the flip-flop which is the classification, to generate a delay constraint a set of classified flip-flop as the division of the flip-flop as a start point and an end point Turkey The circuit design method according to claim 6, wherein: Further, the net list generation means of the circuit design device has already been scanned by inserting a separate system scan path between the frequency-divided flip-flop and the other flip-flops based on the classified flip-flop information. circuit design method according to any of claims 6 8, wherein the benzalkonium to generate a netlist. Additionally, hazard presence checking means of the circuit design apparatus based on the information of the flip-flops and the classification, and performs checking whether there is a presence of hazards to extract the hazard checked flip-flop The circuit design method according to claim 6.

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