JP2008053758A - 半導体集積回路装置 - Google Patents

半導体集積回路装置 Download PDF

Info

Publication number
JP2008053758A
JP2008053758A JP2007292929A JP2007292929A JP2008053758A JP 2008053758 A JP2008053758 A JP 2008053758A JP 2007292929 A JP2007292929 A JP 2007292929A JP 2007292929 A JP2007292929 A JP 2007292929A JP 2008053758 A JP2008053758 A JP 2008053758A
Authority
JP
Japan
Prior art keywords
wiring
plug
film
insulating film
integrated circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2007292929A
Other languages
English (en)
Japanese (ja)
Other versions
JP2008053758A5 (enExample
Inventor
Takako Fujii
貴子 藤井
Hidekazu Murakami
英一 村上
Kazumasa Yanagisawa
一正 柳沢
Miki Takeuchi
幹 竹内
Hideo Aoki
英雄 青木
Hide Yamaguchi
日出 山口
Takafumi Oshima
隆文 大島
Kazuyuki Tsukuni
和之 津国
Kosuke Okuyama
幸祐 奥山
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Renesas Technology Corp
Original Assignee
Renesas Technology Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Renesas Technology Corp filed Critical Renesas Technology Corp
Priority to JP2007292929A priority Critical patent/JP2008053758A/ja
Publication of JP2008053758A publication Critical patent/JP2008053758A/ja
Publication of JP2008053758A5 publication Critical patent/JP2008053758A5/ja
Pending legal-status Critical Current

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
JP2007292929A 2007-11-12 2007-11-12 半導体集積回路装置 Pending JP2008053758A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2007292929A JP2008053758A (ja) 2007-11-12 2007-11-12 半導体集積回路装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2007292929A JP2008053758A (ja) 2007-11-12 2007-11-12 半導体集積回路装置

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
JP2002181974A Division JP2004031439A (ja) 2002-06-21 2002-06-21 半導体集積回路装置およびその製造方法

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2009099263A Division JP2009158987A (ja) 2009-04-15 2009-04-15 半導体集積回路装置

Publications (2)

Publication Number Publication Date
JP2008053758A true JP2008053758A (ja) 2008-03-06
JP2008053758A5 JP2008053758A5 (enExample) 2008-08-14

Family

ID=39237422

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2007292929A Pending JP2008053758A (ja) 2007-11-12 2007-11-12 半導体集積回路装置

Country Status (1)

Country Link
JP (1) JP2008053758A (enExample)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08316330A (ja) * 1995-05-12 1996-11-29 Hitachi Ltd 半導体集積回路のレイアウト方法
JP2001337440A (ja) * 2000-03-24 2001-12-07 Toshiba Corp 半導体集積回路のパターン設計方法、フォトマスク、および半導体装置

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08316330A (ja) * 1995-05-12 1996-11-29 Hitachi Ltd 半導体集積回路のレイアウト方法
JP2001337440A (ja) * 2000-03-24 2001-12-07 Toshiba Corp 半導体集積回路のパターン設計方法、フォトマスク、および半導体装置

Similar Documents

Publication Publication Date Title
US8093723B2 (en) Method of manufacturing a semiconductor integrated circuit device
US6498089B2 (en) Semiconductor integrated circuit device with moisture-proof ring and its manufacture method
US20060205204A1 (en) Method of making a semiconductor interconnect with a metal cap
EP1146558B1 (en) Semiconductor device with damascene wiring structure and method of its fabrication
US12119262B2 (en) Semiconductor device structure with resistive element
TWI793522B (zh) 半導體裝置及其形成方法
US9553017B2 (en) Methods for fabricating integrated circuits including back-end-of-the-line interconnect structures
US6346475B1 (en) Method of manufacturing semiconductor integrated circuit
US10832946B1 (en) Recessed interconnet line having a low-oxygen cap for facilitating a robust planarization process and protecting the interconnect line from downstream etch operations
US20090166868A1 (en) Semiconductor devices including metal interconnections and methods of fabricating the same
US8941182B2 (en) Buried sublevel metallizations for improved transistor density
US9589890B2 (en) Method for interconnect scheme
US9406883B1 (en) Structure and formation method of memory device
JP2009158987A (ja) 半導体集積回路装置
JP5310721B2 (ja) 半導体装置とその製造方法
JP2008053758A (ja) 半導体集積回路装置
CN112490357A (zh) 半导体组件及其制造方法
KR20060107694A (ko) 반도체 소자의 제조방법

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20080702

A711 Notification of change in applicant

Free format text: JAPANESE INTERMEDIATE CODE: A712

Effective date: 20100528

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20110712

A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20111115