JP2008048445A - Transmission line substrate and semiconductor package - Google Patents

Transmission line substrate and semiconductor package Download PDF

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JP2008048445A
JP2008048445A JP2007245847A JP2007245847A JP2008048445A JP 2008048445 A JP2008048445 A JP 2008048445A JP 2007245847 A JP2007245847 A JP 2007245847A JP 2007245847 A JP2007245847 A JP 2007245847A JP 2008048445 A JP2008048445 A JP 2008048445A
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transmission line
substrate
line
signal line
signal
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JP4516101B2 (en
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Takuya Suzuki
拓也 鈴木
Teruo Furuya
輝雄 古屋
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Mitsubishi Electric Corp
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Mitsubishi Electric Corp
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Abstract

<P>PROBLEM TO BE SOLVED: To suppress leakage of unwanted wave components to the outside inside a high frequency package, and to efficiently perform power attenuation and absorption of unwanted waves, without adverse effects upon transmission characteristics, such as required DC bias voltage, control signal or intermediate frequency signal. <P>SOLUTION: A transmission line substrate includes a transmission line for transmitting a drive control signal input to/output from a semiconductor device and forms the transmission line as a triplate line, disposing ground conductors in the upper and the lower layers of a signal line. The transmission line substrate comprises a tip open stab 70, which is connected in parallel with the signal line and has a length of an odd multiple of approximately 1/4 in-substrate effective wavelength of unwanted waves in the microwave band and the millimeter-wave band; a coupling slot 75 which is formed in the grounding conductors of the upper and the lower layers or in the grounding conductor of either the upper or the lower layers at a connecting position of the tip open stab 70 and the signal line, and is coupled to the signal line by opening standing wave distribution in the vicinity of the connecting position; and a resistor 80 provided in at least a portion on the coupling slot 75. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

本発明は、マイクロ波帯またはミリ波帯などの高周波帯で動作する半導体デバイスに対し入出力する信号を伝送する伝送線路基板および半導体パッケージに関し、さらに詳しくは半導体デバイスで発生される高周波信号のパッケージ外部への漏洩を効率よく抑止することが可能な伝送線路基板および半導体パッケージに関するものである。   The present invention relates to a transmission line substrate and a semiconductor package for transmitting signals to and from a semiconductor device operating in a high frequency band such as a microwave band or a millimeter wave band, and more particularly to a package of a high frequency signal generated in a semiconductor device. The present invention relates to a transmission line substrate and a semiconductor package that can efficiently suppress leakage to the outside.

マイクロ波帯またはミリ波帯などの高周波帯で動作する半導体デバイスが搭載される高周波パッケージにおいては、高周波パッケージに形成された外部端子と半導体デバイスの入出力端子との間を多層誘電体基板内に形成された表層信号線路や内層信号線路によって接続している。これらの線路によって、所望の高周波信号を入出力する他、半導体デバイスに対しＤＣバイアス電圧、制御信号などを入出力するようにしている。 In a high-frequency package in which a semiconductor device that operates in a high-frequency band such as a microwave band or a millimeter-wave band is mounted, a space between an external terminal formed in the high-frequency package and an input / output terminal of the semiconductor device is within a multilayer dielectric substrate. They are connected by the formed surface layer signal line and inner layer signal line. In addition to inputting and outputting a desired high-frequency signal, these lines input and output a DC bias voltage, a control signal, and the like to the semiconductor device.

高周波パッケージ内において、高周波帯で動作する半導体デバイスは、その周りが、カバー、シーリング、接地導体面などにより遮蔽されているが、半導体デバイスの入出力端子から伝導的に漏洩する不要波としての高周波信号（不要信号）が、ＤＣバイアス電圧や制御信号等の入出力用の信号線路を介して外部に放射されるという問題がある。このため、この種の高周波パッケージにおいては、各種の電波法のＥＭＩ規格を満足するのが非常に困難な状況下にある。   In a high-frequency package, a semiconductor device that operates in a high-frequency band is shielded by a cover, ceiling, ground conductor surface, etc., but the high-frequency as an unnecessary wave leaking conductively from the input / output terminals of the semiconductor device There is a problem that a signal (unnecessary signal) is radiated to the outside through a signal line for input / output of a DC bias voltage, a control signal, or the like. Therefore, in this type of high-frequency package, it is very difficult to satisfy EMI standards of various radio wave laws.

このような高周波パッケージが含まれる機器モジュール全体を金属カバーで覆うことも考えられるが、この場合は、高価な筐体等が必要となるため、低コスト化のためにも、高周波パッケージ内で、上記のＥＭＩ規格を満足するような対策が望まれる。   Although it is conceivable to cover the entire device module including such a high-frequency package with a metal cover, in this case, an expensive housing or the like is required, so in order to reduce the cost, Measures that satisfy the above EMI standards are desired.

特許文献１では、誘電体基板の表面に、高周波部品搭載部と、高周波部品の高周波端子と接続される高周波用伝送回路と、高周波部品の電源端子と接続される電源回路とが形成された配線基板において、電源回路の中の電源線路やビアホール導体を、比透磁率が８０以上、電気抵抗率が１．０（μΩｍ）以下、Ｆｅ、Ｃｏ、Ｎｉの少なくとも１種を含有する高透磁率低抵抗体で形成することによって、不要高周波信号を吸収するようにした従来技術が開示されている。   In Patent Document 1, a wiring in which a high-frequency component mounting portion, a high-frequency transmission circuit connected to a high-frequency terminal of a high-frequency component, and a power supply circuit connected to a power supply terminal of the high-frequency component are formed on the surface of a dielectric substrate. In the substrate, the power line and the via-hole conductor in the power circuit have a low magnetic permeability that includes a relative permeability of 80 or more, an electric resistivity of 1.0 (μΩm) or less, and at least one of Fe, Co, and Ni. The prior art which absorbs an unnecessary high frequency signal by forming with a resistor is disclosed.

特開２００４−３９７３９号公報JP 2004-39739 A

上記従来技術の場合、内層信号線路に直列に抵抗体を接続していることと等価であり、内層信号線路を伝搬する不要波のみを減衰、吸収するという対処がなされていないので、内層信号線路を介してＤＣバイアスを通過させる場合、少なからず電圧降下が発生して、ＤＣバイアスの伝送特性に悪影響を与えるという問題もある。   In the case of the above prior art, it is equivalent to connecting a resistor in series with the inner layer signal line, and there is no countermeasure to attenuate and absorb only unnecessary waves propagating through the inner layer signal line. When the DC bias is passed through the DC bias, there is a problem that a voltage drop occurs and the transmission characteristics of the DC bias are adversely affected.

本発明は、上記に鑑みてなされたものであって、外部への不要波成分の漏洩を高周波パッケージ内で抑止することができるとともに、必要なＤＣバイアス電圧、制御信号あるいは中間周波数信号などの伝送特性に悪影響を与えることなく、不要波を効率よく電力減衰、吸収することが可能な伝送線路基板および半導体パッケージを得ることを目的とする。   The present invention has been made in view of the above, and it is possible to suppress leakage of unnecessary wave components to the outside in the high frequency package, and transmission of necessary DC bias voltage, control signal, intermediate frequency signal or the like. An object of the present invention is to obtain a transmission line substrate and a semiconductor package capable of efficiently attenuating and absorbing unnecessary waves without adversely affecting the characteristics.

上述した課題を解決し、目的を達成するために、本発明は、半導体デバイスに入出力される駆動制御信号を伝送する伝送線路を有し、信号線路の上下層に接地導体を配置したトリプレート線路として伝送線路を形成した伝送線路基板において、前記信号線路に並列に接続され、マイクロ波帯及びミリ波帯の不要波の基板内実効波長の略１／４の奇数倍の長さを有する先端開放スタブと、該先端開放スタブと信号線路との接続位置の上下層、あるいは上下層のいずれか一方の接地導体に形成され、前記接続位置の周辺で定在波分布が開放となって前記信号線路と結合する結合スロットと、該結合スロット上の少なくとも一部に設けられた抵抗体とを備えることを特徴とする。   In order to solve the above-mentioned problems and achieve the object, the present invention has a transmission line for transmitting a drive control signal inputted to and outputted from a semiconductor device, and a triplate in which ground conductors are arranged on the upper and lower layers of the signal line. A transmission line substrate in which a transmission line is formed as a line, and a tip that is connected in parallel to the signal line and has a length that is an odd multiple of about 1/4 of the effective wavelength in the substrate of unnecessary waves in the microwave band and millimeter wave band. An open stub and the ground conductor at one of the upper and lower layers or the upper and lower layers of the connection position between the open-ended stub and the signal line, and the standing wave distribution is open around the connection position, and the signal It is characterized by comprising a coupling slot coupled to the line and a resistor provided in at least a part of the coupling slot.

以上説明したとおり、この発明によれば、先端開放スタブおよび結合スロットを配置することにより、内層信号線路を伝送する不要波を結合スロットに効率よく結合させ、結合スロットに結合された不要波を結合スロット上の少なくとも一部に設けられた抵抗体で効率よく減衰、吸収させることができる。したがって、ＤＣバイアス電圧、制御信号あるいはＩＦ信号などの駆動制御信号の伝送特性に悪影響を与えることなく、不要波のみを効率よく減衰、吸収させることが可能となり、これにより、不要波が高周波パッケージの外部に放射されることを抑制することができ、高周波パッケージ単体で高周波信号（不要波）の放射を抑制することができる。   As described above, according to the present invention, by disposing the open end stub and the coupling slot, the unnecessary wave transmitted through the inner layer signal line can be efficiently coupled to the coupling slot, and the unnecessary wave coupled to the coupling slot is coupled. It can be attenuated and absorbed efficiently by a resistor provided in at least a part of the slot. Therefore, it is possible to efficiently attenuate and absorb only the unnecessary wave without adversely affecting the transmission characteristics of the drive control signal such as the DC bias voltage, the control signal, or the IF signal. Radiation to the outside can be suppressed, and radiation of high-frequency signals (unnecessary waves) can be suppressed with a single high-frequency package.

以下に、本発明にかかる伝送線路基板及び半導体パッケージの実施の形態を図面に基づいて詳細に説明する。なお、この実施の形態によりこの発明が限定されるものではない。   Hereinafter, embodiments of a transmission line substrate and a semiconductor package according to the present invention will be described in detail with reference to the drawings. Note that the present invention is not limited to the embodiments.

実施の形態１．
図１〜図３はこの発明にかかる半導体パッケージ１を示すものである。この発明は、任意の周波数帯で動作する半導体デバイス（半導体ＩＣ）が搭載された半導体パッケージに適用可能であるが、ここではマイクロ波帯、ミリ波帯などの高周波帯で動作する複数の高周波半導体デバイス（ＭＭＩＣ、以下高周波デバイスと略す）が搭載される半導体パッケージ（以下、高周波パッケージという）１に本発明を適用した場合を示している。半導体パッケージ１は、例えば、ＦＭ−ＣＷレーダに適用して好適である。 Embodiment 1 FIG.
1 to 3 show a semiconductor package 1 according to the present invention. The present invention can be applied to a semiconductor package on which a semiconductor device (semiconductor IC) that operates in an arbitrary frequency band is mounted. Here, a plurality of high-frequency semiconductors that operate in a high-frequency band such as a microwave band and a millimeter-wave band. A case where the present invention is applied to a semiconductor package (hereinafter referred to as a high frequency package) 1 on which a device (MMIC, hereinafter abbreviated as a high frequency device) is mounted is shown. The semiconductor package 1 is suitable for application to FM-CW radar, for example.

なお、ＦＭ−ＣＷレーダは、周知のように、前方に向けて放射した電波が目標物（先行車両）にあたって反射してくる受信波と送信波との差からビート周波数を求め、そのビート周波数を使って目標までの距離および相対速度を算出するものである。   As is well known, the FM-CW radar obtains the beat frequency from the difference between the received wave and the transmitted wave that the radio wave radiated forward reflects on the target (preceding vehicle), and calculates the beat frequency. It is used to calculate the distance to the target and the relative speed.

図１〜図３に示す高周波パッケージ１では、接地されている金属製のキャリア２０（図４参照）上に、多層誘電体基板２が搭載されている。多層誘電体基板２上には、金属製の枠形状のシールリング４が気密性を有してハンダや銀ろうなどのろう材で接合され、さらにシールリング４上には蓋体としてのカバー５が溶接接合されている。図１の例ではシールリング４として、２つの貫通穴（６００）が設けられた日の字型の枠体を示している。   In the high-frequency package 1 shown in FIGS. 1 to 3, a multilayer dielectric substrate 2 is mounted on a grounded metal carrier 20 (see FIG. 4). A metal frame-shaped seal ring 4 is hermetically sealed on the multilayer dielectric substrate 2 and is joined with a brazing material such as solder or silver solder. Further, a cover 5 as a lid is formed on the seal ring 4. Are welded together. In the example of FIG. 1, as a seal ring 4, a Japanese character frame having two through holes (600) is shown.

シールリング４およびカバー５の接合によって、多層誘電体基板２上に設けられた複数の高周波デバイス３は気密封止される。また、シールリング４およびカバー５は、多層誘電体基板２上に設けられた複数の高周波デバイス３から外部への不要放射をシールドする。すなわち、シールリング４およびカバー５によって、多層誘電体基板２の表層の一部および高周波デバイス３を覆う電磁シールド部材を構成している。なお、電磁シールドの構成は、この限りではなく、多層誘電体基板２の表面や内層に設けられた後述する接地導体や接地された複数のビア等の他、様々な構成要素が含まれる。   By joining the seal ring 4 and the cover 5, the plurality of high-frequency devices 3 provided on the multilayer dielectric substrate 2 are hermetically sealed. Further, the seal ring 4 and the cover 5 shield unnecessary radiation from the plurality of high frequency devices 3 provided on the multilayer dielectric substrate 2. That is, the seal ring 4 and the cover 5 constitute an electromagnetic shield member that covers a part of the surface layer of the multilayer dielectric substrate 2 and the high-frequency device 3. The configuration of the electromagnetic shield is not limited to this, and includes various components in addition to a later-described ground conductor and a plurality of grounded vias provided on the surface and inner layer of the multilayer dielectric substrate 2.

図２，図３に示すように、多層誘電体基板２上には、高周波デバイス３を搭載するための１〜複数の凹部（以下、ＩＣ搭載凹部という）６が形成されている。ＩＣ搭載凹部は多層誘電体基板２の上位層にキャビティ（空洞）を形成し、キャビティはＩＣ搭載凹部６の側壁６ａによって囲まれる。ＩＣ搭載凹部の底面（キャビティ底面）には、その表面に接地導体１６が形成されている。ＩＣ搭載凹部６上には、電圧制御発振器（ＶＣＯ）、増幅器、電力分配器、逓倍器、ミクサなどの複数の高周波デバイス３が収容され、高周波デバイス３は接地導体１６にハンダやろう材あるいは樹脂接着剤等の接合材１７で接合されている。   As shown in FIGS. 2 and 3, on the multilayer dielectric substrate 2, one to a plurality of recesses (hereinafter referred to as IC mounting recesses) 6 for mounting the high frequency device 3 are formed. The IC mounting recess forms a cavity in the upper layer of the multilayer dielectric substrate 2, and the cavity is surrounded by the side wall 6 a of the IC mounting recess 6. A ground conductor 16 is formed on the bottom surface (cavity bottom surface) of the IC mounting recess. A plurality of high-frequency devices 3 such as a voltage controlled oscillator (VCO), an amplifier, a power divider, a multiplier, and a mixer are accommodated on the IC mounting recess 6, and the high-frequency device 3 is soldered, brazed, or resin to the ground conductor 16. Bonded with a bonding material 17 such as an adhesive.

また、図３に示すように、シールリング４の２つの貫通穴６００の内側には、それぞれＩＣ搭載凹部６が配置されている。各ＩＣ搭載凹部６には複数の高周波デバイス３が配置されている。シールリング４の２つの貫通穴６００を画成するシールリング４´の下部には、フィードスルー７が設けられている。すなわち、上側のＩＣ搭載凹部６に収容された高周波デバイス３と下側のＩＣ搭載凹部６に収容された高周波デバイス３との間は、フィードスルー７およびマイクロストリップ線路８によって接続されている。フィードスルー７は、信号ピンあるいはマイクロストリップ線路を誘電体で覆うように構成され、これにより各ＩＣ搭載凹部６では気密状態を保持したまま、２つのＩＣ搭載凹部６間で高周波信号が伝送される。マイクロストリップ線路８は多層誘電体基板２の表層に配置され、フィードスルー７に接続されている。高周波デバイス３に設けられた導体パッドとマイクロストリップ線路８とは、ワイヤ１２００によって、ワイヤボンディング接続されている。   Further, as shown in FIG. 3, IC mounting recesses 6 are respectively arranged inside the two through holes 600 of the seal ring 4. A plurality of high-frequency devices 3 are arranged in each IC mounting recess 6. A feedthrough 7 is provided below the seal ring 4 ′ that defines the two through holes 600 of the seal ring 4. That is, the high frequency device 3 accommodated in the upper IC mounting recess 6 and the high frequency device 3 accommodated in the lower IC mounting recess 6 are connected by the feedthrough 7 and the microstrip line 8. The feedthrough 7 is configured to cover the signal pin or the microstrip line with a dielectric, whereby a high frequency signal is transmitted between the two IC mounting recesses 6 while keeping the airtight state in each IC mounting recess 6. . The microstrip line 8 is disposed on the surface layer of the multilayer dielectric substrate 2 and connected to the feedthrough 7. The conductor pads provided in the high-frequency device 3 and the microstrip line 8 are connected by wire bonding with a wire 1200.

多層誘電体基板２の表層には、表層接地導体としての接地導体１８が設けられグランド面で覆われている。接地導体１８は、多層誘電体基板２におけるＩＣ搭載凹部６の周囲に形成された複数のグランドビア（側壁グランドビアという）３０ａにより、半導体デバイス実装面の接地導体１６と接続され、同電位となっている。これら側壁グランドビア３０ａの間隔は、不要波である高周波パッケージ１内にて使用する高周波信号の基板内実効波長λｇの１／２未満の値として設定しており、これによりＩＣ搭載凹部６の側壁６ａを介した多層誘電体基板２内への不要波の進入を抑制し、上述したシールリング４、カバー５とにより立体的に電磁シールドを形成している。   A ground conductor 18 as a surface ground conductor is provided on the surface layer of the multilayer dielectric substrate 2 and is covered with a ground surface. The ground conductor 18 is connected to the ground conductor 16 on the semiconductor device mounting surface by a plurality of ground vias (referred to as side wall ground vias) 30a formed around the IC mounting recess 6 in the multilayer dielectric substrate 2, and has the same potential. ing. The interval between the side wall ground vias 30a is set to a value less than ½ of the effective wavelength λg in the substrate of the high frequency signal used in the high frequency package 1 which is an unnecessary wave. The entrance of unnecessary waves into the multilayer dielectric substrate 2 via 6a is suppressed, and the above-described seal ring 4 and cover 5 form a three-dimensional electromagnetic shield.

シールリング４の内側の多層誘電体基板２の表層には、高周波デバイス３にＤＣバイアス電圧を供給したり、あるいは高周波デバイス３との間で制御信号（ＤＣ領域に近い低周波信号）や高周波デバイス３から出力されるＩＦ信号（中間周波数帯の信号）を入出力するための導体パッド（以下、内部導体パッドという）１０が設けられている。これらＤＣバイアス電圧、制御信号、ＩＦ信号を総称して、高周波デバイス３の「駆動制御信号」ということにする。高周波デバイス３側にも、駆動制御信号入出力パッド１１（以下、導体パッド）が設けられている。内部導体パッド１０と導体パッド１１とは、金などで構成されるワイヤ１２によってワイヤボンディング接続されている。なお、ワイヤ１２による接続に代えて、金属バンプあるいはリボンによってこれらの接続をとるようにしてもよい。   On the surface of the multilayer dielectric substrate 2 inside the seal ring 4, a DC bias voltage is supplied to the high frequency device 3, or a control signal (low frequency signal close to the DC region) or a high frequency device is connected to the high frequency device 3. 3 is provided with a conductor pad (hereinafter referred to as an internal conductor pad) 10 for inputting and outputting an IF signal (intermediate frequency band signal) output from 3. These DC bias voltage, control signal, and IF signal are collectively referred to as a “drive control signal” of the high-frequency device 3. A drive control signal input / output pad 11 (hereinafter referred to as a conductor pad) is also provided on the high frequency device 3 side. The internal conductor pad 10 and the conductor pad 11 are connected by wire bonding with a wire 12 made of gold or the like. In addition, it may replace with the connection by the wire 12 and you may make it take these connections by a metal bump or a ribbon.

シールリング４の外側の多層誘電体基板２上には、外部端子としての複数の導体パッド（以下、外部導体パッドという）１５が設けられている。外部導体パッド１５は、多層誘電体基板２内に形成された、後述する信号ビア（信号スルーホール）及び内層信号線路を介してシールリング４の内側の多層誘電体基板２上に設けられた内部導体パッド１０とＤＣ的に接続されている。これらの外部導体パッド１５は、ワイヤ等を介して、図示しない、電源回路基板、制御基板などに接続される。   On the multilayer dielectric substrate 2 outside the seal ring 4, a plurality of conductor pads (hereinafter referred to as “external conductor pads”) 15 as external terminals are provided. The external conductor pad 15 is an internal portion provided on the multilayer dielectric substrate 2 inside the seal ring 4 via a signal via (signal through hole) and an inner layer signal line, which will be described later, formed in the multilayer dielectric substrate 2. The conductor pad 10 is connected in a DC manner. These external conductor pads 15 are connected to a power circuit board, a control board, etc. (not shown) through wires or the like.

図４は、高周波パッケージ１の多層誘電体基板２内のビア構造（スルーホール構造）を示すものであり、多層誘電体基板２は、接地されている金属製のキャリア２０に設けられている。図４においては、ＤＣバイアス電圧、制御信号、ＩＦ信号等の駆動制御信号が伝送される駆動制御信号用ビア（以下信号ビアという）４０は、白抜きで示し、グランドビア３０（３０ａ，３０ｂ，…）はハッチング付きで示している。   FIG. 4 shows a via structure (through-hole structure) in the multilayer dielectric substrate 2 of the high-frequency package 1, and the multilayer dielectric substrate 2 is provided on a metal carrier 20 that is grounded. In FIG. 4, drive control signal vias 40 (hereinafter referred to as signal vias) 40 to which drive control signals such as DC bias voltage, control signals, and IF signals are transmitted are shown in white and ground vias 30 (30a, 30b, (...) is shown with hatching.

この場合、多層誘電体基板２は第１層〜第６層の６層構造を有しており、多層誘電体基板２の第１層および第２層の中央部が削除されることによって、前述のＩＣ搭載凹部６が形成されている。ＩＣ搭載凹部６の底面、すなわち第３層の表面には、表層接地導体としてのグランド面１６が形成されており、このグランド面１６に半田１７（または導電性接着剤）を介して高周波デバイス３が搭載される。高周波デバイス３の下に配置されるグランド面１６とキャリア２０との間は、複数のグランドビア３０ｂで接続されており、これらのグランドビア３０ｂは放熱のためのサーマルビアの機能も有している。   In this case, the multilayer dielectric substrate 2 has a six-layer structure of first to sixth layers, and the central portions of the first and second layers of the multilayer dielectric substrate 2 are deleted, so that The IC mounting recess 6 is formed. A ground surface 16 as a surface layer ground conductor is formed on the bottom surface of the IC mounting recess 6, that is, the surface of the third layer, and the high-frequency device 3 is connected to the ground surface 16 with solder 17 (or conductive adhesive). Is installed. The ground surface 16 disposed under the high frequency device 3 and the carrier 20 are connected by a plurality of ground vias 30b, and these ground vias 30b also have a thermal via function for heat dissipation. .

ＩＣ搭載凹部６の側壁（多層誘電体基板２の第１〜第２層の側壁面）６ａは、この場合は、誘電体が露出された状態にある。しかし、前述したように、ＩＣ搭載凹部６の周囲および内部導体パッド１０には、複数の側壁グランドビア３０ａが形成されており、これら側壁グランドビア３０ａによって側壁６ａを介した多層誘電体基板２内への不要波の進入を抑制している。側壁グランドビア３０ａは、多層誘電体基板２の第１層の表層に形成されたグランドパターン１８とキャリア２０とを接続している。多層誘電体基板２の第１層の表層には、複数の内部導体パッド１０が設けられているが、これら内部導体パッド１０の周囲の誘電体が露出された部分１９（図３参照）以外は、表層接地導体としてのグランドパターン１８が形成されており、表層を介して多層誘電体基板２の内部に不要波が進入することを防止している。   In this case, the side walls (side wall surfaces of the first and second layers of the multilayer dielectric substrate 2) 6a of the IC mounting recess 6 are in a state where the dielectric is exposed. However, as described above, a plurality of side wall ground vias 30a are formed around the IC mounting recess 6 and the inner conductor pad 10, and the side wall ground vias 30a allow the inside of the multilayer dielectric substrate 2 via the side walls 6a. To prevent unwanted waves from entering the car. The side wall ground via 30 a connects the ground pattern 18 formed on the surface layer of the first layer of the multilayer dielectric substrate 2 and the carrier 20. A plurality of internal conductor pads 10 are provided on the surface layer of the first layer of the multilayer dielectric substrate 2 except for the portion 19 (see FIG. 3) where the dielectric around the internal conductor pads 10 is exposed. A ground pattern 18 as a surface layer ground conductor is formed to prevent unwanted waves from entering the multilayer dielectric substrate 2 through the surface layer.

前述したように、多層誘電体基板２上には、シールリング４が搭載され、さらにシールリング４上には蓋体としてのカバー５が設けられている。このように、多層誘電体基板２上における高周波デバイス３の実装エリアには、シールリング４，カバー５などの電磁シールド部材によって気密のキャビティ３３が形成されており、このキャビティ３３は、シールリング４，カバー５などの電磁シールド部材と、グランド面１６，グランドパターン１８などの表層接地導体と、複数の側壁グランドビア３０ａなどによって、電気的に外部と遮蔽されている。なお、複数の側壁グランドビア３０ａの代わりに、ＩＣ搭載凹部６の側壁６ａをメタライズして側壁６ａにグランド面を形成するようにしてもよい。   As described above, the seal ring 4 is mounted on the multilayer dielectric substrate 2, and the cover 5 as a lid is provided on the seal ring 4. Thus, in the mounting area of the high-frequency device 3 on the multilayer dielectric substrate 2, an airtight cavity 33 is formed by an electromagnetic shield member such as the seal ring 4 and the cover 5. , And an electromagnetic shield member such as the cover 5, a surface layer ground conductor such as the ground surface 16 and the ground pattern 18, and a plurality of side wall ground vias 30 a and the like. Instead of the plurality of sidewall ground vias 30a, the sidewall 6a of the IC mounting recess 6 may be metallized to form a ground surface on the sidewall 6a.

多層誘電体基板２のシールリング４の直下近傍には、高周波デバイス３から発生する不要波をシールドするための複数の（この場合３列）グランドビア（ＲＦシールドビア）３０ｃが設けられている。これらのグランドビア３０，３０ａ，３０ｂ，３０ｃは、表層接地導体、接地されたキャリア２０、あるいは多層誘電体基板２の内層に形成される内層接地導体３５に適宜接続されている。内層接地導体３５は、基本的には、ベタグランド層として全ての層間に設けられている。   A plurality of (in this case, three rows) ground vias (RF shield vias) 30 c for shielding unwanted waves generated from the high-frequency device 3 are provided in the vicinity of the multilayer dielectric substrate 2 immediately below the seal ring 4. These ground vias 30, 30 a, 30 b, 30 c are appropriately connected to a surface layer ground conductor, a grounded carrier 20, or an inner layer ground conductor 35 formed in the inner layer of the multilayer dielectric substrate 2. The inner layer ground conductor 35 is basically provided between all the layers as a solid ground layer.

シールリング４の内側に配置される内部導体パッド１０は、１〜複数の信号ビア４０および１〜複数の内層信号線路４５を介してシールリング４の外側に配置される外部導体パッド１５と接続されている。図４では、明示されていないが、信号ビア４０、内層信号線路４５の周囲には、誘電体を挟んで複数のグランドビア３０が配されており、これら複数のグランドビア３０によるシールドによって、信号ビア４０、内層信号線路４５からの不要波の放射、周囲からの不要波の結合を抑制している。   The inner conductor pad 10 disposed inside the seal ring 4 is connected to the outer conductor pad 15 disposed outside the seal ring 4 through one to a plurality of signal vias 40 and one to a plurality of inner layer signal lines 45. ing. Although not clearly shown in FIG. 4, a plurality of ground vias 30 are disposed around the signal via 40 and the inner layer signal line 45 with a dielectric interposed therebetween, and the signal is shielded by the plurality of ground vias 30. Radiation of unwanted waves from the via 40 and the inner layer signal line 45 and coupling of unwanted waves from the surroundings are suppressed.

しかし、導体パッド１１は半導体デバイス３内のＲＦ回路とＤＣ的に接続されているため、半導体デバイス３内のＲＦチョーク回路（図示せず）で抑圧しきれない相当量の不要信号が漏洩する。この導体パッド１１に対し、直接ＤＣ的に接続されるワイヤ１２、内部導体パッド１０、信号ビア４０および内層信号線路４５、外部導体パッド１５を介して、高周波パッケージ１の外部にも不要信号が漏洩する。   However, since the conductor pad 11 is connected to the RF circuit in the semiconductor device 3 in a DC manner, a considerable amount of unnecessary signals that cannot be suppressed by the RF choke circuit (not shown) in the semiconductor device 3 leak. Unnecessary signals leak to the outside of the high-frequency package 1 via the wires 12, the internal conductor pads 10, the signal vias 40 and the inner layer signal lines 45, and the external conductor pads 15 that are directly DC connected to the conductor pads 11. To do.

また、露出された誘電体部分から多層誘電体基板内に進入して信号ビアや内層信号線路に結合する不要波も存在する。すなわち、上記のような誘電体基板内の不要波の放射・結合を抑圧するようなシールド構造においても、シールドされた空間内で半導体デバイス３から放射する不要波がひとたび内部導体パッドに結合してしまえば、ＤＣバイアス線路は不要波の恰好のリーク経路となってしまう。   There is also an unnecessary wave that enters the multilayer dielectric substrate from the exposed dielectric portion and is coupled to the signal via and the inner signal line. That is, even in a shield structure that suppresses the radiation and coupling of unwanted waves in the dielectric substrate as described above, unwanted waves radiated from the semiconductor device 3 in the shielded space are once coupled to the internal conductor pads. In this case, the DC bias line becomes a good leak path for unnecessary waves.

そこで、実施の形態１においては、内層信号線路４５の途中に、不要波抑制回路５０を設けるようにしており、この不要波抑制回路５０によって不要波を高効率で減衰、吸収させている。   Therefore, in the first embodiment, an unnecessary wave suppression circuit 50 is provided in the middle of the inner layer signal line 45, and the unnecessary wave is attenuated and absorbed by the unnecessary wave suppression circuit 50 with high efficiency.

この際、ＤＣバイアスの伝送特性に悪影響を与えないように、内層信号線路４５に直列に抵抗体を接続せずに、内層信号線路の上下層に接地導体層を形成し抵抗体を内層信号線路４５に平行に接続する。具体的には、内層信号線路４５の表面に抵抗体を塗布する。内層信号線路がトリプレート線路あるいはマイクロストリップ線路を構成する場合、通常は、接地導体層に向かう上下方向の電界が形成されることになる。この場合に、この上下方向に対して電界に垂直な面に抵抗体を形成すると、不要高周波信号の減衰、吸収効率が極めて悪くなる。このため、実施の形態１では、逆相信号の流れる平行２線路（結合差動線路）上に抵抗体を配置することによって、信号線路の電界方向に平行に抵抗体が配置されるようにしている。   At this time, in order not to adversely affect the transmission characteristics of the DC bias, a ground conductor layer is formed on the upper and lower layers of the inner signal line without connecting a resistor in series with the inner signal line 45, and the resistor is connected to the inner signal line. 45 in parallel. Specifically, a resistor is applied to the surface of the inner layer signal line 45. When the inner layer signal line constitutes a triplate line or a microstrip line, an electric field in the vertical direction toward the ground conductor layer is usually formed. In this case, if a resistor is formed on the surface perpendicular to the electric field with respect to the vertical direction, the attenuation and absorption efficiency of unnecessary high-frequency signals are extremely deteriorated. For this reason, in the first embodiment, the resistor is arranged in parallel to the electric field direction of the signal line by arranging the resistor on the parallel two lines (coupled differential lines) through which the reverse-phase signal flows. Yes.

なお、この図の例では、内層信号線路４５は、誘電体を介して上下層の接地導体層３５間に配されるように設けられており、これにより所謂トリプレート線路が構成されている。図４の場合は、第４層と第５層との間に内層信号線路４５が設けられているので、内層信号線路４５が形成されている位置に対応する第３層と第４層との間、第５層と第６層との間には、内層接地導体３５が形成されている。   In the example of this figure, the inner layer signal line 45 is provided so as to be arranged between the upper and lower ground conductor layers 35 via a dielectric, thereby forming a so-called triplate line. In the case of FIG. 4, since the inner layer signal line 45 is provided between the fourth layer and the fifth layer, the third layer and the fourth layer corresponding to the position where the inner layer signal line 45 is formed. In the meantime, an inner layer ground conductor 35 is formed between the fifth layer and the sixth layer.

図５は不要波抑制回路５０の構成例を示す斜視図である。図６−１は、図４に示す高周波パッケージ１において、多層誘電体基板２のＡ面（第４層と第５層との間）に配される不要波抑制回路５０の構成を示す平面図であり、図６−２は多層誘電体基板２のＤ面（第３層と第４層との間）の状況を示すものである。   FIG. 5 is a perspective view showing a configuration example of the unnecessary wave suppression circuit 50. 6A is a plan view showing a configuration of an unnecessary wave suppression circuit 50 arranged on the A surface (between the fourth layer and the fifth layer) of the multilayer dielectric substrate 2 in the high-frequency package 1 shown in FIG. FIG. 6B shows the state of the D surface (between the third layer and the fourth layer) of the multilayer dielectric substrate 2.

図５および図６−１において、一方の信号ビア４０ａが高周波デバイス３側の内部導体パッド１０側に接続され、他方の信号ビア４０ｂが外部導体パッド１５側に接続されている。信号ビア４０ａに接続される内層信号線路４５ａと、信号ビア４０ｂに接続される内層信号線路４５ｂとの間に、不要波抑制回路５０が形成されている。不要波抑制回路５０は、分配器（Ｔ分岐）５１と、遅延器５２と、平行２線路５３と、合成器５４と、抵抗体（印刷抵抗）５５とを備えている。信号ビア４０ａ、４０ｂの周囲には、誘電体６０を挟んで複数のグランドビア３０が配置されている。   5 and 6A, one signal via 40a is connected to the internal conductor pad 10 side on the high frequency device 3 side, and the other signal via 40b is connected to the external conductor pad 15 side. An unnecessary wave suppression circuit 50 is formed between the inner layer signal line 45a connected to the signal via 40a and the inner layer signal line 45b connected to the signal via 40b. The unnecessary wave suppression circuit 50 includes a distributor (T branch) 51, a delay device 52, two parallel lines 53, a combiner 54, and a resistor (printing resistor) 55. A plurality of ground vias 30 are disposed around the signal vias 40a and 40b with the dielectric 60 interposed therebetween.

分配器（Ｔ分岐）５１は、内層信号線路４５ａを２つの等位相の信号線路に分配する。遅延器は５２は、分配器５１で分配された信号線路の一方に形成され、不要波の基板内実効波長λｇの略１／２の長さを有する信号線路で構成される。平行２線路５３は、２つの平行な信号線路５３ａ，５３ｂから成り、一方の信号線路５３ａが分配器５１で分配された線路につながり、他方の信号線路５３ｂが遅延器５２に接続されている。合成器５４は、平行２線路５３の２つの信号線路５３ａ，５３ｂを合成する信号線路を有し、合成信号を外部導体パッド１５側に出力する。抵抗体（印刷抵抗）５５は、体積抵抗率が、0.0002〜0.1（Ω・m）の範囲の抵抗率を有し、平行２線路５３上に配置され、２つの信号線路５３ａ，５３ｂ間を接続する。   The distributor (T branch) 51 distributes the inner layer signal line 45a to two equal-phase signal lines. The delay unit 52 is formed on one of the signal lines distributed by the distributor 51, and is configured by a signal line having a length approximately half of the effective wavelength λg in the substrate of unnecessary waves. The parallel two lines 53 are composed of two parallel signal lines 53 a and 53 b, one signal line 53 a is connected to the line distributed by the distributor 51, and the other signal line 53 b is connected to the delay unit 52. The combiner 54 has a signal line that combines the two signal lines 53a and 53b of the parallel two lines 53, and outputs a combined signal to the external conductor pad 15 side. The resistor (printed resistor) 55 has a volume resistivity in the range of 0.0002 to 0.1 (Ω · m), is disposed on the parallel two lines 53, and connects the two signal lines 53a and 53b. To do.

これら分配器５１、遅延器５２、平行２線路５３および合成器５４を構成する伝送線路は図の例では、トリプレート線路により構成されており、上下の内層接地導体３５間に信号線路が形成されている。すなわち、図６−２に示すように、第３層と第４層との間（Ｄ面）と、第５層と第６層との間には、不要波抑制回路５０を構成する内層信号線路に対応する箇所に、内層接地導体３５が形成されている。また、分配器５１、遅延器５２、平行２線路５３および合成器５４を構成する伝送線路の周りには、誘電体６０を挟んで複数のグランドビア３０および内層接地導体３５が配置されている。グランドビア３０の隣接間隔は、不要波の基板内実効波長λｇの１／４以下に設定されており、また、対向するグランドビア３０間の間隔Ｌは、波長λｇの１／２以下に設定されている。   In the example shown in the figure, the transmission lines constituting the distributor 51, the delay unit 52, the parallel two lines 53, and the combiner 54 are formed by a triplate line, and a signal line is formed between the upper and lower inner ground conductors 35. ing. That is, as shown in FIG. 6B, the inner layer signal constituting the unnecessary wave suppression circuit 50 is provided between the third layer and the fourth layer (D surface) and between the fifth layer and the sixth layer. An inner layer ground conductor 35 is formed at a location corresponding to the line. A plurality of ground vias 30 and inner-layer ground conductors 35 are disposed around the transmission lines constituting the distributor 51, the delay unit 52, the parallel two lines 53, and the combiner 54 with the dielectric 60 interposed therebetween. The adjacent interval between the ground vias 30 is set to ¼ or less of the effective wavelength λg in the substrate of the unnecessary wave, and the interval L between the opposing ground vias 30 is set to ½ or less of the wavelength λg. ing.

遅延器５２は、不要波の基板内実効波長λｇの略１／２の長さを有しているので、遅延器５２において、不要波の位相は略λｇ／２遅延される。このため、不要波は、平行２線路５３の２つの信号線路５３ａ，５３ｂのうち、遅延器５２を経由していない信号線路５３ａのほうが、遅延器５２を経由している信号線路５３ｂにくらべ、λｇ／２だけ、位相が進むことになる。すなわち、平行２線路５３において、不要波は逆相で結合されることになり、図５に示すように、信号線路５３ａ，５３ｂは結合差動線路を構成して、信号線路５３ａ，５３ｂ間に電界Ｅ１が形成される。そして、この電界Ｅ１は、この逆相となる不要波の周波数帯（不要周波数帯）で、強度が最大となる。   Since the delay device 52 has a length that is approximately ½ of the effective wavelength λg in the substrate of the unnecessary wave, the phase of the unnecessary wave is delayed by approximately λg / 2 in the delay device 52. For this reason, of the two signal lines 53 a and 53 b of the parallel two lines 53, the unnecessary wave is less in the signal line 53 a that does not pass through the delay unit 52 than in the signal line 53 b that passes through the delay unit 52. The phase advances by λg / 2. That is, in the parallel two lines 53, unnecessary waves are coupled in opposite phases, and as shown in FIG. 5, the signal lines 53a and 53b constitute a coupled differential line, and between the signal lines 53a and 53b. An electric field E1 is formed. The electric field E1 has the maximum intensity in the frequency band (unnecessary frequency band) of the unwanted wave that has an opposite phase.

抵抗体５５は平行２線路５３上で２つの信号線路５３ａ，５３ｂ間を接続するように塗布されるので、抵抗体５５は上記電界Ｅ１に平行に配置されることになる。このように、抵抗体５５は、従来のように、電界に垂直に配置されるのではなく、平行２線路５３間に故意に形成した電界Ｅ１に平行に配置されるとともに、平行２線路５３間の電界Ｅ１を不要波の周波数で最大となるようにしたので、この不要周波数帯では、並行２線路間に生じた電位差に対し、直列に抵抗を入れた回路と等価となり、選択的に所望の不要周波数帯に対してのみ電圧降下を起こすことができる。すなわち、不要波の電力を抵抗体５５で効率よく減衰、吸収させることが可能となる。   Since the resistor 55 is applied so as to connect the two signal lines 53a and 53b on the parallel two lines 53, the resistor 55 is arranged in parallel to the electric field E1. Thus, the resistor 55 is not arranged perpendicular to the electric field as in the prior art, but is arranged in parallel to the electric field E1 intentionally formed between the two parallel lines 53 and between the two parallel lines 53. Since the electric field E1 is maximized at the frequency of the unnecessary wave, in this unnecessary frequency band, the potential difference generated between the two parallel lines is equivalent to a circuit in which a resistor is inserted in series, and selectively desired. A voltage drop can be caused only in an unnecessary frequency band. That is, it becomes possible to efficiently attenuate and absorb the power of the unnecessary wave by the resistor 55.

なお、前述したように、内層信号線路４５は、トリプレート線路によって構成されているので、内層信号線路４５から上下の内層接地導体３５に対し上下方向の電界が形成されているが、不要波に関しては、位相制御により、平行２線路５３間に形成される電界Ｅ１のほうが支配的であるので、不要波は抵抗体５５で効率よく減衰、吸収されることとなる。また、遅延器の構成としては、上記の限りではなく、たとえば、多層基板の構造を生かした、信号ビアを含めて、不要波の基板内実効波長λｇの略１／２の長さを有する立体線路により構成しても良い。   As described above, since the inner layer signal line 45 is formed of a triplate line, an electric field in the vertical direction is formed from the inner layer signal line 45 to the upper and lower inner layer ground conductors 35. Since the electric field E1 formed between the two parallel lines 53 is more dominant due to the phase control, the unnecessary wave is efficiently attenuated and absorbed by the resistor 55. Further, the configuration of the delay device is not limited to the above, and for example, a three-dimensional solid having a length approximately half of the effective wavelength λg in the substrate of the unnecessary wave, including the signal via, utilizing the structure of the multilayer substrate. You may comprise by a track.

図７は、上記不要波抑制回路５０の伝送特性を示すもので、実線（Ａ１）が長さ（信号線伝送方向の長さ）１ｍｍの抵抗体５５を形成した場合の上記不要波抑制回路５０の伝送特性を示し、一点鎖線（Ａ２）が内層信号線路４５に長さ３．５ｍｍの抵抗体を単純に塗布した場合の伝送特性を示し、破線（Ａ３）が内層信号線路４５に長さ１６．５ｍｍの抵抗体を単純に塗布した場合の伝送特性を示している。この場合は、除去すべき不要波の周波数をｆ0（ＧＨｚ）としている。この図からも判るように、この不要波抑制回路５０によれば、少ない抵抗体を用いて、不要波の周波数ｆ0の周辺帯域で、不要波を高効率で減衰、吸収することができる。 FIG. 7 shows the transmission characteristics of the unwanted wave suppression circuit 50. The unwanted wave suppression circuit 50 in the case where a resistor 55 having a solid line (A1) of 1 mm in length (length in the signal line transmission direction) is formed. The dotted line (A2) shows the transmission characteristic when a resistor of 3.5 mm in length is simply applied to the inner layer signal line 45, and the broken line (A3) shows a length 16 in the inner layer signal line 45. This shows the transmission characteristics when a 5 mm resistor is simply applied. In this case, the frequency of the unnecessary wave to be removed is set to f 0 (GHz). As can be seen from this figure, according to the unnecessary wave suppression circuit 50, it is possible to attenuate and absorb unnecessary waves with high efficiency in the peripheral band of the frequency f 0 of the unnecessary waves using a small number of resistors.

このように実施の形態１によれば、遅延器５２によって平行２線路５３上を伝送する不要波を逆位相とすることにより、平行２線路間に電界を形成し、抵抗体を平行２線路上で前記電界方向に平行に設けているので、ＤＣバイアス電圧、制御信号あるいはＩＦ信号などの駆動制御信号の伝送特性に悪影響を与えることなく、小さな抵抗体を用いて不要波のみを効率よく減衰、吸収させることが可能となり、これにより不要波が高周波パッケージ１の外部に放射されることを抑制することができ、高周波パッケージ単体で高周波信号（不要波）の放射を抑制することができる。   As described above, according to the first embodiment, the unnecessary wave transmitted on the parallel two lines 53 by the delay device 52 is set in the opposite phase, thereby forming an electric field between the two parallel lines, and the resistor on the parallel two lines. Since it is provided in parallel with the electric field direction, only unnecessary waves are efficiently attenuated using a small resistor without adversely affecting the transmission characteristics of a drive control signal such as a DC bias voltage, a control signal or an IF signal. As a result, it is possible to prevent the unnecessary wave from being radiated to the outside of the high-frequency package 1, and to suppress the emission of a high-frequency signal (unnecessary wave) by the high-frequency package alone.

なお、上述では、不要波抑制回路５０をトリプレート線路に設けた例について説明したが、不要波抑制回路５０をマイクロストリップ線路の途中に構成しても良い。このような場合であっても、マイクロストリップ線路から漏れ出る不要波信号を充分に抑圧する効果を得ることができる。   In addition, although the example which provided the unnecessary wave suppression circuit 50 in the triplate line was demonstrated above, you may comprise the unnecessary wave suppression circuit 50 in the middle of a microstrip line. Even in such a case, it is possible to obtain an effect of sufficiently suppressing unnecessary wave signals leaking from the microstrip line.

実施の形態２．
図８は実施の形態２の高周波パッケージ９５を示すものである。実施の形態２においては、図８に示すように、実施の形態１の不要波抑制回路５０（５０ａ〜５０ｃ）を複数個、縦続接続するようにしており、これにより不要波の減衰率，吸収率を向上させるようにしている。 Embodiment 2. FIG.
FIG. 8 shows a high-frequency package 95 according to the second embodiment. In the second embodiment, as shown in FIG. 8, a plurality of unnecessary wave suppression circuits 50 (50a to 50c) of the first embodiment are connected in cascade. I try to improve the rate.

この場合、各不要波抑制回路における遅延器の信号線路の長さを同一にして、同一の周波数を持つ複数の不要波抑制回路５０ａ〜５０ｃを、縦続接続すると良い。例えば、不要波抑制回路を２段接続するだけで、倍の減衰率を得ることができる。   In this case, the lengths of the signal lines of the delay devices in the unnecessary wave suppression circuits may be the same, and a plurality of unnecessary wave suppression circuits 50a to 50c having the same frequency may be connected in cascade. For example, a double attenuation factor can be obtained by simply connecting two unnecessary wave suppression circuits.

また、複数の不要波抑制回路５０ａ〜５０ｃを縦続接続する場合、各不要波抑制回路５０ａ〜５０ｃにおける遅延器５２の信号線路の長さを異ならせることによって、複数の異なる不要波周波数を減衰、吸収させることもできる。例えば、不要波の基板内実効波長をλｇ１，λｇ２，λｇ３とした場合、不要波抑制回路５０ａの遅延器５２の信号線路はλｇ１／２の長さに設定し、不要波抑制回路５０ｂの遅延器５２の信号線路はλｇ２／２の長さに設定し、不要波抑制回路５０ｃの遅延器５２の信号線路はλｇ３／２の長さに設定することで、複数の異なる不要波周波数を減衰、吸収させることができる。   Further, when cascading a plurality of unnecessary wave suppression circuits 50a to 50c, a plurality of unnecessary wave frequencies are attenuated by changing the length of the signal line of the delay device 52 in each unnecessary wave suppression circuit 50a to 50c. It can also be absorbed. For example, when the effective wavelength in the substrate of unnecessary waves is λg1, λg2, and λg3, the signal line of the delay device 52 of the unnecessary wave suppression circuit 50a is set to a length of λg1 / 2, and the delay device of the unnecessary wave suppression circuit 50b. The signal line 52 is set to a length of λg2 / 2, and the signal line of the delay unit 52 of the unnecessary wave suppression circuit 50c is set to a length of λg3 / 2, thereby attenuating and absorbing a plurality of different unnecessary wave frequencies. Can be made.

実施の形態３．
つぎに、図９〜図１２を用いてこの発明の実施の形態３について説明する。この実施の形態３の高周波パッケージ１００においては、図９および図１０に示すように、内層信号線路４５には、不要波の基板内実効波長λｇの１／４の長さを有する先端開放スタブ７０を設けるとともに、この先端開放スタブ７０と内層信号線路４５との接続位置の上層及び下層、あるいは上下層のいずれか一方の内層接地導体３５に不要波の基板内実効波長λｇの１／２の長さを有する結合スロット（内層接地導体３５の抜き部分）７５を形成し、この結合スロット７５上に抵抗体（印刷抵抗）８０を形成するようにしている。図９の場合は、先端開放スタブ７０が形成された内層信号線路４５の上層にのみ結合スロット７５を形成し、この結合スロット７５に抵抗体８０を塗布するようにしている。このように実施の形態３の不要波抑制回路９０は、先端開放スタブ７０、結合スロット７５および抵抗体８０によって構成されている。 Embodiment 3 FIG.
Next, a third embodiment of the present invention will be described with reference to FIGS. In the high-frequency package 100 according to the third embodiment, as shown in FIGS. 9 and 10, the inner layer signal line 45 has an open-end stub 70 having a length of ¼ of the effective wavelength λg in the substrate of unnecessary waves. And the inner layer ground conductor 35 of the upper layer and lower layer, or the upper and lower layers where the tip open stub 70 and the inner layer signal line 45 are connected has a length of ½ of the effective wavelength λg in the substrate of the unnecessary wave. A coupling slot (extracted portion of the inner-layer ground conductor 35) 75 having a thickness is formed, and a resistor (printing resistor) 80 is formed on the coupling slot 75. In the case of FIG. 9, the coupling slot 75 is formed only in the upper layer of the inner signal line 45 where the tip open stub 70 is formed, and the resistor 80 is applied to the coupling slot 75. As described above, the unnecessary wave suppression circuit 90 according to the third embodiment includes the tip open stub 70, the coupling slot 75, and the resistor 80.

図１１−１は、図９に示す高周波パッケージ１００における多層誘電体基板２のＣ面（第４層と第５層との間）に配される先端開放スタブ７０が形成された内層信号線路４５を示す平面図であり、図１１−２は多層誘電体基板２のＢ面（第３層と第４層との間）に配される結合スロット７５を示す平面図であり（抵抗体８０がない状態を示している）、図１１−３は多層誘電体基板２のＢ面（第３層と第４層との間）に配される結合スロット７５および抵抗体８０を示す平面図である。   FIG. 11A is an inner-layer signal line 45 in which an open-ended stub 70 arranged on the C surface (between the fourth layer and the fifth layer) of the multilayer dielectric substrate 2 in the high-frequency package 100 shown in FIG. 9 is formed. 11-2 is a plan view showing a coupling slot 75 arranged on the B surface (between the third layer and the fourth layer) of the multilayer dielectric substrate 2 (resistor 80 is shown in FIG. 11-2). 11-3 is a plan view showing the coupling slot 75 and the resistor 80 arranged on the B surface (between the third layer and the fourth layer) of the multilayer dielectric substrate 2. .

実施の形態３の場合においても、伝送線路はトリプレート線路により構成されており、上下の内層接地導体３５間に内層信号線路４５が形成されている。また、図１０および図１１−１に示すように、内層信号線路４５の周りには、誘電体６０を挟んで複数のグランドビア３０および内層接地導体３５が配置されている。グランドビア３０の隣接間隔は、不要波の基板内実効波長λｇの１／４以下に設定されており、また、対向するグランドビア３０間の間隔Ｌは、波長λｇの１／２以下に設定されている。   Also in the case of the third embodiment, the transmission line is constituted by a triplate line, and the inner layer signal line 45 is formed between the upper and lower inner layer ground conductors 35. Also, as shown in FIGS. 10 and 11-1, around the inner layer signal line 45, a plurality of ground vias 30 and an inner layer ground conductor 35 are arranged with a dielectric 60 interposed therebetween. The adjacent interval between the ground vias 30 is set to ¼ or less of the effective wavelength λg in the substrate of the unnecessary wave, and the interval L between the opposing ground vias 30 is set to ½ or less of the wavelength λg. ing.

次に、実施の形態３の要部について説明する。まず、図１０および図１１−１に示すように、内層信号線路４５には、不要波の基板内実効波長λｇの１／４の長さを有する先端開放スタブ７０を並列に接続している。この場合、先端開放スタブ７０として、ラジアルスタブを採用している。ラジアルスタブは、通常の矩形スタブに比べ、広帯域化が可能であるとともに、線路長がλｇ／４より短くてよいので、小型化が可能である。なお、この場合は、内層信号線路４５における９０度屈曲したクランクの角部に、先端開放スタブ７０を配設しているが、直線状の内層信号線路４５に対し９０度の角度をもって先端開放スタブ７０を接続するようにしてもよい。   Next, the main part of Embodiment 3 will be described. First, as shown in FIG. 10 and FIG. 11A, the inner-layer signal line 45 is connected in parallel with an open-ended stub 70 having a length that is ¼ of the effective wavelength λg in the substrate of unnecessary waves. In this case, a radial stub is adopted as the tip opening stub 70. The radial stub can have a wider band than a normal rectangular stub and can be downsized because the line length can be shorter than λg / 4. In this case, the open end stub 70 is disposed at the corner of the crank bent 90 degrees in the inner layer signal line 45. However, the open end stub has an angle of 90 degrees with respect to the linear inner layer signal line 45. 70 may be connected.

λｇ／４の長さを有する先端開放スタブ７０においては、波長λｇの不要波に関しては、先端部が開放点となり電界が最大レベルとなり、また先端開放スタブ７０と内層信号線路４５との接続位置Ｏが短絡点となり電界が最小レベルとなる。そして、図１０および図１１−２に示すように、接続位置Ｏがその中心と一致するように結合スロット７５を、先端開放スタブ７０が形成された層の上層及び下層、あるいは上下層のいずれか一方に形成する。図９の高周波パッケージ１においては、上層側にのみ結合スロット７５を形成している。結合スロット７５は、この場合、不要波の基板内実効波長λｇの１／２の長さを有し、かつ先端開放スタブ７０に対し直角な方向に延在するように形成されている。結合スロット７５は、内層接地導体３５に抜きを形成することによって形成され、波長λｇの不要波に関しては、その両端部は短絡点となって電界が最小レベルとなり、中心部は開放点となって電界が最大レベルとなる。このように、先端開放スタブ７０の短絡点と結合スロット７５の開放点とを一致させることで、最も強い結合を得ることができ、内層信号線路４５を伝送する不要波を結合スロット７５に効率よく結合させることができる。   In the open-ended stub 70 having a length of λg / 4, with respect to an unnecessary wave having a wavelength λg, the distal end becomes an open point and the electric field reaches a maximum level, and the connection position O between the open-ended stub 70 and the inner signal line 45 Becomes a short circuit point and the electric field is at the minimum level. Then, as shown in FIGS. 10 and 11-2, the coupling slot 75 is set to either the upper layer and the lower layer of the layer on which the tip opening stub 70 is formed, or the upper and lower layers so that the connection position O coincides with the center thereof. Form on one side. In the high frequency package 1 of FIG. 9, the coupling slot 75 is formed only on the upper layer side. In this case, the coupling slot 75 has a length that is ½ of the effective wavelength λg in the substrate of unnecessary waves, and is formed so as to extend in a direction perpendicular to the tip open stub 70. The coupling slot 75 is formed by forming a hole in the inner-layer ground conductor 35. With respect to an unnecessary wave having a wavelength λg, both ends thereof become short-circuit points and the electric field becomes a minimum level, and the central portion becomes an open point. The electric field reaches the maximum level. In this way, the strongest coupling can be obtained by matching the short-circuit point of the open-ended stub 70 and the open point of the coupling slot 75, and unnecessary waves transmitted through the inner layer signal line 45 can be efficiently transmitted to the coupling slot 75. Can be combined.

すなわち、結合スロット７５は、先端開放スタブ７０と内層信号線路４５との接続位置の上下層、あるいは上下層のいずれか一方の接地導体に形成されて、この接続位置の周辺で定在波分布が開放となって、内層信号線路４５と結合するように構成すればよい。   That is, the coupling slot 75 is formed in one of the ground conductors at the upper and lower layers or the upper and lower layers at the connection position between the open-ended stub 70 and the inner layer signal line 45, and the standing wave distribution is around the connection position. What is necessary is just to comprise so that it may become open | released and it may couple | bond with the inner layer signal track | line 45. FIG.

結合スロット７５上に結合した不要波は、結合スロット７５に図示のように結合スロットの短手方向を向いた電界が形成され、これと平行に配置・塗布された抵抗体８０により効率よく減衰、吸収されることとなる。   Unwanted waves coupled on the coupling slot 75 are efficiently attenuated by the resistor 80 arranged and applied in parallel with the coupling slot 75, as shown in FIG. Will be absorbed.

このように実施の形態３では、λｇ／４の先端開放スタブ７０の短絡点と上下層に設けたλｇ／２の結合スロット７５の開放点が一致するように、先端開放スタブ７０および結合スロット７５を配置することにより、内層信号線路４５を伝送する不要波を結合スロット７５に効率よく結合させ、結合スロット７５に結合された不要波を結合スロット７５に形成された電界を用いてこの電界と平行に配置された抵抗体８０で効率よく減衰、吸収させることができる。したがって、ＤＣバイアス電圧、制御信号あるいはＩＦ信号などの駆動制御信号の伝送特性に悪影響を与えることなく、不要波のみを効率よく減衰、吸収させることが可能となり、これにより、実施の形態１と同様、不要波が高周波パッケージ１の外部に放射されることを抑制することができ、高周波パッケージ単体で高周波信号（不要波）の放射を抑制することができる。   Thus, in the third embodiment, the tip open stub 70 and the coupling slot 75 are arranged so that the short circuit point of the λg / 4 tip open stub 70 and the open point of the λg / 2 coupling slot 75 provided in the upper and lower layers coincide. , The unnecessary wave transmitted through the inner layer signal line 45 is efficiently coupled to the coupling slot 75, and the unnecessary wave coupled to the coupling slot 75 is parallel to the electric field using the electric field formed in the coupling slot 75. Can be attenuated and absorbed efficiently. Therefore, only unnecessary waves can be efficiently attenuated and absorbed without adversely affecting the transmission characteristics of the drive control signal such as the DC bias voltage, the control signal, or the IF signal, and as in the first embodiment. Therefore, it is possible to suppress unnecessary waves from being radiated to the outside of the high-frequency package 1, and to suppress the emission of high-frequency signals (unnecessary waves) with a single high-frequency package.

なお、結合スロット７５は、先端開放スタブ７０またはラジアルスタブの中心軸に対し直交する方向に延在されている場合が、結合スロット７５で最も強い結合を得ることができるが、結合スロット７５を他の方向に延在するように形成するようにしてもよい。また、結合スロット７５を、λｇ／２の整数倍の長さとしてもよい。また、上記接続位置Ｏから一方の端部までの長さをλｇ／４の奇数倍の長さに設定し、接続位置Ｏから他方の端部までの長さをλｇ／４の奇数倍の長さに設定した結合スロット７５を採用するようにしてもよい。また、先端開放スタブ７０は、λｇ／４の奇数倍の長さとしてもよい。さらに、抵抗体８０を結合スロット７５の全面ではなく、例えば、一方は不要波を結合するスロットとし、他方のスロット線路上に配設するようにしてもよい。   The coupling slot 75 extends in a direction perpendicular to the center axis of the tip open stub 70 or the radial stub, but the coupling slot 75 can provide the strongest coupling. You may make it form so that it may extend in this direction. Further, the coupling slot 75 may have a length that is an integral multiple of λg / 2. The length from the connection position O to one end is set to an odd multiple of λg / 4, and the length from the connection position O to the other end is an odd multiple of λg / 4. The coupling slot 75 set as described above may be adopted. Further, the tip opening stub 70 may be an odd multiple of λg / 4. Further, the resistor 80 may be arranged not on the entire surface of the coupling slot 75 but on one slot line for coupling unnecessary waves, for example, on the other slot line.

図１２は、実施の形態３の変形例を示すものである。この変形例の場合は、結合スロット８５は、先端開放スタブ７０と内層信号線路４５との接続位置Ｏから一方の端部までの長さを概ねλｇ／４としており、また接続位置Ｏから他方の端部までの長さを任意の長さのスロット線路８５ａとしている。そして、抵抗体８０は、全面に塗布するのではなく、スロット線路８５ａ側にのみ塗布するようにしている。   FIG. 12 shows a modification of the third embodiment. In the case of this modification, the coupling slot 85 has a length from the connection position O of the open end stub 70 and the inner layer signal line 45 to one end portion of approximately λg / 4, and from the connection position O to the other end. The length to the end is a slot line 85a having an arbitrary length. The resistor 80 is not applied to the entire surface, but only to the slot line 85a side.

この変形例においても、λｇ／４の長さを有する先端開放スタブ７０においては、波長λｇの不要波に関しては、先端部が開放点となり電界が最大レベルとなり、また接続位置Ｏが短絡点となり電界が最小レベルとなる。一方、結合スロット８５は、波長λｇの不要波に関しては、その両端部は短絡点となって電界が最小レベルとなり、接続位置Ｏに対応する点が開放点となって電界が最大レベルとなる。このように、図１２に示す変形例においても、先端開放スタブ７０の短絡点と結合スロット８５の開放点とを一致させることで、最も強い結合を得るようにしている。   Also in this modified example, in the open end stub 70 having a length of λg / 4, with respect to an unnecessary wave having a wavelength of λg, the end portion becomes an open point and the electric field becomes the maximum level, and the connection position O becomes a short circuit point and the electric field. Is the minimum level. On the other hand, with respect to the unnecessary wave having the wavelength λg, the coupling slot 85 has a short circuit point at both ends thereof, and the electric field is at the minimum level, and a point corresponding to the connection position O is an open point and the electric field is at the maximum level. Thus, also in the modification shown in FIG. 12, the strongest coupling is obtained by matching the short-circuit point of the tip opening stub 70 with the opening point of the coupling slot 85.

すなわち、この変形例の場合は、内層信号線路４５を伝送する不要波を結合スロット７５に効率よく結合させた後、不要波をスロット線路８５ａを伝搬させることで、不要波をスロット線路８５ａ上に配した抵抗体８０で減衰、吸収させるようにしている。   That is, in the case of this modification, an unnecessary wave transmitted through the inner layer signal line 45 is efficiently coupled to the coupling slot 75, and then the unnecessary wave is propagated through the slot line 85a. The resistor 80 arranged is attenuated and absorbed.

なお、不要波の吸収性のためには、スロット線路８５ａは、長い方が望ましい。また、接続位置Ｏから一方の端部までの長さを概ねλｇ／４の奇数倍の長さとしてもよい。また、抵抗体８０を、スロット線路８５ａ側にのみ塗布するのではなく、結合スロット８５の全面に塗布するようにしてもよい。さらに、この場合も、先端開放スタブ７０は、λｇ／４の奇数倍の長さとしてもよい。   In order to absorb unnecessary waves, the slot line 85a is preferably long. Alternatively, the length from the connection position O to one end may be approximately an odd multiple of λg / 4. Further, the resistor 80 may be applied not only on the slot line 85a side but on the entire surface of the coupling slot 85. Further, in this case as well, the tip open stub 70 may be an odd multiple of λg / 4.

なお、上記実施の形態３の不要波抑制回路９０を、複数個、縦続接続して、これにより不要波の減衰率、吸収率を向上させるようにしてもよい。この場合、各不要波抑制回路における結合スロットの長さを同一にして、同一の周波数を持つ複数の不要波抑制回路を、それぞれ縦続接続するとよい。例えば、不要波抑制回路を２段接続するだけで、倍の吸収率を得ることができる。あるいは、複数の不要波抑制回路を縦続接続し、各不要波抑制回路を構成する結合スロットの長さを、異なる周波数を持つ複数の不要波の基板実行波長の略１／２になるように、それぞれ異ならせてもよい。これによって、対応する複数の異なる波長について、それぞれ不要周波数を減衰、吸収させることができる。   Note that a plurality of unnecessary wave suppression circuits 90 of the third embodiment may be connected in cascade to improve the attenuation rate and absorption rate of unnecessary waves. In this case, the lengths of the coupling slots in the unnecessary wave suppression circuits may be the same, and a plurality of unnecessary wave suppression circuits having the same frequency may be connected in cascade. For example, a double absorption rate can be obtained by simply connecting two unnecessary wave suppression circuits. Alternatively, a plurality of unnecessary wave suppression circuits are connected in cascade, and the length of the coupling slot constituting each unnecessary wave suppression circuit is approximately ½ of the substrate execution wavelength of the plurality of unnecessary waves having different frequencies. Each may be different. Thereby, unnecessary frequencies can be attenuated and absorbed for a plurality of corresponding different wavelengths, respectively.

なお、上記実施の形態では、多層誘電体基板２内に形成したＩＣ搭載凹部６内に高周波デバイス３を収容する構成の高周波パッケージ１に本発明を適用するようにしたが、本発明は、ＩＣ搭載凹部６を持たない平坦な多層誘電体基板２の表層に高周波デバイス３を搭載するような構成の高周波パッケージ１にも適用することができる。   In the above-described embodiment, the present invention is applied to the high-frequency package 1 configured to accommodate the high-frequency device 3 in the IC mounting recess 6 formed in the multilayer dielectric substrate 2. The present invention can also be applied to the high-frequency package 1 configured to mount the high-frequency device 3 on the surface layer of the flat multilayer dielectric substrate 2 that does not have the mounting recess 6.

以上のように、本発明にかかる伝送線路基板および高周波パッケージは、高周波のＥＭＩ対策を講じる必要のあるＦＭ−ＣＷレーダなどの半導体電子機器に有用である。   As described above, the transmission line substrate and the high-frequency package according to the present invention are useful for semiconductor electronic devices such as FM-CW radars that need to take measures against high-frequency EMI.

この発明にかかる半導体パッケージ（高周波パッケージ）の外観を示す斜視図である。It is a perspective view which shows the external appearance of the semiconductor package (high frequency package) concerning this invention. この発明にかかる半導体パッケージのカバーを外した外観を示す斜視図である。It is a perspective view which shows the external appearance which removed the cover of the semiconductor package concerning this invention. この発明にかかる半導体パッケージの内部構成を示す平面図である。It is a top view which shows the internal structure of the semiconductor package concerning this invention. 実施の形態１の半導体パッケージの多層誘電体基板のビア構造を詳細に示す断面図である。FIG. 3 is a cross-sectional view showing in detail a via structure of the multilayer dielectric substrate of the semiconductor package of the first embodiment. 多層誘電体基板内に搭載される実施の形態１の不要波抑制回路の構成を示す斜視図である。It is a perspective view which shows the structure of the unnecessary wave suppression circuit of Embodiment 1 mounted in a multilayer dielectric substrate. 多層誘電体基板内に搭載される実施の形態１の不要波抑制回路の構成を示す平面図であり、図５の多層誘電体基板の面Ａの状態を示す図である。FIG. 6 is a plan view showing a configuration of an unnecessary wave suppression circuit according to the first embodiment mounted in a multilayer dielectric substrate, and shows a state of a surface A of the multilayer dielectric substrate in FIG. 5. 図７の多層誘電体基板の面Ｄの状態を示す図である。It is a figure which shows the state of the surface D of the multilayer dielectric substrate of FIG. 実施の形態１の不要波抑制回路などの伝送特性を示すグラフである。4 is a graph showing transmission characteristics of the unnecessary wave suppression circuit of the first embodiment. 実施の形態２の半導体パッケージの多層誘電体基板のビア構造を詳細に示す断面図である。6 is a cross-sectional view showing in detail a via structure of a multilayer dielectric substrate of a semiconductor package of a second embodiment. 実施の形態３の半導体パッケージの多層誘電体基板のビア構造を詳細に示す断面図である。6 is a cross-sectional view showing in detail a via structure of a multilayer dielectric substrate of a semiconductor package according to a third embodiment. 多層誘電体基板内に搭載される実施の形態３の不要波抑制回路の構成を示す斜視図である。It is a perspective view which shows the structure of the unnecessary wave suppression circuit of Embodiment 3 mounted in a multilayer dielectric substrate. 多層誘電体基板内に搭載される実施の形態３の不要波抑制回路の一部構成を示す平面図であり、図９の多層誘電体基板の面Ｃの状態を示す図である。FIG. 10 is a plan view showing a partial configuration of an unnecessary wave suppressing circuit according to a third embodiment mounted in a multilayer dielectric substrate, and showing a state of a surface C of the multilayer dielectric substrate in FIG. 9. 多層誘電体基板内に搭載される実施の形態３の不要波抑制回路の一部構成を示す平面図であり、図９の多層誘電体基板の面Ｂの状態（抵抗体省略）を示す図である。FIG. 10 is a plan view showing a partial configuration of the unwanted wave suppressing circuit according to the third embodiment mounted in a multilayer dielectric substrate, and showing a state of a surface B (resistor omitted) of the multilayer dielectric substrate in FIG. 9. is there. 多層誘電体基板内に搭載される実施の形態３の不要波抑制回路の一部構成を示す平面図であり、図９の多層誘電体基板の面Ｂの状態（抵抗体記載）を示す図である。FIG. 10 is a plan view showing a partial configuration of the unwanted wave suppression circuit according to the third embodiment mounted in a multilayer dielectric substrate, and is a diagram showing a state (stated as a resistor) of surface B of the multilayer dielectric substrate in FIG. 9. is there. 実施の形態３の変形例を示す平面図である。FIG. 10 is a plan view showing a modification of the third embodiment.

符号の説明Explanation of symbols

１，９５，１００ 高周波パッケージ（半導体パッケージ）
２ 多層誘電体基板
３ 高周波デバイス（半導体デバイス、半導体ＩＣ）
４ シールリング
５ カバー
６ ＩＣ搭載凹部
６ａ 側壁
７ フィードスルー
８ マイクロストリップ線路
１０ 内部導体パッド
１１ 導体パッド
１２ ワイヤ
１５ 外部導体パッド
１６ グランド面
１７ 半田
１８ グランドパターン
２０ キャリア
３０，３０ｂ，３０ｃ グランドビア
３０ａ 側壁グランドビア
３３ キャビティ
３５ 内層接地導体
４０，４０ａ，４０ｂ 信号ビア
４５，４５ａ，４５ｂ 内層信号線路
５０，５０ａ，５０ｂ，５０ｃ 不要波抑制回路
５１ 分配器
５２ 遅延器
５３ 平行２線路
５４ 合成器
５５ 抵抗体
６０ 誘電体
７０ 先端開放スタブ
７５ 結合スロット
８０ 抵抗体
８５ 結合スロット
８５ａ スロット線路
９０ 不要波抑制回路 1,95,100 High frequency package (semiconductor package)
2 Multilayer dielectric substrate 3 High frequency device (semiconductor device, semiconductor IC)
4 Seal ring 5 Cover 6 IC mounting recess 6a Side wall 7 Feedthrough 8 Microstrip line 10 Internal conductor pad 11 Conductor pad 12 Wire 15 External conductor pad 16 Ground surface 17 Solder 18 Ground pattern 20 Carrier 30, 30b, 30c Ground via 30a Side wall Ground via 33 Cavity 35 Inner layer ground conductor 40, 40a, 40b Signal via 45, 45a, 45b Inner layer signal line 50, 50a, 50b, 50c Unwanted wave suppression circuit 51 Divider 52 Delay unit 53 Parallel two line 54 Synthesizer 55 Resistor Reference Signs List 60 dielectric 70 open end stub 75 coupling slot 80 resistor 85 coupling slot 85a slot line 90 unwanted wave suppression circuit

Claims (8)

半導体デバイスに入出力される駆動制御信号を伝送する伝送線路を有し、信号線路の上下層に接地導体を配置したトリプレート線路として伝送線路を形成した伝送線路基板において、
前記信号線路に並列に接続され、マイクロ波帯及びミリ波帯の不要波の基板内実効波長の略１／４の奇数倍の長さを有する先端開放スタブと、
該先端開放スタブと信号線路との接続位置の上下層、あるいは上下層のいずれか一方の接地導体に形成され、前記接続位置の周辺で定在波分布が開放となって前記信号線路と結合する結合スロットと、
該結合スロット上の少なくとも一部に設けられた抵抗体と、
を備えることを特徴とする伝送線路基板。 In a transmission line substrate having a transmission line that transmits a drive control signal input / output to / from a semiconductor device, and forming a transmission line as a triplate line in which ground conductors are arranged on the upper and lower layers of the signal line,
An open-ended stub connected in parallel to the signal line and having a length that is an odd multiple of approximately ¼ of the effective wavelength in the substrate of unnecessary waves in the microwave band and millimeter wave band;
It is formed on the ground conductor at either the upper or lower layer or the upper or lower layer of the connection position between the open stub and the signal line, and the standing wave distribution is open around the connection position to couple with the signal line. A coupling slot;
A resistor provided at least in part on the coupling slot;
A transmission line substrate comprising: 半導体デバイスに入出力される駆動制御信号を伝送する伝送線路を有し、信号線路の上下層に接地導体を配置したトリプレート線路として伝送線路を形成した伝送線路基板において、
前記信号線路に並列に接続されるラジアルスタブと、
該ラジアルスタブと信号線路との接続位置の上下層、あるいは上下層のいずれか一方の接地導体に形成され、前記接続位置の周辺で定在波分布が開放となって前記信号線路と結合する結合スロットと、
該結合スロット上の少なくとも一部に設けられた抵抗体と、
を備えることを特徴とする伝送線路基板。 In a transmission line substrate having a transmission line that transmits a drive control signal input / output to / from a semiconductor device, and forming a transmission line as a triplate line in which ground conductors are arranged on the upper and lower layers of the signal line,
A radial stub connected in parallel to the signal line;
A coupling that is formed on either the upper or lower layer or the upper or lower layer of the ground conductor at the connection position of the radial stub and the signal line, and the standing wave distribution is open around the connection position to couple with the signal line Slots,
A resistor provided at least in part on the coupling slot;
A transmission line substrate comprising: 前記結合スロットは、前記接続位置から一方が不要波の基板内実効波長の略１／４の奇数倍の長さを有し、前記接続位置から他方が少なくとも前記基板内実効波長の略１／４の長さを有することを特徴とする請求項１または２に記載の伝送線路基板。   One of the coupling slots from the connection position has a length that is an odd multiple of about 1/4 of the effective wavelength in the substrate of unnecessary waves, and the other from the connection position is at least about 1/4 of the effective wavelength in the substrate. The transmission line substrate according to claim 1, wherein the transmission line substrate has a length of 前記結合スロットは、前記接続位置に開放点が一致するように配置され、不要波の基板内実効波長の略１／２の長さを有し、前記抵抗体は該結合スロット上の全面に形成されることを特徴とする請求項１または２に記載の伝送線路基板。   The coupling slot is arranged so that the open point coincides with the connection position, and has a length approximately half the effective wavelength in the substrate of unnecessary waves, and the resistor is formed on the entire surface of the coupling slot. The transmission line substrate according to claim 1, wherein the transmission line substrate is provided. 前記スタブと結合スロットとを有する不要波抑制回路を、複数個、縦続接続し、当該複数の不要波抑制回路における結合スロットの長さを、異なる周波数を持つ複数の不要波の基板内実効波長の略１／２となるように、それぞれ異ならせたことを特徴とする請求項１〜４のいずれか一つに記載の伝送線路基板。   A plurality of unnecessary wave suppression circuits having the stub and the coupling slot are connected in cascade, and the length of the coupling slot in the plurality of unnecessary wave suppression circuits is set to the effective wavelength in the substrate of the plurality of unnecessary waves having different frequencies. The transmission line substrate according to any one of claims 1 to 4, wherein the transmission line substrate is made to be approximately ½. 前記信号線路が不要波の基板内実効波長の１／４以下の間隔で配置される複数のグランドビアで囲まれていることを特徴とする請求項１〜５のいずれか一つに記載の伝送線路基板。   6. The transmission according to claim 1, wherein the signal line is surrounded by a plurality of ground vias arranged at intervals of 1/4 or less of an effective wavelength in the substrate of unnecessary waves. Line board. １〜複数の半導体デバイスを収容するために用いられ、請求項１〜６のいずれか一つに記載の伝送線路基板を、前記半導体デバイスの駆動制御信号端子と外部端子との接続経路に設けたことを特徴とする半導体パッケージ。   The transmission line substrate according to any one of claims 1 to 6, wherein the transmission line substrate according to any one of claims 1 to 6 is provided in a connection path between a drive control signal terminal and an external terminal. A semiconductor package characterized by that. １〜複数の半導体デバイスと、
請求項１〜６のいずれか一つに記載の伝送線路基板と、
を備え、該伝送線路基板を、前記半導体デバイスの駆動制御信号端子と外部端子との接続経路に設けたことを特徴とする半導体パッケージ。 One or more semiconductor devices;
The transmission line substrate according to any one of claims 1 to 6,
And a transmission line substrate provided on a connection path between a drive control signal terminal and an external terminal of the semiconductor device.
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Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010011043A (en) * 2008-06-26 2010-01-14 Mitsubishi Electric Corp Transmission line, branch line coupler, and wilkinson division circuit
JP2014204022A (en) * 2013-04-08 2014-10-27 三菱電機株式会社 Electromagnetic wave shield structure and high frequency module structure
JP2015177291A (en) * 2014-03-14 2015-10-05 三菱電機株式会社 gate bias circuit
US9219299B2 (en) 2012-08-27 2015-12-22 Nec Tokin Corporation Resonator, multilayer board and electronic device
KR20180056317A (en) * 2016-11-18 2018-05-28 삼성전자주식회사 Semiconductor Package
JP2022500843A (en) * 2018-09-20 2022-01-04 インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Machines Corporation Transition from printed circuit board to dielectric layer with controlled impedance and / or reduction of crosstalk for quantum applications
JP7287349B2 (en) 2020-05-28 2023-06-06 株式会社デンソー Radar circuit unit, radar equipment

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04290001A (en) * 1991-03-19 1992-10-14 Toshiba Lighting & Technol Corp Electronic circuit board
JPH0555813A (en) * 1991-08-21 1993-03-05 Fujitsu Ltd Microstrip line terminal equipment
JPH07273509A (en) * 1994-04-04 1995-10-20 Toshiba Corp Manufacture of microwave circuit and printed circuit board

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04290001A (en) * 1991-03-19 1992-10-14 Toshiba Lighting & Technol Corp Electronic circuit board
JPH0555813A (en) * 1991-08-21 1993-03-05 Fujitsu Ltd Microstrip line terminal equipment
JPH07273509A (en) * 1994-04-04 1995-10-20 Toshiba Corp Manufacture of microwave circuit and printed circuit board

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010011043A (en) * 2008-06-26 2010-01-14 Mitsubishi Electric Corp Transmission line, branch line coupler, and wilkinson division circuit
US9219299B2 (en) 2012-08-27 2015-12-22 Nec Tokin Corporation Resonator, multilayer board and electronic device
JP2014204022A (en) * 2013-04-08 2014-10-27 三菱電機株式会社 Electromagnetic wave shield structure and high frequency module structure
JP2015177291A (en) * 2014-03-14 2015-10-05 三菱電機株式会社 gate bias circuit
KR20180056317A (en) * 2016-11-18 2018-05-28 삼성전자주식회사 Semiconductor Package
KR102554415B1 (en) 2016-11-18 2023-07-11 삼성전자주식회사 Semiconductor Package
JP2022500843A (en) * 2018-09-20 2022-01-04 インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Machines Corporation Transition from printed circuit board to dielectric layer with controlled impedance and / or reduction of crosstalk for quantum applications
JP7287349B2 (en) 2020-05-28 2023-06-06 株式会社デンソー Radar circuit unit, radar equipment

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