JP2008047042A - Portable electronic device and ic card - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a portable electronic device and an IC card with a data area reusable even when a write failure occurs during data write for allowing efficient data write processing. <P>SOLUTION: When write error (a write failure) occurs in writing data, especially data with a long data length, to a write once binary EF (elementary file), a defective area is found by using a previous write start address and a write ending address stored inside, and a write binary command is received again. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention incorporates an IC (integrated circuit) chip having control elements such as a rewritable nonvolatile memory and a CPU (Central Processing Unit), for example, and performs various processes based on commands (instructions) supplied from the outside. The present invention relates to a portable electronic device such as an IC card and an IC card that execute the above and output the processing result to the outside.

  Recently, as portable electronic devices, an EEPROM as a rewritable nonvolatile memory, a RAM as a volatile memory, a CPU as a control element for accessing (reading or writing data, etc.) these memories, and , Having a ROM storing a CPU operation program and the like, executing a process corresponding to a command supplied from an external device (IC card reader / writer), and outputting the processing result to the external device IC cards incorporating IC chips provided with means are used in various industries.

In this type of IC card, some nonvolatile memories have a large memory capacity and a data area (binary elementary file) in which binary data is written only once and cannot be rewritten is set ( For example, refer nonpatent literature 1).
For example, when writing data having a long data length such as image data, for example, when writing data having a long data length to the data area in which data writing is permitted only once, the data inputted from the outside is sequentially written. become. If the data writing is interrupted due to a communication error in the middle of the writing, even if the same command is executed again, the data has been written halfway, so a writing error occurs and the IC card cannot be reused. Can not.
Japanese Industrial Standard Compliant JICSAP IC Card Specification with External Terminal (July 1998, 1.1 edition) JP-A-10-214232

  However, in the above-described conventional technique, when data writing is interrupted due to a communication error or the like in the middle of writing data having a long data length to the data area in which data writing is permitted only once, Even if the same command is executed, data is written halfway, so that there is a writing abnormality (writing failure), the IC card cannot be reused, and there is a problem that it is not efficient.

  Therefore, the present invention, for example, in the case where a writing error (writing failure) occurs when writing data having a long data length in a data area in which data writing is permitted only once, for example, the previously recorded inside By using the write start address and the write end address, it is possible to find an area where writing has failed and accept the write command again, so that the data area can be reused, enabling efficient data writing processing. An object is to provide a possible electronic device and an IC card.

  The portable electronic device according to the present invention includes a memory in which at least one data area in which data writing is permitted once is set, and data writing in the data area in which data writing is permitted only once When an address storage means for storing a start address and a write end address and a command for instructing data write to the data area in which data write is permitted only once are received, specific information in the command Address calculating means for obtaining a write start address and a write end address indicating the current data write range, and an address writing means for writing the write start address and write end address calculated by the address calculation means into the address storage means, , The data of the length specified by the received command is Write processing means for performing processing to write only to the data area in which data writing is permitted, and when writing of data by this writing processing means is completed normally, the write start address and write end in the address storage means When an initialization means for initializing an address to a specific value and a command for instructing data writing to the data area in which data writing is permitted only once are received again, the address for the command is received. First determination means for determining whether or not the current write start address and write end address calculated by the calculation means match the previous write start address and write end address in the address storage means; As a result of determination by the determination means, the current write start address and write end address are If the start address and the write end address match, it is determined that the previous data write process for the data area did not end normally, and the data in the data area was specified by the re-received instruction. Rewriting processing means for performing processing for rewriting data of length.

  The portable electronic device of the present invention also includes a memory in which at least one data area in which data writing is permitted once is set, and data in the data area in which data writing is permitted only once. When the address storage means for storing the write start address and the write end address and the instruction to write data to the data area in which data writing is permitted only once are received, Address calculation means for obtaining the write start address and write end address indicating the current data write range based on the specific information, and address writing for writing the write start address and write end address calculated by the address calculation means into the address storage means Means and data of a length specified by the received command. Write processing means for performing a process of writing data to a data area permitted to write data once, and an instruction for instructing data writing to the data area permitted to write data only once If received again, whether the current write start address and write end address calculated by the address calculation means for the instruction are within the range of the previous write start address and write end address in the address storage means If the result of the determination by the second determination means and the second determination means is that the current write start address and write end address are within the range of the previous write start address and write end address, the data Third determination means for determining whether or not there has been a write failure in the previous data write processing for the area As a result of the determination by the third determination means, if there is a write failure in the previous data write process, the process of rewriting the data in the data area with the data of the length specified by the command received again Rewriting processing means for performing the above.

  Also, the IC card of the present invention has a memory in which at least one data area in which data writing is permitted once is set, and data writing in the data area in which data writing is permitted only once. When an address storage means for storing a start address and a write end address and a command for instructing data write to the data area in which data write is permitted only once are received, specific information in the command Address calculating means for obtaining a write start address and a write end address indicating the current data write range, and an address writing means for writing the write start address and write end address calculated by the address calculation means into the address storage means, , The data of the length specified by the received command is Write processing means for performing processing to write only to the data area in which data writing is permitted, and when writing of data by this writing processing means is completed normally, the write start address and write end in the address storage means When an initialization means for initializing an address to a specific value and a command for instructing data writing to the data area in which data writing is permitted only once are received again, the address for the command is received. First determination means for determining whether or not the current write start address and write end address calculated by the calculation means match the previous write start address and write end address in the address storage means; As a result of determination by the determination means, the current write start address and write end address are If the start address and the write end address match, it is determined that the previous data write process for the data area did not end normally, and the data in the data area was specified by the re-received instruction. There is provided an IC module having a rewrite processing means for performing a process of rewriting to length data, and an IC card main body containing the IC module.

  Also, the IC card of the present invention has a memory in which at least one data area in which data writing is permitted once is set, and data writing in the data area in which data writing is permitted only once. When an address storage means for storing a start address and a write end address and a command for instructing data write to the data area in which data write is permitted only once are received, specific information in the command Address calculating means for obtaining a write start address and a write end address indicating the current data write range, and an address writing means for writing the write start address and write end address calculated by the address calculation means into the address storage means, , The data of the length specified by the received command is The write processing means for performing the process of writing data only in the data area permitted to write data and the instruction for instructing the data writing to the data area permitted to write data only once are received again. In this case, it is determined whether or not the current write start address and write end address calculated by the address calculation means for the instruction are within the range of the previous write start address and write end address in the address storage means. And when the current write start address and write end address are within the range of the previous write start address and write end address, the previous determination for the data area is made. A third determination means for determining whether or not there has been a write failure in the data write process; As a result of the determination by the third determination means, when there is a write failure in the previous data write process, a process of rewriting the data in the data area with the data of the length specified by the command received again is performed. An IC module having rewrite processing means and an IC card main body storing the IC module are provided.

  According to the present invention, for example, when a write error (write failure) occurs when writing data having a long data length in a data area in which data write is permitted only once, the previous time recorded inside By using the write start address and the write end address, it is possible to find an area where writing has failed and accept the write command again, so that the data area can be reused, enabling efficient data writing processing. Possible electronic devices and IC cards can be provided.

Embodiments of the present invention will be described below with reference to the drawings.
FIG. 1 shows a configuration example of an IC card system that handles an IC card as a portable electronic device according to an embodiment of the present invention. In this IC card system, the IC card 11 can be connected to a terminal device 13 such as a personal computer via a card reader / writer 12, and a keyboard 14, a CRT display unit 15, and a printer 16 are connected to the terminal device 13. Composed.

  FIG. 2 shows the configuration of the IC card 11, and includes a CPU 101 as a control element, a data memory 102 as a storage means (memory) whose contents can be rewritten, a working memory 103, a program memory 104, a card reader, The contact portion 105 is used to obtain electrical contact with the writer 12. Of these, the portion within the broken line (CPU 101, data memory 102, working memory 103, program memory 104) is composed of one (or a plurality) of IC chips 106, and further this IC chip 106 and contact portion 105. Are integrated into an IC module and embedded in the IC card main body 11a.

  The data memory 102 is configured by a nonvolatile memory such as an EEPROM, which can rewrite stored contents, and stores various application data in a file structure.

  For example, the data memory 102 has at least one data area (binary elementary file, hereinafter abbreviated as binary EF) that has a large memory capacity and cannot be rewritten by writing binary data only once. In this binary EF, data having a long data length such as image data (for example, a face image of 10 Kbytes or 20 Kbytes or more) is stored.

The working memory 103 is a working memory for temporarily storing processing data when the CPU 101 performs processing, and is configured by, for example, a RAM.
The program memory 104 is composed of, for example, a non-volatile memory that cannot be rewritten, such as a mask ROM, and stores a control program of the CPU 101 and the like.

  FIG. 3 shows a configuration example of EF definition information for defining the binary EF in the data memory 102. For example, in the example shown in FIG. 3, the three EF definition information 21, 22, and 23 are stored in the data memory 102, and “EFID” that is identification information for identifying the binary EF, the data memory 102 The “start address” which is information indicating the position where the binary EF is defined, “size” which is information indicating the size (data length that can be stored) of the binary EF, and the previous data is written to the binary EF. “Last write start address”, which is information indicating the start address when the last read, and “Last write last address”, which is information indicating the last address when the previous data was written to the binary EF, are included. Configured.

  For example, in the example shown in FIG. 3, the EF definition information 21 has an EFID “0001”, a head address “8000”, and a size “1000”. This indicates that an area from the address “8000” to “1000” bytes in the data memory 102, that is, the address “8000 to 8FFF” is defined as a binary EF of “EFID = 0001”. In the example shown in FIG. 3, the EF definition information 21 indicates a state in which specific values (for example, all FFs) are written as initial values for the previous write start address and the previous write final address.

  In the example shown in FIG. 3, the EF definition information 22 has an EFID of “0002”, a head address of “9000”, and a size of “200”. This indicates that an area from the address “9000” to “200” bytes in the data memory 102, that is, the address “9000 to 91FF” is defined as a binary EF of “EFID = 0002”. In the example shown in FIG. 3, the EF definition information 22 indicates a state in which specific values (for example, all FF) are written as initial values for both the previous write start address and the previous write last address.

  In the example shown in FIG. 3, the EF definition information 23 has an EFID “0003”, a head address “9200”, and a size “100”. This indicates that an area from address “9200” to “100” bytes in the data memory 102, that is, addresses “9200 to 92FF” is defined as binary EF of “EFID = 0003”. In the example shown in FIG. 3, the EF definition information 23 indicates a state in which specific values (for example, all FFs) are written as initial values for the previous write start address and the previous write final address.

  FIG. 4 shows a format of a write binary (WRITE BINARY) command (instruction) when writing binary data to a data area (binary EF) in which data writing is permitted only once in the data memory 102. is there. The write binary command is input from an external card reader / writer 12, and includes a classification unit (CLA: class) having a function for identifying the command, an instruction unit (INS: instruction), and parameter data (P1, P2). The data length (Lc) indicating the length of data to be written and the write data (DATA).

  Information indicating the type of the command is stored in the CLA part and the INS part. In the example shown in FIG. 4, “00” and “D0” indicating a write binary command are stored in the CLA part and the INS part.

  Information indicating processing parameters of the command is stored in the P1 part and the P2 part. That is, information (information indicating EFID) for specifying the binary EF to which data is to be written is stored in the P1 part. In the example shown in FIG. 4, “81 (hexadecimal number) = 10000001 (binary number)” is stored in the P1 part. In the example shown in FIG. 4, it is assumed that the last five digits of the binary number of the value in the P1 part indicate the identification information (EFID) of the EF. That is, in the example shown in FIG. 4, the P1 part designates “00001” as the EFID.

  The P2 part stores an offset value as information indicating a position (address) at which data is written in the binary EF designated by the P1 part. In the example illustrated in FIG. 4, “00” is stored in the P2 portion as information indicating the offset value in the binary EF of “EFID = 0001” specified in the P1 portion. That is, in the example shown in FIG. 4, the EFID is “00001” and the offset value is “0”. Therefore, in the write binary command shown in FIG. 4, the head address for the binary EF of “EFID = 0001” is designated as the data write start position in the P1 and P2 parts.

  In the Lc portion, information indicating the length (data length) of the entire data to be written as binary data is stored. The DATA part stores the first part of the data to be written. In this case, data up to a predetermined length is stored in the DATA section. That is, not all data having the length specified in the Lc part is necessarily stored in the DATA part. If the length of the entire data to be written as binary data is not long enough to be stored in the DATA part, the first part of the data to be written is stored in the DATA part.

  For example, in the example shown in FIG. 4, “1000” is designated as the data length in the Lc portion. This indicates that the data length of the entire binary data to be written is “1000”. In the DATA section, data having a data length of “100” is stored. Here, it is assumed that the data length that can be stored in the DATA section is “100”. In this case, as shown in FIG. 4, in the DATA portion of the write binary command, only the data from the beginning to the data length of “100” is stored in the entire binary data to be written.

  Therefore, the remaining “900” data among the binary data to be written needs to be supplied to the IC card 11 separately from the write binary command. For this reason, in the write binary command, the remaining data (binary data) that cannot be stored in the DATA portion of the command can be continuously supplied to the IC card 11. Here, it is assumed that data having a data length of “100” is sequentially transmitted following the write binary command.

  FIG. 5 is a diagram showing an example of data (command) to be transmitted following the write binary command shown in FIG. The entire binary data to be written specified by the write binary command shown in FIG. 4 is divided into data having a data length of “100” as shown in FIG. These data having a data length of “100” are sequentially transmitted following the write binary command.

  That is, binary data having a large data length that cannot be stored in the DATA portion of the write binary command is divided based on a predetermined data length, and sequentially supplied from the card reader / writer 12 to the IC card 11 following the write binary command. It has come to be. As a result, the IC card 11 sequentially receives binary data having a length specified in the Lc portion of the write binary command as transmission data following the DATA portion of the write binary command and the write binary command. In this case, the IC card 11 performs processing for writing received data.

Next, data write processing for the write binary command according to the first embodiment in such a configuration will be described with reference to the flowcharts shown in FIGS.
When activated by reset cancellation from the card reader / writer 12, the CPU 101 transmits initial response data to the card reader / writer 12 (step S1). When the initial response data is normally transmitted, the CPU 101 waits for reception of a command input from the card reader / writer 12, and when the command is normally received (step S2), the CLA portion and INS portion of the command receive a command. The type is confirmed (step S3). As a result of the confirmation, if the received command is other than the write binary command, the CPU 101 executes the corresponding command processing (step S4), but the description is omitted here.

  If the received command is a write binary command as a result of the confirmation in step S3, the CPU 101 checks whether the binary EF designated by the P1 part and the P2 part of the command exists in the data memory 102 (step S3). S5) If the designated binary EF does not exist, predetermined error processing is executed (step S6), and the process returns to the command reception waiting state in step S2.

  As a result of the check in step S5, if the designated binary EF exists, the CPU 101 calculates the write start address and write end address of the target EF written by the command received this time (step S7). In this calculation, the write start address is obtained by adding the offset value in the P1 part of the received command to the start address in the EF definition information of the EF (start address + offset value = write start address). The write end address is obtained by adding the offset value in the P1 portion of the received command and the data length in the Lc portion to the start address in the EF definition information of the EF (start address + offset value + data length = write end address). .

  Next, the CPU 101 checks whether or not the previous write start address and the previous write last address are written in the EF definition information of the EF (step S8). As a result of the confirmation, if both addresses are written, the process proceeds to step S9. If both addresses are not written, it is determined that the previous data writing is normally completed, and the process proceeds to step S10.

  In step S9, the write start address and write end address of the current write target EF calculated in step S7 match the previous write start address and previous write last address written in the EF definition information of the EF. Check if it is.

  As a result of this confirmation, if both addresses do not match, it is determined that data is written to a new EF, and the process proceeds to step S10. If both addresses match, it is determined that the command is to be retried and the process proceeds to step S11.

In step S10, it is confirmed whether or not the target EF to be written this time is in an unwritten state, that is, specific data (for example, all FF) indicating a data unwritten state. As a result of this confirmation, if the target EF to be written this time is not in an unwritten state, the CPU 101 executes a predetermined error process (step S12) and returns to the command reception waiting state in step S2.
As a result of the confirmation in step S10, when the target EF to be written this time is in an unwritten state, the process proceeds to step S11.

  In step S11, the write start address and write end address of the current write target EF calculated in step S7 are written as the previous write start address and previous write end address of the EF definition information of the EF.

Next, the CPU 101 performs a process of writing data stored in the DATA part of the command from the head address specified by the offset value stored in the P2 part of the received command (step S13).
For example, when a write binary command as shown in FIG. 4 is received, data stored in the DATA portion from the start address “8000” of the binary EF of “EFID = 0001” in the data memory 102 (total data length “1000”) Of the first data length of “100”) is written.

  When the writing process in step S13 is completed, the CPU 101 checks whether or not all data reception and writing processes are completed (step S14). This confirmation is determined by whether or not the writing of the data having the data length stored in the Lc portion of the command (that is, binary data for the entire data length) has been completed.

  As a result of the confirmation in step S14, if reception and writing of all data has not been completed, the CPU 101 transmits a response indicating completion of writing of the received data to the card reader / writer 12, and the next data (binary (Data) waiting to be received. The card reader / writer 12 performs processing for transmitting the next data (binary data) in response to a response indicating the end of writing from the IC card 11.

  When the next data is transmitted from the card reader / writer 12 in the data reception waiting state, the CPU 101 performs a reception process for receiving the data (step S15). In this reception process, the CPU 101 performs a process of checking whether or not data is normally received (step S16).

  If the CPU 101 determines that the data transmitted from the card reader / writer 12 has been normally received as a result of the check in step S16, the CPU 101 returns to step S13 and performs a process of writing the received data.

  As a result of the check in step S16, if it is determined that a communication error has occurred in the data reception process, that is, if a communication error has occurred in the middle of binary data reception, the CPU 101 executes a predetermined error process (step S17). ), The process returns to the command reception waiting state in step S2.

  As described above, the CPU 101 repeatedly executes the processes of steps S13 to S16 until it is determined that all data specified by the write binary command has been received. As a result, if an error such as a communication error does not occur, binary data that is divided and supplied can be written into the data memory 102 according to the conditions specified by the write binary command.

  If it is determined in step S14 that all the data (binary data having the data length specified in the Lc portion of the write binary command) has been received and written, the CPU 101 performs all the processes for the received write binary command. Judged to have completed normally.

  In this case, the CPU 101 performs a process of initializing the previous write start address and the previous write final address in the EF definition information specified by the write binary command to specific values (for example, all FFs) and completes normally. Processing is performed (step S18), and the process returns to the command reception waiting state in step S2. Here, as the normal termination process, for example, a process of notifying the card reader / writer 12 that writing of all data designated by the write binary command is completed.

Next, data write processing for a write binary command according to the second embodiment will be described with reference to the flowcharts shown in FIGS.
When activated by reset cancellation from the card reader / writer 12, the CPU 101 transmits initial response data to the card reader / writer 12 (step S21). When the initial response data is normally transmitted, the CPU 101 waits for reception of a command input from the card reader / writer 12, and when the command is normally received (step S22), the CLA unit and the INS unit of the command receive the command. The type is confirmed (step S23). As a result of the confirmation, if the received command is other than the write binary command, the CPU 101 executes the corresponding command processing (step S24), but the description is omitted here.

  If the received command is a write binary command as a result of the confirmation in step S23, the CPU 101 checks whether the binary EF designated by the P1 part and the P2 part of the command exists in the data memory 102 (step S23). S25) If the designated binary EF does not exist, predetermined error processing is executed (step S26), and the process returns to the command reception waiting state in step S2.

  As a result of the check in step S25, if the designated binary EF exists, the CPU 101 calculates the write start address and write end address of the target EF written by the command received this time (step S27). In this calculation, the write start address is obtained by adding the offset value in the P1 part of the received command to the start address in the EF definition information of the EF (start address + offset value = write start address). The write end address is obtained by adding the offset value in the P1 portion of the received command and the data length in the Lc portion to the start address in the EF definition information of the EF (start address + offset value + data length = write end address). .

  Next, the CPU 101 checks whether or not the previous write start address and the previous write last address are written in the EF definition information of the EF (step S28). As a result of the confirmation, if both addresses are written, the process proceeds to step S29. If both addresses are not written, it is determined that the previous data writing is normally completed, and the process proceeds to step S30.

  In step S29, the write start address and write end address of the current write target EF calculated in step S27 are within the range of the previous write start address and previous write end address written in the EF definition information of the EF. It is confirmed whether or not.

  As a result of this confirmation, if the current write start address and the write last address are within the range of the previous write start address and the previous write last address, the process proceeds to step S31, and the current write start address and the write final address are the previous write start address. If it is not within the range of the last address written last time, it is determined that data is written to a new EF, and the process proceeds to step S31.

In step S30, it is confirmed whether or not the target EF to be written this time is an unwritten state, that is, specific data (for example, all FF) indicating a data unwritten state. As a result of the confirmation, if the target EF to be written this time is not in an unwritten state, the CPU 101 executes a predetermined error process (step S33) and returns to the command reception waiting state in step S22.
As a result of the confirmation in step S30, if the target EF to be written this time is in an unwritten state, the process proceeds to step S32.

In step S31, it is confirmed whether or not the previous data writing process has failed midway. As a result of the confirmation, if the previous writing process has failed in the middle, the CPU 101 determines that the command is to be redone, and proceeds to step S32.
As a result of the confirmation in step S31, if there is no failure in the previous writing process, the CPU 101 determines that the data writing is for the new EF, and proceeds to step S30.

  Here, the confirmation method (determination method) of the previous write processing failure in step S31 is predetermined in advance from the last write last address in the EF because the data unwritten state is specific data (for example, all FF). It is checked whether specific data (FF) for a predetermined number of bytes exists continuously. If specific data (FF) for a predetermined number of bytes exists continuously, it is determined that data could not be written to the end. It is determined that the writing has failed.

  In step S32, the write start address and write end address of the current write target EF calculated in step S27 are written as the previous write start address and previous write end address of the EF definition information of the EF.

Next, the CPU 101 performs processing for writing data stored in the DATA portion of the command from the head address specified by the offset value stored in the P2 portion of the received command (step S34).
For example, when a write binary command as shown in FIG. 4 is received, data stored in the DATA portion from the start address “8000” of the binary EF of “EFID = 0001” in the data memory 102 (total data length “1000”) Of the first data length of “100”) is written.

  When the writing process in step S34 is completed, the CPU 101 confirms whether or not all data reception and writing processes are completed (step S35). This confirmation is determined by whether or not the writing of the data having the data length stored in the Lc portion of the command (that is, binary data for the entire data length) has been completed.

  As a result of the confirmation in step S35, if reception and writing of all data has not been completed, the CPU 101 transmits a response indicating completion of writing of the received data to the card reader / writer 12, and the next data (binary (Data) waiting to be received. The card reader / writer 12 performs processing for transmitting the next data (binary data) in response to a response indicating the end of writing from the IC card 11.

  When the next data is transmitted from the card reader / writer 12 in the data reception waiting state, the CPU 101 performs a reception process for receiving the data (step S36). In this reception process, the CPU 101 performs a process of checking whether or not data is normally received (step S37).

  If the CPU 101 determines that the data transmitted from the card reader / writer 12 has been normally received as a result of the check in step S37, the CPU 101 returns to step S34 and performs a process of writing the received data.

  As a result of the check in step S37, if it is determined that a communication error has occurred in the data reception process, that is, if a communication error has occurred in the middle of binary data reception, the CPU 101 executes a predetermined error process (step S38). ), The process returns to the command reception waiting state in step S22.

  As described above, the CPU 101 repeatedly executes the processes of steps S34 to S37 until it is determined that all the data designated by the write binary command has been received. As a result, if an error such as a communication error does not occur, binary data that is divided and supplied can be written into the data memory 102 according to the conditions specified by the write binary command.

  If it is determined in step S35 that all the data (binary data having the data length specified by the Lc portion of the write binary command) has been received and written, the CPU 101 performs all the processes for the received write binary command. It is determined that the process has been completed normally, normal termination processing is performed (step S39), and the process returns to the command reception waiting state in step S22. Here, as the normal termination process, for example, a process of notifying the card reader / writer 12 that writing of all data designated by the write binary command is completed.

  Next, data write processing for a write binary command according to the third embodiment will be described.

  The third embodiment is different in the process of step S31 in the second embodiment described above, that is, the confirmation method (determination method) of the previous write process failure, and the others are the same as in the second embodiment. Since it is the same, description is abbreviate | omitted and only a different part is demonstrated in detail.

  In rare cases, when the received data is written to the write target EF, the write process has failed, but the response from the IC card 11 to the card reader / writer 12 may be normal. In that case, an unwritten state exists in the middle. What is applied in such a case is the previous write process failure confirmation method (determination method) according to the third embodiment, which will be described below.

  First, as a first method, since the data unwritten state is specific data (for example, all FF), a predetermined number of bytes determined in advance between the previous write start address and the previous write final address in the EF. It is checked whether or not the specific data (FF) exists, and when the specific data (FF) exists for a predetermined number of bytes, it is determined that the data could not be written during the writing, and it is determined that the writing has failed.

  Next, as a second method, when a write binary command is received, the maximum number of consecutive FFs is obtained by performing FF search processing on the data stored in the DATA portion of the command, and this Record the maximum number of consecutive FFs obtained. That is, in the case of this example, as shown in FIG. 10, the EF definition information has a configuration in which “FF detection length” is added to the configuration in FIG. Stores numbers.

  When the next write binary command is received, the number of FFs continuously present in the EF from the previous write start address to the last write last address is obtained, and the obtained FF continuous number is the EF definition information of the EF. It is determined whether or not it is larger than the FF detection length (maximum number of FFs), and if the obtained number of FFs is larger than the FF detection length in the EF definition information, data could not be written during writing. It is determined that the writing has failed.

  In the example illustrated in FIG. 10, the FF detection length indicates a state where a specific value (for example, a numerical value “0”) is written as an initial value.

  As described above, according to the above embodiment, when a write error (write failure) occurs when writing data with a long data length to binary EF that is allowed to write data only once. By using the previous write start address and write end address recorded internally, it is possible to find the area where writing has failed and accept the write binary command again, so that the binary EF can be reused and efficient data Write processing is possible.

  In the above embodiment, the case where the present invention is applied to a contact type IC card as a portable electronic device has been described. However, the present invention is not limited to this and can be applied to a non-contact type IC card. It can also be applied to a portable terminal device or a mobile phone called PDA, and the shape of the portable electronic device is not limited to a card type, but a booklet type, a block type, a tag type, Other shapes may be used.

The block diagram which shows the structural example of the IC card system which handles the IC card as a portable electronic device which concerns on embodiment of this invention. 1 is a block diagram schematically showing the configuration of an IC card. The figure which shows schematically the structural example of EF definition information. The schematic diagram which shows the format of a write binary command. The figure which shows the example of the transmission data following a write binary command. 6 is a flowchart for explaining data write processing for a write binary command according to the first embodiment. 6 is a flowchart for explaining data write processing for a write binary command according to the first embodiment. 9 is a flowchart for explaining data write processing for a write binary command according to the second embodiment. 9 is a flowchart for explaining data write processing for a write binary command according to the second embodiment. The figure which shows schematically the structural example of the EF definition information which concerns on 3rd Embodiment.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 11 ... IC card (portable electronic device), 11a ... IC card main body, 12 ... Card reader / writer, 13 ... Terminal device, 14 ... Keyboard, 15 ... CRT display part, 16 ... Printer, 101 ... CPU (control element) , 102 ... Data memory (storage means), 103 ... Working memory, 104 ... Program memory, 105 ... Contact part, 106 ... IC chip, 21, 22, 23 ... EF definition information.

Claims (10)

A memory in which at least one data area in which data writing is permitted only once is set; and
Address storage means for storing a write start address and a write end address of data for a data area in which data writing is permitted only once;
When a command for instructing data writing to the data area where data writing is permitted only once is received, the write start address and write end address indicating the current data write range based on the specific information in the command Address calculating means for obtaining
Address writing means for writing the write start address and write end address calculated by the address calculation means into the address storage means;
Write processing means for performing a process of writing data of a length specified by the received instruction to the data area in which data writing is permitted only once;
When the writing of data by the writing processing means is normally completed, an initializing means for initializing a write head address and a write end address in the address storage means to specific values;
When a command for instructing data writing to the data area in which data writing is permitted only once is received again, the current write head address and write last address calculated by the address calculation means for the command First determination means for determining whether the address matches the previous write start address and write end address in the address storage means;
As a result of the determination by the first determination means, if the current write start address and write end address match the previous write start address and write end address, the previous data write processing for the data area does not end normally. Rewriting processing means for performing processing for rewriting the data in the data area to data of a length specified by the re-received instruction;
A portable electronic device comprising: A memory in which at least one data area in which data writing is permitted only once is set; and
Address storage means for storing a write start address and a write end address of data for a data area in which data writing is permitted only once;
When a command for instructing data writing to the data area where data writing is permitted only once is received, the write start address and write end address indicating the current data write range based on the specific information in the command Address calculating means for obtaining
Address writing means for writing the write start address and write end address calculated by the address calculation means into the address storage means;
Write processing means for performing a process of writing data of a length specified by the received instruction to the data area in which data writing is permitted only once;
When a command for instructing data writing to the data area in which data writing is permitted only once is received again, the current write head address and write last address calculated by the address calculation means for the command Second determination means for determining whether the address is within the range of the previous write start address and write end address in the address storage means;
As a result of the determination by the second determination means, if the current write start address and write end address are within the range of the previous write start address and write end address, a write failure has occurred in the previous data write process for the data area. Third determination means for determining whether or not there has been,
As a result of the determination by the third determination means, if there is a write failure in the previous data write process, the process of rewriting the data in the data area with the data of the length specified by the command received again Rewrite processing means to be performed;
A portable electronic device comprising:   In the data area, the third determination unit writes the previous data when there is specific data indicating a data unwritten state continuously for a predetermined length ahead from the last write last address in the address storage unit. The portable electronic device according to claim 2, wherein it is determined that there has been a writing failure in the process.   In the data area, when the specific data indicating the data non-written state is continuously present for a predetermined length between the previous write start address and the write end address in the data storage area, The portable electronic device according to claim 2, wherein it is determined that there has been a writing failure during the previous data writing process.   The third determination means stores the number of consecutive specific data by searching for specific data indicating a data unwritten state in the data written by the command when the previous command is received, and receives the current command By searching for specific data indicating a data non-written state in the data area sometimes, the specific data indicating the data non-written state continuously between the previous write start address and the write final address in the address storage means 3. The portable electronic device according to claim 2, wherein when there are more than the stored number, it is determined that there has been a writing failure during the previous data writing process. A memory in which at least one data area in which data writing is permitted only once is set, and a write start address and a write end address of data in the data area in which data writing is permitted only once are stored. Address storage means for receiving data and a command for instructing data writing to the data area in which data writing is permitted only once, the current data writing range is indicated based on specific information in the command. An address calculation means for obtaining a write start address and a write end address, an address write means for writing the write start address and the write end address calculated by the address calculation means into the address storage means, and designated by the received instruction The length data is allowed to be written only once. Write processing means for performing processing for writing to the data area, and when writing of data by the write processing means is normally completed, the write start address and write end address in the address storage means are initialized to specific values. And when the instruction for instructing data writing to the data area in which data writing is permitted only once is received again, the present time calculated by the address calculating means for the instruction The first determination means for determining whether or not the write start address and write end address of the first address coincide with the previous write start address and write end address in the address storage means, and the result of determination by the first determination means This write start address and write end address are the previous write start address and write end address. If it matches the address, it is determined that the previous data writing process for the data area did not end normally, and the data in the data area is changed to data of the length specified by the received instruction again. An IC module having a rewrite processing means for performing a rewrite process;
An IC card body containing the IC module;
An IC card comprising: A memory in which at least one data area in which data writing is permitted only once is set, and a write start address and a write end address of data in the data area in which data writing is permitted only once are stored. Address storage means for receiving data and a command for instructing data writing to the data area in which data writing is permitted only once, the current data writing range is indicated based on specific information in the command. An address calculation means for obtaining a write start address and a write end address, an address write means for writing the write start address and the write end address calculated by the address calculation means into the address storage means, and designated by the received instruction The length data is allowed to be written only once. A write processing means for performing processing for writing to the data area, and a command for instructing data writing to the data area for which data writing is permitted only once. Second determination means for determining whether or not the current write start address and write end address calculated by the address calculation means are within the range of the previous write start address and write end address in the address storage means; If, as a result of the determination by the second determination means, the current write head address and write last address are within the range of the previous write start address and write last address, the previous data write process for the data area failed to be written. Third determination means for determining whether or not there has been, and determination by the third determination means As a result, there is a rewrite processing means for performing a process of rewriting the data in the data area to the data of the length specified by the re-received instruction when there is a write failure in the previous data write process. A configured IC module;
An IC card body containing the IC module;
An IC card comprising:   In the data area, the third determination unit writes the previous data when there is specific data indicating a data unwritten state continuously for a predetermined length ahead from the last write last address in the address storage unit. 8. The IC card according to claim 7, wherein it is determined that there has been a writing failure in the processing.   In the data area, when the specific data indicating the data non-written state is continuously present for a predetermined length between the previous write start address and the write end address in the data storage area, 8. The IC card according to claim 7, wherein it is determined that a writing failure has occurred during the previous data writing process.   The third determination means stores the number of consecutive specific data by searching for specific data indicating a data unwritten state in the data written by the command when the previous command is received, and receives the current command By searching for specific data indicating a data non-written state in the data area sometimes, the specific data indicating the data non-written state continuously between the previous write start address and the write final address in the address storage means 8. The IC card according to claim 7, wherein when there are more than the stored number, it is determined that there has been a writing failure during the previous data writing process.

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