JP2007122394A - Portable electronic device, and ic card - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a portable electronic device and an IC card enabling to reuse a data area by writing data from an opposite direction in the same area when all data can not be written due to communication failure or the like in the middle of data writing, for example, in writing large quantities of data in the data area in which data writing is allowed only once. <P>SOLUTION: The IC card is provided with a memory for storing the data, and a control element for reading and/or writing the data from/in the memory, executes processing corresponding to a command input from the outside, and outputs a result to the outside. At least one or more data areas in which the data writing is allowed only once are set in the memory. When all of the data can not be written due to the communication failure or the like in the middle of the data writing in wiring the data (especially the large quantities of the data such as image data) in the data area in which the data writing is allowed only once, the data is written from the opposite direction in the same area. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention incorporates an IC (Integrated Circuit) chip having control elements such as a writable and rewritable nonvolatile memory and a CPU (Central Processing Unit), and performs various processes based on commands supplied from the outside. The present invention relates to a portable electronic device such as an IC card that executes and outputs the result to the outside, and an IC card.

  Recently, as a portable electronic device, an EEPROM as a nonvolatile memory, a RAM as a volatile memory, a CPU as a control element for accessing (reading or writing data, etc.) the memory, and the CPU Built-in IC chip with ROM that stores operation programs, etc., and means for executing processing corresponding to commands supplied from an external device (IC card reader / writer) and outputting the result to the external device IC cards are used in various industries.

In this type of IC card, some nonvolatile memories have a large memory capacity and a data area (binary elementary file) in which binary data is written only once and cannot be rewritten is set ( For example, refer nonpatent literature 1).
For example, when long data such as image data is written in the data area in which data writing is permitted only once, data input from the outside is divided and written sequentially. If the data writing is interrupted due to a communication error in the middle of the writing, even if the same command is executed again, the data has been written halfway. Can not.
Japanese Industrial Standards compliant JICSAP IC card with external terminal specifications (July 1998, 1.1 version)

  However, in the conventional technique described above, if data writing is interrupted in the middle of writing a particularly long data in a data area in which data writing is permitted only once, the same command may be executed again. Since the data has been written halfway, there is a problem that the writing is abnormal, the IC card cannot be reused, and it is not efficient.

  Therefore, in the present invention, for example, when a large amount of data is written in a data area in which data writing is permitted only once, all data cannot be written due to a communication error or the like during the data writing. An object of the present invention is to provide a portable electronic device and an IC card that can reuse a data area by writing data from the opposite direction in the same area.

  The portable electronic device of the present invention has a memory for storing data and a control element for reading and writing data to the memory, and executes processing corresponding to an externally input command. In the portable electronic device in which the result is output to the outside and at least one data area in which writing of data is permitted only once is set in the memory, the arrangement of data in the data area Indicates whether the direction is "from the first address to the last address", "from the last address to the first address", or "unwritable in both directions", and the initial state is set to "from the first address to the last address" Data writing to the first identifier and the data area in which data writing is permitted only once in the memory When performing the first identifier, the first identifier for checking the state of the first identifier, and as a result of the check by the first identifier, the first identifier has a data arrangement direction “from the first address to the last address. , The first writing means for writing data to the data area in the arrangement direction from the head address, and when a writing error occurs when writing data by the first writing means, As a result of the check by the first control means for switching the first identifier from “last address to head address” as the data arrangement direction and the first check means, the first identifier is the data arrangement direction. Is “From the last address to the top address”, the data is written to the data area in the arrangement direction from the last address. And a second control unit that switches the first identifier to “unwritable in both directions” when a write error occurs when data is written by the second writing unit. .

  The IC card of the present invention has a memory for storing data and a control element for reading and writing data to the memory, and executes processing corresponding to a command input from the outside. In the IC card in which at least one data area in which data writing is permitted only once is set in the memory, the data alignment direction in the data area is It indicates whether it is “from the top address to the last address”, “from the last address to the headless” or “unwritable in both directions”, and the initial state is set to “from the head address to the last address” Data is written to the first identifier and the data area in which data is allowed to be written only once in the memory. As a result of checking by the first checking means for checking the state of the first identifier and the first checking means, the first identifier has the data arrangement direction “from the first address to the last address”. The first write means for writing data to the data area in the arrangement direction from the head address, and when a write error occurs when data is written by the first write means, the first write means As a result of the check by the first control means for switching the identifier from “last address to head address” as the data arrangement direction, and the first check means, the first identifier indicates that the data arrangement direction is “final 2nd write that writes data to the data area in the arrangement direction from the last address. And an IC module having a second control means for switching and setting the first identifier to “unwritable in both directions” when a write error occurs when data is written by the second writing means, And an IC card main body containing the IC module.

  According to the present invention, for example, when a large amount of data is written to a data area in which data writing is permitted only once, all data cannot be written due to a communication error or the like during the data writing. By writing data from the opposite direction in the same area, a portable electronic device and an IC card that can reuse the data area can be provided.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
First, the first embodiment will be described.
FIG. 1 shows a configuration example of an IC card system that handles an IC card as a portable electronic device according to the present embodiment. In this IC card system, the IC card 11 can be connected to a terminal device 13 such as a personal computer via a card reader / writer 12, and a keyboard 14, a CRT display unit 15, and a printer 16 are connected to the terminal device 13. Composed.

  FIG. 2 shows the configuration of the IC card 11, and includes a CPU 101 as a control element, a data memory 102 as a storage means (memory) whose contents can be rewritten, a working memory 103, a program memory 104, a card reader, The contact portion 105 is used to obtain electrical contact with the writer 12. Of these, the portion within the broken line (CPU 101, data memory 102, working memory 103, program memory 104) is composed of one (or a plurality) of IC chips 106, and further this IC chip 106 and contact portion 105. Are integrated into an IC module and embedded in the IC card main body 11a.

  The data memory 102 is configured by a nonvolatile memory such as an EEPROM, which can rewrite stored contents, and stores various application data in a file structure.

  For example, the data memory 102 has at least one data area (binary elementary file) EF that has a large memory capacity and cannot be rewritten by writing binary data only once. This data area EF Assume that long data such as image data (for example, a face image of 10 Kbytes or 20 Kbytes or more) is stored in.

  The data area EF indicates whether the data arrangement direction in the data area EF is “from the start address to the end address”, “from the end address to the start address”, or “writable in both directions”. Thus, the initial state is set at the time of writing data to the data area EF and the flag F1 as the first identifier set to “from the first address to the last address” and cleared at the end of the data writing. Each flag F2 as a second identifier is stored. The flag F1 is applied to both data write processing and data read processing.

The working memory 103 is a working memory for temporarily storing processing data when the CPU 101 performs processing, and is configured by, for example, a RAM.
The program memory 104 is composed of, for example, a non-volatile memory that cannot be rewritten, such as a mask ROM, and stores a control program of the CPU 101 and the like.

  FIG. 3 shows a write binary (WRITE BINARY) command format for writing binary data to a data area in the data memory 102 in which data writing is permitted only once. The write binary command is input from the card reader / writer 12, and includes a classification unit (CLA: class) having a function for identifying the command, an instruction unit (INS: instruction), parameter data (P1, P2), a writing It consists of a data length (Lc) representing the length of data to be inserted and write data (DATA).

  Next, in such a configuration, when data is written to the data areas shown in the flowcharts shown in FIGS. 4 and 5 and the data areas shown in FIGS. 6 and 7 in the data writing process for the write binary command according to the first embodiment. This will be described with reference to the image diagram.

  When activated by reset cancellation from the card reader / writer 12, the CPU 101 transmits initial response data to the card reader / writer 12 (step S1). When the initial response data is normally transmitted, the CPU 101 waits for reception of a command input from the card reader / writer 12, and when the command is normally received (step S2), the CLA portion and INS portion of the command receive a command. The type is confirmed (step S3). As a result of the confirmation, if the received command is other than the write binary command, the CPU 101 executes the corresponding command processing, but the description is omitted here.

  If the received command is a write binary command as a result of the confirmation in step S3, the CPU 101 determines whether or not the data area (binary file) EF designated by the P1 part and P2 part of the command exists in the data memory 102. Is checked (step S4), and if the designated data area EF does not exist, the process ends, and the process returns to the command reception waiting state in step S2.

  As a result of the check in step S4, when the designated data area EF exists, the CPU 101 checks the state of the flag F2 in the data area EF (see step S5, FIG. 6A). This time, the flag F2 is in a clear state for the first writing process.

  As a result of the check in step S5, if the flag F2 is in the clear state, the CPU 101 checks the state of the flag F1 in the data area EF (step S6). This time, for the first writing, the flag F1 is in an initial state, and the data arrangement direction is “from the first address to the last address”.

  As a result of the check in step S6, when the flag F1 indicates that the data arrangement direction is “from the first address to the last address”, the CPU 101 determines the values of the P1 part and P2 part of the received write binary command and the Lc part. Based on the value (write size) and the state of the flag F1, whether the write destination range seen from the start address of the data area EF is less than the size of the data area EF (the write destination range seen from the start address is area over) (Step S7, see FIG. 6B), and if the write destination range seen from the head address is over the area, the process is terminated and the process returns to the command reception waiting state in step S2.

  As a result of the check in step S7, if the write destination range seen from the top address is not over the area, the CPU 101 checks whether all the write destination ranges seen from the top address of the data area EF are initial values ( In step S8), if all the write destination ranges viewed from the top address are not initial values, the process is terminated and the process returns to the command reception waiting state in step S2.

  As a result of the check in step S8, when all the write destination ranges viewed from the top address are initial values, the CPU 101 starts data write processing. That is, first, the flag F2 in the data area EF is set (step S9, see FIG. 6C). Next, the CPU 101 writes data in the data area EF in the data arrangement direction (from the top address) indicated by the flag F1 (see step S10, FIG. 6C).

  Next, the CPU 101 checks whether or not all data has been normally written (step S11). If the data has been written halfway due to a communication failure or the like, the CPU 101 sets the flag F1 in the data area EF for the data. The arrangement direction is switched to “from the last address to the head address”, and then the flag F2 is cleared and the process returns to the command reception waiting state in step S2 (see steps S12 and S13, FIGS. 6D and 6E). ).

  As a result of the check in step S11, when all data has been written normally, the CPU 101 clears the flag F2 while keeping the flag F1 (step S13), and returns to the command reception waiting state in step S2. This completes the writing process.

  If the IC card 11 cannot be processed during the data writing process (for example, the power is turned off during writing), the flag F2 remains set. Become.

  Next, a case will be described in which data writing processing is performed on the same data area EF when writing has failed last time (however, the IC card 11 performs termination processing).

  As described above, the process proceeds to steps S1 to S4. When the designated data area EF exists, the CPU 101 checks the state of the flag F2 in the data area EF (see step S5, FIG. 7A). This time, the flag F2 is in the clear state because the end processing is performed due to the previous writing failure in the second writing processing.

  Therefore, the CPU 101 continues to check the state of the flag F1 in the data area EF (step S6). In this case, in the second writing process, the end process is performed due to the previous writing failure, and the data alignment direction of the flag F1 is not “from the first address to the last address”. It is checked whether or not the data arrangement direction of F1 is “from the last address to the head address” (step S14).

  As a result of the check in step S14, if the flag F1 does not indicate that the data arrangement direction is “from the last address to the head address”, the CPU 101 ends the process and returns to the command reception waiting state in step S2.

  As a result of the check in step S14, when the flag F1 indicates that the data arrangement direction is “from the last address to the head address”, the CPU 101 sets the offset value, write size, and flag F1 state of the received write binary command. Based on this, it is checked whether the write destination range seen from the final address of the data area EF is less than the size of the data area EF (the write destination range seen from the final address is area over) (step S15, FIG. 7). (Refer to (b)), when the write destination range seen from the final address is over the area, the process is terminated and the process returns to the command reception waiting state in step S2.

  As a result of the check in step S15, if the write destination range seen from the final address is not over the area, the CPU 101 checks whether all the write destination ranges seen from the final address of the data area EF are initial values ( In step S16), if all the write destination ranges viewed from the final address are not initial values, the process is terminated, and the process returns to the command reception waiting state in step S2.

  As a result of the check in step S16, if all the write destination ranges viewed from the final address are initial values, the CPU 101 starts data write processing. That is, first, the flag F2 in the data area EF is set (step S17, see FIG. 7C). Next, the CPU 101 writes data in the data area EF in the data arrangement direction (from the last address) indicated by the flag F1 (see step S18, FIG. 7C).

  Next, the CPU 101 checks whether or not all the data has been normally written (step S19). If the data has been written halfway due to communication failure or the like, the CPU 101 sets the flag F1 in the data area EF to “bidirectional”. Then, the flag F2 is cleared and the process returns to the command reception waiting state in step S2 (see steps S20 and S21, FIG. 7 (d)).

  As a result of the check in step S19, when all data has been written normally, the CPU 101 clears the flag F2 while keeping the flag F1 (see step S21, FIG. 7E), and waits for command reception in step S2. Return to state. This completes the writing process.

  Next, a description will be given of a case where data writing processing is performed on the same data area EF when writing failed last time (however, the IC card 11 is forcibly terminated).

  As described above, the process proceeds to steps S1 to S4. When the designated data area EF exists, the CPU 101 checks the state of the flag F2 in the data area EF (see step S5, FIG. 7A). Although this time is the second writing process, the flag F2 is in the set state because the termination process is not performed due to the previous writing failure (forced termination).

  Therefore, the CPU 101 continues to check the state of the flag F1 in the data area EF (step S22). As a result of this check, if the flag F1 indicates that the data arrangement direction is “from the first address to the last address”, the CPU 101 switches the flag F1 from “last address to the first address”. After setting (step S23), the flag F2 is cleared (step S24), and the process proceeds to step S14.

  As a result of the check in step S22, if the flag F1 does not indicate that the data arrangement direction is “from the first address to the last address”, the CPU 101 switches and sets the flag F1 to “unwritable in both directions” (step S25). Thereafter, the flag F2 is cleared (step S26), and the process returns to the command reception waiting state in step S2.

  In step S14, it is checked whether or not the data arrangement direction of the flag F1 is “from the last address to the head address”, and the flag F1 is “data heading from the last address to the head address”. If not, the CPU 101 ends the process and returns to the command reception waiting state in step S2.

  As a result of the check in step S14, when the flag F1 indicates that the data arrangement direction is “from the last address to the head address”, the CPU 101 determines the values of the P1 part and P2 part of the received write binary command and the Lc part. Based on the value (write size) and the state of the flag F1, whether the write destination range seen from the final address of the data area EF is less than the size of the data area EF (write destination range seen from the final address is area over) (Step S15, see FIG. 7B), and if the write destination range seen from the final address is over the area, the process is terminated and the process returns to the command reception waiting state in step S2.

  As a result of the check in step S15, if the write destination range seen from the final address is not over the area, the CPU 101 checks whether all the write destination ranges seen from the final address of the data area EF are initial values ( In step S16), if all the write destination ranges viewed from the final address are not initial values, the process is terminated, and the process returns to the command reception waiting state in step S2.

  As a result of the check in step S16, if all the write destination ranges viewed from the final address are initial values, the CPU 101 starts data write processing. That is, first, the flag F2 in the data area EF is set (step S17, see FIG. 7C). Next, the CPU 101 writes data in the data area EF in the data arrangement direction (from the last address) indicated by the flag F1 (see step S18, FIG. 7C).

  Next, the CPU 101 checks whether or not all the data has been normally written (step S19). If the data has been written halfway due to communication failure or the like, the CPU 101 sets the flag F1 in the data area EF to “bidirectional”. Then, the flag F2 is cleared and the process returns to the command reception waiting state in step S2 (see steps S20 and S21, FIG. 7 (d)).

  As a result of the check in step S19, when all data has been written normally, the CPU 101 clears the flag F2 while keeping the flag F1 (see step S21, FIG. 7E), and waits for command reception in step S2. Return to state. This completes the writing process.

  When data writing is performed to the same data area EF when the writing has failed twice, the command processing is terminated when it is determined that the state of the flag F1 is “impossible in both directions”.

Next, a second embodiment will be described.
In the second embodiment, the initial state of the data area EF is set to “data area is initialized”, and when data writing is completed, the data area EF is switched to “data area is already written”. A flag F3 as a third identifier is stored.

  Hereinafter, the data write processing for the write binary command according to the second embodiment will be described. However, the description of the same parts as those of the first embodiment (FIGS. 4 and 5) is omitted, and different parts are illustrated. 8 and an image diagram when data is written in the data area shown in FIG. 9 will be described.

  As shown in FIG. 8, the difference from the first embodiment described above is that step S27 is added between step S15 and step S16, and step S28 is executed between step S18 and step S19. Is different, and the others are the same.

  That is, as in the first embodiment described above, the process proceeds to steps S1 to S14, and when the flag F1 indicates that the data arrangement direction is “from the last address to the head address”, the CPU 101 receives the received write binary. Based on the values of the P1 and P2 parts of the command, the value of the Lc part (write size), and the state of the flag F1, the write destination range viewed from the final address of the data area EF is less than the size of the data area EF (final address (See step S15, FIG. 9 (b)), and if the write destination range seen from the final address is over the area, the process is terminated. Return to the command reception waiting state in step S2.

  As a result of the check in step S15, if the write destination range viewed from the final address is not over the area, the CPU 101 checks the state of the flag F3 in the data area EF (step S27). If it is set to “enable state”, the data writing process is started. If the flag F3 is set to “data area has been written” as a result of the check in step S27, the CPU 101 starts the data writing process after performing the process in step S16.

  That is, first, the flag F2 in the data area EF is set (step S17, see FIG. 9C). Next, the CPU 101 writes data to the data area EF in the data arrangement direction (from the last address) indicated by the flag F1 (see step S18, FIG. 9C). At this time, the CPU 101 switches and sets the flag F3 to “data area has been written” (step S28).

  Next, the CPU 101 checks whether or not all the data has been normally written (step S19). If the data has been written halfway due to communication failure or the like, the CPU 101 sets the flag F1 in the data area EF to “bidirectional”. Then, the flag F2 is cleared and the process returns to the command reception waiting state in step S2 (steps S20 and S21).

  As a result of the check in step S19, if all data has been written normally, the CPU 101 clears the flag F2 while keeping the flag F1 (see step S21, FIG. 9D), and waits for command reception in step S2. Return to state. This completes the writing process.

  The flag F3 is not checked when the flag F1 indicates that the data alignment direction is “from the first address to the last address” as a result of the check in step S6.

  As described above, when the flag F3 is "initialized state" as a result of the check in step S27, even if data is written in the data area EF, it is ignored and the data from the last address is ignored. When data is written in the arrangement direction and the flag F3 is “data area has been written”, it is confirmed that all the write destination ranges viewed from the final address of the data area EF are initial values, and the final address Data is written in the arrangement direction from.

  As described above, according to the above-described embodiment, when data (especially a large amount of data such as image data) is written to a data area in which data writing is permitted only once, the data is being written. If all data cannot be written due to a communication error or the like, the data area can be reused by writing data from the opposite direction in the same area, which is very efficient.

  In the above embodiment, the case where the present invention is applied to a contact type IC card as a portable electronic device has been described. However, the present invention is not limited to this and can be applied to a non-contact type IC card. It can also be applied to a portable terminal device or a mobile phone called PDA, and the shape of the portable electronic device is not limited to a card type, but a booklet type, a block type, a tag type, Other shapes may be used.

The block diagram which shows the structural example of the IC card system which handles the IC card as a portable electronic device concerning the present invention. 1 is a block diagram schematically showing the configuration of an IC card. The schematic diagram which shows the format of a write binary command. 6 is a flowchart for explaining data write processing for a write binary command according to the first embodiment. 6 is a flowchart for explaining data write processing for a write binary command according to the first embodiment. The image figure at the time of writing data in a data area in the data write-in process with respect to the write binary command which concerns on 1st Embodiment. The image figure at the time of writing data in a data area in the data write-in process with respect to the write binary command which concerns on 1st Embodiment. The main part flowchart explaining the data write-in process with respect to the write binary command which concerns on 2nd Embodiment. The image figure at the time of writing data in a data area in the data write-in process with respect to the write binary command which concerns on 2nd Embodiment.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 11 ... IC card (portable electronic device), 11a ... IC card main body, 12 ... Card reader / writer, 13 ... Terminal device, 14 ... Keyboard, 15 ... CRT display part, 16 ... Printer, 101 ... CPU (control element) , 102 ... Data memory (storage means), 103 ... Working memory, 104 ... Program memory, 105 ... Contact part, 106 ... IC chip, EF ... Data area (binary elementary file), F1 ... Flag (first identifier) ), F2... Flag (second identifier), F3... Flag (third identifier).

Claims (6)

It has a memory for storing data and a control element for reading and writing data to this memory, executes processing corresponding to a command input from the outside, and outputs the result to the outside. And in the portable electronic device in which at least one data area in which data writing is permitted only once is set in the memory,
This indicates whether the data alignment direction in the data area is “from the start address to the end address”, “from the end address to the start address”, or “unwritable in both directions”. A first identifier set to `` to the final address '',
First check means for checking a state of the first identifier when data is written to a data area in which writing of data is permitted only once in the memory;
As a result of the check by the first checking means, if the first identifier indicates that the data alignment direction is “from the first address to the last address”, the data is stored in the data area in the alignment direction from the first address. First writing means for writing
A first control unit that switches and sets the first identifier to “from the last address to the first address” when a write error occurs when data is written by the first writing unit;
As a result of the check by the first checking means, if the first identifier indicates that the data arrangement direction is “from the last address to the head address”, the data for the data area is arranged in the arrangement direction from the last address. Second writing means for writing
A second control unit that switches and sets the first identifier to “unwritable in both directions” when a write error occurs when data is written by the second writing unit;
A portable electronic device comprising: A second identifier that is set when data is written by the first writing means or the second writing means, and is cleared when the writing of the data is completed;
A second check means for checking a state of the second identifier when data is written to the data area in which data writing is permitted only once;
If the second identifier is set as a result of the check by the second checking means, a third control for switching and setting the first identifier from “last address to head address” in the data arrangement direction And further comprising means,
The said 1st check means checks the state of the said 1st identifier, when the 2nd identifier is cleared as a result of the check by the said 2nd check means, The said 1st identifier is characterized by the above-mentioned. Portable electronic device. The initial state is set to “initialized state for a data area in which data writing is permitted only once”. When data writing by the second writing unit is completed, “data writing is permitted only once” A third identifier that is set to be switched to “data area is already written”;
As a result of the check by the first check means, if the first identifier has a data arrangement direction “from the last address to the head address”, a third check for checking the state of the third identifier And further comprising means,
When the third identifier is "a data area in which data writing is permitted only once is initialized" as a result of the check by the third checking means, the second writing means Even if data is written in the area, it is ignored and the data is written in the arrangement direction from the last address, and the third identifier is “data area in which data writing is permitted only once has been written”. 2. The mobile phone according to claim 1, wherein the data is written in the arrangement direction from the final address after confirming that all the write destination ranges viewed from the final address of the data area are initial values. Possible electronic device. It has a memory for storing data and a control element for reading and writing data to this memory, executes processing corresponding to a command input from the outside, and outputs the result to the outside. In the IC card in which at least one data area in which data writing is permitted only once is set in the memory,
This indicates whether the data alignment direction in the data area is “from the start address to the end address”, “from the end address to the start address”, or “unwritable in both directions”. Checks the status of the first identifier when writing data to the first identifier set to “to the last address” and the data area in which data writing is permitted only once in the memory. The first checking means that performs the check, and if the first identifier indicates that the data alignment direction is “from the first address to the last address”, the first identifier is the alignment direction from the first address. The first writing means for writing data to the data area and the data writing at the time of data writing by the first writing means When an error occurs, the first control means for switching the first identifier from “the last address to the head address” and setting the data arrangement direction, and the result of the check by the first check means, In the case where the identifier of 1 indicates that the data arrangement direction is “from the last address to the head address”, the second writing means for writing data to the data area in the arrangement direction from the last address; An IC module having a second control means for switching and setting the first identifier to "unwritable in both directions" when a write error occurs when data is written by the second write means;
An IC card body containing the IC module;
An IC card comprising: The IC module further includes:
A second identifier that is set when data is written by the first writing means or the second writing means, and is cleared when the writing of the data is completed, and the data area in which data writing is permitted only once When the data is written, the second check means for checking the state of the second identifier, and if the second identifier is set as a result of the check by the second check means, the first identifier And a third control means for switching and setting the identifier of the data from “last address to head address” in the data alignment direction,
The said 1st check means checks the state of the said 1st identifier, when the 2nd identifier is cleared as a result of the check by the said 2nd check means, The said 1st identifier is characterized by the above-mentioned. IC card. The IC module further includes:
The initial state is set to “initialized state for a data area in which data writing is permitted only once”. When data writing by the second writing unit is completed, “data writing is permitted only once” As a result of the check by the first checking means and the first identifier, the data arrangement direction of the first identifier is “from the last address to the head address”. And a third check means for checking the state of the third identifier,
When the third identifier is "a data area in which data writing is permitted only once is initialized" as a result of the check by the third checking means, the second writing means Even if data is written in the area, it is ignored and the data is written in the arrangement direction from the last address, and the third identifier is “data area in which data writing is permitted only once has been written”. 5. The IC according to claim 4, wherein if the data is written, data is written in the arrangement direction from the final address after confirming that all the write destination ranges viewed from the final address of the data area are initial values. card.

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