JP2008044120A - Image forming apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To continue activity by reducing affects to image data by a failure in a period until a part is replaced even if a trouble occurs on a specified bit by an LSI failure. <P>SOLUTION: A failed bit specifying section 11-1 specifies the failed bit from bits bit0 to 7. A bit replacing section 12-1 shifts each bit to a lower rank one by one when the failed bit is specified. Also, a bit returning section 13-1 shifts each bit to a higher rank one by one. Input data are inputted in a block 2-1 when each bit is shifted to the lower rank one by one by the bit replacing section 12-1, and a specified image process is applied to the input data, and the input data are outputted. The bit returning section 13-1 outputs the bit on a next step by shifting each bit to the higher rank one by one. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to an image forming apparatus that mounts a large-scale and a large number of memories in an LSI, performs image processing using these memories, and outputs a printout.

  In recent years, failure of LSIs has increased due to the complexity of chip structures such as multilayer wiring in addition to miniaturization and higher density of semiconductor processes. Many of the initial failures due to problems in the manufacturing process are removed by a screening test at the time of LSI shipment, but it is not possible to remove all failures such as an accidental failure that occurs after a lapse of time from the start of use.

  By the way, in some image forming apparatuses such as copying machines and printers, one pixel data is handled by multi-value data representing gradation. When a failure occurs in a specific bit of an LSI that handles such image data, the gradation increases or decreases as a whole, and a desired image cannot be obtained. When a failure is detected in a copier / printer, it is common to stop the system and notify the user. However, the user uses the necessary copier / printer until the failed part is replaced. There was a problem that I could not.

  FIG. 9 is a block diagram illustrating an internal configuration of an LSI of an image forming apparatus according to a conventional technique. FIG. 10 is a conceptual diagram showing an example of a problem that occurs when an LSI of an image forming apparatus according to the prior art has a failure. The LSI 1 used in the image forming apparatus incorporates at least one or more blocks (image processing systems) 2-1 and 2-2 for performing predetermined image processing. For the input image data (8-bit gradation data), for example, in the block (image processing system) 2-1, a failure occurs in the most significant bit bit7, and 1 bit is always set. When the image data having the gradation as shown in FIG. 10A is input, the overall gradation increases as in the image data shown in FIG.

  When a failure such as that described above is detected in a copier / printer, it is common to stop the system and notify the user. However, during the period up to repair, such as replacing the failed part, There is a problem that a necessary copier / printer cannot be used.

  In view of this, some techniques have been proposed that enable the image forming apparatus to be used during a period until repair even if a failure is detected. For example, when a black control system fails in a color image forming apparatus that forms an image using a plurality of colors, a technique for synthesizing / substituting black with another color (for example, see Patent Document 1), or multi-beam image formation In the apparatus, a technique for printing using a beam other than the broken beam has been proposed (for example, see Patent Document 2).

JP-A-5-303243 Japanese Patent Laid-Open No. 11-48528

  However, the above-described prior art (Patent Document 1) has a problem that it can be dealt with only when a color machine and black color break down. Further, the above-described prior art (Patent Document 2) is only related to the failure of the laser diode, and there is a problem that it cannot be dealt with when a failure of a circuit such as an LSI occurs.

  Therefore, the present invention provides an image forming apparatus capable of reducing the influence on image data due to a failure during a period until parts replacement even if a failure occurs in a specific bit due to an LSI failure. The purpose is to provide.

  To achieve the above object, an image forming apparatus according to a first aspect of the present invention includes an image processing system that performs image processing on image data composed of a plurality of bits supplied by a data path arranged in parallel and outputs the image data. In the image forming apparatus according to the present invention, when a failure bit is specified by the failure bit specification means for specifying the failure bit in the data path and the failure bit specification means, the path of the failure bit is replaced with a path of another bit. Bit replacement means.

  As a preferred mode, for example, as in claim 2, in the image forming apparatus according to claim 1, the plurality of bits have priority, and the bit replacement means is prioritized by the fault bit specifying means. When a bit having a high degree is identified as a failure bit, the path of the bit having a higher priority is replaced with a path having a bit having a lower priority.

  As a preferred mode, for example, as in claim 3, in the image forming apparatus according to claim 2, the plurality of bits are gradation data, and the upper bit has higher priority than the lower bit. It is characterized by.

  As a preferred aspect, for example, as in claim 4, in the image forming apparatus according to claim 2, the plurality of bits include gradation data and tag information representing additional information for the gradation data. The bit representing the gradation data has a higher priority than the bit representing the tag information.

  Further, as a preferred aspect, for example, as in claim 5, the image forming apparatus according to claim 1, further comprising a bit return means for returning the path of the bits exchanged by the bit exchange means to the original state. Features.

  According to the present invention, the faulty bit in the data path is specified by the faulty bit specifying means, and when the faulty bit is specified, the path of the faulty bit is replaced with a path of another bit by the bit replacement means. Therefore, even if a failure occurs in the upper bits of the gradation data due to the LSI failure, there is an advantage that the influence on the gradation due to the failure can be reduced even during the period until the parts are replaced.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
A. First embodiment A-1. Configuration of First Embodiment FIG. 1 is a block diagram showing a configuration of an image forming apparatus according to a first embodiment of the present invention. In the figure, the image forming apparatus includes a plurality of blocks 2-1, 2-2, failure bit identification units 11-1, 11-2, bit replacement units 12-1, 12-2, and bit return units 13-1, 13. -2. The plurality of blocks 2-1, 2-2, failure bit identification units 11-1 and 11-2, bit swapping units 12-1 and 12-2, and bit return units 13-1 and 13-2 Built in.

  The plurality of blocks 2-1 and 2-2 are image processing systems that perform predetermined image processing (image cut, image shift, LUT, etc.) on input data (gradation data) and output to the next stage. The failure bit identification units 11-1 and 11-2 respectively input predetermined data to the corresponding blocks 2-1 and 2-2 when the power is turned on or when a job is not executed. The input data and the output data from the blocks 2-1 and 2-2 are compared to identify a failure bit. A method for identifying the failure bit will be described later.

  When the failure bit identification unit 11-1 or 11-2 detects a failure in the most significant bit, the failure bit specification unit 11-1 or 11-2 instructs the bit replacement unit 12-1 or 12-2 to perform bit replacement, and the bit return unit 13-1 , 13-2 is instructed to return bits.

  The bit swapping units 12-1 and 12-2 bit the bus lines so that the upper bit becomes the lower bit when the failure bit identification unit 11-1 or 11-2 detects a failure in the most significant bit. Swap in units. For example, in the case of a failure in which the upper bits are fixed at “1”, each bit is shifted to the lower position one by one. If the failure is such that the upper bit is fixed at “0”, the most significant bit is moved to the least significant bit. However, this is a specific example, and neither “1” fixing nor “0” fixing is limited thereto.

  The bit return units 13-1 and 13-2 are bits replaced by the bit replacement units 12-1 and 12-2 when a failure is detected in the most significant bit by the failure bit specifying units 11-1 and 11-2. Is returned to the next stage.

  The input image data (gradation data) may be image data read by a scanner (not shown) or image data transferred from another apparatus via a network (not shown).

Next, the above-described failure bit specifying method will be described.
FIG. 2 is a conceptual diagram for explaining an LSI failure bit identification method in the image forming apparatus according to the present embodiment. As shown in FIG. 2A, the failure bit specifying units 11-1 and 11-2 respectively send predetermined data “0x55” and “0xAA” to the blocks 2-1 and 2-2. Compare with the output of blocks 2-1, 2-2. If the most significant bit bit7 is normal, the input data is output as it is.

  On the other hand, in the case of a failure in which the most significant bit bit7 is fixed to “1”, when the data is “0x55”, the output is “0xD5” and the most significant bit bit7 is fixed to “0”. In the case of a failure, when the data is “0xAA”, the output is “0x2A”. Thus, when the output becomes “0xD5” or “0x2A”, it is determined that the most significant bit bit7 has a failure.

  When the blocks 2-1 and 2-2 are memories (for example, LUT for performing gradation correction: look-up table), as shown in FIG. Write predetermined data “0x55, 0xAA”, read data from the same address, and check whether the written data is the same as the written data. If the written data and the read data are the same, it is determined that there is no failure (OK), and if the written data and the read data are different, it is determined that there is a failure (NG). The determination of whether the most significant bit bit7 is fixed to “1” or “0” is as described above.

  In this way, the address determined as having a failure becomes the failure location. In the case of an LUT, gradation data different from the original value is input to the LUT by moving the bit position of the gradation data to be input. For this reason, it is necessary to switch the data of the LUT appropriately so that correct data is output from the LUT even if the bits are moved.

  As described above, the bit replacement units 12-1 and 12-2 detect the failure in which the most significant bit bit 7 is fixed to “1” by the failure bit specification units 11-1 and 11-2. , Each bit is shifted one by one, and in the case of a failure in which the most significant bit bit7 is fixed to “0”, the most significant bit is moved to the least significant bit. However, this is a specific example, and neither “1” fixing nor “0” fixing is limited thereto. Also, the bit return units 13-1 and 13-2 are replaced by the bit replacement units 12-1 and 12-2 when a failure is detected in the most significant bit by the failure bit specifying units 11-1 and 11-2. The original bit is restored and output to the next stage. As a result, if the upper bits of the data representing the gradation break down, the lower bit is used to transfer the upper bit data to the subsequent module, so that the period until the part replacement can affect the gradation due to the failure. Can be minimized.

B. Operation of Embodiment Next, the operation of this embodiment will be described.
FIG. 3 is a flowchart for explaining the operation of the image forming apparatus according to the present embodiment. The failure bit identification units 11-1 and 11-2 respectively send predetermined data “0x55” and “0” to the blocks 2-1 and 2-2 when the power is turned on or when a job is not executed. 0xAA "and the output of the blocks 2-1 and 2-2 are compared (S10). Next, it is determined whether or not a failure bit has been specified (S12). If the most significant bit bit7 is normal, the input data is output as it is. If it is determined that there is no failure, the process is terminated and the process returns to a predetermined main routine.

  On the other hand, in the case of a failure in which the most significant bit bit7 is fixed to “1”, when the data is “0x55”, the output is “0xD5” and the most significant bit bit7 is fixed to “0”. In the case of a failure, when the data is “0xAA”, the output is “0x2A”. Thus, when the output becomes “0xD5” or “0x2A”, it is determined that the most significant bit bit7 has a failure.

  When it is determined that there is a failure in the most significant bit bit7, the failure bit identification units 11-1 and 11-2 instruct the bit replacement units 12-1 and 12-2 to perform bit replacement. The bit return units 13-1 and 13-2 are instructed to return bits (S14). Thereafter, the process is terminated and the process returns to a predetermined main routine.

  Here, FIG. 4 is a block diagram illustrating an operation example of the image forming apparatus according to the present embodiment. The operation example illustrated in FIG. 4 illustrates the operation of each unit when the most significant bit of the block 2-1 is a failure (fixed to “1”). When the failure bit specifying unit 11-1 detects a failure in which the most significant bit bit7 is fixed to “1”, the bit replacement unit 12-1 shifts each bit to the lower order. Also, the bit return unit 13-1 shifts each bit to the upper level one by one.

  The input data is input to the block 2-1 by shifting the bits one by one in the bit replacement unit 12-1. After predetermined image processing is performed in the block 2-1, each bit is shifted up by one in the bit returning unit 13-1 and output to the next stage. The least significant bit bit0 is fixed to “1”. The data is input to the block 2-2 through the bit exchange unit 12-2 as it is, subjected to predetermined image processing, and then output through the bit return unit 13-2 as it is.

  Next, FIG. 5 is a block diagram illustrating another operation example of the image forming apparatus according to the present embodiment. The other operation example shown in FIG. 5 shows the operation of each unit when the most significant bit of the block 2-1 is a failure (fixed to “0”). When the failure bit specifying unit 11-1 detects a failure in which the most significant bit bit7 is fixed to “0”, the bit replacing unit 12-1 replaces the most significant bit bit7 with the least significant bit bit0. The bit return unit 13-1 replaces the least significant bit bit0 with the most significant bit bit7. Further, since there is no failure in the block 2-2, as described above, the bit exchange unit 12-2 and the bit return unit 13-2 do not exchange bits.

  The input data is input to the block 2-1 by the bit exchanging unit 12-1 and the most significant bit bit7 becomes the least significant bit bit0. After the predetermined image processing is performed in the block 2-1, In the return unit 13-1, the least significant bit bit0 is returned to the most significant bit bit7 and output to the next stage. The least significant bit bit0 is fixed to “1”. The data is input to the block 2-2 through the bit exchange unit 12-2 as it is, subjected to predetermined image processing, and then output through the bit return unit 13-2 as it is.

  Next, FIG. 6 is a block diagram illustrating another operation example of the image forming apparatus according to the present embodiment. The example illustrated in FIG. 6 illustrates the operation of each unit when the most significant bit of the subsequent block 2-2 is a failure (fixed to “1”). When the failure bit specifying unit 11-2 detects a failure in which the most significant bit bit7 is fixed to “1”, the bit swapping unit 12-2 shifts each bit downward by one. In addition, the bit return unit 13-2 shifts each bit to the upper level one by one. In addition, since there is no failure in the block 2-1, the bit exchange unit 12-1 and the bit return unit 13-1 do not exchange bits.

  First, the input data is input to the block 2-1 through the bit exchange unit 12-1 as it is. After predetermined image processing is performed in the block 2-1, the input data is directly transmitted through the bit return unit 13-1. Output to the next stage. In the bit exchange unit 12-2, each bit of the input data is shifted one by one to the lower order and input to the block 2-2. After predetermined image processing is performed in the block 2-2, each bit is returned to the higher order one by one in the bit returning unit 13-2 and output. The least significant bit bit0 is fixed to “1”.

  Next, FIG. 7 is a block diagram illustrating another operation example of the image forming apparatus according to the present embodiment. In the example shown in FIG. 7, the most significant bit of the preceding block 2-1 is faulty (fixed to “0”), and the most significant bit of the succeeding block 2-2 is faulty (fixed to “1”). It shows the operation of each part when there is. When the failure bit specifying unit 11-1 detects a failure in which the most significant bit bit7 is fixed to “0”, the bit replacing unit 12-1 replaces the most significant bit bit7 with the least significant bit bit0. The bit return unit 13-1 replaces the least significant bit bit0 with the most significant bit bit7. Further, when the failure bit specifying unit 11-2 detects a failure in which the most significant bit bit7 of the block 2-2 is fixed to “1”, the bit replacement unit 12-2 subtracts each bit one by one. Shift to Also, the bit return unit 13-1 shifts each bit to the upper level one by one.

  The input data is input to the block 2-1 by the bit exchanging unit 12-1 and the most significant bit bit7 becomes the least significant bit bit0. After the predetermined image processing is performed in the block 2-1, In the return unit 13-1, the least significant bit bit0 is returned to the most significant bit bit7 and output to the next stage. The least significant bit bit0 is fixed to “1”. Next, the data is input to the block 2-2 by shifting each bit one by one in the bit replacement unit 12-2. After predetermined image processing is performed in the block 2-2, each bit is returned to the higher order one by one in the bit returning unit 13-2 and output. The least significant bit bit0 is fixed to “1”.

  According to the above-described embodiment, even when the upper bits of the data representing the gradation are broken, by passing the upper bit data to the subsequent module using the lower bits, it is possible to replace the parts. Also in the period, when image data having a gradation as shown in FIG. 8A is input, as shown in FIG. 8B, the influence on the gradation due to the failure can be minimized. .

  In the above-described embodiment, only the failure of the most significant bit has been described. However, the present invention is not limited to this, and failure detection is performed on a bit having a high priority, and a failure is detected in the bit having a high priority. May be replaced with lower priority bits. In the above-described embodiment, the data to be handled is the gradation data. However, the present invention is not limited to this, and tag information representing additional information for the gradation data may be used. Further, the gradation data bit is the tag information. The priority may be higher than the bits.

1 is a block diagram illustrating a configuration of an image forming apparatus according to an embodiment of the present invention. It is a conceptual diagram for explaining a failure bit specifying method in the image forming apparatus according to the embodiment. 5 is a flowchart for explaining the operation of the image forming apparatus according to the embodiment. FIG. 5 is a block diagram illustrating an operation example of an image forming apparatus according to an embodiment. FIG. 10 is a block diagram illustrating another example of the operation of the image forming apparatus according to the embodiment. FIG. 10 is a block diagram illustrating another example of the operation of the image forming apparatus according to the embodiment. FIG. 10 is a block diagram illustrating another example of the operation of the image forming apparatus according to the embodiment. FIG. 5 is a schematic diagram for explaining an influence on gradation when a bit failure occurs in the image forming apparatus according to the embodiment. It is a block diagram for demonstrating operation | movement at the time of a bit failure of the image forming apparatus by a prior art. It is a schematic diagram for demonstrating the influence on the gradation at the time of the bit failure of the image forming apparatus by a prior art.

Explanation of symbols

2-1, 2-2 blocks (image processing system)
10 LSI
11-1, 11-2 Failure bit identification unit (failure bit identification means)
12-1, 12-2 Bit exchange unit (bit exchange means)
13-1, 13-2 Bit return unit (bit return means)

Claims (5)

In an image forming apparatus having an image processing system that performs image processing on image data composed of a plurality of bits supplied by a data path arranged in parallel, and outputs the processed image data.
A failure bit specifying means for specifying a failure bit in the data path;
An image forming apparatus comprising: a bit exchanging unit that, when a faulty bit is specified by the faulty bit specifying unit, replaces a path of the faulty bit with a path of another bit. The plurality of bits have a priority,
The bit replacement means replaces a path of a bit having a higher priority with a path of a bit having a lower priority when the bit having a higher priority is specified as a failed bit by the failure bit specifying means. The image forming apparatus according to claim 1, wherein:   The image forming apparatus according to claim 2, wherein the plurality of bits are gradation data, and the upper bit has a higher priority than the lower bit.   The plurality of bits include gradation data and tag information representing additional information for the gradation data, and the bit representing the gradation data has higher priority than the bit representing the tag information. The image forming apparatus according to claim 2.   The image forming apparatus according to claim 1, further comprising a bit return unit that returns a path of the bits exchanged by the bit exchange unit to an original state.

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