JP2008034826A - Thin-film semiconductor device, lateral bipolar thin-film transistor, hybrid thin-film transistor, mos thin-film transistor, and method of manufacturing the thin film transistor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a device configuration and a method of manufacturing the same whereby a MOS transistor and a bipolar transistor can be simultaneously integrated on a glass substrate. <P>SOLUTION: A lateral bipolar transistor (100) has an emitter (102), a base (103), and a collector (104) which are formed on a semiconductor thin film (105) formed on an insulating substrate (101), wherein the semiconductor thin film (105) is a semiconductor thin film crystallized in a predetermined direction. Further, a MOS-bipolar hybrid transistor (200) is formed on a semiconductor thin film formed on an insulating substrate, wherein the semiconductor thin film (205) is a semiconductor thin film crystallized in a predetermined direction. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a thin film transistor formed over an insulating substrate.

  2. Description of the Related Art An active matrix type flat display using a thin film transistor (hereinafter referred to as TFT) is known as a display device for image information and character information of OA equipment and the like. In recent years, with the development of multimedia communication technology, it is compact and lightweight for personal use, has high resolution and high image quality, and is related to image display of driver circuits, other memory circuits, DA converter circuits, image processing circuits, etc. A function-integrated display called a system-on-panel in which peripheral functions are integrated on a display panel is attracting attention as a next-generation display.

Conventionally, MOS (Metal Oxide Semiconductor) type transistors, which are a kind of field effect type transistors, are exclusively used for TFTs formed on glass substrates for displays. MOS transistors are widely used because they are advantageous in constructing digital circuits such as display pixel switches and shift registers of displays.
JP 2003-76345 A JP-A-2005-18088 JP 10-32337 BYTSAUR, MEMBER, IEEE, DJ SILVERSMITH, SENIOR MEMBER, IEEE, JCC FAN, AND RW, MOUNTAIN; “Fully Isolated Lateral Bipolar-MOS Transistors Fabricated in Zone-Melting-Recrystallized Si Filmes on SiO2“ IEEE ELECTRON DEVICE LETTERRS, VOL, EDL -4, NO.8, pp.269-271 AUGUST 1983 JAMES C. STURM, MEMBER, IEEE, JAMES P. McVITTIE, MEMBER, IEEE, JAMES F. GIBBONS, FELLOW, IEEE AND L.PFIFFER “A Lateral Silicon-on-Insulator Bipolar Transistor with a Self-Alingned Base Contact” 0741- 3106/87 / 0300-0104 $ 01.00 (c) 1987 IEEE Stephen Parke, Fariborz Assaderaghi Jian Chen, Joe King, Chenming Hu, and Ping K..Ko “A Versatile, SOI BiCMOS Technology with Complementary Lateral BJT's”, 0-7803-0817-4 / 92 $ 3.00 (c) IEDM92 453-456 1992 IEEE T. Shino, K. Inoh T. Yamada, H. Nii, S. Kawanaka, T. Fuse, M. Yoshimi, Y. Katsumata, S. Watanabe, and J. Matsunaga “A 31 GHz fmax Lateral BJT on SOI Using Self -Aligned External Base Formation Technology ”; 0-7803-4774-9 / 98 $ 10.00 (c) IERM 98 953-956 1998 IEEE Richard McCartney, Jsmes Kozisek, Marshall Bell ”9.3: WhisperBus TM: An Advanced Interconnect Link For TFT Column Driver Data”, SID 01 DIGEST, pp.1-4

  In recent years, attempts have been made to increase the added value of display devices by integrating various functions in addition to display functions on a display substrate. For example, Japanese Patent Laid-Open No. 2005-18088 discloses a liquid crystal display device in which a photoelectric conversion element is provided in each pixel and an input function using light such as a light pen is mounted.

  For example, in the case of the above example, a function for detecting and amplifying the photocurrent is required. However, the common source amplifier circuit composed of MOS transistors has a high input impedance and cannot directly amplify the current. In such a case, a current buffer circuit with a grounded gate is provided to receive current. However, in order to obtain a sufficient gain with only a MOS transistor, the circuit configuration becomes complicated. For this reason, there is a problem that it is difficult to obtain sufficient detection sensitivity with a simple circuit.

  On the other hand, bipolar transistors are known as transistors using current as an input signal. In the case of using a single crystal Si or SOI (Silicon On Insulator) substrate, BiCMOS technology has already been established in which a bipolar transistor and a CMOS transistor are mixed in the same substrate and selectively used as necessary. However, it has been difficult in the prior art to form such a configuration in which two types of devices are mixed on a substrate having low heat resistance such as a glass substrate. The reason for this is that the present inventor has been researching a technique that satisfies this requirement, and for example, it has been found that the minimum processing dimension that can be realized on a large glass substrate of nearly 1 m is limited to about 3 microns at most. Furthermore, it is thought that one of the reasons is that the crystal quality of the Si thin film that can be formed on the glass substrate at a low temperature is low and the minority carrier lifetime in the Si thin film layer is short.

  An object of the present invention was made to solve the above-described problems. A thin film transistor, a hybrid thin film transistor, a MOS thin film transistor, or the like, in which at least one type such as a lateral bipolar thin film transistor and a MOS thin film transistor is formed on a semiconductor thin film provided on an insulating substrate with low heat resistance, A thin film semiconductor device is provided.

  For example, an object of the present invention is to provide an element structure and a manufacturing method capable of integrating MOS transistors and bipolar transistors on a glass substrate.

  In order to achieve the above object, the present invention includes the following configuration.

  The invention described in the embodiment of the present invention has a source, a channel and a drain region formed in a semiconductor thin film formed on an insulating substrate, and a gate electrode is formed on the surface of the channel region via an insulating film. A thin film semiconductor device including at least one MOS transistor and at least one lateral bipolar transistor having an emitter, a base, and a collector formed on a semiconductor thin film formed on the same insulating substrate as the MOS transistor is included.

  The invention described in the embodiment of the present invention includes a step of forming a non-single-crystal semiconductor thin film on an insulating substrate, and a crystallization region by irradiating the non-single-crystal semiconductor thin film with a pulse laser beam having a reverse peak pattern. And a method of forming at least one thin film transistor of a lateral bipolar thin film transistor and a MOS thin film transistor in the crystallization region.

  Furthermore, the invention described in the embodiments of the present invention is a lateral bipolar transistor having an emitter, a base, and a collector formed on a semiconductor thin film formed on an insulating substrate. The semiconductor thin film is crystallized in a predetermined direction. A lateral bipolar thin film transistor which is a semiconductor thin film is included.

  Furthermore, lateral bipolar thin film transistors in which the carrier movement direction of the lateral bipolar transistor is the direction of crystallization of the semiconductor thin film, the collector is placed on the crystal growth start point side of the crystallized semiconductor thin film, and the emitter is placed on the crystal growth end point side A lateral bipolar thin film transistor.

  Furthermore, the invention described in the embodiment of the present invention has an emitter, a base, a collector, and a lead electrode connected to the base formed on a semiconductor thin film formed on an insulating substrate, and the base region has an insulating surface. A gate electrode is formed through a film, the base lead electrode and the gate electrode are connected to have the same potential, the emitter is the source of the MOS transistor, the base is the channel of the MOS transistor, and the collector is the MOS In a MOS-bipolar hybrid thin film transistor that also operates as a drain of a transistor, the semiconductor thin film includes a hybrid thin film transistor that is a semiconductor thin film crystallized in a predetermined direction.

  In addition, each includes a plurality of emitters (sources), bases (channels) and collectors (drains) forming a transistor, each emitter (source) being connected to a common emitter (source) electrode, and each base (channel) being Hybrid transistor connected to a common base (gate) electrode, each collector (drain) is connected to a common collector (drain) electrode, the carrier movement direction in the MOS-bipolar hybrid transistor is the direction of crystallization of the semiconductor thin film A hybrid thin film transistor.

  Furthermore, the invention described in the embodiment of the present invention has a source, a channel, and a drain region formed in a semiconductor thin film formed on an insulating substrate, and a gate electrode is formed on the surface of the channel region via an insulating film. The MOS thin film transistor in which the semiconductor thin film is crystallized in a predetermined direction and includes a MOS thin film transistor in which the source is disposed on the crystal growth start point side and the drain is disposed on the crystal growth end point side. .

  The invention described in the embodiments of the present invention further includes a lateral bipolar thin film transistor having a base length (LB) of 2 μm or less, a lateral bipolar thin film transistor having a base width (w) of 5 μm or less, and base electrodes drawn from both sides of the base. A lateral bipolar thin film transistor, and a lateral bipolar thin film transistor in which a base electrode is directly connected to a base operating region.

  At least one of a lateral bipolar thin film transistor and a MOS thin film transistor can be provided over an insulating substrate with low heat resistance. Furthermore, it is possible to provide an element structure capable of integrating a MOS transistor and a bipolar transistor on a glass substrate and a method for manufacturing the element structure.

  Embodiments of the present invention will be described below with reference to the drawings.

(Embodiment 1)
FIG. 1A is a plan view of a bipolar transistor 100 formed on an alkali-free glass substrate 101 according to Embodiment 1 of the present invention. 1B is a cross-sectional view taken along line XX ′ of FIG. 1A. 1C is a cross-sectional view taken along line YY ′ of FIG. 1A.

  1A to 1C show an emitter 102, a base 103, and a collector 104 formed on a crystallized semiconductor thin film 105. FIG. The semiconductor thin film 105 is crystallized in a predetermined direction. The semiconductor thin film 105 crystallized in a predetermined direction is a crystal region that is crystallized in the lateral direction (horizontal direction) by irradiating the semiconductor thin film with a pulsed laser beam having a light intensity distribution having an inverse peak pattern shape, for example. . The semiconductor thin film 105 crystallized in a predetermined direction can be formed by a crystallization method described in detail later. On the semiconductor thin film 105, an emitter electrode 106, a base electrode 107, and a collector electrode 108 are formed.

  As shown in FIGS. 1B and 1C, the entire bipolar transistor 100 is formed on a buffer insulating film 111 made of, for example, a 50 nm thick SiNx film 109 and a 100 nm thick SiO 2 film 110 on an alkali-free glass substrate 101. ing. The buffer insulating film 111 has a role of preventing diffusion of impurities from the glass substrate 101. The buffer insulating film 111 may have a configuration other than that illustrated, for example, only a SiO2 film, only a SiNx film, or the like, and a usable substrate is a substrate having low heat resistance and is limited to alkali-free glass. For example, a quartz substrate, a plastic substrate, a silicon substrate with a SiO2 film formed on the surface, or the like can be used.

On the SiO ₂ film 110, as shown in FIG. 2, a crystallized semiconductor thin film having a film thickness of 200 nm and having a substantially T-shape constituting the transistor 100, for example, a Si film crystallized in a predetermined direction is formed. An island-shaped region pattern 112 is formed. The semiconductor material is not limited to Si, and for example, Ge, GaAs or the like can be used. The film thickness is not limited to 200 nm. The crystallized Si film is not limited to the case where all of the Si film formed on the buffer insulating film 111 is crystallized, and includes a film formed only in a transistor formation region.

In the crystallized Si film 105, an N ⁺ -type emitter 102, an N ⁻ -type collector 104, an N ⁺ -type collector contact portion 113, and a P ⁻ -type are doped. A base 103 and a base contact portion 104 doped in a P ⁺ type are formed.

An electrode wiring (106, 107) made of, for example, a three-layer metal film of Ti / Al / Ti is formed on the Si film 105 through a contact through hole 116 provided in the first interlayer insulating film 115 made of, for example, an SiO ₂ film. , 108) are connected. Then, to cover all the members, for example, a second interlayer insulating film 22 made of SiO ₂ is formed.

In this embodiment, the width W of the base region 103 is 5 μm, and the length (equal to the emitter-collector distance) LB is 1.0 μm. The emitter 102 is doped with 1 × 10 ²⁰ (cm ⁻³ ) of phosphorus. In this embodiment, the base is doped with 1 × 10 ¹⁶ (cm ⁻³ ) boron, and the base contact portion 114 is doped with 1 × 10 ²⁰ (cm ⁻³ ) boron. . The collector 104 is doped with 1 × 10 ¹⁷ (cm ⁻³ ) phosphorus, and the collector contact portion 113 is doped with 1 × 10 ²⁰ (cm ⁻³ ) phosphorus. These selective dopings can be performed using an ion implantation technique in a normal semiconductor manufacturing technique. The doping material is not limited to the above materials. This structure is an NPN lateral bipolar thin film transistor element that allows current to flow in the horizontal direction, not the film thickness direction of the Si film, so that it can be formed simultaneously with the MOS transistor. The base contact is also drawn from the side of the base. Have. It is not limited to the NPN type shown in the first embodiment, but can be formed as a PNP type lateral bipolar thin film transistor element.

  The operation of the transistor 100 is the same as that of a normal bipolar transistor. While applying a positive voltage to the collector 104, a base current is passed between the base 103 and the emitter 102 to control the current between the emitter and the collector.

  In the lateral bipolar thin film transistor, the most important parameters for determining the current amplification factor hFE are the crystal quality of the Si film and the base length LB. The quality of the Si film can be solved by using a crystal film having a length of several microns or more by adopting a lateral crystal growth method using a laser as described later. In this case, the carrier movement direction in the lateral bipolar transistor is preferably the crystallization direction of the semiconductor thin film. This is because the moving carriers hardly cross the crystal grain boundary. Further, it has been found that the base length LB is at most 2 μm or less, preferably 1 μm or less, in order to secure a large hFE. In a polycrystalline silicon TFT used in a conventional display, it is difficult to obtain a large hFE because the lifetime of holes is short and it is difficult to form a base length of 1 μm or less due to lithography limitations.

  In the structure in which the contact is drawn from the side as shown in FIG. 1A, the design of the width W of the transistor is important. Bipolar operation occurs only in the region where holes injected from the base are present. The hole concentration decreases with distance from the side contact. The degree of this decrease is determined by the diffusion distance of holes in the Si film. According to the simulation experiment by the inventors, it has been found that when the distance from the side surface portion is 5 μm or more, the hole concentration is remarkably reduced and almost no collector current flows. For this reason, the width W of the base is about 5 μm or less, preferably 3 μm or less.

  Further, in FIG. 1A, the contacts are drawn out only from one side of the base, but may be drawn out from both sides as shown in FIG. 3A. By doing so, the width of the effective Si film that functions as a bipolar transistor can be increased, so that the collector current can be increased. As shown in FIG. 3B, the base electrode 107 can be directly connected to the base operation region 118 sandwiched between the emitter 102 and the collector 104.

  A lateral bipolar thin film transistor on an insulating substrate is suitable for high-frequency operation because the junction cross-sectional area between the base and the emitter and between the collector and the base is small and the junction capacitance is small.

  On the other hand, a disadvantage is that a large current cannot be taken out as in a normal vertical bipolar transistor because the emitter cross-sectional area is small. The drive current itself is smaller than the MOS transistor formed on the same Si thin film. For this reason, the feature of the large current driving capability that has been conventionally recognized as an advantage of the bipolar transistor does not apply to this device. Rather, it is a device suitable for high-speed operation with a small current. This feature is suitable for an input / output interface of a display, a preamplifier for current sensing, and the like.

  FIG. 4 shows input / output characteristics of the lateral bipolar thin film transistor 100 according to the first embodiment shown in FIGS. 1A to 1C. In FIG. 4, the horizontal axis represents the emitter-collector voltage, and the vertical axis represents the collector current. The result of increasing the base current at a 5 μA step is shown. FIG. 5 is a Gummel plot. The horizontal axis in FIG. 5 is the base-emitter voltage, and the vertical axis is the base current and the collector current, respectively. FIG. 4 shows that a current gain of 10 or more is obtained, for example, at an output current of 0.01 mA. It can also be seen that good saturation characteristics are obtained, and characteristics desirable for application to analog circuits are obtained.

(Embodiment 2)
FIG. 6 is a plan view of the MOS-bipolar hybrid thin film transistor 200 on the glass substrate according to the second embodiment of the present invention. FIG. 7 is a cross-sectional view taken along the line ZZ ′ of FIG. FIG. 8 is a cross-sectional view taken along the line AA ′ of FIG. 1A. The MOS-bipolar hybrid thin film transistor is a transistor having both functions of a MOS transistor and a bipolar transistor. The source of the MOS transistor also functions as the emitter of the bipolar transistor, the channel of the MOS transistor also functions as the base of the bipolar transistor, and the drain of the MOS transistor also functions as the collector of the bipolar transistor.

The entirety is formed on a non-alkali glass substrate 201 on a buffer insulating film 204 made of a 50 nm-thick SiNx film 202 and a 100 nm-thickness SiO ₂ film 203. The usable substrate material is not limited to the alkali-free glass substrate, and for example, a quartz substrate, a plastic substrate, a silicon substrate having a SiO2 film formed on the surface, or the like can be used. The buffer insulating film 204 has a role of preventing impurity diffusion from the glass substrate 201. As the buffer insulating film 204, a configuration other than that illustrated, for example, another configuration such as only a SiO 2 film or only a SiNx film can be used. In some cases, the semiconductor thin film 205 may be formed directly on an insulating substrate such as the glass substrate 201.

On the SiO ₂ film 203, as in the first embodiment, a semiconductor thin film 205 having a film thickness of 200 nm and having a substantially T shape is formed as an example constituting a transistor, and an Si film is formed as an example (112 in FIG. 2). reference). In this embodiment, a Si film having a single crystal grain having a length of several microns or more formed by a lateral crystal growth method using a laser, which will be described in detail later, is used as the Si film. In the semiconductor thin film 205, an N ⁺ -type emitter (source) 206, an N ⁻ -type collector (a part of the drain) 207, an N ⁺ -type collector contact (a part of the drain) ) 208, P ⁻ doped base (channel) 209, P ⁺ -doped base (channel) contact 210. The element of the present embodiment is different from the first embodiment in that a gate electrode 211 made of a MoW alloy film is formed on a base via a gate insulating film 214 made of SiO ₂ having a thickness of 30 nm. . Although the above description relates to an NPN transistor (N-channel MOS thin film transistor), a PNP transistor (P-channel MOS thin film transistor) structure can also be used.

  On the Si film 205 and the gate electrode 211, a wiring 213 made of a three-layer metal film of Ti / Al / Ti is connected through a contact through hole 216 provided in the first interlayer insulating film 215. As can be seen from the cross-sectional view taken along the line AA 'in FIG. 8, the gate electrode 211 and the base (channel) contact 212 are formed by an electrode wiring pattern 213, which is a pattern of a three-layer metal film of Ti / Al / Ti in this embodiment. It is configured to be connected and have the same potential.

A second interlayer insulating film 217 made of SiO ₂ is formed so as to cover all the members.

  Although the width W and length LB of the base region are not limited to the following values, in this embodiment, the width W of the base region is 2.5 μm and the length (equal to the emitter-collector distance) LB is 1 μm.

  As in the first embodiment, the emitter (source) 206 is doped with phosphorus, the base (channel) 209 is doped with boron, and the collectors (drains) 207 and 208 are doped with phosphorus. Note that the doping material is not limited to the above materials. The selective doping of these impurity atoms can be performed using an ion implantation technique in a normal semiconductor manufacturing technique.

  The MOS-bipolar hybrid thin film transistor 200 can be formed on the same insulating substrate as the lateral bipolar thin film transistor 100 of the first embodiment, for example, an alkali-free glass substrate. In such a case, single crystallization of the semiconductor thin film (105, 205) in which these transistors are formed can be performed in the same crystallization process.

  FIG. 9 shows a part of a hybrid thin film transistor having a base (channel) width W of 100 μm in total in which 20 hybrid thin film transistors shown in FIGS. 6 to 8 (in this example, base (channel) width W is 5 μm) are connected in parallel. It is a top view. A plurality of bases (channels) 209 formed at intervals on the Si pattern 219 are inserted, and a plurality of corresponding emitters (sources) 206 and collectors (drains) 207 are formed. Each base (gate electrode) 209, emitter (source), and collector (drain) are connected to a common gate (base) electrode 220, a common emitter (source) electrode 221, and a common collector (drain) electrode 222. ing.

  As described above, since the base (channel) width is limited in the element of the side contact, good characteristics can be maintained by arranging a plurality of transistors having small W in parallel in a transistor that drives a large current. . Further, such a structure can prevent the element from self-heating during a large current operation.

  The operation of this element is to apply a base current between the base (gate) 209 and the emitter (source) 206 while applying a positive voltage to the collector (drain) 208 in the same manner as in a normal bipolar transistor, and thereby the emitter (source). Control the current between the collectors (drains). Since the gate electrode 211 and the base (channel) contact 212 are connected, a voltage of 1 to 2 V applied between the base and the emitter at this time becomes a gate-source voltage. If this voltage is larger than the threshold voltage Vt of the MOS transistor, a surface channel is formed in the channel region 209 and a surface current flows. Electrons injected into the base (channel) 209 from the emitter (source 206) by the bipolar operation flow through this surface channel. For this reason, this device can obtain a larger driving current than when the device is operated by bipolar or MOS alone.

  10 and 11 are input / output characteristics and a Gummel plot of the hybrid TFT described above. A driving current larger than that of the lateral bipolar thin film transistor 100 shown in FIGS. It can also be seen that the current amplification factor hFE is large. It has been found that the current value in FIG. 10 is about twice the current when the MOS is operated alone without connecting the base electrode.

  FIG. 12 shows the relationship between the collector (drain) current and the current amplification factor hFE of the hybrid TFT 200 of the second embodiment. A current amplification factor hFE close to 500 at maximum is obtained. Thus, a higher current gain can be obtained by performing the hybrid operation.

FIG. 13A shows the relationship between the field effect mobility when operated in the MOS mode and the current amplification factor when operated in the bipolar mode in the hybrid TFT 200 in which the quality of the Si film 205 is changed. The field effect mobility and the current amplification factor are substantially proportional. For example, in order to obtain an hFE of 10 or more, a high-quality Si film capable of obtaining a surface channel mobility of 350 (cm ² / V · s) is required. is necessary. Therefore, it is preferable to use a crystallized Si film.

FIG. 13B shows the carrier transit time (τ) between the emitter and the collector with respect to the base length LB in the hybrid TFT 200. The carrier transit time (τ) is derived from a plot of 1 / 2πf _T versus 1 / I _C. The carrier transit time increases almost linearly with respect to the base length LB, indicating that the movement of electrons is limited by drift. The presence of the surface channel contributes to this, and the surface channel effectively absorbs the injected electrons and increases the movement in the base.

14A and 14B are a sectional view and a plan view of a MOS TFT 300 that can be formed on the same substrate simultaneously with the bipolar TFT 100 or the hybrid TFT 200 described above. The whole is formed on a non-alkali glass substrate 301 on a buffer insulating film made of a 50 nm thick SiNx film 321 and a 100 nm thick SiO ₂ film 322.

The MOS TFT 300 can be a P-type transistor or an N-type transistor having a source or drain 324 and a channel 330 by appropriate selection of impurities to be doped, like a normal field effect transistor. For example, a gate insulating film 325 made of SiO _{2 with a} film thickness of 30 nm, for example, is formed on a silicon single crystal region 323 that can be formed by crystallizing an amorphous Si film in a predetermined direction. A gate electrode 326 made of, for example, a MoW alloy film extending across the single crystal region 323 is formed on the surface. The channel length is defined by the width of the gate electrode 326. An interlayer insulating film 327 made of, for example, SiO ₂ is formed so as to cover all the members. Through a contact through hole 328 provided in the interlayer insulating film 327, an electrode wiring 329 made of, for example, a three-layer metal film of Ti / Al / Ti is formed. In addition to Ti / Al / Ti, various conductive materials can be used for the metal film.

FIG. 14C shows a breakdown voltage (V _BD ) with respect to the gate length of the N-channel poly-SiMOS thin film transistor and the SOI-MOS thin film transistor. In a MOS thin film transistor used for a display device, a decrease in V _BD caused by the floating body effect becomes a serious problem. The crystallized poly-SiMOS thin film transistor has a higher breakdown voltage than the SOI-MOS thin film transistor, and is suitable as an element used in a display device.

(Formation of semiconductor thin film)
For example, control for image display using a liquid crystal panel may be performed using a thin film transistor using an amorphous silicon thin film formed on a substrate, for example, a glass substrate, which is used for manufacturing a normal thin film transistor. Is possible. In general, an amorphous silicon thin film is used after being annealed. However, as the display substrate, it is particularly effective to use a substrate having a plurality of island-like regions made of a substantially single crystal thin film formed in an array described below. This is because, in such a substrate, a plurality of regions substantially made of a single crystal thin film can be obtained in a uniform state as a whole on a large-area substrate required for a display device. The term “substantially” means that this part is preferably formed of a complete single crystal thin film, but is formed by a plurality of single crystal regions when the crystal is grown by the method of the present invention described below. This is because there are cases where it is necessary.

  FIG. 15 is an electron microscope image of such a substrate 400 used in the present invention. The substrate on which a plurality of regions made of the arrayed single crystal thin film is formed is not limited to a glass substrate, but transparent non-alkali glass substrates 101 and 201 are used in this embodiment. This display substrate has a structure in which, for example, a region made of, for example, a silicon thin film having a size of about 5 μm × 5 μm made of a silicon thin film arranged in a two-dimensional matrix is spread at intervals of, for example, 5 μm vertically and horizontally.

  In FIG. 15, a polycrystalline region 402 exists at a boundary portion surrounding each single crystal region 401, and a large number of crystal grain boundaries 403 exist. This crystal grain boundary 403 has an electrically active defect that functions as a carrier generation / recombination center. For this reason, the polycrystalline region 402 is excluded from the formation of the base or channel region portion of the thin film transistor.

  FIG. 16 is an enlarged view of region A, which is one of the single crystal regions in FIG. Of the 5 μm region, the peripheral region of about 0.5 μm is the polycrystalline region 402, and there are a large number of defects found in the grain boundaries. Therefore, the base (channel) region of the transistor is arranged so as not to include the defect region 402 of about 0.5 μm.

  A method of manufacturing a substrate having such a crystallized semiconductor thin film is described in detail in Japanese Patent Application No. 2003-209598 filed on Aug. 29, 2003 by the present applicant.

  Here, an example of a method for forming a thin film array having a substantially rectangular single crystal region with a side of about 4 μm arranged at a pitch of 5 μm as shown in FIGS. 15 and 16 will be described.

  When the substrate used as the display substrate is a glass substrate, a high temperature as in the case of producing a silicon wafer to obtain a single crystal cannot be used. Therefore, first, for example, an amorphous silicon thin film is formed on the glass substrate by an arbitrary method. Next, this amorphous silicon thin film is irradiated with pulsed ultraviolet laser light to melt the amorphous silicon film. Subsequently, the melted silicon is recrystallized to obtain a partially thinned silicon thin film region. Although silicon is used in this embodiment, the semiconductor material used is not limited to silicon, for example, using a III-V semiconductor.

  In the case of recrystallization, as one method for obtaining a single crystallized region having as large an area as possible, a temperature gradient is applied to each array part to melt the thin film, and then the substrate temperature is lowered while maintaining the temperature gradient to perform recrystallization. The method to be used is used. For this reason, using a phase shift mask with an appropriate pattern, the transmitted light having the light intensity distribution of the reverse peak pattern is generated, and the light intensity of the laser beam irradiated on the substrate surface has a spatial distribution, and the lateral direction A method of giving a temperature gradient in the (horizontal direction) is adopted. By this method, in the non-irradiation period after the laser beam irradiation, the temperature of each part of the substrate decreases based on the temperature gradient at the time of melting, and the solid-liquid interface moves sequentially from the low temperature part to the high temperature part, Lateral crystal growth occurs. For this reason, crystal growth using a crystal portion particularly suitable for growth as a seed is expanded from the first generated polycrystalline portion, and a large single crystal region is obtained. In some cases, a plurality of single crystal regions may be formed, but even in this case, the size of the grown crystal is usually larger than the size of the channel region of the thin film transistor. By this method, an array having a plurality of substantially rectangular single-crystal regions 401 each having a size of about 4 μm on a side can be obtained.

  Next, the recrystallization process using, for example, a phase shift macro will be described with reference to FIG. A phase shift mask 510 shown in FIG. 17A is a transparent medium, for example, a quartz substrate provided with regions adjacent to each other with different thicknesses. Then, the incident laser beam is diffracted and interfered at the boundary of the stepped portion (phase shift portion) 510a between these regions. Thus, a periodic spatial distribution is given to the intensity of the incident laser beam.

  The phase shift mask 510 is configured such that adjacent patterns are in reverse phase (180 ° shift). That is, the alternately arranged regions are composed of a first strip region (phase region) 510b having a phase of π and a second strip region (phase region) 510c having a phase of 0. These strip regions (phase shift line regions) have a width of 10 μm in this example. Specifically, the phase shift mask 510 is manufactured by pattern-etching a rectangular quartz substrate having a refractive index of 1.5 to a depth corresponding to π with respect to 248 nm light, that is, a depth of 248 nm. To do. The region formed thin by this etching becomes the first strip region 510b, and the region not etched becomes the second strip region 510c.

  In the phase shift mask 510 having such a configuration, the laser beam that has passed through the thick second phase region 510c is delayed by 180 ° compared to the laser beam that has passed through the thin first phase region 510b. As a result, interference and diffraction occur between the laser beams, and an intensity distribution 530 of the reverse peak pattern laser beam as shown in FIG. 17B is obtained. That is, the light that has passed through the phase shift unit has a light intensity that is minimum, for example, 0, at a corresponding position between these regions because adjacent transmitted lights are in opposite phases. For this reason, the temperature of the part where the light intensity is minimum is lowest, and a periodic temperature distribution 540 is formed on the substrate surface.

  When the irradiation with the laser beam is stopped, first, the temperature becomes the melting point or lower in the minimum temperature portion 341 or a region in the vicinity thereof, and a large number of polycrystals serving as nuclei are generated when the semiconductor is recrystallized. For this reason, in the minimum part 541 of this temperature, a polycrystal is produced | generated initially. However, during the sequential growth of the crystal due to the temperature gradient, the growth of the crystal portion having a crystal orientation particularly suitable for the growth is expanded, so that a substantially single crystal region is obtained in each temperature gradient portion 542.

  In this description, the phase shift mask 510 is described as having a plurality of linearly parallel phase shift portions as shown in FIGS. 17A and 17B, but is not limited thereto. . For example, it is possible to make the phase shift lines orthogonal and to arrange the portions of the phases 0 and π in a checkered pattern (not shown). In this case, a lattice-like region having a light intensity of 0 is formed along the phase shift line. For this reason, crystal nuclei are generated at an arbitrary position on this line, and it may be difficult to control the position and shape of the crystal grains.

  In order to control the generation of crystal nuclei, it is desirable that the region where the light intensity is zero is formed in a dot-like manner with a predetermined period. As one method for this purpose, for example, each phase shift amount of orthogonal phase shift lines is less than 180 °. In this case, although the light intensity is reduced at the position corresponding to each phase shift line, it is not completely zero. However, as described below, the sum of complex transmittances around the intersection of the phase shift lines can be made zero by appropriately selecting the shift amount. In this case, the light intensity at the position corresponding to this intersection can be made zero.

  An example of this will be described with reference to FIG. 17C. The phase shift mask 570 has a plurality of sets each formed of a square pattern 552 including four square regions 550e, 550f, 550g, and 550h having different thicknesses as shown in FIG. In each set, as shown in FIG. 17C, the first region 550e is the thinnest and the phase is zero. The fourth region 550h is the thickest and the phase is shifted by 3π / 2 from the first region 550e. The second and third regions 550f and 550g having a thickness between the thicknesses of the regions 550e and 550h are shifted from the first region by π / 2 and π, respectively.

  In such a mask, a portion where the first to fourth regions are adjacent to each other, that is, a center point 551 of a square pattern is a region having zero intensity. Therefore, this point becomes the nucleus of crystal growth. In FIG. 17C, the center point of the pattern, that is, each lattice point 551 can be set as a zero intensity region. For this reason, the generation | occurrence | production position of a crystal grain can be controlled easily. The technology using such a phase shift mask is described in the specification of international application PCT / JP03 / 03366 filed on March 19, 2003 by the same applicant as the basic application of Japanese Patent Application No. 2002-12312. Has been.

(Embodiment 3)
FIG. 18 is a cross-sectional view of another phase shift used for forming a single crystal Si film, a mask 560, and a schematic diagram of a light intensity distribution. The phase shift mask 560 has a structure in which, for example, a plurality of convex patterns 562 of a predetermined size made of SiO ₂ are arranged at a predetermined density on a quartz plate 561. By passing the spatially uniform laser beam 563 through the phase shifter 560, a light intensity distribution 564 having a sawtooth repetitive pattern can be formed on the irradiation surface of a multilayer substrate (not shown).

In this embodiment, the repeated pitch Lx of the convex pattern 562 is 10 μm, but this value can be set to a desired value by design. In the light intensity distribution 564 of FIG. 18, each saw tooth portion is formed by a pair of linear portions 565 and 566 having different inclinations. The luminous intensity distribution is not limited to such a sawtooth distribution, and any luminous intensity distribution suitable for crystallization can be adopted.

  FIG. 19 is a surface SEM image of the crystallized Si film formed according to the present invention. After the multilayer substrate is heated by such laser light irradiation to melt the semiconductor film, the laser light irradiation is stopped and the temperature is lowered to crystallize the semiconductor film. At this time, melt recrystallization occurs from a low laser intensity region to a high region (from the top to the bottom in FIG. 19). As a result, the crystallization start portion 570 is in a polycrystalline state, but as crystal growth proceeds in the horizontal direction of the substrate, crystal grains having directivity that facilitates crystallization gradually increase. For this reason, it is possible to make a collection of single crystal grains exceeding the dimensions of the TFT formed later. In the vicinity of the crystallization end portion 571 where crystallization progresses and collides with an adjacent crystallization region, it becomes polycrystalline.

  In the above embodiment, an example of a pulsed ultraviolet laser beam as a laser beam for crystallization has been described. However, the laser beam only needs to emit a laser beam having an energy for melting an amorphous semiconductor (silicon) thin film. Alternatively, continuous wave laser light may be used. Crystallizers using continuous wave laser light crystallize large grains by emitting continuous wave laser light with the laser light source and the amorphous semiconductor (silicon) thin film relatively moved. Regions can be formed.

  In the above embodiment, the size of the crystallization region is such that at least the channel region (active layer) of each transistor is formed in one crystallization region.

  FIG. 19 shows a pattern image of a bipolar transistor arranged on this film. The transistors are arranged so that the collector and emitter directions through which current flows are parallel to the crystal growth direction. By doing so, the carrier flow is not hindered by the crystal grain boundaries, so that better characteristics can be obtained. In this arrangement, the collector is arranged close to the crystal growth start point and the emitter is arranged close to the crystal growth end point. Hereinafter, such an arrangement is defined as a forward arrangement, and an arrangement in which the positions of the collector and the emitter are exchanged is defined as a reverse arrangement.

  FIG. 20 is a Gummel plot in the Forward arrangement and the Reverse arrangement of the transistor of FIG. The forward arrangement (FIG. 20a) has a larger current amplification factor than the reverse arrangement (FIG. 20b). FIG. 21 is a diagram in which the current amplification factor β in each arrangement is plotted against the base-emitter voltage Vbs. In the Forward arrangement, β is a value close to 30, whereas in the Reverse arrangement, β is only about 6. From this result, it is desirable that better transistor characteristics can be obtained by arranging the collector close to the crystal growth start point and the emitter close to the crystal growth end point. This asymmetry of characteristics is thought to be due to the difference in electrical characteristics between the base-collector junction and the base-emitter junction.

  FIG. 22 shows the diode characteristics of the base-collector junction and the base-emitter junction of the same element. It can be seen that the base-collector junction has a larger reverse leakage current and a larger forward characteristic n value, and the base-collector junction has a higher defect density acting as a recombination center. As can be seen from the SEM image in FIG. 19, the width of the crystal grain increases with the progress of the lateral crystal growth, so the density of the crystal grain boundary decreases as the crystal growth end point is approached. As described above, when a bipolar transistor is formed on a crystal grown in one direction, a larger current amplification factor can be obtained by forming the collector close to the crystal growth start point and the emitter close to the crystal growth end point. Can be obtained.

  FIG. 23 is a schematic plan view of a MOS transistor arranged on a crystal having the same form as FIG. The transistors are arranged so that the source-drain direction in which current flows and the crystal growth direction are parallel. By doing so, the carrier flow is not hindered by the crystal grain boundaries, so that better characteristics can be obtained. In this arrangement, the drain is arranged close to the crystal growth start point and the source is arranged close to the crystal growth end point. Similar to the bipolar transistor, such an arrangement is hereinafter defined as a forward arrangement, and an arrangement in which the drain and source positions are exchanged is similarly defined as a reverse arrangement. FIG. 24 is a cross-sectional transmission electron microscope image of the MOS transistor thus arranged.

  FIG. 25 shows the results of measurement in the forward arrangement and the reverse arrangement while changing the ID-VG characteristics of the MOS transistor fabricated in this way while changing the source and drain voltages between 0.1V and 5,1V. FIG. 26 is a result of plotting the threshold voltage Vth of the transistor as a function of the drain voltage from the result of FIG.

  In the Reverse arrangement, the dependency of Vth on the drain voltage is small, but in the Forward arrangement, Vth decreases as the drain voltage increases, and when the drain voltage is 0.5 V or more, Vth is a negative value. It can also be seen that the drain voltage dependency of the leakage current in the negative region of the gate voltage is larger in the forward arrangement.

  It is considered that the decrease in Vth is due to the body potential modulation caused by the drain junction leakage current. The slowly decreasing Vth in the medium Vd region in the Forward arrangement is considered to be related to body potential modulation due to both drain leakage and impact ionization. The difference in the degree of decrease in Vth between the Forward arrangement and the Reverse arrangement indicates that the intensity of body potential modulation between the two arrangements is different.

  When Vth decreases as the drain voltage increases, a large through current flows at the drain voltage actually used in the circuit, which is not desirable. Detailed analysis reveals that this asymmetry of the Vth drain voltage dependency is due to the leakage current and the current amplification factor β asymmetry in the drain junction and the source junction shown in FIGS. . FIG. 21 shows changes in β with respect to Vbs. Note that β differs about 5 times between the Forward and Reverse configurations. Since both the leakage current of the junction and the bipolar gain are different, it is considered that when the source and the drain are changed, an asymmetry is caused with respect to a decrease in Vth.

  From this result, when a MOS transistor is formed on a crystal grown in one direction, the source is close to the crystal growth start point and the drain is close to the crystal growth end point, so that Vth depends on the drain voltage. It is desirable because it can be smaller than the drainage current and drainage current.

(Embodiment 4)
As described above, the lateral bipolar transistor 100 or the hybrid transistor 200 on the glass substrate shown in FIGS. 1A and 6 is not used in a circuit that requires a large drive current, unlike a normal bipolar transistor. It is suitable for amplifying a small current. As an application to the display device 600 using such features, a current-driven serial interface can be considered. FIG. 27 shows an example of the front-end circuit 601 of such a current drive type interface.

  As the image definition and the number of colors increase, the amount of data to be transmitted increases accordingly. However, since the refresh rate of the image display is constant, the clock frequency of the transmission line 602 needs to be increased as the amount of data increases. Thus, when the frequency of the transmission line 602 increases, there arises a problem that unnecessary electromagnetic radiation is radiated from the transmission line and causes noise to an external device due to electromagnetic interference (EMI). For this purpose, a technique known as LVDS (Low Voltage Differential Signaling) or the like is used to reduce EMI by low voltage differential driving. An example of such a technique is disclosed in, for example, Japanese Patent Application Laid-Open No. 2002-176350.

In recent years, a current-driven serial interface has been proposed as a transmission method that can more effectively reduce EMI. An example is disclosed in Japanese Patent Application Laid-Open No. 2003-76345. The circuit shown in FIG. 27 assumes that a binary current signal Isig is supplied from the system side, converts this into a received voltage signal by an input interface circuit (IF) 603, and performs voltage amplification by a level shift circuit 604. This is sent to the subsequent serial-parallel conversion circuit 605. Here, a feature is that a lateral bipolar transistor is used in the input portion of the input interface circuit.

  FIG. 28 shows a circuit configuration example of the input interface circuit (IF) 603 and the level shift circuit 604. The input section has a configuration in which a grounded lateral bipolar transistor Q1 and a grounded MOS transistor M1 are cascode-connected. In Q1, the input signal Isig is amplified. The voltage signal is converted by M1 and the load resistance Rd. Thereafter, this voltage signal is input to a level shift circuit 604 composed of a CMOS inverter. By using the bipolar transistor Q1 capable of directly amplifying the current at the input, the level of the input signal current Isig can be further reduced. For this reason, the power consumption on the signal transmission system side can be reduced.

  FIG. 29 shows signal waveforms of the input current signal Isig, the collector current Ic flowing through the lateral bipolar transistor Q1, and the output voltage Vout of the level shift circuit 604 in the circuit of FIG. Since the level of Isig is as very small as 0 to 70 μA, EMI is minimized. In addition, a current signal of 0 to 70 μA can be converted into a voltage signal of 0 to 3 V with a very simple circuit comprising four transistors.

  In this embodiment, a cascode connection circuit of a lateral bipolar transistor and a MOS transistor is used for the input interface circuit 603, and a CMOS inverter is used for the level shift circuit 604. However, the circuit configuration is not limited to these, and a general differential amplifier circuit or the like can also be used.

  FIG. 30 is a block diagram of the entire liquid crystal display device including the interface circuit 603 shown in FIG. The interface circuit 603 receives not only a video signal but also a clock signal Iclk, a control signal, and the like as a current signal and converts it into a voltage signal. After being adjusted to an appropriate voltage level via the level shift circuit 604, the video signal is converted into a parallel signal by the serial / parallel conversion circuit 605. The clock signal Iclk is frequency-divided by the frequency dividing circuit 612 according to the degree of parallelization and sent to the timing controller 606. The parallelized video signal is sent to the horizontal driver circuit 608 together with the clock signal divided through the buffer memory 607. The horizontal driver circuit 608 latches the video signal at an appropriate timing, and this is provided for each signal line. The analog signal is sent to the DA converter circuit 609 and supplied to the display unit. In the display unit, the switch transistor 611 provided in each pixel is turned on and off by the scanning signal supplied from the vertical scanning circuit 610, the analog voltage from the horizontal driver circuit is supplied to the liquid crystal layer, and the active matrix display unit 614 displays an image. Done.

  FIG. 30 is a bird's-eye view of the entire liquid crystal display device 620. FIG. 31 is a cross-sectional view of the liquid crystal display device 620. A liquid crystal material 623 is disposed between the transparent insulating substrates 621 and 622. On the transparent insulating substrate 621, a plurality of pixel electrodes 624 arranged in a matrix driven by the active matrix circuit of FIG. 27 are formed. A counter electrode 625 is disposed on the transparent insulating substrate 622. The potential of each pixel electrode 624 is controlled by the switch transistor 611 in FIG. By controlling the potential applied to the liquid crystal material 623 disposed between the counter electrode 625 and each pixel electrode 624, the optical characteristics of the liquid crystal material 623 are controlled.

  By adopting a current drive type input interface and using the lateral bipolar transistor Q1 in the input circuit on the display device side, signal transmission can be performed at a signal level lower than that of the prior art, so that EMI can be reduced and the power consumption of the entire system can be reduced. Further, since this method can increase the transmission frequency due to the low EMI property of the current interface, it is more suitable for a high-definition, multi-gradation liquid crystal display device.

  In the present embodiment, the example in which the signal transmission by current drive is applied to the transmission path between the display external system and the display substrate is described. However, the present invention is not limited to this, and the circuit in the active matrix substrate is used. It can also be used for signal transmission within a block. For example, when the horizontal driver circuit is divided into a plurality of blocks, it can be used for signal transmission between the blocks.

(Embodiment 5)
FIG. 32 is a configuration diagram of an active matrix display device according to the fifth embodiment of the present invention. A plurality of scanning wirings 702 and a plurality of video signal wirings 703 are arranged on an alkali-free glass substrate 701 so as to form a matrix, and two P-type thin film transistors are arranged in a rectangular pixel region defined by these wirings. A TFT active matrix display unit 707 in which capacitive elements are arranged, and a scanning circuit 704 and a signal supply circuit 705 made up of TFTs are arranged to drive the TFT active matrix display unit 707. In the present embodiment, a display operation is performed by supplying a current to an organic LED element to emit light, and a current supply source 706 to the organic LED element is formed on the same substrate, and the TFT active matrix display unit 707 is provided. A current is supplied to the transistor by a current supply wiring 708.

  A DC-DC converter circuit 709 for converting the power supply voltage DC supplied from the outside and supplying it as a necessary voltage to these drive circuits, video data, control signals, and the like are received, and necessary processing is performed. , 705, the timing control circuit 710 is also constituted by TFTs and integrated on the glass substrate.

  In the present embodiment, an inductor 711 made of a metal thin film is formed in a region on the glass substrate outside the TFT active matrix display portion 707 as an element for receiving compressed image data from the outside. The inductor 711 is connected to a data processing circuit including a signal amplification circuit 712 and a decompression circuit for decompressing the compressed data. Further, a TFT is formed in the semiconductor memory circuit 713 adjacent to the data processing circuit, which once stores the compressed image data and is used at the time of data expansion processing. These circuits and the memory circuit 713 are all composed of TFTs formed on a glass substrate.

  FIG. 33 is a schematic cross-sectional view of an inductive coupling non-contact transmission line constituted by an inductor element 711 on the display substrate and another inductor element TL formed on the substrate 714 constituting the data transmission side system.

  On the system board 714, an image data transmission circuit 715 and an inductor 716 having a self inductance L1 are formed. The self-inductance L2 inductor 711 on the display substrate is arranged substantially coaxially. The signal voltage from the image data transmission circuit 715 is transmitted from the inductor 716 to the inductor 711 via the mutual inductance Lm therebetween, amplified by the TFT in the data processing circuit, and stored in the memory.

  FIG. 34 shows a circuit configuration in which a lateral bipolar transistor is used for the amplifier circuit 712 of the signal received by the inductor RL in the above system.

  In this system, the signal transmission path is formed by electromagnetic coupling (coupling coefficient k) between two opposing inductors 716 and 711. In the transmission circuit, the signal is generated by changing the current supplied to the transmission inductor 716 between 0 and 2 mA. A current proportional to the current change rate of Isig and the coupling coefficient k appears only in the receiving-side inductor 711 while Isig is changing. This signal has a small amplitude of several μA, and it is difficult to directly convert it into a voltage by a MOS type TFT circuit. For this reason, after the current is once amplified by the lateral bipolar transistor Q1, it is converted into a voltage by the cascode-connected M1 and Rd and sent to the amplifier circuit 717 for voltage amplification. In the figure, R1 and R2 are resistors for supplying a bias current to Q1. In this circuit, since the amplitude of the current detected by the inductor 711 is small, it is necessary to set a proper operating point by supplying a bias current to Q1.

  FIG. 35 shows waveforms of the current Isig of the input signal transmitting inductor, the current Iin of the receiving inductor, and the output voltage Vout of the amplifier circuit in FIG. It can be seen that appropriate signal transmission is performed. By using a lateral bipolar transistor in a non-contact type signal transmission system using an inductor as in this embodiment, it becomes possible to detect a signal of a lower level signal, thus ensuring a noise margin during transmission and transmission. The speed can be improved.

(Embodiment 6)
36 and 37 show a display substrate 721 and an optical receiver circuit 722 according to the sixth embodiment of the present invention. Instead of signal transmission by capacitive coupling in the first embodiment, non-contact signal transmission is performed by optical coupling. In this embodiment, an optical transmission line is used as the transmission means. An optical sensor is integrated on the display substrate 721 instead of the capacitor and the inductor. FIG. 37 shows a configuration example of a circuit that receives a signal current from the optical sensor. In this example, it is composed of a photodiode 723, an interface circuit 724, and the like made of a single crystal silicon thin film. The configuration of the interface circuit 724 is the same as that of the fifth embodiment, and the current signal from the photodiode 723 is subjected to current amplification, converted into a voltage signal, and then sent to the serial / parallel conversion circuit.

  By using light as the signal transmission means, the influence of electromagnetic noise can be eliminated. Moreover, a favorable SN ratio can be achieved by using a bipolar transistor for the input section. As a result, the transmission rate can be improved. In particular, by using a photodiode composed of a single crystal silicon thin film on a transparent glass substrate, signals can be received regardless of whether the transmitter circuit is placed on the front or back side of the glass substrate, so that the degree of freedom in mounting is increased.

[Industrial applicability]
INDUSTRIAL APPLICABILITY The present invention can be used as an image display device for information equipment such as an image display device for a portable information terminal, a mobile phone, or a personal computer.

1 is a plan view of a thin film transistor according to a first embodiment of the present invention. XX 'sectional drawing of the thin-film transistor concerning the 1st Embodiment of this invention. FIG. 4 is a YY ′ cross-sectional view of the thin film transistor according to the first embodiment of the present invention. 1 is a pattern diagram of a semiconductor thin film according to a first embodiment of the present invention. FIG. 3 is a plan view of the thin film transistor in which the base electrode is taken out from both sides of the base layer in the first embodiment of the present invention. 1 is a plan view of a thin film transistor in which a base electrode is directly formed in a substantial base region in the first embodiment of the present invention. The input / output characteristics of the thin film transistor of the first embodiment of the present invention. 4 is a Gummel plot of the thin film transistor according to the first embodiment of the present invention. The electron microscope image of the crystal array pattern used for embodiment of this invention. The top view of the thin-film transistor concerning the 2nd Embodiment of this invention. ZZ 'sectional drawing of the thin-film transistor concerning the 2nd Embodiment of this invention. AA 'sectional view of the thin-film transistor concerning the 2nd Embodiment of this invention. FIG. 6 is a plan view showing a part of a transistor having a base width of 100 microns in which 20 thin film transistors according to a second embodiment of the present invention are connected in parallel. Input / output characteristics of the thin film transistor according to the second embodiment of the present invention. The Gummel plot of the thin-film transistor of the 2nd Embodiment of this invention. The collector current dependence of the current amplification factor of the thin film transistor of the second embodiment of the present invention. The relationship between the current gain of the thin-film transistor of the 2nd Embodiment of this invention, and field effect mobility. The characteristic carrier transit time with respect to the base length in the thin film transistor according to the second embodiment of the present invention is shown. Sectional drawing of the MOS thin-film transistor which can be formed with the transistor of the 1st or 2nd Embodiment of this invention. The top view of the MOS type thin-film transistor of FIG. 14A. Breakdown voltage (V _BD ) between the source and drain with respect to the gate length of the N-channel poly-SiMOS thin film transistor and SOIMOS thin film transistor. The electron microscope image of the crystal array pattern which can be used in the 1st and 2nd embodiment of this invention. It is an enlarged view of the electron microscope image of the crystal array pattern used in embodiment of this invention. It is a figure which shows the luminous intensity distribution and temperature distribution of the laser beam in the phase shift crystallization method used in order to obtain the phase shift mask used for obtaining a single crystal array and the single crystal array in embodiment of this invention. It is a figure which shows the phase shift mask used in order to obtain a single-crystal array in embodiment of this invention. It is a figure which shows the cross section of a phase shift mask, the luminous intensity distribution of a laser beam, and temperature distribution in embodiment of this invention. It is a figure which shows the other example of the phase shift mask used in order to obtain a single-crystal array in embodiment of this invention. It is a figure which shows the other example of the phase shift mask used in order to obtain a single-crystal array in embodiment of this invention. It is a surface SEM image of the crystallized Si film. It is a Gummel plot of the bipolar thin-film transistor concerning the 3rd Embodiment of this invention. It is the base voltage dependence of the current amplification factor β of the bipolar thin film transistor according to the third embodiment of the present invention. It is a junction characteristic figure between the base-emitter and the base-collector of the bipolar thin-film transistor concerning the 3rd Embodiment of this invention. It is a schematic diagram of the electron microscope image of the Si crystal film concerning the 3rd Embodiment of this invention, and the MOS type thin-film transistor arrange | positioned on it. It is a cross-sectional transmission electron microscope image of the MOS type thin-film transistor concerning the 3rd Embodiment of this invention. It is an ID-VG characteristic view of a MOS thin film transistor according to a third embodiment of the present invention. It is the drain voltage dependency of the threshold voltage Vth of the MOS type thin film transistor according to the third embodiment of the present invention. It is a whole block diagram of the liquid crystal display device concerning the 4th Embodiment of this invention. It is a signal interface circuit block diagram concerning the 4th Embodiment of this invention. It is the input current of the signal interface circuit concerning the 4th Embodiment of this invention, a collector current, and an output voltage waveform. It is a perspective view of the liquid crystal display device concerning the 4th Embodiment of this invention. It is sectional drawing of the liquid crystal display device concerning the 4th Embodiment of this invention. It is a whole block diagram of the liquid crystal display device concerning the 5th Embodiment of this invention. It is a cross-sectional schematic diagram of the inductive coupling non-contact transmission line concerning the 5th Embodiment of this invention. It is a signal interface circuit block diagram concerning the 5th Embodiment of this invention. It is the signal current of the signal interface circuit concerning the 5th Embodiment of this invention, a detection current, and an output voltage waveform. It is a whole block diagram of the liquid crystal display device concerning the 6th Embodiment of this invention. It is a signal interface circuit block diagram concerning the 6th Embodiment of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 100 ... Bipolar transistor, 101 ... Alkali glass, 102 ... Emitter, 103 ... Base, 104 ... Collector, 105 ... Semiconductor thin film (Si film), 106 ... Emitter electrode, 107 ... Base electrode, 108 ... Collector electrode, 109 ... SiNx 110: SiO 2 film, 111: Buffer insulating film, 112: Pattern, 113 ... Collector contact part, 114 ... Base contact part, 115 ... First interlayer insulating film, 116 Contact through hole ..., 117 ... Second interlayer Insulating film, 118 ... base operating region, 200 ... MOS-bipolar hybrid transistor, 201 ... glass substrate, 202 ... SiNx film, 203 ... SiO2 film, 204 ... buffer insulating film, 205 ... semiconductor thin film (Si film), 206 ... Emitter (source), 207 ... Collector (part of drain), 208 ... Collector contact (part of drain), 209 ... Base (channel), 210 ... Base (channel) contact, 211 ... Gate electrode, 212 ... Base (channel) contact, 213 ... electrode wiring pattern, 214 ... gate insulating film, 215 ... first interlayer insulating film, 216 ... contact hole, 217 ... second interlayer insulating film, 219 ... Si pattern, 220 ... gate ( Base) electrode 221 Emitter (source) electrode 221 222 Drain (collector) electrode 300 MOS TFT 301 Glass substrate 321 SiNx film 322 SiO ₂ film 323 Silicon single crystal region 324 ... source or drain, 3 25 ... Gate insulating film, 326 ... Gate electrode, 327 ... Interlayer insulating film, 328 ... Contact through hole, 329 ... Electrode wiring, 330 ... Channel, 400 ... Substrate, 401 ... Single crystal region, 402 ... Polycrystalline region, 403 ... Grain boundary, 510 ... Phase shift mask, 510 a ... Stepped part, 510 b ... First strip area, 510 c ... Second strip area, 530 ... Light intensity distribution, 540 ... Temperature distribution, 541 ... Temperature minimum part, 542 ... Temperature gradient portion, 550 ... phase shift mask, 550e, 550f, 550g, 550h ... square region, 560 ... phase shift mask, 561 ... quartz substrate, 562 ... convex pattern, 563 ... laser light, 564 ... light intensity distribution, 565, 566 ... Straight line part, 570 ... Crystallization start part 571 ... Crystallization end part, 600 ... Display device, 601 ... Front end circuit, 602 ... Transmission path, 603 ... Input interface circuit, 604 ... Level shift circuit, 605 ... Serial / parallel conversion circuit, 606 ... Timing controller, 607 ... Buffer Memory, 608 ... Horizontal driver circuit, 609 ... DA converter circuit, 610 ... Vertical scanning circuit, 611 ... Switching transistor, 612 ... Frequency divider circuit, 613 ... Buffer frequency divider circuit, 614 ... Active matrix display unit, 615 ... Scanning wiring, 616 ... Video signal wiring, 617 ... Substrate, 618 ... Latch circuit, 620 ... Liquid crystal display device, 621, 622 ... Transparent insulating substrate, 623 ... Liquid crystal material, 624 ... Pixel electrode, 625 ... Counter electrode, 701 ... None Alkali glass substrate, 702 ... scanning wiring, 703 ... video signal wiring, 704 ... scanning circuit, 705 ... signal supply circuit, 706 ... current supply source, 707 ... TFT active matrix display section, 708 ... current supply wiring, 709 ... DC- DC converter circuit, 710 ... Timing control circuit, 711 ... Inductor, 712 ... Signal amplification circuit, 713 ... Semiconductor memory circuit, 714 ... System board, 715 ... Image data transmission circuit, 716 ... Inductor, 717 ... Amplification circuit, 721 ... Display Substrate, 722 ... Optical receiver circuit, 723 ... Photodiode, 724 ... Interface circuit

Claims (9)

A MOS transistor having a source, a channel and a drain region formed in a semiconductor thin film formed on an insulating substrate, and a gate electrode formed on the surface of the channel region via an insulating film; and the same as the MOS transistor A thin film semiconductor device comprising at least one lateral bipolar transistor having an emitter, a base, and a collector formed on a semiconductor thin film formed on an insulating substrate. Forming a non-single crystal semiconductor thin film on an insulating substrate;
Irradiating the non-single-crystal semiconductor thin film with a pulse laser beam having a reverse peak pattern to form a crystallization region;
Forming at least one thin film transistor of a lateral bipolar thin film transistor and a MOS thin film transistor in the crystallized region;
A method for producing a thin film transistor, comprising: A lateral bipolar thin film transistor having an emitter, a base, and a collector formed on a semiconductor thin film formed on an insulating substrate, wherein the semiconductor thin film is a semiconductor thin film crystallized in a predetermined direction. 4. The lateral bipolar thin film transistor according to claim 3, wherein a carrier moving direction of the lateral bipolar transistor is a crystallization direction of the semiconductor thin film. 5. The lateral bipolar thin film transistor according to claim 4, wherein the collector is disposed on a crystal growth start point side of the crystallized semiconductor thin film, and the emitter is disposed on a crystal growth end point side. An emitter, a base, a collector formed on a semiconductor thin film formed on an insulating substrate, and an extraction electrode connected to the base, and a gate electrode is formed on the surface of the base region via an insulating film, The base lead electrode and the gate electrode are connected to have the same potential, the emitter operates as a source of a MOS transistor, the base operates as a channel of the MOS transistor, and the collector operates as a drain of the MOS transistor. A MOS-bipolar hybrid thin film transistor, wherein the semiconductor thin film is a semiconductor thin film crystallized in a predetermined direction. Each includes a plurality of emitters (sources), bases (channels) and collectors (drains) forming a transistor, each emitter (source) being connected to a common emitter (source) electrode, and each base (channel) being a common The hybrid transistor according to claim 6, wherein the hybrid transistor is connected to a base (gate) electrode, and each collector (drain) is connected to a common collector (drain) electrode. 8. The hybrid transistor according to claim 6, wherein a carrier movement direction in the MOS-bipolar hybrid transistor is a crystallization direction of the semiconductor thin film. In a MOS thin film transistor having a source, a channel, and a drain region formed in a semiconductor thin film formed on an insulating substrate, and a gate electrode is formed on the surface of the channel region via an insulating film, the semiconductor thin film is A MOS thin film transistor which is a semiconductor thin film crystallized in a predetermined direction, and is arranged such that the source is on the crystal growth start point side and the drain is on the crystal growth end point side.

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