CN101140940A - Electronic device, display device, interface circuit and differential amplification device, which are constituted by using thin-film transistors - Google Patents

Electronic device, display device, interface circuit and differential amplification device, which are constituted by using thin-film transistors Download PDF

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Publication number
CN101140940A
CN101140940A CNA200710141657XA CN200710141657A CN101140940A CN 101140940 A CN101140940 A CN 101140940A CN A200710141657X A CNA200710141657X A CN A200710141657XA CN 200710141657 A CN200710141657 A CN 200710141657A CN 101140940 A CN101140940 A CN 101140940A
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film
thin
transistor
film transistor
circuit
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河内玄士朗
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Sharp Corp
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Liguid Crystal Advanced Technology Development Center K K
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Abstract

An integrated circuit, which is configured such that a MOS transistor and a bipolar transistor are integrated at the same time, is formed on an insulating substrate which includes a display device. An electronic device or a display includes a plurality of semiconductor devices which are formed by using a semiconductor thin film and are formed in the semiconductor thin film that is provided on an insulating substrate and is crystallized in a predetermined direction. The plurality of semiconductor devices include a MOS transistor and at least either one of a lateral bipolar thin-film transistor and a MOS-bipolar hybrid thin film transistor.

Description

Electronic installation, display unit, interface circuit and differential amplifying device
Technical field
The present invention relates to adopt electronic installation, display unit, interface circuit and the differential amplifying device of the thin-film transistor structure that is formed on the dielectric substrate.
Background technology
As the display unit of (for example) OA equipment of displays image information and character information, the active matrix flat panel display of employing thin-film transistor (TFT) is arranged.In recent years, along with the development of multimedia communication technology, people begin to pay close attention to the integrated functionality escope as display of future generation, and it is called as " system on the screen board " display.The design of this integrated functionality escope is primarily aimed at personal use, and its volume is little, and is in light weight, and has high-resolution and high image quality.In addition, the integrated peripheral function that image shows, for example drive circuit, DA transducer and the image processing circuit of relating in display panel.As the example of integrated functionality escope, Japanese Patent Application Laid-Open No.2005-18088 discloses a kind of liquid crystal indicator, and it is independently providing photo-electric conversion element in the pixel, thereby has the input function of employing from the light of (for example) light pen.
If the resolution of the display image on the raising display unit and number of colors, institute's data quantity transmitted also can correspondingly improve so.But, because the refresh rate that image shows fixes, if thereby data volume improve, the clock frequency of transmission path also must improve.In this way, if the frequency of transmission path increases, will cause the problem that in transmission path, produces unwanted electromagnetic radiation and under the effect of electromagnetic interference (EMI), externally cause noise in the device.In order to address this problem, taked a kind of like this method, wherein, drive reduction EMI by the low-voltage differential that is called as (for example) LVDS (low voltage differential command).The example of this technology for example, is disclosed in Japanese Patent Application Laid-Open No.2002-176350.In addition, in recent years, as the transmission plan that can more effectively reduce EMI, the someone has proposed the serial line interface by current drives.An example is disclosed in Japanese Patent Application Laid-Open No.2003-76345.
With regard to conventional, main MOS (metal-oxide semiconductor (MOS)) transistor that drops in the field-effect transistor classification that adopts is as the TFT that is formed on the display glass substrate.Because MOS transistor can advantageously constitute such as the display pixel switch of display and the digital circuit of shift register, thereby has obtained extensive use.
The example of patent documentation is Japanese Patent Application Laid-Open No.2005-18088, Japanese Patent Application Laid-Open No.2002-176350, Japanese Patent Application Laid-Open No.2003-76345 and Japanese Patent Application Laid-Open No.10-32337.
The example of technical literature is: (1) B.Y.TSAUR, MEMBER, IEEE, D.J.SILVERSMITH, SENIOR MEMBER, IEEE, J.C.C.FAN and R.W.MOUNTAIN; " Fully Isolated Lateral Bipolar-MOS TransistorsFabricated in Zone-Melting-Recrystallized Si Films on SiO 2", IEEEELECTRON DEVICE LETTERS, VOL, EDL-4, No.8, pp.269-271, AUGUST 1983; (2) JAMES C.STURM, MEMBER, IEEE, JAMES PMcVITTIE, MEMBER, IEEE, JAMES F.GIBBONS, FELLOW, IEEE and L.PFIFFER, " A Lateral Silicon-on-Insulator Bipolar Transistor witha Self-Aligned Base Contact ", 0741-3106/87/0300-0104$01.00 (c) 1987IEEE; (3) Stephen Parke, Fariborz Assaderaghi Jian Chen, Joe King, Chenming Hu, with Ping K.Ko, " A Versatile, SOI BiCMOS Technologywith Complementary Lateral BJT ' s ", 0-7803-0817-4/92$3.00 (c) IEDM92453-4561992IEEE; (4) T.Shino, K.Inoh, T.Yamada, H.Nii, S.Kawanaka, T.Fuse, M.Yoshimi, Y.Katsumata, S.Watanabe, and J.Matsunaga, " A 31 GHz f MaxLateral BJT on SOI Using Self-AlignedExtemal Base Formation Technology "; 0-7803-4774-9/98$10.00 (c) IERM 98953-9561998IEEE; (5) Richard McCartney, Jsmes Kozisek, Marshall Bell, " 9.3:WhisperBus TM: An Advanced Interconnect Link ForTFT Column Driver Data ", SID 01 DIGEST, pp.1-4; (6) Jorgen Qlsson, Bengt Edholm, Anders Soderbiirg and Kjell Bohlin, " High Current GainHybrid Bipolar Operation of DMOS Transistors ", IEEETRANSACTIONS ON ELECTRON DEVICES, VOL.42, No.9, SEPTEMBER, pp.1628-1635,1995; (7) Stephen A.Parke, ChenmingHu and Ping K.KO, " Bipolar-FET Hybrid-Mode Operation ofQuarter-Microm; And (8) Sophie Verdonckt-Vandebroek, S.SimonWong, Jason C.S.Woo and Ping K.KO, " High-Gain Lateral BipolarAction in a MOSFET Structure; " IEEE TRANSACTIONS ONELECTRON DEVICES, VOL.38, No.11, NOVEMBER, pp.2487-2496,1991.
Summary of the invention
As mentioned above, in the TFT circuit, when integrated various function, survey and the function of amplified current, can simplify circuit structure so if having, and the power consumption of reduction circuit.But, in the common source polar form amplifying circuit that constitutes by MOS transistor, the input impedance height, and can not directly amplify electric current.In this case, by the received current of the current buffer with public grid structure is provided.But, obtaining enough gains in order to rely on MOS transistor separately, it is complicated that circuit structure will become.Thereby, exist to be difficult to rely on circuit simple in structure to obtain the problem of enough detectivities.
On the other hand, known bipolar transistor is a kind of transistor that adopts the electric current input to drive.Under the situation that adopts single crystalline Si or SOI (silicon-on-insulator) substrate, established BiCMOS (bipolar complementary metal oxide semiconductor) technology, wherein, on same substrate, provide bipolar transistor and CMOS transistor, can adopt these transistors as required selectively.
But, in routine techniques, be difficult on such as the low heat resistant substrate of glass substrate, realize such structure.Its reason is considered to, the minimum device size that realizes on the large-size glass substrate about (for example) 1m mostly be most 3 small about, the crystal mass that can be formed at the Si film on the glass substrate at low temperatures is poor, and the life-span of minority carrier is short.
The objective of the invention is to address the above problem, and provide a kind of display unit, to realize display with more various function, in described display unit, integrated MOS thin-film transistor and the bipolar film transistor that is used as the serial line interface of current drives simultaneously on glass substrate.
To achieve these goals, the present invention has taked following measure.
According to an aspect of the present invention, a kind of electronic installation that comprises a plurality of semiconductor device is provided, described a plurality of semiconductor device is to utilize semiconductor film film formed and be formed in the described semiconductive thin film, described semiconductive thin film is provided on the dielectric substrate and along the predetermined direction crystallization, described a plurality of semiconductor device comprise: MOS transistor; And at least a in lateral bipolar thin-film transistor and the bipolar mixed film transistor of MOS.
According to a further aspect in the invention, a kind of display unit that comprises a plurality of semiconductor device is provided, described a plurality of semiconductor device is to utilize semiconductor film film formed and be formed in the described semiconductive thin film, described semiconductive thin film is provided on the dielectric substrate and along the predetermined direction crystallization, wherein said display unit comprises the current-mode signal input interface circuit with two current values or two or more current values, and described current-mode signal input interface circuit comprises: thin-film transistor, described thin-film transistor be utilize film formed at least one the lateral bipolar thin-film transistor of described semiconductor film and at least one mixed film transistorized at least any; And at least one utilizes the film formed MOS transistor of described semiconductor film.
According to a further aspect in the invention, a kind of display unit that comprises a plurality of semiconductor device is provided, described a plurality of semiconductor device is to utilize semiconductor film film formed and be formed in the described semiconductive thin film, described semiconductive thin film is provided on the dielectric substrate and along the predetermined direction crystallization, described display unit comprises voltage differential signal type signal input interface circuit, wherein, described voltage differential signal type signal input interface circuit comprises: thin-film transistor, described thin-film transistor be utilize film formed at least one the lateral bipolar thin-film transistor of described semiconductor film and at least one mixed film transistorized at least any; And at least one utilizes the film formed MOS transistor of described semiconductor film.
According to a further aspect in the invention, a kind of display unit that comprises a plurality of semiconductor device is provided, described a plurality of semiconductor device is to utilize semiconductor film film formed and be formed in the described semiconductive thin film, described semiconductive thin film is provided on the dielectric substrate and along the predetermined direction crystallization, described display unit comprises the signal input interface circuit of noncontact electromagnetic coupled transmission plan, wherein, the signal input interface circuit of described noncontact electromagnetic coupled transmission plan comprises: thin-film transistor, described thin-film transistor be utilize film formed at least one the lateral bipolar thin-film transistor of described semiconductor film and at least one mixed film transistorized at least any; And at least one utilizes the film formed MOS transistor of described semiconductor film.
According to a further aspect in the invention, a kind of display unit that comprises a plurality of semiconductor device is provided, described a plurality of semiconductor device is to utilize semiconductor film film formed and be formed in the described semiconductive thin film, described semiconductive thin film is provided on the dielectric substrate and along the predetermined direction crystallization, described display unit comprises the input interface circuit of non-contact optical transmission plan, wherein, the signal input interface circuit of described non-contact optical transmission plan (scheme) comprising: at least one photo-electric conversion element; Thin-film transistor, described thin-film transistor be utilize film formed at least one the lateral bipolar thin-film transistor of described semiconductor film and at least one mixed film transistorized at least any; And at least one utilizes the film formed MOS transistor of described semiconductor film.
According to a further aspect in the invention, a kind of display unit that comprises a plurality of semiconductor device is provided, described a plurality of semiconductor device is to utilize semiconductor film film formed and be formed in the described semiconductive thin film, described semiconductive thin film is provided on the dielectric substrate and along the predetermined direction crystallization, described display unit comprises memory circuit, described memory circuit comprises a plurality of storage elements unit, level shift circuit unit and sense amplifier unit, wherein, described sense amplifier unit comprises: thin-film transistor, described thin-film transistor be utilize film formed at least one the lateral bipolar thin-film transistor of described semiconductor film and at least one mixed film transistorized at least any; And at least one utilizes the film formed MOS transistor of described semiconductor film.
According to a further aspect in the invention, a kind of display unit that comprises a plurality of semiconductor device is provided, described a plurality of semiconductor device is to utilize semiconductor film film formed and be formed in the described semiconductive thin film, described semiconductive thin film is provided on the dielectric substrate and along the predetermined direction crystallization, described display unit comprises one of memory circuit of DC-DC converter circuit, timing control circuit, signal amplification circuit, the decompression circuit that is used for depressurizing compression data and storing image data, and each of described circuit comprises: the MOS thin-film transistor; And at least a in lateral bipolar thin-film transistor and the bipolar mixed film transistor of MOS.
In comprising the display unit of a plurality of semiconductor device, described a plurality of semiconductor device is to utilize semiconductor film film formed and be formed in the described semiconductive thin film, described semiconductive thin film is provided on the dielectric substrate and along the predetermined direction crystallization, signal input circuit comprises: adopted the current amplification unit of thin-film transistor, described thin-film transistor be utilize film formed at least one the lateral bipolar thin-film transistor of described semiconductor film and at least one mixed film transistorized at least any; And the voltage amplification unit, it is connected to described current amplification unit and has adopted and utilized the film formed MOS transistor of described semiconductor film.
In comprising the display unit of a plurality of semiconductor device, described a plurality of semiconductor device is to utilize semiconductor film film formed and be formed in the described semiconductive thin film, described semiconductive thin film is provided on the dielectric substrate and along the predetermined direction crystallization, signal input circuit comprises the differential amplifier circuit of cascade, disposing described differential amplifier circuit makes load transistor and two lateral bipolar thin-film transistors or two the transistorized set of devices of mixed film comprise series connection successively and another group load transistor that comprises series connection successively and two lateral bipolar thin-film transistors or two transistorized set of devices of mixed film be connected in parallel, one of two set of devices in parallel are connected to power supply, another group of two set of devices in parallel is via MOSFET ground connection, and described MOSFET plays the effect of constant current source.
In described display unit, the minimum value of lateral bipolar thin-film transistor or the transistorized base length of mixed film is 2 μ m or littler.
In described display unit, the minimum value of lateral bipolar thin-film transistor or the transistorized base width of MOS mixed film is 2 μ m or littler, and the minimum value of the grid length of described MOS transistor is 1 μ m or littler.
In described display unit, the maximum of described lateral bipolar thin-film transistor or the transistorized current amplification factor of the bipolar mixed film of MOS is 10 or bigger.
In described display unit, the maximum of described lateral bipolar thin-film transistor or the transistorized current amplification factor of the bipolar mixed film of described MOS is 10 or bigger, and the maximum of the field-effect mobility of described MOS transistor is 350cm 2/ Vs or bigger.
In described electronic installation or display unit, predetermined direction is the horizontal of crystallization non-single crystal semiconductor film.
According to a further aspect in the invention, provide interface circuit to comprise: to be provided in the semiconductive thin film on the dielectric substrate; Be provided in the crystal region in the described semiconductive thin film; Be provided in the thin-film transistor in the described crystal region, described thin-film transistor is at least a in lateral bipolar thin-film transistor and the mixed film transistor; And be provided in the described crystal region and be connected to the MOS thin-film transistor of described thin-film transistor.
According to a further aspect in the invention, a kind of electronic installation that comprises a plurality of semiconductor device is provided, described a plurality of semiconductor device is to utilize semiconductor film film formed and be formed in the described semiconductive thin film, described semiconductive thin film is provided on the dielectric substrate and along the predetermined direction crystallization, wherein, described a plurality of semiconductor device comprises: MOS transistor; And at least a in lateral bipolar thin-film transistor and the bipolar mixed film transistor of MOS, and described lateral bipolar thin-film transistor or the bipolar mixed film transistor of MOS have the function of surveying little electric current and described little current conversion being become curtage.
According to a further aspect in the invention, a kind of display unit that comprises a plurality of semiconductor device is provided, described a plurality of semiconductor device is to utilize semiconductor film film formed and be formed in the described semiconductive thin film, described semiconductive thin film is provided on the dielectric substrate and along the predetermined direction crystallization, wherein, described display unit comprises the imported signal interface circuit of difference, and the imported signal interface circuit of described difference comprises and utilizes one of film formed at least one pair of the lateral bipolar thin-film transistor of described semiconductor film and at least one pair of mixed film transistor and at least one pair of to utilize the film formed MOS transistor of described semiconductor film.
According to a further aspect in the invention, a kind of display unit that comprises a plurality of semiconductor device is provided, described a plurality of semiconductor device is to utilize semiconductor film film formed and be formed in the described semiconductive thin film, described semiconductive thin film is provided on the dielectric substrate and along the predetermined direction crystallization, wherein signal input circuit is a differential amplifier circuit, and it comprises: the current mirror type current source that is made of a pair of P type MOS transistor; Be connected respectively to a pair of mixed film transistor of the drain terminal of the described a pair of P type MOS transistor that constitutes described current source; And be connected to the transistorized public source terminal of described a pair of mixed film and as the N type MOS transistor of constant current source work.
In described display unit, the transistorized maximum oscillation frequency of described mixed film is higher than 2GHz.
According to a further aspect in the invention, a kind of differential amplifying device that comprises a plurality of semiconductor device is provided, described a plurality of semiconductor device is to utilize semiconductor film film formed and be formed in the described semiconductive thin film, described semiconductive thin film is provided on the dielectric substrate and along the predetermined direction crystallization, described differential amplifying device comprises the imported signal interface circuit of difference, wherein, the imported signal interface circuit of described difference comprises: utilize one of film formed at least one pair of the lateral bipolar thin-film transistor of described semiconductor film and at least one pair of mixed film transistor; And utilize film formed at least one pair of MOS transistor of described semiconductor film.
According to a further aspect in the invention, a kind of differential amplifying device that comprises a plurality of semiconductor device is provided, described a plurality of semiconductor device is to utilize semiconductor film film formed and be formed in the described semiconductive thin film, described semiconductive thin film is provided on the dielectric substrate and along the predetermined direction crystallization, wherein signal input circuit is a differential amplifier circuit, and it comprises: the current mirror type current source that is made of a pair of P type MOS transistor; Be connected respectively to a pair of mixed film transistor of the drain terminal of the described a pair of P type MOS transistor that constitutes described current source; And be connected to the transistorized public source terminal of described a pair of mixed film and as the N type MOS transistor of constant current source work.
As mentioned above, the present invention can provide such electronic installation, and it comprises at least one and MOS transistor in lateral bipolar thin-film transistor and the bipolar mixed film transistor of MOS, and can directly amplify input current.
Description of drawings
Figure 1A is the plane graph according to the lateral bipolar thin-film transistor of first embodiment of the invention;
Figure 1B is the sectional view that obtains along the X-X ' line that shows according to Fig. 1 of the lateral bipolar thin-film transistor of the first embodiment of the present invention;
Fig. 1 C is the sectional view that obtains along the Y-Y ' line that shows according to Fig. 1 of the lateral bipolar thin-film transistor of the first embodiment of the present invention;
Fig. 2 shows the pattern of the semiconductive thin film in the first embodiment of the present invention;
Fig. 3 A is the plane graph of the thin-film transistor in the first embodiment of the present invention, and in described thin-film transistor, base electrode is drawn from the both sides of base layer;
Fig. 3 B is the plane graph of the thin-film transistor in the first embodiment of the present invention, and in described thin-film transistor, base electrode directly is formed in the actual base region;
Fig. 4 shows the curve chart according to the I/O characteristic of the thin-film transistor of the first embodiment of the present invention;
Fig. 5 shows the curve chart according to the Gumel curve of the thin-film transistor of the first embodiment of the present invention;
Fig. 6 is the plane graph according to the bipolar hybrid transistor of MOS of the first embodiment of the present invention;
Fig. 7 is the sectional view that obtains along the Z-Z ' line along Fig. 6 that shows according to the bipolar hybrid transistor of MOS of the first embodiment of the present invention;
Fig. 8 is the sectional view that obtains along the A-A ' line along Fig. 6 that shows according to the bipolar hybrid transistor of MOS of the first embodiment of the present invention;
Fig. 9 shows the plane graph of the transistorized part of the base width with 100 μ m, 20 bipolar hybrid transistor of the MOS according to the first embodiment of the present invention wherein in parallel;
Figure 10 shows the curve chart according to the I/O characteristic of the bipolar hybrid transistor of MOS of the first embodiment of the present invention;
Figure 11 shows the curve chart according to the Gummel curve of the bipolar hybrid transistor of MOS of the first embodiment of the present invention;
Figure 12 shows the curve chart according to the collector current correlation of the current amplification factor of the bipolar hybrid transistor of MOS of the first embodiment of the present invention;
Figure 13 A shows the curve chart according to the current amplification factor and the relation between the field-effect mobility of the bipolar hybrid transistor of MOS of the first embodiment of the present invention;
Figure 13 B shows in according to a second embodiment of the present invention the intrinsic carrier transit time curve chart with respect to base length;
Figure 14 A is the sectional view of the MOS thin-film transistor that can form with lateral bipolar thin-film transistor according to the present invention or the bipolar hybrid transistor of MOS;
Figure 14 B is the plane graph of the MOS thin-film transistor shown in Figure 14 A;
Figure 14 C shows the source electrode-drain breakdown voltage (V with respect to the grid length of N raceway groove polysilicon MOS thin-film transistor and SOI-MOS thin-film transistor BD) curve chart;
Figure 15 be can be used for according to the bipolar hybrid transistor of lateral bipolar thin-film transistor, MOS of the first embodiment of the present invention and MOS thin-film transistor, according to the electron micrograph image of the crystal array pattern of second embodiment;
Figure 16 is the enlarged drawing of electron micrograph image that can be used for the crystal array pattern of the first embodiment of the present invention;
Figure 17 A shows the phase shifting mask of the monocrystalline array that is used for obtaining the second embodiment of the present invention;
Figure 17 B shows the phase shifting mask sectional view in the second embodiment of the present invention, the light distribution and the Temperature Distribution of laser beam;
Figure 17 C shows another example of phase shifting mask, and it is used for obtaining the monocrystalline array in the second embodiment of the present invention;
Figure 17 D is the plane graph that is used for obtaining the phase shifting mask shown in Figure 17 C of the monocrystalline array in the second embodiment of the present invention;
Figure 18 shows another example of phase shifting mask, and it is used for obtaining the monocrystalline array in the third embodiment of the present invention;
Figure 19 shows the surperficial SEM image and the layout that is formed at the bipolar TFT in the described Si film of the crystallization Si film of a fourth embodiment in accordance with the invention;
Figure 20 A shows the curve chart according to the Gummel curve of bipolar TFT (forward layout) shown in Figure 19 of the present invention;
Figure 20 B shows the curve chart according to the Gummel curve of bipolar TFT (reciprocal transformation) shown in Figure 19 of the present invention;
Figure 21 A shows the curve chart according to the base voltage correlation of the current amplification factor β of bipolar TFT (forward layout) shown in Figure 19 of the present invention;
Figure 21 B shows the curve chart according to the base voltage correlation of the current amplification factor β of bipolar TFT (reciprocal transformation) shown in Figure 19 of the present invention;
Figure 22 shows the curve chart according to the characteristic of the substrate-emitter junction of bipolar TFT shown in Figure 19 of the present invention and base-collector junction;
The schematic diagram of the MOS thin-film transistor of the electron micrograph image of the Si crystal film during Figure 23 shows according to a fifth embodiment of the invention and the described electron micrograph image of covering;
Figure 24 shows the cross section transmission electron microscope image according to MOS thin-film transistor shown in Figure 23 of the present invention;
Figure 25 A shows the curve chart according to the ID-VG characteristic of MOS thin-film transistor (forward layout) shown in Figure 23 of the present invention;
Figure 25 B shows the curve chart according to the ID-VG characteristic of MOS thin-film transistor (reciprocal transformation) shown in Figure 23 of the present invention;
Figure 26 shows the threshold voltage V according to MOS thin-film transistor shown in Figure 23 of the present invention ThThe curve chart of drain voltage correlation;
Figure 27 shows the total of liquid crystal indicator according to a sixth embodiment of the invention;
Figure 28 shows the structure of signal interface circuit according to a sixth embodiment of the invention;
Figure 29 shows input current waveform, collector current waveform and the output voltage waveforms of signal interface circuit according to a sixth embodiment of the invention;
Figure 30 is the perspective view of liquid crystal indicator according to a sixth embodiment of the invention;
Figure 31 is the sectional view of liquid crystal indicator according to a sixth embodiment of the invention;
Figure 32 shows the total of liquid crystal indicator according to a seventh embodiment of the invention;
Figure 33 is the schematic sectional view in the inductance coupling high type non-contact transmission path in the seventh embodiment of the present invention;
Figure 34 shows the structure of the signal interface circuit in the seventh embodiment of the present invention;
Figure 35 shows current waveform signal, probe current waveform and the output voltage waveforms of the signal interface circuit in the seventh embodiment of the present invention;
Figure 36 shows the total according to the liquid crystal indicator of the eighth embodiment of the present invention;
Figure 37 shows the structure of the signal interface circuit in the eighth embodiment of the present invention;
Figure 38 shows the structure according to the signal interface circuit of the ninth embodiment of the present invention;
Figure 39 shows the memory circuit of utilization according to the bipolar TFT of the tenth embodiment of the present invention;
Figure 40 shows the plane graph pattern of mixing TFT according to another embodiment of the present invention;
Figure 41 A shows the curve chart of the Gummel curve of TFT, 18 mixing TFT shown in Figure 40 in parallel in described TFT;
Figure 41 B shows according to the collector current of mixing TFT 200 of the present invention and the curve chart of the relation between the current amplification factor hFE;
Figure 41 C shows the curve chart of the I/O characteristic of mixing TFT;
Figure 42 A shows the base length correlation that (can find) hFE when collector current is 0.1mA from the performance diagram of Figure 41 B;
Figure 42 B shows the curve chart of the base length correlation of early voltage (VA);
Figure 43 A shows the cut-off frequency (f of the mixing TFT with different base length T) the curve chart of collector current correlation;
Figure 43 B shows the curve chart of collector current correlation of the maximum oscillation frequency (fmax) of the mixing TFT with different base length;
Figure 43 C shows cut-off frequency (f T) and the curve chart of the base length correlation of maximum oscillation frequency (fmax);
Figure 44 A is a curve chart, and wherein, base length is that the S measured value of parameters of the mixing TFT of 0.5 μ m is converted into Y parameter, and has been depicted as curve with respect to frequency, and wherein, ordinate is represented the absolute value (amplitude) of Y parameter;
Figure 44 B is a curve chart, and wherein, base length is that the S measured value of parameters of the mixing TFT of 0.5 μ m is converted into Y parameter, and has been depicted as curve with respect to frequency, and wherein, ordinate is represented the phase place of Y parameter;
Figure 44 C shows mounted cast, wherein, and in parallel bipolar transistor and MOS transistor;
Figure 44 D shows the equivalent electric circuit of the bipolar transistor shown in Figure 44 C;
Figure 44 E shows the equivalent electric circuit of the MOS transistor shown in Figure 44 C;
Figure 45 A shows another embodiment of the present invention, and it relates to by mixing TFT combines the LVDS interface circuit that constitutes with MOS TFT receiver side circuit;
Figure 45 B shows the curve chart of the input and output signal waveform of the interface circuit shown in Figure 45 A; And
Figure 45 C shows the plan view layout according to interface circuit of the present invention.
Embodiment
Referring now to accompanying drawing embodiments of the invention are described.
(first embodiment)
Present embodiment relates to and comprises a plurality of electronic installations that are formed at the semiconductor device in the semiconductive thin film, and described semiconductive thin film is arranged on the dielectric substrate.Especially, provided description to the lateral bipolar thin-film transistor in the described electronic installation, described electronic installation comprises MOS transistor, and comprises at least and being formed at according to lateral bipolar thin-film transistor in the semiconductive thin film of predetermined direction crystallization or the bipolar mixed film transistor of MOS.
The bipolar mixed film transistor of above-mentioned MOS thin-film transistor and lateral bipolar thin-film transistor or MOS is formed on the same dielectric substrate.Have such feature, that is, in described lateral bipolar thin-film transistor or transistorized base region of the bipolar mixed film of described MOS or channel region, do not have the grain boundary at least, and described base region or channel region are crystal region.For example, can adopt amorphous semiconductor films, polycrystalline semiconductor thin film or single-crystal semiconductor thin film to form the channel region of MOS thin-film transistor selectively, it specifically depends on described device is used for high-current circuit, little current circuit etc.
(1-1) lateral bipolar thin-film transistor
Figure 1A is the plane graph that is formed at the lateral bipolar thin-film transistor 100 on the alkali-free glass substrate 101.Figure 1B is the sectional view that the X-X ' line along Figure 1A obtains.Fig. 3 is the sectional view that the Y-Y ' line along Figure 1A obtains.
Figure 1A shows emitter 102, base stage 103 and the collector electrode 104 that is formed in the crystalline semiconductor film 105 to Fig. 1 C.Make semiconductive thin film 105 crystallizations according to predetermined direction.Semiconductive thin film 105 according to the predetermined direction crystallization is to shine semiconductive thin film and the crystal region of horizontal (horizontal direction) crystallization in edge by the pulse laser beam that adopts (for example) light distribution to show as negative peak (inverted peak) pattern.Can form semiconductive thin film 105 by the method for crystallising that will be described in more detail below according to the predetermined direction crystallization.It may not be whole semiconductive thin film that zone to be crystallized is arranged, and it can be the presumptive area that will form device.On semiconductive thin film 105, form emitter electrode 106, base electrode 107 and collector electrode 108.
Shown in Figure 1B and Fig. 1 C, on buffer insulating film 111, form whole bipolar TFT 100.Buffer insulating film 111 comprises that the thickness that is formed on the alkali-free glass substrate 101 is the SiNx film 109 of (for example) 50nm and the thickness SiO for (for example) 100nm 2Film 110.Buffer insulating film 111 plays a part to prevent from glass substrate 101 diffusion impurities.The structure of buffer insulating film 111 is not limited to this example.For example, buffer insulating film 111 can be separately by SiO 2Film or separately by SiN xFilm forms.Available substrate is the low substrate of thermal endurance, and it is not limited to the alkali-free glass substrate.For example, can adopt quartz substrate, plastic, have a SiO in its surface 2The stacked substrate of the silicon substrate of film or metal or Semiconductor substrate and dielectric substrate.
As shown in Figure 1, at SiO 2Forming thickness on the film 110 is the semiconductive thin film of (for example) 200nm, to form transistor 100.This semiconductive thin film is a crystalline semiconductor film, and as shown in Figure 2, it has (for example) and is the plan view shape of T shape substantially.This crystalline semiconductor film is the island district pattern 112 that is essentially T shape, and it is by according to predetermined direction, for example, forms along the Si film 105 of transverse crystallizing.Described semi-conducting material is not limited to Si, can adopt the other materials such as Ge and GaAs.In addition, described film thickness is not limited to 200nm, it can be arranged on can implement crystallization 30nm in the scope of 360nm.Crystallization Si film can be the Si film that is formed at the complete crystallization on the buffer insulating film 111, perhaps can be to have only transistor formation region to be subjected to the Si film of crystallization.
On crystallization Si film 105, form and be mixed with N +The emitter region 102 of impurity, be mixed with N -The collector area 104 of impurity, be mixed with N +The collector electrode contact portion 113 of impurity, be mixed with P -The base region 103 of impurity and be mixed with P +The base stage contact portion 114 of impurity.
Will be by three-layered metal film, for example, the telegraph circuit line (106,107,108) that Ti/Al/Ti constitutes is by being formed at by (for example) SiO 2Contact through hole 116 in first interlayer dielectric 115 that film constitutes is connected to the upper surface of Si film 105.Formation is by (for example) SiO 2 Second interlayer dielectric 117 that film constitutes is to cover whole above-mentioned parts.
In current embodiment, the width W of base region 103 is 5 μ m, and length (equaling the distance between the emitter and collector) LB is 1.0 μ m.Emitter 102 is mixed with impurity, for example, in this embodiment for having 1 * 10 20(cm -3) the phosphorus of concentration, base region 103 is mixed with impurity, for example, has 1 * 10 16(em -3) boron of concentration, base stage contact zone 114 is mixed with impurity, for example, has 1 * 10 20(cm -3) the boron of concentration.Collector area 104 is mixed with impurity, for example, has 1 * 10 17(cm -3) the phosphorus of concentration, collector electrode contact portion 113 is mixed with impurity, for example, has 1 * 10 20(cm -3) the phosphorus of concentration.Can adopt the ion implantation technique in the general semiconductor manufacturing technology to carry out these selective doping processes.Described dopant is not limited to above-mentioned material.The structure of this thin-film transistor is the structure of NPN type lateral bipolar film transistor device 100, wherein, is not that electric current is flowed along the film thickness direction of Si film, flows but make it along continuous straight runs, forms when realizing with MOS transistor thus.With base stage contact portion 114 from the base region 103 lateral parts draw.First embodiment is not limited to NPN type lateral bipolar film transistor device 100, and it also can be a positive-negative-positive lateral bipolar film transistor device.
The operation of transistor 100 is identical with the operation of common double gated transistors.By when collector area 104 applies positive voltage, making base current mobile emitter-collector current of controlling between base region 103 and emitter region 102.
In lateral bipolar thin-film transistor 100, the most important parameter of decision current amplification factor hFE is the crystal mass and the base length LB of Si film 105.The minimum value of base length is preferably 2 μ m or littler.As mentioned below, can take to utilize the lateral crystal growth method of laser, adopting length is the sufficiently high quality that several μ m or higher crystal film obtain Si film 105.In this case, wish that the carrier moving direction in the lateral bipolar thin-film transistor 100 is identical with the crystallization direction of semiconductive thin film.Its reason is that the charge carrier that moves is difficult to cross over the grain boundary.In addition, it is found that,, preferably it is made as smaller or equal to 1 μ m, to guarantee high hFE because the diffusion length of the minority carrier that is injected is no more than 2 μ m, thereby importantly, is made as base length LB at the most smaller or equal to 2 μ m.With regard to regard to the multi-crystal TFT that adopts in the conventional display, the life-span in hole is short, and because the restriction of photoetching is difficult to form the base stage of length smaller or equal to 1 μ m.Thereby be difficult to obtain high hFE.
Will contact in the structure that part is drawn from the side shown in Figure 1A, the design of transistorized width W is important.Only occurring in the zone of base region 103 injected holes, just bipolar operation can taking place.The concentration in hole reduces along the direction away from the base stage contact, and described base stage contact is arranged on the side surface of base region 103.Degree by diffusion length of holes decision reduction in the Si film.According to the inventor's simulated experiment, to find significantly to reduce in concentration apart from described side surface portion 5 μ m or bigger distance hole, collector current flows hardly.Thereby the width W of wishing base region 103 is set to about 5 μ m or is lower, preferably smaller or equal to 3 μ m.
In Figure 1A and Fig. 1 C, with base stage contact portion 114 only from the base region 103 side surface draw.Perhaps, can be with base stage contact portion 114 only from the base region 103 opposite side surface draw, perhaps as shown in Figure 3A, base stage contact portion 114 103 both sides can be drawn from the base region.Thus, can increase the width W of the effective Si film that plays a part bipolar transistor, thereby improve collector current.In addition, perhaps, shown in Fig. 3 B, base electrode 107 can be configured to be connected directly to the base stage operating space 118 that is inserted between emitter region 102 and the collector area 104.The selectivity ion implantation step that can adopt the selectivity diffusing step that adopts and/or utilize photoetching in the manufacturing process of general semiconductor device forms base stage operating space 118.
Be formed at dielectric substrate, for example in the lateral bipolar thin-film transistor 100 on the glass substrate 101, the area of section of the knot between the area of section of the knot between base region and the emitter region and collector area and the base region is little, thereby correspondingly junction capacitance is also little.Therefore, this transistor is the TFT that is suitable for high-frequency operation.
On the other hand, this transistorized shortcoming is, because the area of section of emitter region 102 is little, thereby the big electric current can not obtaining to resemble in the common vertical-type bipolar transistor.Described drive current self is less than the drive current that is formed at the MOS transistor on the same Si film 105.Thereby the common high current drives performance characteristic that realizes as the advantage of bipolar transistor is unsuitable for current device.On the contrary, current device is suitable for little electric current high speed operation.For the input/output interface or current sense preamplifier of (for example) display, this feature is favourable.
Fig. 4 shows the curve chart to the I/O characteristic of the NPN type lateral bipolar thin-film transistor 100 of first embodiment shown in Fig. 1 C according to Figure 1A.In Fig. 4, abscissa is represented emitter-collector voltage (Vce), and ordinate is represented collector current (Ic).Fig. 4 shows by with 5 μ A being the measurement result that step-length raising base current obtains.Fig. 5 shows the curve chart of Gummel curve.In Fig. 5, abscissa is represented base-emitter voltage (Vcb), and ordinate is represented base current (Ib) and collector current (Ic).Be appreciated that from Fig. 4 and Figure 13 A output current by 0.01mA has obtained (for example) more than or equal to 10 current amplification factor.Can also understand from Figure 13 A, mobility should be preferably greater than and equal about 350cm2/Vs.In addition, be appreciated that to have obtained good saturation characteristic, and this analog circuit is needed just.For example, this transistor is applicable to the transistor of the importation of Figure 28 or current drives serial interface circuit shown in Figure 34.
Next, will provide explanation with reference to figure 6 to Figure 13 B to the transistorized embodiment of MOS lateral bipolar mixed film in the above-described electronic installation.
(1-2) the bipolar mixed film transistor of MOS-
Fig. 6 is the plane graph that is formed at the bipolar mixed film transistor 200 of MOS on the glass substrate according to an embodiment of the invention.Fig. 7 is the sectional view along Z-Z ' line of Fig. 6.Fig. 8 is the sectional view along A-A ' line of Fig. 6.The bipolar mixed film transistor 200 of MOS is the transistors that have the function of MOS thin-film transistor and bipolar transistor simultaneously.The source electrode of MOS thin-film transistor also plays a part the emitter of bipolar transistor.The raceway groove of MOS thin-film transistor also plays a part the base stage of bipolar transistor.The drain electrode of MOS thin-film transistor also plays a part the collector electrode of bipolar transistor.
On (for example) buffer insulating film 204, form the bipolar hybrid transistor 200 of whole M OS.Buffer insulating film 204 comprises that the thickness that is formed on the alkali-free glass substrate 201 is the SiN of (for example) 50nm xFilm 202 and thickness are the SiO of (for example) 100nm 2Film 203.The substrate that can adopt is not limited to the alkali-free glass substrate, for example, can adopt quartz substrate, plastic or have SiO in its surface 2The silicon substrate of film.Described buffer insulating film 204 plays a part to prevent from glass substrate 201 diffusion impurities.The structure of buffer insulating film 204 is not limited to this example.For example, buffer insulating film 204 can be separately by SiO 2Film or separately by SiN xFilm forms.As the case may be, semiconductive thin film 205 directly can be formed on the dielectric substrate such as glass substrate 201.
At SiO 2Form basic on the film 203 for the thickness of T shape is the semiconductive thin film 205 of 200nm, as the example that is used to form transistorized film.Form the example (with reference in figure 2 112) of Si film as semiconductive thin film 205.In this embodiment, as this Si film, adopt to comprise that length is the Si film of a few μ m or bigger single crystal grain, described Si film is to form by the lateral crystal growth method that adopts laser, will be illustrated it hereinafter.
In semiconductive thin film 205, form N +Doping emitter region (source area) 206, N -Impure collecting electrode district (part of drain electrode) 207, N +Impure collecting electrode contact zone (part of drain region) 208, P -Impure base district (channel region) 209 and P +Impure base district (channel region) contact 210.
The difference of the device of this embodiment and lateral bipolar thin-film transistor is, on the base region via being the SiO of 30nm by thickness 2The gate insulating film 214 that forms has formed the gate electrode 211 that is made of the MoW alloy film.Above-mentioned explanation relates to the bipolar mixed film transistor 200 of NPN type MOS (N-channel MOS thin-film transistor).But, can take similar mode to construct the bipolar mixed film transistor of positive-negative-positive MOS (P channel MOS thin-film transistor).The circuitry lines 213 that will be made of three-layered metal film (for example) Ti/Al/Ti is connected to the upper surface of Si film 205 and gate electrode 211 by being formed at contact through holes 216 in first interlayer dielectric 215.Be appreciated that the gate electrode 211 of base region (channel region) 209 and contact zone 212 by electrode line pattern 213 from the sectional view of Fig. 8 of obtaining along A-A ' line, promptly the Ti/Al/Ti three-layer metal film figure among this embodiment connects, thereby its electromotive force is equated.Formation is by (for example) SiO 2 Second interlayer dielectric 217 that film constitutes is to cover whole above-mentioned parts.
Although the value that the width W of base region 209 and length L B are not limited to mention below, the minimum value of preferred base length is set to 2 μ m or lower.In this embodiment, the width W of base region 209 is 2.5 μ m, and length (equaling the distance between the emitter and collector) LB is 1 μ m.
Similar with the embodiment of lateral bipolar thin-film transistor, emitter region (source area) 206 is mixed with phosphorus, and base region (channel region) 209 is mixed with boron, the impurity that collector area (drain region) 207,208 is mixed with such as phosphorus.Described dopant is not limited to above-mentioned material.Can adopt the selective doping of the ion implantation technique execution foreign atom in the general semiconductor manufacturing technology.
Can be as required on the dielectric substrate identical with lateral bipolar thin-film transistor 100, for example form the bipolar mixed film transistor 200 of above-mentioned MOS on the alkali-free glass substrate.In this case, can in identical crystallisation step, carry out the crystal formation process that forms these transistorized semiconductive thin films (105,205).
The overall width that Fig. 9 shows base region (channel region) is the plane graph of the transistorized part of mixed film of 100 μ m, the mixed film transistor (base region in this example (channel region) width is 5 μ m) shown in 20 Fig. 6 to 8 wherein in parallel.Between a plurality of dependency basis polar region (channel region) 209 that is formed on the Si pattern 219, form a plurality of emitter regions (source area) 206 and collector area (drain region) 207 with certain intervals.Base region (gate electrode) 209, emitter region (source area) and collector area (drain region) are connected to public grid (base stage) electrode 220, common-emitter (source electrode) electrode 221 and common collector (drain electrode) electrode 222 respectively.
Described as mentioned, with regard to the device that has the side surface contact, limited base region (channel region) width.Thereby, in the transistor that drives big electric current, can keep good characteristic by the transistor of arranging a plurality of parallel connections with little width W.This structure can prevent the spontaneous heating of device when big current practice.
In the operation of current device, similar with common bipolar transistor, when collector area (drain region) 208 applies positive voltage, by the electric current between base current control emitter region (source area) that flows between base region (gate regions) 209 and the emitter region (source area) 206 and collector area (drain region).Owing to connected gate electrode 211 and contact 212 with base region (channel region), thereby the voltage that puts on 1 to 2V between base region and the emitter region has become the voltage between gate regions and the source area.If this voltage is higher than the threshold voltage vt of MOS thin-film transistor, will in channel region 209, forms surface channel so, and produce the surface current that flows.Be injected into the electron stream of base region (channel region) 209 through surface channel by bipolar operation from emitter region (source area) 206.Thereby, compare with the situation of independent employing bipolar device or MOS device, will obtain bigger drive current by this device.
Figure 10 and Figure 11 show the I/O characteristic of the Gummel curve of the bipolar mixed film transistor 200 of above-mentioned MOS (hereinafter being called " TFT " again).Rely on this thin-film transistor 200, can be than relying on Fig. 4 and lateral bipolar thin-film transistor 100 shown in Figure 5 to obtain higher drive current.In addition, be appreciated that current amplification factor hFE will be higher also.Be appreciated that current value shown in Figure 10 approximately is two times of electric current when only there is the operation of MOS device in the situation that does not connect base electrode.
Figure 12 shows collector electrode (drain electrode) electric current of mixing TFT 200 and the relation between the current amplification factor hFE.According to characteristic shown in Figure 12, obtained about 500 maximum current magnification factor hFE.Thereby mixing TFT 200 can obtain higher current gain by married operation.
Figure 13 A shows in the mixing TFT200 of the film quality that has changed Si film 205, the relation between the current amplification factor of the field-effect mobility that is in MOS pattern when operation when being in double pole mode and operating.Field-effect mobility and current amplification factor are proportional substantially.
For example, under the situation of the input circuit that is used for display unit,, must adopt its quality to be enough to obtain 350 (cm in order in the middle of practice, to obtain abundant high current amplification factor hFE more than or equal to 10 2/ V/s) the Si film of surface channel mobility.
Be appreciated that the expection characteristic that has obtained analogue circuit applications by this mixing TFT.
For example, this mixing TFT 200 is suitable for the transistor as the importation of Figure 28 or current drives serial interface circuit shown in Figure 34.
Figure 13 B shows the curve chart that mixes the carrier transit time (τ) between the emitter and collector among the TFT 200 with respect to base length LB.Carrier transit time (τ) is by 1/2 π f TCurve with respect to 1/Ic is derived.Figure 13 B shows carrier transit time and increases with respect to base length LB is linear basically, and the electronic motion restriction of being drifted about.The existence of surface channel has been lighted effect to this, and surface channel has absorbed injected electrons effectively, and has improved the motion in the base stage.
(1-3) MOS thin-film transistor
Next, will provide description with reference to figure 14A and Figure 14 B to the embodiment of the MOS thin-film transistor in the above-mentioned electronic installation.
Figure 14 A and Figure 14 B show with above-mentioned bipolar TFT 100 or mix TFT 200 and be formed at MOS type TFT 300 sectional views and plane graph on same (single) dielectric substrate.
Form whole M OS type TFT 300 on buffer insulating film, described buffer insulating film comprises that the thickness that is formed on the alkali-free glass substrate 321 is that SiNx film 321 and the thickness of 50nm is the SiO of 100nm 2Film 322.
Similar with common field-effect transistor, can MOS type TFT 300 be formed P transistor npn npn or N transistor npn npn by the suitable impurity of selecting to mix with source/drain regions 324 and raceway groove 330.Form by the thick SiO of (for example) 30nm on (for example) by the silicon single crystal district 323 that makes amorphous Si film and form along the predetermined direction crystallization 2The gate insulating film 325 that constitutes.On the surface of gate insulating film 325, form and cross over the gate electrode 326 that single-crystal region 323 is extended by (for example) MoW alloy film formation.Width by gate electrode 326 is determined channel length.For this MOS transistor being used as the circuit element of display unit, preferably the grid length of MOS transistor is set to smaller or equal to 1 μ m, and the maximum that preferably is formed at the field-effect mobility of this MOS transistor in the silicon metal single-crystal region is set to 350cm 2/ Vs or higher.
Formation is by (SiO for example 2) interlayer dielectric 327 that constitutes, make it to cover whole above-mentioned parts.Form the telegraph circuit line 329 that constitutes by three-layered metal film by the contact through hole 328 that is formed in the interlayer dielectric 327 such as Ti/Al/Ti.Described metal film can be formed by the various electric conducting materials except Ti/Al/Ti.According to the service condition relevant, can in the non-crystalline semiconductor film, form the MOS thin-film transistor, and can form two types transistor by the form of mixing with the electronic circuit that will adopt.
With regard on dielectric substrate, form comprise a plurality of semiconductor device according to regard to the electronic installation of the present invention, described device formed comprise at least a in the bipolar mixed film transistor of above-mentioned MOS film and lateral bipolar thin-film transistor and MOS as such semiconductor device, described device is formed in the crystalline semiconductor film, and has high current amplification factor.
Form integrated circuit comprising on the insulated substrate of display unit, described integrated circuit has been configured to MOS transistor and bipolar transistor simultaneously integrated.
Figure 14 C shows the source electrode-drain breakdown voltage (V with respect to the grid length of N raceway groove polysilicon MOS thin-film transistor and SOI-MOS thin-film transistor BD) curve chart.In the MOS type thin-film transistor that display unit adopts, the V that causes owing to floater effect BDReduction brought serious problem.The crystallization polycrystalline Si MOS thin-film transistor that forms in single-crystal region has higher puncture voltage than SOI-MOS thin-film transistor, and is suitable as the device that adopts in display unit.
(second embodiment)
The crystallization embodiment of semiconductive thin film
Next, will provide explanation, in described semiconductive thin film, will form (for example) above-mentioned lateral bipolar thin-film transistor 100 and the bipolar mixed film transistor 200 of MOS forming along the embodiment of the semiconductive thin film of predetermined direction crystallization.
Can adopt thin-film transistor to carry out the control that the image that adopts (for example) liquid crystal screen is shown, described thin-film transistor adopted in the transistorized manufacturing of general thin, adopt, be formed at such as the amorphous silicon membrane on the dielectric substrate of glass substrate.Usually, after described amorphous silicon membrane is annealed again to its use.But, adopt such substrate particularly effective, promptly as display base plate, described substrate has that a plurality of forms according to array form, the island district that constitutes by monocrystal thin films substantially, promptly, zone along the semiconductive thin film of predetermined direction crystallization will be illustrated it hereinafter.
Its reason is that the semiconductive thin film of deposit is subjected to further crystallization by making, and can obtain a plurality of zones that " substantially " is made of monocrystal thin films with uniform condition on the required whole large-area substrates of display unit." substantially " vocabulary under this background shows, in some cases, when carrying out crystal growth, might constitute described a plurality of zone by a plurality of single-crystal region, but described a plurality of zones should be made of desirable monocrystal thin films preferably by method of the present invention as described below.
Figure 15 is the electron micrograph image according to the substrate 400 of second embodiment that the present invention adopts.Substrate with a plurality of zones that are made of the monocrystal thin films of array arrangement is not limited to glass substrate.But, in this embodiment, adopted transparent alkali-free glass substrate 101 and 201.This substrate that is used for display has such structure, thereby arrange a plurality of zones of arranging with the form of two-dimensional matrix with the interval of 5 μ m along the vertical and horizontal directions, described a plurality of zones are formed by the silicon thin film that (for example) every person has the size of about 5 μ m * 5 μ m.
In Figure 15, polycrystalline zone 402 is present in the boundary member that has obtained the single-crystal region 401 of crystallization around each, and has a lot of grain boundaries 403.In grain boundary 403, has the electroactive defective in the generation/complex centre that plays a part charge carrier.Thereby, multi-crystal silicon area 402 is got rid of from the formation district of the base stage of thin-film transistor or channel region.Figure 15 shows a kind of like this state, and wherein, entire substrate all has been subjected to crystallization treatment.Perhaps, only by a part of substrate, for example, have only the part that forms any one thin-film transistor can be subjected to crystallization treatment.
Figure 16 is the enlarged drawing in the zone of one of single-crystal region as among Figure 15.In the zone that is of a size of 5 μ m, the marginal zone of about 0.5 μ m is a polycrystalline 402, has a lot of defectives in crystal boundaries.Thereby transistorized base stage (raceway groove) district is set to not comprise the defect area 402 of about 0.5 μ m.
In the Japanese patent application No.2003-209598 that submitted on August 29th, 2003, describe the method that a kind of manufacturing has the substrate of crystalline semiconductor film applicant in detail by the application.
To provide description now to the example of the formation method of membrane array, described membrane array have with the spacing arrangement of 5 μ m be the single-crystal region of rectangle substantially, each single-crystal region is of a size of about the 4 μ m of every limit, as Figure 15 and shown in Figure 16.
At the substrate that is used as display base plate is under the situation of glass substrate, can not adopt high temperature to obtain monocrystalline as making silicon wafer.At first, adopt any means on glass substrate, to form (for example) amorphous silicon membrane.Afterwards, on amorphous silicon membrane, apply the pulse type ultraviolet laser beam, make the laser of amorphous silicon film apply the zone thawing thus.Make the amorphous silicon film crystallization once more of thawing, and form the silicon thin film district that part has changed into monocrystalline.In this embodiment, adopt silicon, but available semi-conducting material is not limited to silicon.For example, can adopt III-V family semiconductor.
When carrying out crystallization once more, take following method to obtain to have the single-crystal region of big as far as possible area.Described film is melted, thereby give temperature gradient for each array portion.
Under the situation that keeps temperature gradient, reduce substrate temperature, thereby make silicon crystallization once more.In order to realize this purpose, take such method, promptly, the phase shifting mask generation light distribution that employing has suitable pattern is the transmitted light of negative peak pattern, give spatial distribution for the light intensity that shines the laser beam on the substrate surface thus, and give laterally (level) temperature gradient for each array portion.According to this method, in the non-exposure period after having shone laser beam, reduce the temperature of the appropriate section of substrate on the basis of the temperature gradient when melting, make solid-liquid interface move towards high-temperature part from the minimum temperature part, thereby along crystal growth laterally takes place.Thereby crystal growth relies on and to be particularly suited for the polycrystalline part sustainable development of crystal seed crystal growth, crystal block section from initial generation, and has formed big single-crystal region.
In some cases, a plurality of single-crystal region have been formed.Even in this case, the size of grown crystal also will be greater than the size of the transistorized channel region of general thin.By this method, becoming to obtain to have the array of a plurality of basic single-crystal region 401 for monocrystalline, and each single-crystal region 401 has and is the shape of rectangle substantially, and it is of a size of about the 4 μ m of every limit.
Next, will the crystallisation step once more that adopt (for example) phase shifting mask be described to Figure 17 D with reference to figure 17A.Phase shifting mask 510 shown in Figure 17 A is formed, will be provided as such as the transparent medium of quartz material and have the different adjacent area of a plurality of thickness.At step part (phase shift section) the 510a place that is between these adjacent areas, incoming laser beam will be subjected to diffraction or interference.In this way, given the cycle spatial distribution for the intensity of incoming laser beam.
Be configured to make adjacent patterns to have opposite phase (having 180 ° of phase differences) phase shifting mask 510.Particularly, the zone of arranged alternate comprises first zone (phase region) 510b with phase place π and second zone (phase region) 510c with phase place 0.In this example, each zone (phase shift line district) has the width of 10 μ m.More specifically, refractive index is that 1.5 rectangle quartz plate carries out pattern etching, makes it to have the degree of depth corresponding to the phase place π for the light that is 248nm with respect to wavelength, and promptly the degree of depth of 248nm is made phase shifting mask 510 thus.Zone by the etching attenuate has become the first zone 510b, has become the second zone 510c without etched zone.
When employing had the phase shifting mask 510 of this structure, the laser beam that passes the second big phase region 510c of thickness had been subjected to 180 ° delay for the laser beam that passes the first little phase region 510b of thickness.As a result, interference and diffraction have taken place between laser beam.Obtained to have the laser beam intensity shown in Figure 17 B thus and distributed 530 with negative peak pattern.Especially, because the adjacent laser beam that passes described phase region has opposite phase, thereby the laser beam that passes the phase shift section between the adjacent phase region has minimum intensity of light, and for example 0.Temperature with part of minimum intensity of light is reduced to minimum, thereby cycle Temperature Distribution 540 is provided on substrate surface.
When stopping laser beam irradiation, near minimum temperature district 241 or the zone zones 241 have melting temperature or lower temperature, thereby have produced in this zone much as the semiconductor polycrystalline of subcrystalline nucleus again.At first, in minimum temperature district 241, produce polycrystalline.But when crystal was grown in succession according to temperature gradient, growth had taken place in the crystal block section with crystal orientation of the crystal growth of being particularly suited for.Thereby, in each temperature gradient part 542, obtained to be substantially the zone of monocrystalline.
In above-mentioned explanation kind, phase shifting mask 510 is configured to have line and the space structure that (for example) comprises the wire phase shift section that is parallel to each other, shown in Figure 17 A and 17B.But the structure of phase shifting mask 510 is not limited to this example.For example, the phase shift line can be with right angle intersection, and arranges part with phase place 0 and the part (not shown) with phase place π according to latticed form.In this case, the light intensity that is formed on this place's dot matrix along the phase shift line is 0 zone.Therefore, crystal seed will produce on the optional position of phase shift line, will be difficult to control the position and the shape of crystal grain in some cases.Simultaneously, also can adopt area modulated type phase-shifter.
In order to control the generation of crystal seed, wish with light intensity be 0 zone with point-like according to predetermined period profile.In a kind of possible method that is used for realizing this purpose, the phase-shift phase of every square crossing phase shift line is set to less than 180 °.In this case, in the position corresponding to every phase shift line, light intensity descends, but does not thoroughly become 0.But, as mentioned below, by suitable selection phase-shift phase can be near the phase shift line crosspoint compound transmissivity and reduce to 0.In this case, the light intensity that is in infall can be reduced to 0.
Below with reference to Figure 17 C and Figure 17 D an example is described.Shown in Figure 17 C and 17D, phase shifting mask 550 comprises a plurality of square pattern 552, and each square pattern 552 comprises four square region 550e, 550f, 550g and 550h with different-thickness.Shown in Figure 17 C, in each pattern, 550e is the thinnest in the first area, and its phase place is 0.The 4th regional 550h is the thickest, and it has had from the phase deviation of first area 550e the phase place of 3 pi/2s.The thickness of the second and the 3rd regional 550f and 550g is between the thickness of first area 550e and the 4th regional 550h, and has the phase place that has been offset pi/2 and π from first area 550e respectively.
In aforementioned mask, the central point 551 of the square pattern of first to the 4th regional adjacent layout has intensity 0.Therefore, this central point has become the nucleus of crystal growth.In Figure 17 C, can be with the central point of pattern, promptly each lattice point 551 is set to have intensity 0.Therefore, be easy to control the generation position of crystal grain.Based on Japanese patent application No.2002-120312, and in the specification of the International Application PCT/JP03/03366 that submits on March 19th, 2003 by the application's applicant the technology that adopts this phase shifting mask has been described.
(the 3rd embodiment)
Another embodiment of phase-shifter
To describe being used to form now, in described semiconductive thin film, will form the bipolar mixed film transistor of above-mentioned lateral bipolar thin-film transistor and MOS along the embodiment of the phase-shifter of the semiconductive thin film of predetermined direction crystallization.
Figure 18 shows the cross section that is used to form along another phase-shifter 560 of the semiconductive thin film of predetermined direction crystallization, also schematically shows light distribution.This phase-shifter 560 is configured to, have on (for example) quartz plate 561 of predetermined thickness arrange a plurality of by SiO 2The outstanding pattern 562 that forms and have preliminary dimension.By making the equally distributed laser beam 563 in space pass phase-shifter 560, can on the irradiating surface (not shown) of MULTILAYER SUBSTRATE, provide to have the zigzag repeat patterns, for example, the light distribution 564 of 100 patterns.
In this embodiment, the repetition interval Lx of outstanding pattern 562 is set to 10 μ m, but can be set to desired value by this value of design.Light distribution 564 shown in Figure 180 comprises the serrated portion that is formed by a pair of straight line portion 565 and 566 with different angle.Light distribution 564 is not limited to sawtooth and distributes, and it can be any light distribution that is suitable for crystallization.
(the 4th embodiment)
Another embodiment relevant with lateral bipolar transistor
Figure 19 shows the surperficial SEM image of crystallization Si film formed according to the present invention.Figure 19 shows the embodiment of the layout that is formed at the lateral fet in the described crystallization Si film.By laser beam irradiation MULTILAYER SUBSTRATE is heated, thereby amorphous semiconductor film is melted with light distribution shown in Figure 180 564.Afterwards, stop laser beam irradiation in the cycle, thereby make temperature decline and make semiconductor thin film crystallization closing of laser beam.At this moment, will (that is, the upper area from Figure 19 is to lower area) melts/crystallization once more towards the zone with high laser intensity from zone with low laser intensity.As a result, crystallization start-up portion 570 is in the polycrystalline attitude, and along with crystal growth is advanced along the horizontal direction of substrate, the crystal grain with directivity of the crystallization of being easy to becomes increasing.Thereby, can form the gathering of single crystal grain, the size of described single crystal grain is greater than the TFT that next forms.The crystallization dwell section 571 that proceeds to this place in crystallization has formed polycrystalline, conflicts in described crystal and adjacent bonds crystalline region.
In the above-described embodiments, pulse type ultraviolet laser beam as the example of crystal laser bundle has been described.But it is just enough to launch the laser beam with the energy that makes amorphous semiconductor (silicon) thawing, also might adopt continuous-wave laser beam.Adopt the crystallization apparatus of continuous-wave laser beam to launch continuous-wave laser beam under such state, that is, laser beam sources and amorphous semiconductor (silicon) film relative to each other moves.Can form crystal region thus with big crystallite dimension.
In the above-described embodiments, the size of crystal region makes that each transistorized channel region (active layer) is formed in the crystal region at least.
Figure 19 shows the pattern image according to the bipolar transistor of described embodiment, and described bipolar transistor is arranged on along on the semiconductive thin film of predetermined direction crystallization, and described predetermined direction is by the Temperature Distribution decision that distributes corresponding to intensity of laser beam.Be to make collector electrode-emitter direction that electric current flows be parallel to crystal growth direction with this transistor layout.Therefore, flowing of charge carrier can not be subjected to stopping of grain boundary, thereby obtains good characteristic.In this layout, make collector area be positioned at the crystal growth starting point near, make emitter region be positioned at the crystal growth terminating point near.Hereinafter, with this layout definition be " forward layout ".On the other hand, the layout definition with the position of the collector and emitter that reversed is " reciprocal transformation ".Same layout is applicable to the bipolar mixed film transistor of MOS.
Figure 20 A and Figure 20 B show the forward layout of bipolar transistor shown in Figure 19 and the Gummel curve in the reciprocal transformation.Current amplification factor in the forward layout (Figure 20 A) is higher than the current amplification factor in the reciprocal transformation (Figure 20 B).Figure 21 A and Figure 21 B are the curve charts of having drawn current amplification factor β respectively with respect to the base-emitter voltage in forward layout and the reciprocal transformation.In the forward layout, β is near 30, and in reciprocal transformation, β is about 6.From this result as can be seen, preferably collector area is arranged near the crystal growth starting point, emitter region is arranged near the crystal growth terminating point, obtain good transistor characteristic thus.It is believed that the asymmetric of this characteristic is to be caused by the electrical characteristics difference between base-collector junction and the base-emitter knot.
Figure 22 shows the curve chart of the diode characteristic that is in interior base-collector junction of same device and base-emitter knot.With regard to base-collector junction, reverse leakage current is bigger, and the n value of forward direction characteristic is also bigger.Be appreciated that in base-collector junction the density of defects that plays the complex centre effect is higher.As if its reason be, owing to the width of crystal grain along with the carrying out of lateral crystal growth increases (this point can from SEM image understanding shown in Figure 19), the density of grain boundary reduces towards the crystal growth terminating point.As mentioned above, be formed at regard to the situation on the crystal of a certain direction growth with regard to bipolar transistor, can be by collector electrode being arranged near the crystal growth starting point, emitter is arranged near the crystal growth terminating point and obtains bigger current amplification factor.
(the 5th embodiment)
With the relevant embodiment of MOS transistor in being formed at crystalline semiconductor film
Figure 23 shows the schematic plan view of the embodiment that is formed at the MOS transistor in the crystalline semiconductor film with structure shown in Figure 19.Particularly, in this embodiment, be to make the mobile source electrode-drain directions of electric current be parallel to the direction of crystal growth with this transistor layout.Therefore, flowing of charge carrier can not be subjected to stopping of grain boundary, thereby obtains better characteristic.In the layout of this embodiment, making the drain electrode be positioned at the crystal growth starting point near, make source electrode be positioned at the crystal growth terminating point near.Similar with the situation of bipolar transistor, be " forward layout " with this layout definition.On the other hand, the layout definition with the position of reversed drain electrode and source electrode is " reciprocal transformation ".Figure 24 is the cross section transmission electron microscope image of the MOS thin-film transistor that is provided with in this way.
Figure 25 A and Figure 25 B show the Id-Vg characteristic of the MOS transistor of manufacturing like this, and described characteristic records by source electrode-drain voltage is changed between 0.1V and 5.1V in forward layout and reciprocal transformation.Figure 26 shows the result who obtains by the transistorized threshold voltage vt h that draws based on the result shown in Figure 25 A and Figure 25 B as the function of drain voltage.
In reciprocal transformation, the drain voltage correlation of Vth is low.In the forward layout, Vth reduces along with the increase of drain voltage, and when drain voltage during more than or equal to 0.5V, Vth gets negative value.Be further appreciated that the drain voltage correlation of leakage current is bigger in the forward layout in grid voltage is the zone of bearing.
Can think that the reduction of Vth is caused by the variation of bulk potential under the effect of drain electrode-junction leakage.Can think that the Vth that the intermediate level Vd district in the forward layout reduces slightly changes relevant with bulk potential under the two effect of drain leakage and ionization by collision.The difference of Vth reduction degree shows that the intensity that bulk potential changes there are differences between forward layout and the reciprocal transformation between two kinds of layouts.
If Vth reduces along with the increase of drain voltage, under the effect of the drain voltage that reality adopts in electronic installation, big breakdown current will take place to flow under undesirable situation so.Find that by labor this asymmetry of the drain current correlation of Vth is because the drain junction and the leakage current at source junction place and the asymmetry of current amplification factor β cause, as Figure 21 A, 21B and shown in Figure 22.Figure 21 A and Figure 21 B show the variation of β with respect to Vbs.Should be noted that there is about 5 times difference in β between forward layout and the reciprocal transformation.Can think,, thereby under the situation of counter-rotating source area and drain region, will in the decline of Vth, produce asymmetry because the leakage current at knot place is all different with bipolar gain.
From The above results as can be seen, when MOS transistor is formed on the crystal of a certain direction growth, preferably MOS transistor is formed, source area is near the crystal growth starting point, the drain region is near the crystal growth terminating point.Thus, can reduce drain voltage correlation and the drain leakage of Vth.If will be formed at the thin-film transistor of crystal region is fabricated to and makes electric current flow the thin-film transistor that just can obtain to have good mobility characteristics along crystal growth direction.
(the 6th embodiment)
The embodiment relevant with the current drives style interface
As mentioned above, be different from common bipolar transistor as lateral fet 100 and the hybrid transistor 200 that forms in Figure 1A or the crystalline semiconductor film on being formed at glass substrate shown in Figure 6.These transistors are not the electronic circuit that is used for the big drive current of needs, but are suitable for the amplification of less electric current.Can consider the current drive-type serial line interface of these transistor application in the display unit 600 of utilizing this feature.Figure 27 shows the example of the front-end circuit 601 of such current drive-type interface.Figure 27 shows the electrical block diagram of the embodiment that is applied to amplifying circuit, for example, when described amplifying circuit receives radio signal and is translated into the signal of telecommunication at antenna, the little electric current smaller or equal to 100 μ A that flows in antenna is amplified, with input as the display unit such as liquid crystal indicator of liquid crystal TV or terminal.Be illustrated in the little electric current that flows in the antenna by Isig.This embodiment is characterised in that described amplifying circuit is made of thin-film transistor circuit.Can amplify such little electric current by the electric current scale-up version thin-film transistor circuit that forms in the semiconductive thin film on being formed at dielectric substrate smaller or equal to 100 μ A, and by voltage amplification type thin-film transistor circuit to carrying out voltage amplification through amplified current.
Described electric current scale-up version thin-film transistor circuit is characterised in that by above-mentioned lateral fet 100 or hybrid transistor 200 and constitutes that described transistor is formed at the crystalline semiconductor film that is positioned at such as on the dielectric substrate of glass substrate.Described electric current scale-up version thin-film transistor circuit had both played a part interface circuit, played a part to be used for current input signal is converted into the circuit of voltage output signal again.Voltage amplification type thin-film transistor circuit is made of the MOS thin-film transistor circuit in crystal region that is formed at semiconductive thin film or the noncrystalline domain.
Particularly, if the resolution of image and number of colors increase, want data quantity transmitted also correspondingly to increase so.But, because the refresh rate that image shows fixes, if thereby data volume increase, the clock frequency of transmission path 602 also must increase so.
In this way,, will produce such problem, that is, from transmission path, generate unnecessary electromagnetic radiation, and under the effect of electromagnetic interference (EMI), externally cause noise in the device if improve the frequency of transmission path 602.In order to address this problem, taked a kind of like this method, wherein, drive reduction EMI by the low-voltage differential that is called as (for example) LVDS (low voltage differential command).The example of this technology for example, is disclosed in Japanese Patent Application Laid-Open No.2002-176350.In addition, in recent years, as the transmission plan that can more effectively reduce EMI, the someone has proposed the serial line interface by current drives.An example is disclosed in Japanese Patent Application Laid-Open No.2003-76345.In circuit shown in Figure 27, suppose to provide to have two values or more than or equal to the current signal Isig of two values from system end.Input interface circuit (IF) 603 is configured to received signal Isig, and is translated into voltage signal.The voltage amplification that level shift circuit 604 is carried out voltage signal, and the voltage after will amplifying offers follow-up serial/parallel change-over circuit 605.It is characterized in that, adopt the lateral fet that is formed in the crystalline semiconductor film in described input interface importation.Can adopt the bipolar mixed film transistor of MOS that is formed in the crystalline semiconductor film to substitute above-mentioned lateral bipolar thin-film transistor (other embodiment that this point is equally applicable to will be described below).
Figure 28 shows the example of the circuit structure of input interface circuit (IF) 603 shown in the block diagram of Figure 27 and level shift circuit 604.Described importation is configured to, makes the grounded emitter lateral bipolar thin-film transistor Q1 and the grounded-grid MOS thin-film transistor M1 cascade that are formed in the crystalline semiconductor film.First order transistor Q1 as the electric current amplifier section carries out the electric current amplification to input signal Isig.Afterwards, by second level MOS thin-film transistor M1 and load resistance Rd described input signal is converted into voltage signal.Next, voltage signal is input to the level shift circuit 604 that constitutes by the CMOS phase inverter (inverter) that is in the third level.Employing can reduce the level of current input signal Isig to the electric current bipolar TFT Q1 directly that amplify, that have high amplification coefficient of importation.Thereby, can reduce the power consumption of signal transmission system end (not shown).In this example, formed thereon and formed on the substrate 617 of display unit 601 according to lateral bipolar thin-film transistor Q1 of the present invention and MOS thin-film transistor M1, constituted input interface circuit (IF) 603 and the level shift circuit 604 of described display unit thus to M3.In the electric current amplifier section, can adopt the bipolar hybrid transistor of MOS according to the present invention to substitute the lateral bipolar thin-film transistor.When adopting the bipolar mixed film transistor of lateral bipolar thin-film transistor or MOS in input interface circuit, the maximum of these transistorized current amplification factors should be preferably greater than and equal 10.
The signal waveform of the collector current Ic that Figure 29 shows in circuit shown in Figure 28 input current signal Isig, flow in lateral bipolar thin-film transistor Q1 and the output voltage V out of level shift circuit 604.Because the level of little electric current I sig is very low, only is 0 to 70 μ A, thereby the EMI of importation is minimized.In addition, very simple circuit that can be by comprising four transistor Q1, M1, M2 and M3 is converted into the little current signal of 0 to 70 μ A 0 to 3V voltage signal.
In the present embodiment, in input interface circuit 603, adopt the cascade circuit of lateral bipolar thin-film transistor Q1 and MOS thin-film transistor M1, in level shift circuit 604, adopt the CMOS phase inverter.But described circuit structure is not limited to this example, for example, can adopt common differential amplifier circuit.
As mentioned above, Figure 27 shows the structure of the entire liquid crystal display device that comprises input interface circuit 603 and level shift circuit 604.Figure 27 and interface circuit 603 shown in Figure 28 be receiving video signals not only, also receives clock signal Iclk as current signal, control signal etc., and is translated into voltage signal.Described signal is offered the level shift circuit 604 of following interface circuit 603, and it is adjusted to suitable voltage levvl.By serial/parallel change-over circuit 605 vision signal is converted into parallel signal.
According to parallel conversion degree (degree of parallel) clock signal Iclk is carried out frequency division by frequency sharing circuit 612, and will offer timing controller 606 through the signal of frequency division.To offer horizontal drive circuit 608 together with the frequency division clock signal by buffer storage 607 through parallel video signal converted.In horizontal drive circuit 608, be in due course and latch described vision signal, and provide it to the DA change-over circuit 609 that each holding wire of contact provides.Described DA change-over circuit 609 is converted into analog signal with vision signal, and provides it to the display part.In the display part, the switching transistor 611 that each pixel, provides by the sweep signal On/Off that provides from vertical scanning circuit 610, and will offer liquid crystal layer, thereby by Active Matrix LCD At unit 614 display images from the aanalogvoltage of horizontal drive circuit.
Figure 30 is the birds-eye view of entire liquid crystal display device 620.Figure 31 is the sectional view of liquid crystal indicator 620.Liquid crystal material 623 is arranged between transparent insulation substrate 621 and 622.On transparency carrier 621, form and a plurality ofly drive and according to the form pixel electrodes arranged 624 of matrix by active matrix circuit shown in Figure 27.Counterelectrode 625 is arranged on the transparent insulation substrate 622.Electromotive force by switching transistor shown in Figure 27 611 each pixel electrode 624 of control.Be applied to the optical characteristics that the electromotive force that is arranged at the liquid crystal material 623 between counterelectrode 625 and the pixel electrode 624 is controlled liquid crystal material 623 by control.
By taking the current drive-type input interface, and in the input circuit 603 of display unit one side, adopt lateral bipolar thin-film transistor Q1, can with than in the prior art more low-signal levels realize the signal transmission.Therefore, can reduce the EMI and the power consumption of whole system.In addition, in current system, can increase transmission frequency by the low EMI of current interface.Therefore, native system advantageously is applicable to the liquid crystal indicator with high definition and a large amount of gray scales.
In addition, in the present embodiment, current drive signal transmission has been applied to (for example) has been in the middle of the transmission path between the importation 603 of outside display system (not shown) and display base plate 617.But, the invention is not restricted to this example, the present invention is applicable to the signal transmission in the interior circuit block of active-matrix substrate.For example, under the situation that horizontal drive circuit constitutes by a plurality of, signal transmission of the present invention is applicable to the signal transmission between each piece.
(the 7th embodiment)
With the relevant embodiment of active matrix liquid crystal display apparatus that adopts organic LED
Figure 32 shows the structure of active matrix display devices according to a seventh embodiment of the invention.In this display unit, adopt inductance element 711 receiving inputted signals, adopt the organic LED element as display element.On alkali-free glass substrate 701, press arranged in form multi-strip scanning line 702 and many video signal cables 703 of matrix.In addition, tft active matrix display part 707 and scanning circuit 704 and signal provision circuit 705 are set on alkali-free glass substrate 701, in described tft active matrix display part 707, in each the rectangular pixels district that defines by scan line 702 and video signal cable 703, two P type thin-film transistors and capacity cell are set, described scanning circuit 704 and signal provision circuit 705 are made of TFT, and drive described tft active matrix display part 707.
In this embodiment, electric current is offered the organic LED element that constitutes pixel, thereby make the organic LED element luminous, and carry out display operation.To provide the electric current source of supply 706 of electric current to be configured to provide electric current to the organic LED element by the transistor on the same substrate of electric current supply line 708 in being formed at tft active matrix display part 707.
In this embodiment, the outside supply voltage DC that provides is provided and provides drive circuit 704 and the common DC-DC change-over circuit 709 of 705 required voltages, and receiving video data, control signal etc., afterwards it is carried out necessary processing, and the common timing control circuit 710 that treated data, control signal etc. offer drive circuit 704 and 705 also is made of TFT according to the present invention, and be integrated on the glass substrate.
In the present embodiment, on the zone of the glass substrate 701 that is in the position outside the tft active matrix display part 707, form the inductor 711 that constitutes by metallic film, thus with it as the element that the compressing image data that provides from the outside is provided.Inductor 711 is connected to comprises normal signal amplifying circuit 712 and be used for data processing circuit the common decompression circuit of packed data decompress(ion).In addition, temporary transient store compressed view data and the general semiconductor memory circuit 713 that adopts when data are carried out decompression processing are made of the TFT that is in data processing circuit position adjacent place, and described TFT is formed in the crystalline semiconductor film.These circuit and memory circuit 713 constitute by the TFT that is formed on the glass substrate.
Figure 33 is by being formed at the inductance element 711 on the display base plate and being formed at the schematic sectional view in the inductance coupling high type non-contact transmission path that another inductance element TL on the substrate 714 that has constituted the transfer of data side system constitutes.
Image data transmission circuit 715 is formed on the system substrate 714 with the inductor 716 with self-inductance L1, inductor 716 and the 711 essentially concentric settings of the inductor with self-inductance L2 that are formed on the display base plate.To transfer to inductor 711 via therebetween mutual inductance from inductor 716 from the signal voltage of image data transmission circuit 715, and amplify the signal voltage that is transmitted by the TFT in the data processing circuit, and it is stored in the memory.
Figure 34 shows a kind of circuit structure, wherein, adopted the lateral bipolar thin-film transistor Q1 that is formed in the crystalline semiconductor film in amplifying circuit 712, described amplifying circuit 712 is electric current amplifier sections of the signal that received by inductor 711 in said system.
In current system, by the electromagnetic coupled (coupling coefficient: k) formed signal transmission path between two inductors 716 respect to one another and 711.In described transmission circuit, be in the scope between 0 to 2mA by changing signal that electric current generates, described signal is provided for transmission equipment side inductor 716.In receiver side inductor 711, only when Isig is in the state of continuous variation, just can produce the electric current that is directly proportional with current changing rate and the coupling coefficient k of Isig.This signal has a few μ A by a small margin, thereby is difficult to by MOS type TFT circuit described signal directly is converted to voltage.
Thereby, as shown in figure 34, adopt the lateral bipolar thin-film transistor Q1 that is formed in the crystalline semiconductor film that signal code is once amplified, and will be converted into voltage through amplified current by cascade MOS thin-film transistor M1 and resistor R d.The voltage of gained is offered amplifying circuit 717, and amplify by it.In Figure 34, R1 and R2 are the resistors that is used for providing to horizontal bipolar TFT Q1 bias current.In this circuit,, thereby transistor Q1 is set to point of normal operation because the amplitude of the electric current that inductor 711 detects is little, thereby provides bias current to horizontal bipolar TFT Q1.In the electric current amplifier section, can adopt the bipolar hybrid transistor of MOS according to the present invention to substitute the lateral bipolar thin-film transistor.For example, when adopting the bipolar mixed film transistor of lateral bipolar thin-film transistor or MOS in the electric current amplifier section, the maximum of these transistorized current amplification factors should be preferably greater than and equal 10.
The waveform that Figure 35 shows the electric current I sig of input signal transmission inductor, flow in the receiving inductance device smaller or equal to the output voltage V out of the little electric current I in of 100 μ A and amplifying circuit.Be appreciated that and carried out the normal signal transmission that comprises the amplification of electric current and voltage thus.As in the present embodiment, in the non-contact type signal transmission system that adopts inductor 711, can survey more low level electric current by the lateral bipolar thin-film transistor that employing is formed in the crystalline semiconductor film.Therefore, the noise margin in the time of can guaranteeing to transmit, and can improve transmission speed.
(the 8th embodiment)
The embodiment relevant with the display base plate that comprises optical receiving circuit
Figure 36 and Figure 37 show according to the display base plate 721 of the eighth embodiment of the present invention and optical receiving circuit 722.Carry out non contact signal transmission by the optical coupling of adopting the optical sensor 723 that forms by (for example) photodiode, rather than carry out by the electromagnetic coupled of capacitive coupling or employing inductor.In this embodiment, adopt the light transmission path (not shown) as transmission means.Optical sensor 723 is integrated on the display base plate 721, substitutes the electromagnetic coupled of capacitive coupling or employing inductor.Figure 37 shows and comprises from the optical sensor current receive signal and to the example of structure of the circuit of described signal code amplified current amplifier section.In this example, described circuit comprises photodiode 723 and the interface circuit 724 that is formed by monocrystalline silicon thin film.Interface circuit 724 have with the 7th embodiment in identical structure.Current signal from photodiode 723 is carried out electric current amplify, and be converted into voltage signal, described voltage signal is offered serial/parallel change-over circuit.
By adopting light, can eliminate the influence of electromagnetic noise as signal transmission means.In addition, by in the importation, adopting lateral bipolar thin-film transistor or the bipolar hybrid transistor of MOS that is formed in the crystalline semiconductor film, can obtain good SN ratio.Thereby, improved transmission speed.Particularly, when adopting when being positioned at the photodiode that the crystal silicon film on the transparent glass substrate forms,, all can receive signal no matter transmission circuit is arranged on the front surface or the rear surface of glass substrate.Therefore, can improve the degree of freedom of installation and design.
(the 9th embodiment)
The embodiment relevant with interface circuit
Figure 38 shows structure and example of structure 802 according to the different signal interface circuit of the signal interface circuit 724 of Figure 34 or embodiments of the invention shown in Figure 37.In this embodiment, the receiver side circuit of the interface circuit of standard LVDS (low voltage differential command) scheme constitutes according to bipolar TFT of the present invention or the transistorized cascade connection type differential amplifier circuit 806 of mixed film by adopting.
Will be from the video data of system side together with control signal (HSYNC, VSYNC, ENABLE SCLOCK) 805 is sent to the standard LDVS transceiver ic (TrIC) 804 that is installed on system's side plate from graphics controller (GCONT) 802 as the 18 parallel-by-bit data 803 of 6 * 3 (corresponding to three kinds of colors of RGB) together.Signal level in this case is the CMOS level of 3.3V.It is the also string conversion of serial data that transceiver ic is carried out 6 parallel-by-bit data conversion of every kind of color, and the input signal that signal level has the amplitude of 3.3V is converted into the differential signal of the low amplitude value with 0.35V, and described differential signal is sent to transmission line 808 from transmission amplifier (LDVS) 807.
Clock signal (SCLOCK) is subjected to multiplied clock and handles and the phase place adjustment in PLL circuit 809, and takes similar mode to export transmission line to from transmission amplifier (clock) 810.
Described transmission line is the balanced type difference transmission lines, it is characterized in that having robustness with respect to external noise.In addition, because the amplitude of transmission signals is the little value of 0.35V, thereby can reduce electromagnetic interference.
On LCD substrate 815, apply the differential signal 808 that is transmitted by terminating resistor (RL) the 816 bidirectional bipolar transistor Q1 of 100 Ω and the base stage 818 of Q2, described bipolar transistor Q1 and Q2 are the structure members of first order amplifier 817, and are formed in the crystalline semiconductor film.First order amplifier 817 is a cascade connection type differential amplifier 806, and it comprises that four bipolar transistor Q1 being formed in the crystalline semiconductor film are to Q4, loading resistor Rc1 and Rc2 and the MOSFET (Q5) that plays a part constant voltage source.Transistor Q1 can be above-mentionedly to be formed at the lateral bipolar thin-film transistor 100 (for example, with reference to Figure 1A and Figure 1B) on the crystallization Si film or to be formed at mixed film transistor 200 (for example, with reference to figure 6 and Fig. 7) on the crystallization Si film to Q4.
Because the voltage spoke value of input signal is little, thereby is difficult to detect such small-signal by the MOS FET with big threshold voltage variation that is formed on the Si film.Thereby generally speaking, conventional first order amplifier has adopted the special-purpose LVDS receiver of making on the Si wafer.
In the present embodiment, differential amplifier 817 is made of the bipolar TFT that is formed in the crystalline semiconductor film.Therefore, the detectivity of input is improved above an order of magnitude.Therefore, the LVDS receiver IC of common employing can be omitted, and the cost of LCD screen board can be reduced effectively.In addition, because like this can be from having the transmitter receipt signal of standard LVDS standard, thereby can adopt general service reflector IC, and needn't make amendment to the system type interface.This point also helps the reduction of cost.
The structure of this circuit also is applicable to Figure 28, Figure 34 and gallon interface 603 and 724 shown in Figure 37.
(the tenth embodiment)
With the relevant embodiment of memory circuit that adopts bipolar TFT
Figure 39 shows the embodiment that employing is particularly effective in display shown in figure 32, be formed at the memory circuit of the bipolar TFT in the crystalline semiconductor film, in described display, provides memory circuit 901 on glass substrate.Memory circuit according to this embodiment relates to static RAM (SRAM) (SRAM), and it is configured to, and each storage element (memorycell) 902 is made of six MOS FET 903.Form memory array by capable storage element 902 of arranged in form n and m row storage element 902 according to matrix.Figure 39 only shows a row storage element 902.Can select a certain row by array selecting signal CSm.In addition, for example, row selection signal is applied to LSn.Correspondingly, select the storage element of n in capable, and output is in the position information of the storage element stored of selecting by pair of data lines D1 and D2.As a result, the electromotive force of data wire D1 and D2 changes.Make output signal move 2Vbe (Vbe is the base-emitter voltage of bipolar TFT) by the level shift circuit 904 that has connected two diodes in it.To be input to the paired difference transistor Q1 of sense amplifier 905 and the base stage of Q2 through the signal of level shift.
Transistor Q1 and Q2 are together with similarly transistor Q3 and Q4 and loading resistor Re1 and Rc2 have constituted cascade connection type differential amplifier 906.To export from Vout907 through amplifying signal, and be entered into the next stage circuit.
When the sense amplifier of memory circuit is made of the aforesaid bipolar TFT that is formed in the crystalline semiconductor film, can detect littler change in voltage under the situation about constituting by MOSFET than sense amplifier.Owing to do not need the fully high spent time of value is arrived in voltage amplification, thereby can carry out zero access.Particularly, under the situation that sense amplifier is made of the MOSFET that is formed on the Si film, the heteropical circuit structure that is used to eliminate threshold voltage is indispensable, thereby needs to carry out the time of the operation of eliminating threshold voltage.Therefore, the store access time becomes very long.Can adopt the bipolar TFT that is formed in the crystalline semiconductor film to address this problem, thereby realize zero access.
In the above-described embodiments, by way of example form is illustrated SRAM.But, under the situation that adopts dynamic ram (DRAM), also can rely on similar structure to obtain same advantageous effects.With regard to DRAM, the electrical potential difference between two data wires surveying diminishes, thereby adopts the bipolar TFT that is formed in the crystalline semiconductor film can obtain the greater role of zero access.
(the 11 embodiment)
Another embodiment that mixes TFT
Figure 40 shows the plane graph pattern that mixes TFT according to another embodiment of the present invention.This TFT is formed on the Si island 268, and the form with level prolongation rectangle in Figure 40 shows described Si island 268.The cross-sectional structure of this embodiment and shown in Figure 7 basic identical.In the plane graph structure of this embodiment, with the similar shown in Fig. 3 A, with base stage contact portion 261 from the base region 103 both side surface draw, and be connected to gate electrode 266.The width of base region 103 is 4 μ m.By this structure, whole base region 103 plays a part the effective coverage of bipolar transistor.Therefore, can improve collector current.
Emitter 262 and collector electrode 263 are formed at the two ends of base region 103.When this mixing TFT operated as MOS transistor, emitter 262 and collector electrode 263 played a part source electrode 264 and drain electrode 265.Grid 266 is formed on the base region 103 via the gate insulating film (not shown).Grid 266 is connected to other elements via gate electrode 269.Reference numeral 271 expression emitter (source electrode) electrodes, 272 expression collector electrode (drain electrode) electrodes.
Figure 41 A shows the curve chart of the Gummel curve of TFT, 18 mixing TFT shown in Figure 40 in parallel in described TFT.Base length Lb is 0.5 μ m.Abscissa among Figure 41 A is represented base-emitter voltage (Vbe), and ordinate is represented base current (Ib) and collector current (Ic).
Figure 41 B shows the collector current (Ic) of mixing TFT 200 and the curve chart of the relation between the current amplification factor hFE.According to the characteristic shown in Figure 41 B, obtained maximum about 200 current amplification factor hFE.
Figure 41 C shows the curve chart of the I/O characteristic of mixing TFT.Wherein, obtained to be fit to be used as the saturation characteristic of current-control type current source.Be appreciated that and also obtained to be applied to the required characteristic of analog circuit.
Figure 42 A shows the base length correlation that (can find) hFE when collector current is 0.1mA from the performance diagram of Figure 41 B.Current amplification factor hFE has the Lb near hFE ∝ with respect to base length Lb -2Correlation.It shows that in base current, recombination current is main.Because hFE has shown high correlation to Lb in this way, thus by reducing base length Lb to improve hFE be effective.Figure 42 B shows the curve chart of the base length correlation of early voltage (VA).
Figure 43 A shows the have different base length cut-off frequency (f of mixing TFT of (0.5 μ m is to 1.5 μ m) with Figure 43 B T) and the collector current correlation of maximum oscillation frequency (fmax).With cut-off frequency (f T) be defined as that to make current gain (h21) be 1 frequency.Maximum oscillation frequency (fmax) is defined as to make maximum available power gain (MAG) and Mason unilateral gain (U) be 1 frequency.
Maximum available power gain (MAG) is the power gain under the situation of the impedance matching of input side and the equal performer of outlet side.Mason unilateral gain (U) is to reduce to the power gain that obtains when zero neutralizing circuit (neutralizingcircuit) is carried out the unilateralization processing by in fact providing to make from the backward gain that outputs to input.
MAG is provided by following formula
MAG＝|S 21/S 12|(k-(k 2-1) 0.5)
Wherein, k is called as " stabilisation coefficient ", and it is by following formula definition
k＝(1+|S 11S 11-S 12S 21| 2-|S 11| 2-|S 22| 2)/2|S 12S 21|。
U is provided by following formula
U＝(|S 21/S 12-1| 2/2)/(k|S 21/S 12|-Re(S 21/S 12))
＝MAG|S 21/S 12-1| 2/|S 21/S 12-MAG| 2。
Be appreciated that when the MAG=1 U=1 from above-mentioned equation.Therefore, no matter in the middle of MAG and the U which is used for assessment, all can obtain fmax.
In above-mentioned equation, S 11, S 12, S 21And S 22Be 4-terminal scattering (S) parameter of mixing TFT, and be the value that adopts vector network analyzer to record.
With regard to the device that base length is 0.5 μ m,, under the condition of collector current=1mA (≈ 14 μ A/ μ m), obtained f at base-emitter voltage=3V T=2GHz, fmax=5.2GHz.
Figure 43 C shows cut-off frequency (f T) and the curve chart of the base length correlation of maximum oscillation frequency (fmax).Cut-off frequency (f T) and maximum oscillation frequency (fmax) increase along with the reduction of base length.In order to realize better high-frequency characteristic, importantly reduce base length Lb.With regard to each value of base length, maximum oscillation frequency (fmax) is the value that is in the GHz magnitude, and it is for being sufficiently high a value at tens MHz to the application in the high-frequency circuit of hundreds of MHz.
In order to adopt above-mentioned TFT to design to be used for the circuit of high-frequency operation, must derive equivalent electric circuit from admittance (Y) parameter of device.
In the curve chart shown in Figure 44 A and Figure 44 B, be that the S measured value of parameters of the mixing TFT of 0.5 μ m transforms for Y parameter with base length, and it be depicted as curve with respect to frequency.Figure 44 A shows the absolute value of Y parameter.Figure 44 B shows the phase place of Y parameter.In these figure, such as the symbolic representation measured value of " ", " zero ", "  " and " Δ ".Solid line has been represented based on parallel connection the calculated value of the device model of bipolar transistor and MOS transistor, and this device model is shown in Figure 44 C.Be appreciated that based on the calculated value of described device model basic consistent with measured value.
Figure 44 D and Figure 44 E show the equivalent electric circuit of bipolar transistor shown in Figure 44 C and MOS transistor.Figure 44 D is the equivalent circuit diagram that plays a part the part of bipolar transistor.Figure 44 E is the equivalent circuit diagram that plays a part the part of MOS transistor.Can reproduce the measured value of Y parameter well by selecting suitable parameter value.Thereby, be appreciated that the device model shown in Figure 44 C can advantageously be applied to adopt the breadboardin that mixes TFT.
(the 12 embodiment)
Another embodiment relevant with the receiver side circuit of LVDS interface circuit
Figure 45 A shows another the relevant embodiment of receiver side circuit with the LVDS interface circuit of display unit shown in Figure 38, and it is constituted by above-mentioned mixing TFT and MOSFET's.This circuit is a differential amplifier circuit 924, it comprises the current source load 917 that is made of a pair of P type MOS-FET M3 and M4, by a pair of above-mentioned mixed film transistor (M1, Q1) and (M2, Q2) transistor 921 of Gou Chenging and the constant current source 923 that constitutes by N type MOS-FET M5.
Transmission line 910 is the balanced type difference transmission lines, it is characterized in that having robustness with respect to external noise.In addition, because the amplitude of transmission signals is the little value of 0.30V, thereby can reduce electromagnetic interference.Can by make ± terminating resistor (RL) 916 that the electric current of 3mA flows through 50 Ω generates differential signal voltage, the differential signal voltage that is generated is applied to the base stage 918 of mixing TFT Q1 and Q2, described mixing TFT Q1 and Q2 are the structure members of differential amplifier circuit 924, and are formed in the crystalline semiconductor film.The output of first order amplifier is further amplified by the buffer amplifier that is made of CMOS phase inverter 920, and it is promoted to certain level, makes it possible to handle described output by the TFT in the LCD screen board.
Figure 45 B shows the curve chart of the input and output signal waveform of the interface circuit shown in Figure 45 A.Frequency is 50MHz.Under the situation that does not influence waveform, the input voltage of general ± 0-15V is amplified to the amplitude of about 4V.
Figure 45 C shows the plan view layout of the interface circuit shown in Figure 45 A.Interface circuit is arranged in the area of 200 μ m * 250 μ m, thereby described interface circuit can be arranged on the marginal portion of LCD substrate just.
In the plan view layout shown in Figure 45 C, for example, the left side transistor M1 and the Q1 of the driving transistors 921 shown in Figure 45 A is arranged in the first order piece 930.The left side transistor M3 of current loading 917 is arranged in the second level piece 931.The right side transistor M4 of current loading 917 is arranged in the third level piece 932.The right side transistor M2 and the Q2 of driving transistors 921 are arranged in the fourth stage piece 933.In each level, 3 * 6=18 TFT in parallel.The N type MOS-TFT M5 of constant current source 923 is arranged in the left side block 934 of Figure 45 C.Constant current source 923 is configured to 3 * 2=6 TFT parallel connection.
To be input to Vin+940 and Vin-941 from the input signal of the transmission line among Figure 45 A 910, export to its amplification and from Vo942 afterwards.
Because the voltage spoke value of input signal is little in this differential transfer system, thereby is difficult to detect such small voltage signal by the MOS FET with big threshold voltage variation that is formed on the Si film.Thereby generally speaking, conventional first order amplifier has adopted the special-purpose LVDS receiver of making on the Si wafer.
In the present embodiment, differential amplifier 817 is made of the mixing TFT that is formed in the crystalline semiconductor film.Therefore, the detectivity of input is improved above an order of magnitude.Therefore, the LVDS receiver IC of common employing can be omitted, and the cost of LCD screen board can be reduced effectively.In addition, because like this can be from having the transmitter receipt signal of standard LVDS standard, thereby can adopt general service reflector IC, and needn't make amendment to system-side interface.This point also helps the reduction of cost.
The present invention can be applied to the image display device of personal digital assistant device or mobile phone or be used for image display device such as the information equipment of personal computer.

Claims (21)

1. electronic installation that comprises a plurality of semiconductor device, described a plurality of semiconductor device is to utilize semiconductor film film formed and be formed in the described semiconductive thin film, described semiconductive thin film is provided on the dielectric substrate and along the predetermined direction crystallization, described a plurality of semiconductor device comprise:
MOS transistor; And
At least a in the bipolar mixed film transistor of lateral bipolar thin-film transistor and MOS.
2. display unit that comprises a plurality of semiconductor device, described a plurality of semiconductor device are to utilize semiconductor film film formed and be formed in the described semiconductive thin film, and described semiconductive thin film is provided on the dielectric substrate and along the predetermined direction crystallization,
It is characterized in that described display unit comprises the current-mode signal input interface circuit with two current values or two or more current values, and
Described current-mode signal input interface circuit comprises:
Thin-film transistor, described thin-film transistor be utilize film formed at least one the lateral bipolar thin-film transistor of described semiconductor film and at least one mixed film transistorized at least any; And
At least one utilizes the film formed MOS transistor of described semiconductor film.
3. display unit that comprises a plurality of semiconductor device, described a plurality of semiconductor device is to utilize semiconductor film film formed and be formed in the described semiconductive thin film, described semiconductive thin film is provided on the dielectric substrate and along the predetermined direction crystallization, described display unit comprises voltage differential signal type signal input interface circuit
It is characterized in that described voltage differential signal type signal input interface circuit comprises:
Thin-film transistor, described thin-film transistor be utilize film formed at least one the lateral bipolar thin-film transistor of described semiconductor film and at least one mixed film transistorized at least any; And
At least one utilizes the film formed MOS transistor of described semiconductor film.
4. display unit that comprises a plurality of semiconductor device, described a plurality of semiconductor device is to utilize semiconductor film film formed and be formed in the described semiconductive thin film, described semiconductive thin film is provided on the dielectric substrate and along the predetermined direction crystallization, described display unit comprises the signal input interface circuit of noncontact electromagnetic coupled transmission plan
The signal input interface circuit that it is characterized in that described noncontact electromagnetic coupled transmission plan comprises:
Thin-film transistor, described thin-film transistor be utilize film formed at least one the lateral bipolar thin-film transistor of described semiconductor film and at least one mixed film transistorized at least any; And
At least one utilizes the film formed MOS transistor of described semiconductor film.
5. display unit that comprises a plurality of semiconductor device, described a plurality of semiconductor device is to utilize semiconductor film film formed and be formed in the described semiconductive thin film, described semiconductive thin film is provided on the dielectric substrate and along the predetermined direction crystallization, described display unit comprises the signal input interface circuit of non-contact optical transmission plan
The signal input interface circuit that it is characterized in that described non-contact optical transmission plan comprises:
At least one photo-electric conversion element;
Thin-film transistor, described thin-film transistor be utilize film formed at least one the lateral bipolar thin-film transistor of described semiconductor film and at least one mixed film transistorized at least any; And
At least one utilizes the film formed MOS transistor of described semiconductor film.
6. display unit that comprises a plurality of semiconductor device, described a plurality of semiconductor device is to utilize semiconductor film film formed and be formed in the described semiconductive thin film, described semiconductive thin film is provided on the dielectric substrate and along the predetermined direction crystallization, described display unit comprises memory circuit, level shift circuit unit and sense amplifier unit, described memory circuit comprises a plurality of storage elements unit
It is characterized in that described sense amplifier unit comprises:
Thin-film transistor, described thin-film transistor be utilize film formed at least one the lateral bipolar thin-film transistor of described semiconductor film and at least one mixed film transistorized at least any; And
At least one utilizes the film formed MOS transistor of described semiconductor film.
7. display unit that comprises a plurality of semiconductor device, described a plurality of semiconductor device is to utilize semiconductor film film formed and be formed in the described semiconductive thin film, described semiconductive thin film is provided on the dielectric substrate and along the predetermined direction crystallization, described display unit comprises one of memory circuit of DC-DC converter circuit, timing control circuit, signal amplification circuit, the decompression circuit that is used for depressurizing compression data and storing image data, and each of described circuit comprises:
The MOS thin-film transistor; And
At least a in the bipolar mixed film transistor of lateral bipolar thin-film transistor and MOS.
8. according to each the described display unit in the claim 2 to 4, comprise a plurality of semiconductor device, described a plurality of semiconductor device is to utilize semiconductor film film formed and be formed in the described semiconductive thin film, described semiconductive thin film is provided on the dielectric substrate and along the predetermined direction crystallization
It is characterized in that signal input circuit comprises:
Adopted the current amplification unit of thin-film transistor, described thin-film transistor be utilize the film formed lateral bipolar thin-film transistor of described semiconductor film and mixed film transistorized at least any; And
The voltage amplification unit, it is connected to described current amplification unit and has adopted and utilized the film formed MOS transistor of described semiconductor film.
9. according to each the described display unit in the claim 2 to 4, comprise a plurality of semiconductor device, described a plurality of semiconductor device is to utilize semiconductor film film formed and be formed in the described semiconductive thin film, described semiconductive thin film is provided on the dielectric substrate and along the predetermined direction crystallization
It is characterized in that signal input circuit comprises the differential amplifier circuit of cascade, disposing described differential amplifier circuit makes load transistor and two lateral bipolar thin-film transistors or two the transistorized set of devices of mixed film comprise series connection successively and the load transistor that comprises series connection successively and two lateral bipolar thin-film transistors or two transistorized set of devices of mixed film be connected in parallel, one of two set of devices in parallel are connected to power supply, another group of two set of devices in parallel is via MOSFET ground connection, and described MOSFET plays the effect of constant current source.
10. according to each described display unit of claim 2 to 7, the minimum value that it is characterized in that described lateral bipolar thin-film transistor or the transistorized base length of described mixed film is 2 μ m or littler.
11. each described display unit according to claim 2 to 7, the minimum value that it is characterized in that described lateral bipolar thin-film transistor or the transistorized base width of the bipolar mixed film of described MOS is 2 μ m or littler, and the minimum value of the grid length of described MOS transistor is 1 μ m or littler.
12., it is characterized in that the maximum of described lateral bipolar thin-film transistor or the transistorized current amplification factor of the bipolar mixed film of described MOS is 10 or bigger according to each described display unit of claim 2 to 7.
13. each described display unit according to claim 2 to 7, the maximum that it is characterized in that described lateral bipolar thin-film transistor or the transistorized current amplification factor of the bipolar mixed film of described MOS is 10 or bigger, and the maximum of the field-effect mobility of described MOS transistor is 350cm 2/ Vs or bigger.
14. electronic installation according to claim 1 or according to each described display unit of claim 2 to 7, it is characterized in that described predetermined direction be the crystallization non-single crystal semiconductor film laterally.
15. an interface circuit is characterized in that comprising:
Be provided in the semiconductive thin film on the dielectric substrate;
Be provided in the crystal region in the described semiconductive thin film;
Be provided in the thin-film transistor in the described crystal region, described thin-film transistor is at least a in lateral bipolar thin-film transistor and the mixed film transistor; And
Be provided in the described crystal region and be connected to the MOS thin-film transistor of described thin-film transistor.
16. an electronic installation that comprises a plurality of semiconductor device, described a plurality of semiconductor device are to utilize semiconductor film film formed and be formed in the described semiconductive thin film, described semiconductive thin film is provided on the dielectric substrate and along the predetermined direction crystallization,
It is characterized in that described a plurality of semiconductor device comprises at least a in the bipolar mixed film transistor of MOS transistor and lateral bipolar thin-film transistor and MOS, and
The bipolar mixed film transistor of described lateral bipolar thin-film transistor or MOS has the function that detects little electric current and described little current conversion is become curtage.
17. a display unit that comprises a plurality of semiconductor device, described a plurality of semiconductor device are to utilize semiconductor film film formed and be formed in the described semiconductive thin film, described semiconductive thin film is provided on the dielectric substrate and along the predetermined direction crystallization,
It is characterized in that described display unit comprises the imported signal interface circuit of difference, and
The imported signal interface circuit of described difference comprises and utilizes one of film formed at least one pair of the lateral bipolar thin-film transistor of described semiconductor film and at least one pair of mixed film transistor and at least one pair of to utilize the film formed MOS transistor of described semiconductor film.
18. a display unit that comprises a plurality of semiconductor device, described a plurality of semiconductor device are to utilize semiconductor film film formed and be formed in the described semiconductive thin film, described semiconductive thin film is provided on the dielectric substrate and along the predetermined direction crystallization,
It is characterized in that signal input circuit is a differential amplifier circuit, it comprises:
The current mirror type current source that constitutes by a pair of P type MOS transistor;
Be connected respectively to a pair of mixed film transistor of the drain terminal of the described a pair of P type MOS transistor that constitutes described current source; And
Be connected to the transistorized public source terminal of described a pair of mixed film and as the N type MOS transistor of constant current source work.
19., it is characterized in that the transistorized maximum oscillation frequency of described mixed film is higher than 2GHz according to claim 17 or 18 described display unit.
20. differential amplifying device that comprises a plurality of semiconductor device, described a plurality of semiconductor device is to utilize semiconductor film film formed and be formed in the described semiconductive thin film, described semiconductive thin film is provided on the dielectric substrate and along the predetermined direction crystallization, described differential amplifying device comprises the imported signal interface circuit of difference
It is characterized in that the imported signal interface circuit of described difference comprises:
Utilize one of film formed at least one pair of the lateral bipolar thin-film transistor of described semiconductor film and at least one pair of mixed film transistor; And
Utilize film formed at least one pair of MOS transistor of described semiconductor film.
21. a differential amplifying device that comprises a plurality of semiconductor device, described a plurality of semiconductor device are to utilize semiconductor film film formed and be formed in the described semiconductive thin film, described semiconductive thin film is provided on the dielectric substrate and along the predetermined direction crystallization,
It is characterized in that signal input circuit is a differential amplifier circuit, it comprises:
The current mirror type current source that constitutes by a pair of P type MOS transistor;
Be connected respectively to a pair of mixed film transistor of the drain terminal of the described a pair of P type MOS transistor that constitutes described current source; And
Be connected to the transistorized public source terminal of described a pair of mixed film and as the N type MOS transistor of constant current source work.
CNA200710141657XA 2006-08-18 2007-08-17 Electronic device, display device, interface circuit and differential amplification device, which are constituted by using thin-film transistors Pending CN101140940A (en)

Applications Claiming Priority (3)

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JP223310/2006 2006-08-18
JP197893/2007 2007-07-30

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2020140790A1 (en) * 2019-01-04 2020-07-09 京东方科技集团股份有限公司 Pixel structure for flat panel detector, flat panel detector, and image capturing system
CN112313798A (en) * 2018-06-25 2021-02-02 索尼半导体解决方案公司 Circuit board, semiconductor device and electronic apparatus

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0616371A2 (en) * 1993-03-18 1994-09-21 Canon Kabushiki Kaisha Silicon on insulator semiconductor device and its fabrication method
JPH06267970A (en) * 1993-03-15 1994-09-22 Toshiba Corp Semiconductor device
CN1101167A (en) * 1993-05-26 1995-04-05 株式会社半导体能源研究所 Semiconductor device and fabrication method of the same

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06267970A (en) * 1993-03-15 1994-09-22 Toshiba Corp Semiconductor device
EP0616371A2 (en) * 1993-03-18 1994-09-21 Canon Kabushiki Kaisha Silicon on insulator semiconductor device and its fabrication method
CN1101167A (en) * 1993-05-26 1995-04-05 株式会社半导体能源研究所 Semiconductor device and fabrication method of the same

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112313798A (en) * 2018-06-25 2021-02-02 索尼半导体解决方案公司 Circuit board, semiconductor device and electronic apparatus
CN112313798B (en) * 2018-06-25 2024-04-16 索尼半导体解决方案公司 Circuit board, semiconductor device, and electronic apparatus
WO2020140790A1 (en) * 2019-01-04 2020-07-09 京东方科技集团股份有限公司 Pixel structure for flat panel detector, flat panel detector, and image capturing system
US11221422B2 (en) 2019-01-04 2022-01-11 Beijing Boe Optoelectronics Technology Co., Ltd. Pixel structure of flat panel detection device, flat panel detection device and camera system

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