JP2008034633A - Semiconductor device, and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device with which electromigration or stress-induced void is suppressed and which exhibits a high connection reliability, and to provide its manufacturing method. <P>SOLUTION: The semiconductor device includes an insulating film 10 which has a concave (wiring groove 10a) formed in a semiconductor substrate, a barrier metal film 12 which is formed in such a way that it covers the inner wall of the wiring groove 10a, a conductive film 14 which is formed on the barrier metal 12 in the wiring groove 10a, a wiring film 16 which is formed on the conductive film 14 in the wiring groove 10a, and a metal cap film 18 which is selectively formed on the top of the wiring film 16 and the conductive film 14. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor device having a metal cap film on a wiring film and a method for manufacturing the same.

  As a conventional method for manufacturing a semiconductor device, for example, there is one described in Patent Document 1. FIG. 10 shows a method for manufacturing the semiconductor device described in this document.

  First, a recess is formed in the insulating film 142 formed on the semiconductor substrate 140. An adhesive layer 144 and a first barrier metal film 146 are sequentially formed on the inner wall of the recess, and a metal film 148 such as copper is formed so as to fill the recess. Then, an insulating film 150 is formed so as to cover the entire surface of the insulating film 142 (FIG. 10A).

Next, an opening 152 is formed so that the upper surface of the metal film 148 is exposed on the bottom surface (FIG. 10B). Then, a metal cap film 154 is formed on the upper surface of the metal film 148 by electroless plating (FIG. 10C). Thereafter, a semiconductor device is manufactured according to a normal process.
US Pat. No. 6,180,523

  However, in the manufacturing method described in Patent Document 1, when misalignment occurs when the opening 152 is formed, a portion that is not covered with the metal cap film 154 is generated at the end of the metal film 148. That is, since the metal cap film 154 is selectively formed only on the surface of the metal film 148 exposed by the opening 152, the margin for misalignment is small, and the metal film 148 and the insulating film 150 are directly formed by misalignment. I had contact. For this reason, the metal constituting the metal film 148 diffuses into the insulating film 150 at this location, thereby causing electromigration and stress-induced voids, which may reduce connection reliability.

  Further, in the wiring structure of the semiconductor device as shown in FIG. 6, electromigration and stress-induced voids occur in the recess 116a at the end of the wiring film 116 that is not covered with the metal cap film 118, and connection reliability is improved. There was a decline. A method for manufacturing the wiring structure in the semiconductor device shown in FIG. 6 will be described below with reference to FIG. 7 which is a process diagram and FIGS. 8 and 9 which are process cross-sectional views.

  First, as shown in FIG. 8A, a wiring groove 110a is formed in an insulating film 110 formed on a semiconductor substrate (not shown) (step S11). Then, as shown in FIG. 8B, a barrier metal film 124 is formed on the entire surface of the insulating film 110, and a Cu seed film 128 is further formed on the barrier metal film 124 (step S12). Subsequently, as shown in FIG. 8C, the entire surface of the insulating film 110 is covered with a wiring film 130 containing Cu or the like (step S13).

  Next, as shown in FIG. 9A, the unnecessary wiring film 130 and barrier metal film 124 formed outside the wiring groove 110a are removed by chemical mechanical polishing (CMP) to form wiring. The wiring film 116 and the barrier metal film 112 are left only in the trench 110a (step S14). At this time, the end portion of the upper surface of the wiring film 116 in contact with the barrier metal film 112 is etched by the CMP slurry, and a recess 116a is formed.

  Subsequently, as shown in FIG. 9B, a metal cap film 118 is formed on the upper surface of the wiring film 116 (step S15). Since the recess 116a is formed at the end of the upper surface of the wiring film 116, the metal cap film 118 is not formed in the recess 116a. Then, as shown in FIG. 9C, the first insulating film 120 and the second insulating film 122 are sequentially formed so as to cover the entire surface of the insulating film 110 (step S16). Then, a semiconductor device is manufactured by a normal process.

  In the manufacturing method of the semiconductor device having such a process, the recess 116a is not covered with the metal cap film 118, and the wiring film 116 and the first insulating film 120 are in direct contact with each other at this location. That is, in the case shown in FIGS. 6 to 9 as well, the metal cap film 118 is selectively formed only on the surface of the wiring film 116 as described above. A surface of the wiring film 116 not covered with the cap film 118 is generated. Therefore, a metal such as Cu constituting the wiring film 116 diffuses into the first insulating film 120, causing electromigration and stress-induced voids, and connection reliability may be reduced.

  The semiconductor device of the present invention includes an insulating film having a recess formed on a semiconductor substrate, a barrier metal film formed to cover an inner wall of the recess, and a conductive film formed on the barrier metal film in the recess. And a wiring film formed on the conductive film in the recess, and a metal cap film selectively formed on the wiring film and the upper surface of the conductive film.

  The semiconductor device of the present invention has a metal cap film selectively formed on the upper surface of the wiring film and the conductive film. That is, since the upper surface of the wiring film is reliably covered without being affected by the surface shape of the wiring film such as a recess, diffusion of the metal constituting the wiring film can be suppressed. Therefore, electromigration and stress-induced voids are suppressed, and the connection reliability of the semiconductor device is improved.

  The method for manufacturing a semiconductor device of the present invention includes a step of forming a recess in an insulating film formed on a semiconductor substrate, a step of forming a barrier metal film on an inner wall of the recess and an upper surface of the insulating film, and the insulation Forming a conductive film on the upper surface of the film and the surface of the barrier metal film in the recess, forming a wiring film on the insulating film so as to fill the recess, and the barrier metal outside the recess Forming a metal cap film in a self-aligning manner on the upper surface of the wiring film and the conductive film in which the recess is embedded, by removing the film, the conductive film, and the wiring film by polishing, and by electroless plating And a step of performing.

  According to the method for manufacturing a semiconductor device of the present invention, a conductive film is formed between a barrier metal film and a wiring film, and a metal cap film is formed in a self-aligning manner so as to cover the wiring film and the conductive film by electroless plating. Is done. In other words, it is possible to reliably cover the surface of the wiring film without considering a margin for misalignment, etc., so that it is possible to suppress electromigration and stress-induced voids due to diffusion of the metal constituting the wiring film. The connection reliability of the semiconductor device is improved.

  According to the present invention, it is possible to provide a semiconductor device in which electromigration and stress-induced voids are suppressed and connection reliability is improved, and a manufacturing method thereof.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In all the drawings, the same reference numerals are given to the same components, and the description will be omitted as appropriate.

(First embodiment)
FIG. 1 is a cross-sectional view showing the wiring structure of the semiconductor device according to the first embodiment.
As shown in FIG. 1, the wiring structure of the first embodiment is formed so as to cover an insulating film 10 having a recess (wiring groove 10a) formed on a semiconductor substrate (not shown) and an inner wall of the wiring groove 10a. Formed on the barrier metal film 12, the conductive film 14 formed on the barrier metal film 12 in the wiring groove 10 a, the wiring film 16 filling the wiring groove 10 a, and the upper surface of the wiring film 16 and the conductive film 14. Metal cap film 18. Further, a first insulating film 20 and a second insulating film 22 are sequentially stacked so as to cover the insulating film 10 and the metal cap film 18.

  In this embodiment, as the barrier metal film 12, a tantalum-based barrier metal film in which Ta and TaN are sequentially stacked can be used. The wiring film 16 can be a metal film containing Cu as a main component, and may contain impurities such as Al. The first insulating film 20 can use SiN, SiCN, or the like, and the second insulating film 22 can use SiON or the like.

  As the conductive film 14 and the metal cap film 18, a metal film containing one or more metals selected from the group consisting of Ni, Co, Pd, Pt, Au, Ag, Ru, and alloys thereof can be used. A metal film containing one or more metals selected from the group consisting of Co, Pd, and alloys thereof can be used. The metals constituting the conductive film 14 and the metal cap film 18 may be the same or different.

  Specific examples of the constituent material of the metal cap film 18 include cobalt-containing metals such as Co, CoWP, CoWB, CoB, and CoP; nickel-containing metals such as Ni, NiMoP, NiMoB, NiWP, NiWB, NiReP, NiReB, NiB, and NiP. Metal: Silver-containing metals such as Ag and AgCu can be exemplified. In the present embodiment, the conductive film 14 can be made of Ni, Co, or an alloy thereof. On the other hand, the metal cap film 18 can be made of CoWP or NiWP. These metal materials may be any combination. By using such a metal material, the conductive film 14 and the metal cap film 18 are excellent in adhesion.

  In the present embodiment, the film thickness a of the barrier metal film 12 can be 5 nm to 20 nm, and the film thickness b of the conductive film 14 can be 5 nm to 20 nm. These film thicknesses are extremely smaller than the film thickness c of the wiring film 16. The film thickness d of the metal cap film 18 can be 5 nm or more and 20 nm or less. In the present embodiment, the barrier metal film 12 is about 15 nm thick, the conductive film 14 is about 15 nm thick, and the metal cap film 18 is about 15 nm thick.

  The metal cap film 18 is provided in a self-aligned manner as will be described later, and is formed only on the upper surfaces of the wiring film 16 and the conductive film 14. It may be formed. However, from the viewpoint of suppressing the occurrence of TDDB (Time Dependent Dielectric Breakdown) or the like, it is preferably not formed on the upper surface of the insulating film 10.

  In the present embodiment, a recess (gap) may be formed at the upper end portion of the wiring film 16 in contact with the conductive film 14. Also in this case, since the metal cap film 18 embeds the recess and is selectively formed on the upper surfaces of the conductive film 14 and the wiring film 16, the wiring film 16 and the first insulating film 20 are in direct contact with each other at the recess portion. This can be suppressed.

  1 will be described with reference to the process diagram of FIG. 2 and the process cross-sectional views of FIGS.

  The semiconductor device manufacturing method according to the present embodiment includes a step (step S1) of forming a recess (wiring groove 10a) in an insulating film 10 formed on a semiconductor substrate (not shown), an inner wall of the wiring groove 10a, and an insulating film. A step of forming a barrier metal film 24 on the upper surface of the insulating film 10 (step S2), a step of forming a conductive film 26 on the upper surface of the insulating film 10 and the surface of the barrier metal film 24 in the wiring trench 10a (step S3), The step of forming the wiring film 30 on the insulating film 10 so as to fill the wiring groove 10a (step S4), and the barrier metal film 24, the conductive film 26, and the wiring film 30 outside the wiring groove 10a are removed by polishing. A metal cap film 18 is formed in a self-aligned manner on the upper surfaces of the wiring film 16 and the conductive film 14 in which the wiring groove 10a is embedded by the process (step S5) and electroless plating. Including the step of forming (step S6), and forming a first insulating film 20 and the second insulating film 22 in this order so as to cover the insulating film 10 over the entire surface (the step S7).

Hereinafter, it demonstrates along each process.
First, as shown in FIG. 3A, a wiring groove 10a is formed in the insulating film 10 formed on a semiconductor substrate (not shown) (step S1). Specifically, after forming the insulating film 10, a resist film (not shown) patterned in a predetermined shape is provided thereon, and the insulating film 10 is etched to form the wiring trench 10a.

  Then, as shown in FIG. 3B, a barrier metal film 24 is formed on the entire surface of the insulating film 10 (step S2), and a conductive film 26 and a seed film 28 are sequentially formed on the barrier metal film 24 (step S3). ). Specifically, a tantalum-based barrier metal film in which Ta and TaN are laminated in this order is formed on the entire surface of the substrate by a normal sputtering method, and a conductive film 26 and a seed film 28 are further formed in order. The conductive film 26 only needs to be formed from the upper surface of the insulating film 10 to the opposite side surfaces in the wiring trench 10a. As the seed film 28, a metal film containing Cu can be used. The conductive film 26 includes one or more metals selected from the group consisting of Ni, Co, Pd, Pt, Au, Ag, Ru, and alloys thereof as described above.

Subsequently, as shown in FIG. 3C, the wiring film 30 is formed so as to cover the entire surface of the insulating film 10, and the wiring groove 10a is embedded with the wiring film 30 (step S4).
Next, unnecessary barrier metal film 24, conductive film 26, and wiring film 30 formed outside the wiring trench 10a are removed by chemical mechanical polishing (CMP), and FIG. As shown, the barrier metal film 12, the conductive film 14, and the wiring film 16 are left only in the wiring groove 10a (step S5).

  Subsequently, as shown in FIG. 4B, a metal cap film 18 is formed on the upper surfaces of the conductive film 14 and the wiring film 16 (step S6). The metal cap film 18 can be formed on the upper surfaces of the conductive film 14 and the wiring film 16 in a self-aligning manner by an electroless plating method. Specifically, the metal cap film 18 is formed by electroless plating using a plating solution containing dimethylaminoborane or hydrazine as a reducing agent. Examples of the constituent material of the metal cap film 18 include a cobalt-containing metal such as CoWP, a nickel-containing metal such as NiWP, and a silver-containing metal such as AgCu.

  Then, as shown in FIG. 4C, the first insulating film 20 and the second insulating film 22 are sequentially formed so as to cover the entire surface of the insulating film 10 (step S7). Furthermore, a semiconductor device is manufactured by a normal process.

Hereinafter, effects of the semiconductor device according to the present embodiment will be described.
According to the semiconductor device having the wiring structure as in the present embodiment, the metal cap film 18 is selectively formed on the upper surfaces of the wiring film 16 and the conductive film 14. Thereby, even if a recess or the like occurs in the wiring film 16, the metal cap film 18 is formed so as to embed the recess, so that the upper surface of the wiring film 16 is reliably covered, and the metal constituting the wiring film 16 is the first metal. It is possible to suppress diffusion into the insulating film 20. Therefore, electromigration and stress-induced voids are suppressed, and the connection reliability of the semiconductor device is improved.

  In the semiconductor device of the present embodiment, the conductive film 14 includes one or more metals selected from the group consisting of Ni, Co, Pd, Pt, Au, Ag, Ru, and alloys thereof. Can do. Furthermore, the metal constituting the metal cap film 18 can be configured to include one or more metals selected from the above metals. By such a combination of the conductive film 14 and the metal cap film 18, electromigration and stress-induced voids can be more effectively suppressed.

  As shown in FIG. 9A of the semiconductor device process sectional view for explaining the problem of the present invention, the upper end of the wiring film 116 in contact with the barrier metal film 112 made of Ta / TaN by the CMP slurry used in the CMP process. The portion is etched to form a recess 116a. It is considered that chemically stable tantalum oxide is formed on the surface of Ta in the recess 116a. In the vicinity of the surface of the tantalum oxide, the reduction reaction of Co or the like does not occur, so it is assumed that the recess 116a is not covered with the metal cap film 118.

  On the other hand, in this embodiment, even if the upper end portion of the wiring film 16 in contact with the conductive film 14 is etched by the CMP slurry, even if the recess is formed, since the conductive film 14 is included, it is affected by the recess. The metal cap film 18 can be selectively formed on the surfaces of the conductive film 14 and the wiring film 16. That is, even if a recess is formed in the wiring film 16, the upper surface of the wiring film 16 can be reliably covered, and electromigration and stress-induced voids can be more effectively suppressed.

(Second Embodiment)
FIG. 5 is a sectional view showing a wiring structure of the semiconductor device according to the second embodiment.
As shown in FIG. 5, the semiconductor device of the second embodiment has the same configuration as that of the semiconductor device of the first embodiment except that the first insulating film 20 having the function of an etching stopper film is not formed. Also in the second embodiment, the same effects as those of the first embodiment can be obtained, and further, the following effects can be obtained.

  In the second embodiment, the second insulating film 22 is provided with a via hole exposing the upper surface of the metal cap film 18 to the bottom surface, and then a via plug is formed in the via hole to form a wiring structure. Therefore, as shown in FIG. 6, when there is a recess 116a that is not covered with the metal cap film 118, if misalignment occurs when the via hole is formed by etching, the etching stopper film as in the present embodiment. If the first insulating film having the above function is not formed, the wiring film 116 is also etched. For this reason, the connection reliability of the semiconductor device is significantly reduced.

  On the other hand, according to the semiconductor device of this embodiment, there is no upper surface of the wiring film 16 that is not covered with the metal cap film 18. Therefore, even if misalignment occurs when the via hole is formed by etching, the wiring film 16 is not etched even if the first insulating film 20 having the function of an etching stopper film is not formed. Does not affect connection reliability.

As mentioned above, although embodiment of this invention was described with reference to drawings, these are the illustrations of this invention, Various structures other than the above are also employable.
For example, the conductive film 14 may be formed of two or more layers.

It is sectional drawing which shows the structure of the semiconductor device in 1st Embodiment of this invention. It is process drawing which shows the manufacturing procedure of the semiconductor device in 1st Embodiment of this invention. It is process sectional drawing which shows the manufacturing procedure of the semiconductor device in 1st Embodiment of this invention. It is process sectional drawing which shows the manufacturing procedure of the semiconductor device in 1st Embodiment of this invention. It is sectional drawing which shows the structure of the semiconductor device in 2nd Embodiment of this invention. It is sectional drawing which shows the structure of the semiconductor device explaining the subject of this invention. It is process drawing which shows the manufacturing procedure of the semiconductor device explaining the subject of this invention. It is process sectional drawing which shows the manufacturing procedure of the semiconductor device explaining the subject of this invention. It is process sectional drawing which shows the manufacturing procedure of the semiconductor device explaining the subject of this invention. It is process sectional drawing which shows the manufacturing procedure of the conventional semiconductor device.

Explanation of symbols

10, 110 Insulating film 10a, 110a Wiring groove 12, 112 Barrier metal film 14 Conductive film 16, 116 Wiring film 116a Recess 18, 118 Metal cap film 20, 120 First insulating film 22, 122 Second insulating film 24, 124 Barrier Metal film 26 Conductive film 28, 128 Seed film 30, 130 Wiring film

Claims (13)

An insulating film having a recess formed on the semiconductor substrate;
A barrier metal film formed to cover the inner wall of the recess,
A conductive film formed on the barrier metal film in the recess;
A wiring film formed on the conductive film in the recess;
A metal cap film selectively formed on the upper surface of the wiring film and the conductive film;
A semiconductor device comprising: The semiconductor device according to claim 1,
The semiconductor device, wherein the wiring film contains Cu. The semiconductor device according to claim 1 or 2,
The semiconductor device, wherein the conductive film contains one or more metals selected from the group consisting of Ni, Co, Pd, Pt, Au, Ag, Ru, and alloys thereof. The semiconductor device according to claim 3.
The semiconductor device, wherein the metal cap film includes one or more metals selected from the group consisting of Ni, Co, Pd, Pt, Au, Ag, Ru, and alloys thereof. The semiconductor device according to claim 3.
The semiconductor device, wherein the metal cap film includes one or more metals selected from the group consisting of Ni, Co, Pd, and alloys thereof. The semiconductor device according to claim 1 or 2,
The semiconductor device, wherein the conductive film is made of Ni, Co or an alloy containing these, and the metal cap film is made of CoWP or NiWP. Forming a recess in an insulating film formed on a semiconductor substrate;
Forming a barrier metal film on the inner wall of the recess and the upper surface of the insulating film;
Forming a conductive film on the upper surface of the insulating film and the surface of the barrier metal film in the recess;
Forming a wiring film on the insulating film so as to be embedded in the recess;
Removing the barrier metal film, the conductive film, and the wiring film outside the recess by polishing;
Forming a metal cap film in a self-aligning manner on the upper surface of the wiring film and the conductive film in which the recess is embedded by electroless plating;
A method for manufacturing a semiconductor device, comprising: In the manufacturing method of the semiconductor device according to claim 7,
The method of manufacturing a semiconductor device, wherein the step of forming the wiring film includes a step of forming a wiring film containing Cu. In the manufacturing method of the semiconductor device according to claim 7 or 8,
The method of forming a metal cap film is a process of forming the metal cap film by electroless plating using a plating solution containing dimethylaminoborane or hydrazine as a reducing agent. . In the manufacturing method of the semiconductor device in any one of Claims 7 thru | or 9,
The step of forming the conductive film includes a step of forming the conductive film with one or more metals selected from the group consisting of Ni, Co, Pd, Pt, Au, Ag, Ru, and alloys thereof. A method of manufacturing a semiconductor device. In the manufacturing method of the semiconductor device according to claim 10,
In the step of forming the metal cap film, the metal cap film is formed of one or more metals selected from the group consisting of Ni, Co, Pd, Pt, Au, Ag, Ru, and alloys thereof. A method for manufacturing a semiconductor device, comprising: In the manufacturing method of the semiconductor device according to claim 10,
The step of forming the metal cap film includes a step of forming the metal cap film with one or more metals selected from the group consisting of Ni, Co, Pd, and alloys thereof. Device manufacturing method. In the manufacturing method of the semiconductor device according to claim 7,
The step of forming the conductive film includes a step of forming a conductive film from Ni, Co or an alloy containing these,
The method of manufacturing a semiconductor device, wherein the step of forming the metal cap film includes a step of forming a metal cap film made of CoWP or NiWP.

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