JP2008027981A - Thin film transistor, its manufacturing method, semiconductor device and display unit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a thin film transistor capable of inhibiting occurrence of a parasitic transistor, realizing high performance, and obtaining high reliability by inhibiting deterioration of withstand voltage of a gate; and to provide its manufacturing method, a semiconductor device, and a display unit. <P>SOLUTION: The thin film transistor has a structure in which a semiconductor layer and a gate electrode are cross-positioned across a gate insulation film. The semiconductor layer has an end of a channel inclined. The gate insulation film has a silicon oxide equivalent thickness of a part overlapping the end of the channel thicker than that of a part overlapping the center of the channel. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

The present invention relates to a thin film transistor, a method for manufacturing the same, a semiconductor device, and a display device. More specifically, the present invention relates to a thin film transistor suitably used as a switching element of a pixel, a manufacturing method thereof, a semiconductor device, and a display device.

Liquid crystal display devices are used in a wide range of fields, taking advantage of their thinness, light weight, and low power consumption. For example, in an active matrix liquid crystal display device, a switching element such as a thin film transistor (hereinafter also referred to as “TFT”) is provided for each pixel, and when the switching element is turned on, a driving voltage is written to the pixel. Even after the switching element is turned off, the driving voltage is held by the holding capacitor element, and a clear image with little crosstalk can be provided. Therefore, it is widely used as a mobile information device such as a personal computer (PC), a mobile phone, and a personal digital assistant (PDA), and a display device such as a car navigation.

By the way, when a TFT having a top gate structure is formed as a pixel switching element or the like, it is provided under the gate insulating film in order to ensure the step coverage of the gate insulating film and to obtain a high withstand voltage. The end of the semiconductor layer may be tapered (inclined). For example, a channel layer (semiconductor layer) having a taper angle (side surface inclination angle in a cross-sectional shape) of 10 to 45 °, a gate electrode formed on the channel layer and intersecting the channel layer, A structure of a TFT having source / drain regions formed in channel layers on both sides is disclosed (for example, see Patent Document 1).

However, according to such a TFT, when the channel layer is doped with impurity ions such as boron and phosphorus, the doping amount per unit area at the end of the channel layer is equal to the doping per unit area at the center of the channel layer. Therefore, there is room for improvement in that a parasitic transistor that is turned on at a threshold value smaller than that of the central portion of the channel layer is generated at the end portion of the channel layer, and as a result, the off-current is increased. was there.

The generation of a parasitic transistor due to the taper (inclination) formed at the end of the semiconductor layer is described in Patent Document 2, for example. Therefore, there has been a demand for a TFT that suppresses the generation of parasitic transistors and has a high withstand voltage.

On the other hand, as a semiconductor device for reducing the off-state current and increasing the withstand voltage, the thin film transistor in which the distance between the semiconductor island and the gate electrode is longer in the peripheral portion of the semiconductor island than in the central portion of the semiconductor island Has been disclosed (for example, refer to Patent Document 3). However, according to the semiconductor device of Patent Document 3, there is room for improvement in that the gate dielectric breakdown voltage is liable to deteriorate when attempting to improve the performance of the thin film transistor, and the reliability is not sufficient.
JP 2000-31493 A JP 2003-258262 A JP-A-8-274339

The present invention has been made in view of the above situation, and can suppress the generation of parasitic transistors, improve performance, and obtain high reliability by suppressing deterioration of gate dielectric breakdown voltage. It is an object of the present invention to provide a thin film transistor, a manufacturing method thereof, a semiconductor device, and a display device.

The present inventor has conducted various studies on thin film transistors that can suppress the generation of parasitic transistors, achieve high performance, and can obtain high reliability by suppressing deterioration of gate dielectric breakdown voltage. First, in the gate insulating film, according to the configuration in which the film thickness of the part overlapping the end part of the channel part is larger than the film thickness of the part overlapping the central part of the channel part, the film thickness of the part overlapping the end part of the channel part Focusing on the fact that the generation of parasitic transistors due to the decrease in thickness can be suppressed and the off-current can be reduced. Note that in the case where the gate insulating film has a structure in which two or more insulating films are stacked, an insulating material other than silicon oxide is often used as an insulating material constituting the gate insulating film. Of the gate insulating film, not the physical thickness of the portion overlapping the end of the channel portion, but the equivalent silicon oxide thickness of the portion is related to the generation of the parasitic transistor. Therefore, in order to suppress the occurrence of the parasitic transistor, the equivalent silicon oxide thickness of the portion of the gate insulating film that overlaps the end of the channel portion is more than the equivalent oxide thickness of the portion that overlaps the central portion of the channel portion. I found that it is important to make it bigger.

In addition, in order to improve the performance of a thin film transistor, it is necessary to reduce the film thickness of a portion of the gate insulating film that overlaps with the channel portion. Further examination has revealed that the gate insulating film is formed by stacking two or more insulating films. In the case of having a structure, the film thickness and film quality of an insulating film (hereinafter also referred to as a “lower gate insulating film”) that is disposed on the semiconductor layer side and forms an interface with the channel portion are important. I found something. Therefore, even if the silicon oxide equivalent film thickness of the portion overlapping the end portion of the channel portion in the gate insulating film is larger than the silicon oxide equivalent film thickness of the portion overlapping the central portion of the channel portion, the semiconductor of Patent Document 3 When the end of the channel portion is formed vertically as in the device, it is a region that overlaps with the end of the channel portion when the thickness of the lower gate insulating film is reduced in order to improve the performance of the thin film transistor. The present inventor has found that the lower gate insulating film is likely to be broken, and as a result, the gate dielectric breakdown voltage is liable to deteriorate, which is not sufficient in terms of reliability.

On the other hand, when the end of the channel portion of the semiconductor layer is inclined, when the channel portion is doped with impurity ions such as boron and phosphorus, the doping amount of impurity ions per unit area is It is known that a parasitic transistor that is turned on at a threshold value smaller than that of the central portion of the channel portion may be generated at the end portion of the channel portion because it becomes smaller at the end portion than the central portion.

However, the present inventor has disclosed that the step coverage of the lower gate insulating film is improved even when the gate insulating film has a structure in which two or more insulating films are stacked by inclining the end of the channel portion of the semiconductor layer. (Step coverage) can be improved, and it has been found that the performance of the thin film transistor can be improved by reducing the thickness of the lower gate insulating film. Further, according to this, since the step coverage of the entire gate insulating film can be improved as compared with the case where the end of the channel portion is formed vertically as in the semiconductor device of Patent Document 3, the gate can be improved. As a result, it was found that high reliability can be obtained as a result of suppressing the dielectric breakdown voltage degradation. Furthermore, the silicon oxide equivalent film thickness of the portion of the gate insulating film that overlaps the end of the channel portion is larger than the equivalent silicon oxide thickness of the portion that overlaps the central portion of the channel portion. We found that the amount of doping per area can be reduced at the end of the channel part than at the center part of the channel part, and that the occurrence of parasitic transistors can be suppressed, and the above problem can be solved brilliantly. The present invention has been achieved.

That is, the present invention is a thin film transistor having a structure in which a semiconductor layer and a gate electrode are arranged to cross each other with a gate insulating film interposed therebetween, and the semiconductor layer has an inclined end portion of a channel portion, and the gate insulating film The film is a thin film transistor in which a silicon oxide equivalent film thickness in a portion overlapping with the end portion of the channel portion is larger than a silicon oxide equivalent film thickness in a portion overlapping with the central portion of the channel portion.
The present invention is described in detail below.

The thin film transistor of the present invention has a structure in which a semiconductor layer and a gate electrode are arranged to cross each other with a gate insulating film interposed therebetween. The material of the gate insulating film is not particularly limited. For example, as a material having a dielectric constant lower than that of silicon oxide (SiO ₂ ) or SiO ₂ , a material having a dielectric constant higher than that of SiO ₂ such as SiOF or SiOC can be used. Silicon nitride such as trisilicon nitride (Si ₃ N ₄ ) (SiN _x (x is a positive number)), silicon oxynitride (SiNO), titanium dioxide (TiO ₂ ), dialuminum trioxide (Al ₂ O ₃ ), Examples thereof include tantalum oxide such as tantalum pentoxide (Ta ₂ O ₅ ), hafnium dioxide (HfO ₂ ), and zirconium dioxide (ZrO ₂ ). As the material of the gate electrode, a refractory metal such as tantalum (Ta), tungsten (W), molybdenum (Mo), or a compound containing a refractory metal nitride or the like is used. As a material for the semiconductor layer, silicon is preferable from the viewpoint of low cost and mass productivity, and polysilicon, continuous grain boundary crystal (CG) silicon, and the like are more preferable from the viewpoint of realizing high mobility.

In this specification, “intersection arrangement” means a state in which one is arranged to cross the other. In the thin film transistor of the present invention, there are one or more end portions of the semiconductor layer. For example, when the shape of the semiconductor layer when viewed in plan is a quadrangle, there are four end portions. The gate electrode and the semiconductor layer may be arranged so as to cross at least one of the portions, and preferably in a form in which the gate electrode and the semiconductor layer draw a cross when viewed from above across two opposite ends of the semiconductor layer. is there. The thin film transistor of the present invention is not particularly limited as long as it has the semiconductor layer, the gate insulating film, and the gate electrode as constituent elements, and may or may not have other constituent elements. The thin film transistor may have, for example, the above laminated structure on an insulating substrate or an insulating film provided on the substrate. The thin film transistor of the present invention may have a top gate structure, may have a dual gate structure, or may have a bottom gate structure.

In the semiconductor layer, the end of the channel portion is inclined. In this specification, the “channel portion” refers to a portion of the semiconductor layer that overlaps with the gate electrode. According to this, the step coverage of the entire gate insulating film can be improved. As a result, gate dielectric breakdown voltage deterioration can be suppressed and reliability can be improved. In addition, even when the gate insulating film has a structure in which two or more insulating films are stacked, the step coverage of the lower gate insulating film can be improved, so that high performance of the thin film transistor can be achieved. .

In the semiconductor layer, generally, the cross-sectional shape of the upper surface constituting the central portion of the channel portion is substantially horizontal, and the cross-sectional shape of the side surface constituting the end portion of the channel portion is a forward tapered shape. In this specification, “the cross-sectional shape of the upper surface is substantially horizontal” refers to a state in which the upper surface is substantially parallel to the lower surface constituting the channel portion and the upper surface constituting the insulating substrate. The “substantially parallel state” includes not only a completely parallel state but also a state that is not parallel within a range that can be equated with a completely parallel state. “Inclined” and “forward tapered shape” refer to a state and shape in which the taper angle (inclination angle with respect to the substrate surface of the cross-sectional shape) is larger than the “substantially horizontal” state and less than 90 °, respectively. In the present invention, the taper angle of the end portion of the channel portion is preferably 30 to 70 °. If it is less than 30 °, the size of the thin film transistor may be too large, and if it exceeds 70 °, the gate dielectric breakdown voltage may be deteriorated, and sufficient reliability may not be obtained.

The gate insulating film has a silicon oxide equivalent film thickness in a portion overlapping with the end portion of the channel portion, and a silicon oxide equivalent film thickness in a portion overlapping with the central portion of the channel portion. According to this, the equivalent silicon oxide film thickness is smaller at the end of the channel part than at the center part of the channel part, or per unit area of impurity ions when the channel part is doped with impurity ions such as boron and phosphorus. As the doping amount of the transistor becomes smaller at the end portion of the channel portion than at the center portion of the channel portion, a transistor (parasitic transistor) that is turned on with a threshold smaller than that at the central portion of the channel portion is generated at the end portion of the channel portion. Therefore, off-state current can be reduced. In general, attempts to obtain the effect of suppressing the occurrence of parasitic transistors often fail to obtain the effect of suppressing the gate dielectric breakdown voltage degradation. In many cases, the effect of suppressing the generation of a transistor cannot be obtained. On the other hand, the thin film transistor of the present invention is suitable in that both effects can be achieved.

In this specification, the “equivalent silicon oxide film thickness of the part overlapping the end part of the channel part” refers to an average value of the equivalent silicon oxide film thickness in the entire part overlapping the end part of the channel part. “Silicon oxide equivalent film thickness of the part overlapping the central part of the channel part” means an average value of equivalent silicon oxide film thickness in the entire part overlapping the central part of the channel part. Although there are usually two end portions of the channel portion, in the present invention, the equivalent silicon oxide thickness of the portion that overlaps at least one end portion is larger than the equivalent oxide thickness of the portion that overlaps the central portion of the channel portion. What is necessary is just to have a silicon oxide conversion film thickness of the part which overlaps with both edge parts larger than the silicon oxide conversion film thickness of the part which overlaps with the center part of a channel part. In addition, the average value of the silicon oxide equivalent film thickness in the part which overlaps with two edge parts of a channel part may be the same, and may mutually differ.

It is preferable that the silicon oxide equivalent film thickness of the portion overlapping the end portion of the channel portion is 10 nm or more larger than the silicon oxide equivalent film thickness of the portion overlapping the central portion of the channel portion. If it is less than 10 nm, the effect of suppressing the generation of parasitic transistors may not be sufficiently obtained.

As a preferred mode of the thin film transistor of the present invention, (1) the gate insulating film is made of a material in which a portion overlapping the end portion of the channel portion forms a portion overlapping the central portion of the channel portion; (2) The gate insulating film is composed of a lower gate insulating film and an upper gate insulating film, and the channel portion overlaps the thickness of the portion overlapping the central portion of the channel portion. An upper gate insulating film is stacked at the center of the gate, and an end of the channel section is formed by stacking a lower gate insulating film and an upper gate insulating film. (3) The gate insulating film is formed by lower gate insulating. The lower gate insulating film is laminated at the center of the channel portion, and the lower gate insulating film and the upper gate insulating film are laminated at the end of the channel portion. Form, and the like. According to these embodiments, the silicon oxide equivalent film thickness of the portion of the gate insulating film that overlaps the end portion of the channel portion is larger than the silicon oxide equivalent film thickness of the portion that overlaps the central portion of the channel portion. Generation of parasitic transistors can be suppressed.

With respect to the form of (1), “the film thickness of the portion overlapping the end of the channel portion” refers to the average value of the physical film thickness over the entire portion overlapping the end of the channel portion. “The film thickness of the portion overlapping the central portion of the channel portion” refers to the average value of the physical film thickness over the entire portion overlapping the central portion of the channel portion. In the form of (1), the portion that overlaps the end portion of the channel portion and the portion that overlaps the central portion of the channel portion may have a single-layer structure or a laminated structure. From the viewpoint of improving the performance of the thin film transistor, it is preferable to have a stacked structure. Note that in the case of having a stacked structure, the number of stacked gate insulating films and the stacking order are the same in the portion overlapping the end portion of the channel portion and the portion overlapping the center portion of the channel portion. The film thickness of one layer should just differ from each other. Moreover, it is preferable that the film thickness of the part which overlaps with the edge part of a channel part is 10 nm or more larger than the film thickness of the part which overlaps with the center part of a channel part. If it is less than 10 nm, the effect of suppressing the parasitic transistor may not be sufficiently obtained.

In the forms (2) and (3), the number of stacked gate insulating films differs between the part overlapping the end of the channel part and the part overlapping the center part of the channel part, unlike the form (1). . The lower gate insulating film may be made of the same material as the upper gate insulating film, or may be made of a different material. In addition, each of the lower gate insulating film and the upper gate insulating film may have a single layer structure or a stacked structure.

The present invention is also a method of manufacturing the thin film transistor having the form of (1), wherein the manufacturing method includes a step of forming a gate insulating film on a semiconductor layer, and a gate stacked in a central portion of the channel portion. A method of manufacturing a thin film transistor including a step of removing an upper portion of the insulating film. According to this, since the interface between the semiconductor layer and the lower gate insulating film is not exposed by etching or the like, abnormal characteristics of the thin film transistor can be reduced.

The present invention further relates to a method of manufacturing the thin film transistor having the form of (3), wherein the manufacturing method includes a step of forming a lower gate insulating film and an upper gate insulating film on a semiconductor layer, and a channel portion. And a step of removing the upper gate insulating film stacked in the central portion. Also by this, since the interface between the semiconductor layer and the lower gate insulating film is not exposed by etching or the like, the characteristic abnormality of the thin film transistor can be reduced. When this manufacturing method is used, it is preferable that the lower gate insulating film is made of a material different from that of the upper gate insulating film. According to this, in the case where the step of removing the upper gate insulating film is performed by etching, the etching can be completed with a different gate insulating film, so that the film thickness of the gate insulating film can be easily controlled. When the step of removing the upper gate insulating film is performed by etching, the etch selectivity between the lower gate insulating film and the upper gate insulating film is (etching rate of the lower gate insulating film) / (upper side). It is preferable that the etching rate of the gate insulating film is equal to or higher than ¼.

The present invention is also a semiconductor device or a display device including the thin film transistor. According to the thin film transistor of the present invention, off-state current can be reduced, so that a high-quality semiconductor device and display device can be provided. An example of the semiconductor device is a MOS transistor. Examples of the display device include a liquid crystal display device and an organic electroluminescence display device.

According to the thin film transistor of the present invention, since the end portion of the channel portion in the semiconductor layer is inclined, the step coverage of the entire gate insulating film can be improved. Reliability can be improved. Further, even when the gate insulating film has a structure in which two or more insulating films are stacked, the step coverage of the lower gate insulating film can be improved, so that high performance of the thin film transistor can be achieved. In addition, since the equivalent silicon oxide thickness of the portion of the gate insulating film that overlaps the end of the channel portion is larger than the equivalent oxide thickness of the portion that overlaps the central portion of the channel portion, the channel portion is formed at the end of the channel. It is possible to suppress the occurrence of a transistor that is turned on with a threshold value smaller than that of the central portion.

The present invention will be described in more detail below with reference to embodiments, but the present invention is not limited to these examples.

The present invention controls the threshold value of the thin film transistor (TFT) by changing the thickness of the gate insulating film between the flat portion (center portion) and the end portion of the silicon layer (semiconductor layer), and thereby the end portion of the silicon layer. By shifting the threshold value of the parasitic transistor generated in the region to the higher side, the generation of the parasitic transistor is suppressed.

FIG. 1 is a graph showing the drain current (Id) versus gate voltage (Vg) characteristics of a TFT. Note that the two solid lines represent a normal N-channel (Nch) TFT and a P-channel (Pch) TFT, respectively. Each of the two dotted lines represents a TFT in which a parasitic transistor is observed. According to the present invention, the threshold values of the parasitic transistors of the Nch and Pch TFTs can be shifted to the high threshold value side, so that the generation of parasitic transistors can be suppressed. As shown in FIG. 1, the Id-Vg characteristic of a Pch TFT in which a parasitic transistor is observed is almost the same as that of a normal Pch TFT.

<Embodiment 1>
FIGS. 2-1 to 2-9 are schematic cross-sectional views illustrating the manufacturing steps of the TFT according to the first embodiment of the present invention. The left side of the figure represents the formation of the Pch TFT, and the right side represents the formation of the Nch TFT.

(1) Formation process of undercoat layer and semiconductor layer As shown in FIG. 2-1, an undercoat layer 11 (lower layer) is formed on a substrate 10 by plasma enhanced chemical vapor deposition (PECVD) or the like. : silicon oxynitride film (SiNO) film 11a, the upper layer: forming a silicon oxide (SiO ₂₎ film 11b) and amorphous silicon (a-Si) layer 12 in this order. The film thickness of the undercoat layer 11 is not particularly limited. For example, the film thickness of the SiNO film 11a may be 30 to 70 nm, and the film thickness of the SiO ₂ film 11b may be 50 to 150 nm. Further, the thickness of the a-Si layer 12 is not particularly limited, but may be, for example, 30 to 70 nm.

Examples of the source gas for forming the SiNO film 11a include a mixed gas of monosilane (SiH ₄ ), nitrous oxide gas (N ₂ O), and ammonia (NH ₃ ). Further, examples of the source gas for the SiO ₂ film 11b include tetraethylorthosilicate (TEOS) gas. Furthermore, examples of the source gas for forming the a-Si layer 12 include monosilane (SiH ₄ ) and disilane (Si ₂ H ₆ ). As the undercoat layer 11, a silicon nitride (SiN _x (x is a positive number)) film formed using a mixed gas of monosilane (SiH ₄ ) and ammonia (NH ₃ ) or the like as a source gas is used. Also good.

Next, in order to polycrystallize the a-Si layer 12, solid phase crystal growth (SPC) is performed by heat treatment at approximately 600 ° C. At this time, before the SPC, a pretreatment for applying a metal catalyst such as nickel (Ni) to form continuous grain boundary crystalline silicon (CG silicon) may be performed. By the way, the field effect mobility of polysilicon (p-Si) is low due to the fact that the crystal grain size is reduced only by performing SPC and the crystal grain size includes a large number of crystal defects. Undesirable characteristics such as may occur. Therefore, it is preferable to improve the quality of polysilicon (p-Si) crystal grains by laser annealing using excimer laser light as laser light after SPC. As the laser light, solid laser light or the like may be used. Finally, by patterning the resist film by photolithography and further etching, the p-Si layer is formed into a desired shape. As shown in FIG. 2-2, the island-like shape having a taper angle of 45 ° is formed. The p-Si layers (semiconductor layers) 13a and 13b are formed.

(2) Step of Forming Gate Insulating Film Next, as shown in FIG. 2-3, the gate insulating film 14 (SiO ₂ film (lower gate insulating film) 14a, SiN _x film (upper gate insulating film) 14b) is formed. Form continuously. The thicknesses of the SiO ₂ film 14a and the SiN _x film 14b are not particularly limited, but may be 30 to 150 nm, for example. The material of the lower gate insulating film 14a is not particularly limited, and a SiN _x film, a SiON film, or the like may be used.

(3) Channel doping step Next, as shown in FIG. 2-4, in order to control the threshold values of the Nch TFT and the Pch TFT, a doped layer is formed by doping boron as an impurity on the entire surface of the substrate by an ion doping method or the like. To do. The concentration of boron to be doped is not particularly limited, but may be, for example, 10 ¹² to 10 ¹⁴ ion / cm ² . If the threshold control of the Pch TFT is not necessary, this doping need not be performed. Next, in order to control the threshold value of the Nch TFT, a region where the Pch TFT is formed is covered with a resist film by photolithography, and then a predetermined amount of boron is channel-doped by an ion doping method or the like only in the region where the Nch TFT is formed. An Nch doped layer is formed. The concentration of boron doped in the Nch-doped layer is not particularly limited, but may be, for example, 10 ¹² to 10 ¹⁴ ion / cm ² . At this time, if a gate overlap (GOLD) structure is required as a countermeasure against hot carrier deterioration, a resist film is patterned into a desired shape by photolithography and a predetermined amount of phosphorus is doped. May be. Note that channel doping can also be performed before the gate insulating film 14 is etched.

(4) Upper Gate Insulating Film Etching Step Next, as shown in FIG. 2-5, a resist film is patterned by photolithography, and the upper gate insulating film 14b is etched using this resist film. As a result, a structure is obtained in which the upper gate insulating film 14b stacked in the channel portion is etched to the lower gate insulating film 14a. According to this, since the interface between the p-Si layers 13a and 13b and the gate insulating film 14 which are important in the TFT is not exposed by etching, the TFT characteristic abnormality is hardly generated. Further, since the lower gate insulating film 14a and the upper gate insulating film 14b are formed of different materials, the thickness control of the gate insulating film 14 is easy.

As described above, when the silicon oxide (SiO ₂ ) equivalent film thickness in the portion overlapping the central portion of the channel portion of the p-Si layers 13a and 13b is set to 50 nm, for example, as shown in Table 1, it overlaps with the end portion of the channel portion. By making the SiO ₂ equivalent film thickness in the portion larger than the SiO ₂ equivalent film thickness in the portion overlapping the central portion of the channel portion, a parasitic transistor generated at the end of the channel portion with respect to the Nch and Pch thresholds of the channel portion Can be shifted to a higher side, so that the generation of parasitic transistors can be suppressed. The amount of change in threshold in Table 1 is the amount of change from the threshold when the SiO ₂ equivalent film thickness in the portion overlapping the center portion of the channel portion and the portion overlapping the end portion of the channel portion is 50 nm. Show.

(5) Step of Forming Gate Electrode Next, as shown in FIGS. 2-6, a tantalum nitride (TaN) film 15a and a tungsten (W) film 15b are formed by sputtering or the like. The film thickness of the TaN film 15a and the W film 15b is not particularly limited. For example, the film thickness of the TaN film 15a may be 40 to 60 nm, and the film thickness of the W film 15b may be 300 to 400 nm. Next, after a resist film is patterned into a desired shape by photolithography, argon (Ar), sulfur hexafluoride (SF ₆ ), carbon tetrafluoride (CF ₄ ), oxygen (O ₂ ), chlorine Dry etching is performed using an etching gas whose mixed gas content is adjusted, such as (Cl ₂ ), to form a gate electrode 15 having a two-layer structure. Examples of the metal used for the gate electrode 15 include a low-resistance metal such as tantalum (Ta), molybdenum (Mo), molybdenum tungsten (MoW), and aluminum (Al), and a refractory metal having a flat surface and stable characteristics. It is done. Further, the gate electrode 15 may be a stacked body made of the plurality of materials.

(6) Source / Drain Electrode Formation Process Next, although not shown, after forming a resist film in a desired shape by photolithography to form a diffusion region of Nch and PchTFT, NchTFT uses phosphorus, PchTFT Then, boron is ion-doped at a high concentration by an ion doping method or the like. The concentrations of phosphorus and boron to be doped are not particularly limited, but may be, for example, 10 ¹⁵ to 10 ¹⁷ ions / cm ² . At this time, if necessary, a resist film may be patterned into a desired shape by a photolithography method to form an LDD (Lightly Doped Drain) structure. In addition, when CG silicon is used for the semiconductor layers 13a and 13b, doping of a gettering material such as phosphorus may be performed at the same time in order to eliminate an undesirable effect of the residual metal catalyst. Next, in order to activate the impurity ions existing in the p-Si layers 13a and 13b, a thermal activation process is performed at about 600 ° C. for 4 hours. Thereby, the electrical conductivity of the diffusion region can be improved. The electrical conductivity of the diffusion region is not particularly limited, but is preferably 1 kΩ / □ or less at 25 ° C. in terms of resistivity. As the activation method, other methods such as irradiating excimer laser light can be used. As a result, the Nch TFT has a channel portion and an outer diffusion portion composed of an n ⁺ region. On the other hand, the Pch TFT has a channel part and a p ⁺ outer diffusion part.

(7) Formation Process of Interlayer Insulating Film Next, as shown in FIG. 2-7, an interlayer insulating film 16 having a film thickness of 800 to 1200 nm is formed by PECVD. Examples of the material of the interlayer insulating film 16 include a SiN _x film, a SiON film, and a SiO ₂ film. The interlayer insulating film 16 may be a laminated film of the above materials.

(8) Contact Part Formation Step Next, as shown in FIG. 2-8, after a resist film is patterned into a desired shape by photolithography, the interlayer insulating film 16 is etched using a hydrofluoric acid-based etching solution. Then, wet etching is performed on the gate insulating film 14 to form contact holes. At the time of microfabrication, dry etching or a combination of dry etching and wet etching may be used.
(9) Annealing treatment step Next, in order to further improve the quality of the semiconductor layers 13a and 13b, a hydrogenation annealing treatment is performed at about 400 ° C.

(10) Source Metal Formation Step Next, as shown in FIG. 2-9, a titanium (Ti) film having a thickness of 100 to 200 nm and an aluminum-silicon (Al—Si) film having a thickness of 500 to 1000 nm by sputtering or the like. A metal thin film is formed in the order of a system alloy film and a Ti film having a thickness of 100 to 200 nm. Next, after forming a resist film into a desired shape by photolithography, the metal thin film is patterned by dry etching to form the source wiring 18.

According to the TFT fabricated in the first embodiment, the end portions of the channel portions of the p-Si layers 13a and 13b are inclined at a taper angle of 45 °, so that the step coverage of the gate insulating film 14 is sufficiently obtained. As a result, gate dielectric breakdown voltage degradation can be suppressed. In addition, the gate insulating film 14 has a silicon oxide equivalent film thickness in a portion that overlaps the central portion of the channel portion of the p-Si layers 13a and 13b is larger than a silicon oxide equivalent film thickness in a portion that overlaps the end portion of the channel portion. Since the threshold value of the parasitic transistor generated at the end of the channel portion can be shifted to the higher side, the generation of the parasitic transistor can be suppressed.

<Embodiment 2>
FIGS. 3-1 to 3-3 are schematic cross-sectional views illustrating manufacturing steps of the thin film transistor according to the second embodiment of the present invention. Note that the left side of the figure represents the formation region of the Pch TFT, and the right side represents the formation region of the Nch TFT.
(1) Process of forming undercoat layer and semiconductor layer As shown in FIGS. 2-1 and 2-2, the same process as in the first embodiment is performed.

(2) Step of Forming Gate Insulating Film Next, as shown in FIG. 3A, an SiO ₂ film (gate insulating film) 14 is formed on the semiconductor layers 13a and 13b using TEOS gas. The thickness of the SiO ₂ film 14 is not particularly limited, but may be, for example, 30 to 150 nm. The material of the gate insulating film 14 is not particularly limited, and other materials such as a SiN _x film and a SiON film may be used. Examples of the source gas for forming the SiN _x film and the SiON film are the same as those described in the formation of the undercoat layer 11.

(3) Channel doping process As shown in FIG.
(4) Etching Process of Gate Insulating Film As shown in FIG. 3-3, the gate insulating film 14 at the center of the channel part is etched halfway to reduce the thickness. According to this structure, the interface between the p-Si layers 13a and 13b and the gate insulating film 14, which are important in the TFT, is not exposed by etching, so that it is difficult to cause an abnormal characteristic of the TFT.
(5) Gate electrode formation step to source metal formation step The same steps as in the first embodiment are performed.

Also in the TFT manufactured in the second embodiment, the end portions of the channel portions of the p-Si layers 13a and 13b are inclined at a taper angle of 45 °, and the gate insulating film 14 is formed of the channel of the p-Si layers 13a and 13b. Since the equivalent silicon oxide film thickness of the part overlapping the central part of the part is larger than the equivalent silicon oxide film thickness of the part overlapping the end part of the channel part, the same effect as that of the first embodiment can be obtained.

<Embodiment 3>
FIGS. 4-1 to 4-4 and FIGS. 5-1 to 5-4 are cross-sectional schematic diagrams illustrating manufacturing steps of the thin film transistor according to the third embodiment of the present invention. The left side of the figure represents the formation of the Pch TFT, and the right side represents the formation of the Nch TFT.
(1) Process of forming undercoat layer and semiconductor layer As shown in FIGS. 2-1 and 2-2, the same process as in the first embodiment is performed.

(2) Lower Gate Insulating Film Formation Step As shown in FIG. 4A, a SiO ₂ film (lower gate insulating film) 14a is formed on the semiconductor layers 13a and 13b using TEOS gas. The thickness of the SiO ₂ film 14a is not particularly limited, but may be, for example, a thickness of 30 to 150 nm. The material of the lower gate insulating film 14a is not particularly limited, and other materials such as a SiN _x film and a SiON film may be used. Further, as shown in FIG. 5A, the lower gate insulating film 14a may be a stacked body made of a plurality of materials. Examples of the source gas for forming the SiN _x film and the SiON film are the same as those described in the formation of the undercoat layer 11.

(3) Channel doping step As shown in FIGS. 4-2 and 5-2, the channel doping step is performed in the same manner as in the first embodiment.
(4) Etching process of lower gate insulating film As shown in FIGS. 4-3 and 5-3, the lower gate insulating film 14a stacked at the center of the channel portion is etched to the surface of the semiconductor layers 13a and 13b. .

(5) Step of Forming Upper Gate Insulating Film Next, as shown in FIGS. 4-4 and 5-4, the upper gate insulating film 14b is formed using TEOS gas as a source gas. The thickness of the upper gate insulating film 14b is not particularly limited, but may be, for example, 30 to 100 nm. The material of the upper gate insulating film 14b is not particularly limited, and other materials such as a SiN _x film and a SiON film may be used. The upper gate insulating film 14b may be a stacked body made of a plurality of materials. Examples of the source gas for forming the SiN _x film and the SiON film are the same as those described in the formation of the undercoat layer 11.

(6) Gate electrode formation step to source metal formation step The same as in the first embodiment.

Also in the TFT manufactured in the third embodiment, the end portions of the channel portions of the p-Si layers 13a and 13b are inclined at a taper angle of 45 °, and the gate insulating film 14 is formed of the channel of the p-Si layers 13a and 13b. Since the equivalent silicon oxide film thickness of the part overlapping the central part of the part is larger than the equivalent silicon oxide film thickness of the part overlapping the end part of the channel part, the same effect as that of the first embodiment can be obtained.

It is a figure which shows a mode that generation | occurrence | production of the parasitic transistor of N channel (Nch) and P channel (Pch) TFT is suppressed by this invention. (A) And (b) is the plane schematic diagram and cross-sectional schematic diagram which respectively show the formation process of an undercoat layer (Embodiments 1-3). (A) And (b) is the plane schematic diagram and cross-sectional schematic diagram which respectively show the formation process of a semiconductor layer (Embodiments 1-3). (A) And (b) is the plane | planar schematic diagram and sectional schematic diagram which respectively show the formation process of a gate insulating film (embodiment 1). (A) And (b) is the plane schematic diagram and cross-sectional schematic diagram which respectively show a channel doping process (embodiment 1). (A) And (b) is the plane | planar schematic diagram and the cross-sectional schematic diagram which respectively show the etching process of an upper side gate insulating film (embodiment 1). (A) And (b) is the plane | planar schematic diagram and sectional schematic diagram which respectively show the formation process of a gate electrode (embodiment 1). (A) And (b) is the plane | planar schematic diagram and sectional schematic diagram which respectively show the formation process of an interlayer insulation film (embodiment 1). (A) And (b) is the plane schematic diagram and sectional schematic diagram which respectively show the formation process of a contact part (embodiment 1). (A) And (b) is the plane schematic diagram and sectional schematic diagram which respectively show the formation process of a source metal (embodiment 1). (A) And (b) is the plane | planar schematic diagram and the cross-sectional schematic diagram which respectively show the etch process of a gate insulating film (embodiment 2). (A) And (b) is the plane schematic diagram and sectional schematic diagram which respectively show a channel doping process (embodiment 2). (A) And (b) is the plane | planar schematic diagram and the cross-sectional schematic diagram which respectively show the etch process of a gate insulating film (embodiment 2). (A) And (b) is the plane schematic diagram and sectional schematic diagram which respectively show the formation process of a lower gate insulating film (embodiment 3). (A) And (b) is the plane schematic diagram and cross-sectional schematic diagram which respectively show a channel doping process (embodiment 3). (A) And (b) is the plane schematic diagram and sectional schematic diagram which respectively show the etching process of a lower gate insulating film (embodiment 3). (A) And (b) is a cross-sectional schematic diagram which respectively shows the formation process of an upper gate insulating film (embodiment 3). (A) And (b) is the plane schematic diagram and sectional schematic diagram which respectively show the formation process of a lower gate insulating film (embodiment 3). (A) And (b) is the plane schematic diagram and cross-sectional schematic diagram which respectively show a channel doping process (embodiment 3). (A) And (b) is the plane schematic diagram and sectional schematic diagram which respectively show the etching process of a lower gate insulating film (embodiment 3). (A) And (b) is a cross-sectional schematic diagram which respectively shows the formation process of an upper gate insulating film (embodiment 3).

Explanation of symbols

10: Substrate 11: Undercoat layer 11a: Lower layer 11b of the undercoat layer: Upper layer 12 of the undercoat layer 12: Amorphous silicon (a-Si) layer 13a, 13b: Polysilicon (p-Si) layer 14: Gate insulation Film 14a: Lower gate insulating film 14b: Upper gate insulating film 15: Gate electrode 15a: Lower layer portion 15b of gate electrode: Upper layer portion 16 of gate electrode: Interlayer insulating films 17a-17e: Contact holes 18a-18e: Source wiring

Claims (9)

A thin film transistor having a structure in which a semiconductor layer and a gate electrode are arranged to cross each other with a gate insulating film interposed therebetween,
The semiconductor layer has an inclined end portion of the channel portion,
The thin film transistor characterized in that the gate insulating film has a silicon oxide equivalent film thickness in a portion overlapping with an end portion of a channel portion larger than a silicon oxide equivalent film thickness in a portion overlapping with a central portion of the channel portion. The gate insulating film is made of a material that forms a portion where the end of the channel portion overlaps the central portion of the channel portion, and the thickness of the portion overlapping the end portion of the channel portion is the center of the channel portion. 2. The thin film transistor according to claim 1, wherein the thickness of the thin film transistor is larger than a thickness of a portion overlapping the portion. The gate insulating film is composed of a lower gate insulating film and an upper gate insulating film,
In the central part of the channel part, an upper gate insulating film is laminated,
2. The thin film transistor according to claim 1, wherein a lower gate insulating film and an upper gate insulating film are stacked at an end of the channel portion. The gate insulating film is composed of a lower gate insulating film and an upper gate insulating film,
In the central part of the channel part, a lower gate insulating film is laminated,
2. The thin film transistor according to claim 1, wherein a lower gate insulating film and an upper gate insulating film are stacked at an end of the channel portion. A method for producing the thin film transistor according to claim 2, comprising:
The manufacturing method includes forming a gate insulating film on the semiconductor layer;
And a step of removing an upper portion of the gate insulating film stacked in the central portion of the channel portion. A method of manufacturing the thin film transistor according to claim 4, comprising:
The manufacturing method includes forming a lower gate insulating film and an upper gate insulating film on a semiconductor layer;
And a step of removing the upper gate insulating film stacked in the center portion of the channel portion. 7. The method of manufacturing a thin film transistor according to claim 6, wherein the lower gate insulating film is made of a material different from that of the upper gate insulating film. A semiconductor device comprising the thin film transistor according to claim 1. A display device comprising the thin film transistor according to claim 1.

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