JP2008017389A - Design method for synchronous circuit having reduced emi noise - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a design method for a synchronous circuit for reducing a peak value of EMI noise by verifying where and how many skews are given and by diversifying the timing of current of power dissipation on the time axis. <P>SOLUTION: The design method for synchronous circuit comprises a first step for implementing a primary layout and wiring of the synchronous circuit using an automatic layout wiring tool by inputting the predetermined condition including a network list, a second step for analyzing a skew as a difference of arriving times of the clock up to each terminal path from the clock source in accordance with a clock tree of the arranged and wired synchronous circuit, a third step for dividing into a plurality of modules I, II, III and IV where the analyzed skew has margin for setup/hold time, a fourth step for additionally inserting a clock skew setting circuit 10 to at least one of the plurality of divided modules I, II, III and IV, and a fifth step for implementing a secondary layout and wiring by adding the clock skew setting circuit 10. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a method for designing a synchronous circuit with reduced EMI noise.

As a design method of this type, there is a design method described in Patent Document 1. According to this method, a circuit including a flip-flop and a combinational circuit is divided into blocks, and a clock tree having a slightly different delay amount is inserted for each block. Thereafter, the skew calculated for each block is designed to be smaller than the upper limit of the skew value of the entire synchronous circuit.
JP 2004-120084 A

  However, with the method of Patent Document 1, it is difficult to first divide a circuit into a plurality of blocks. This block division is an important element that constrains the subsequent design procedure, and becomes a factor that determines, for example, a place where a clock tree is to be inserted. In practice, however, there is no clear criterion for determining block partitioning in the first stage.

  In Patent Document 1, when the skew value of the entire synchronous circuit is not less than or equal to the upper limit value, the process returns to the beginning and starts again from block division (Claim 2). It is difficult to say that it is an efficient design method.

  Therefore, an object of the present invention is to verify how much skew can be attached to which location, and to disperse the timing of current consumption on the time axis, thereby reducing any peak of EMI. It is to provide a method for designing a synchronous circuit.

  The method for designing a synchronous circuit according to the present invention includes a first step of inputting a given condition including a netlist and performing primary placement and routing of the synchronization circuit using an automatic placement and routing tool, and synchronization of placement and routing In accordance with the clock tree of the circuit, a second step of analyzing the skew that is the difference in arrival time of the clock from the clock source to each end path, and the analyzed skew is divided into a plurality of modules having margins with respect to the setup / hold time. A third step, a fourth step of additionally inserting a clock skew setting circuit into at least one of the plurality of divided modules, and a fifth step of adding the clock skew setting circuit and performing secondary placement and routing It is characterized by having.

  According to the present invention, by performing the first to third steps, it is possible to verify where the skew can be further added, and since the place where the skew is to be added is not specified in advance as in Patent Document 1, the EMI noise is not specified. The degree of freedom and certainty of the skew adjustment for reducing the error is improved. Also, by performing the fourth and fifth steps, EMI noise can be distributed on the time axis more than in the case of primary automatic placement and routing, and the peak of ENI noise can be reliably reduced.

  In the present invention, in the fourth step, at least one of the top two modules has the clock clock so that a maximum skew difference is generated between the top two modules having a large circuit scale among the plurality of modules. A queue setting circuit can be inserted.

  Since the amount of current consumption that causes EMI noise depends on the circuit scale, if the largest skew difference occurs between the two most significant modules with a large circuit scale, the two largest peaks of EMI noise are dispersed on the time axis. Thus, the two major peaks do not overlap each other, and the EMI noise peak can be reduced.

  Further, in the present invention, in the fourth step, the module having the third largest circuit scale among the plurality of modules has a maximum skew difference with respect to each of the top two modules. The clock skew setting circuit can be inserted into a module having the third largest circuit scale.

  In this way, since the third largest EMI noise peak is dispersed on the time axis, both the EMI noise peaks can be reduced.

  In the present invention, the skew amount of the clock skew setting circuit is variable by a logic signal, and the fourth step can include a step of setting the skew amount of the clock skew setting circuit for each module.

  In this way, the skew adjustment not only changes the insertion position of the clock skew setting circuit but also makes the skew variable for each module, so that finer adjustment for reducing the EMI noise peak is possible.

  In the present invention, the position at which the clock skew setting circuit is inserted into at least one of the plurality of modules is a position that does not cause a skew fluctuation to other modules, and the position at which at least one of the plurality of modules is at least one of the plurality of modules. It may be located further upstream than the most upstream buffer to which it belongs.

  In this way, the insertion of the clock skew setting circuit does not change the skew margin in other modules, and the circuit scale of the module in which the clock skew setting circuit is inserted can be utilized to the maximum, and the EMI noise peak is reduced. Can contribute.

  In the present invention, after the fifth step, according to the clock tree to which the clock skew setting circuit is added, a skew that is a difference in arrival time of the clock from the clock source to each end path is analyzed, and the analyzed skew is set up / holded. A sixth step of verifying whether or not there is a margin with respect to time can be further included.

  In this way, it is possible to reconfirm whether or not the setup / hold time requirement necessary for the synchronization circuit is satisfied after the clock skew setting circuit is additionally inserted.

  Hereinafter, preferred embodiments of the present invention will be described in detail. The present embodiment described below does not unduly limit the contents of the present invention described in the claims, and all the configurations described in the present embodiment are indispensable as means for solving the present invention. Not necessarily.

  FIG. 1 is a flowchart showing an embodiment of the method of the present invention. Hereinafter, a method for designing an LSI, which is an ASIC (application-specific IC), will be described with reference to a flowchart.

(1) Primary placement and routing (1 ^ST P & R)
First, given conditions including a net list are input, and LSI placement and routing is performed using an automatic placement and routing tool (step 1 in FIG. 1). At this time, clock tree synthesis (synthesis) is performed using a clock tree generator (CTGen), and netlist optimization is further performed.

  (2) Next, a skew analysis of the clock tree is performed (step 2 in FIG. 1). FIG. 2 schematically shows a clock tree arranged and routed. As shown in FIG. 2, the clock tree is branched, and buffers (shown by triangles) are inserted before and after the branch. A square at each end of the clock tree indicates a flip-flop at the final stage. A line connecting the flip-flops is a data line.

  Skew analysis is performed using a tool called a static timing analyzer (STA). As a result, the difference (skew) in the arrival time generated when the clock passes through the paths of the plurality of signal lines is analyzed.

  Here, the minimum time that the data signal must be determined and held before the clock signal is called `` setup time '', and conversely, the data signal must be held even after the timing signal is given. The time that must be called is called “(input) hold time”. In the synchronous circuit, the “setup time” and “hold time” must be satisfied in all circuits of the IC. Otherwise, the data signal cannot be correctly processed inside the IC. In step 2 of FIG. 1, by analyzing the skew from the clock source to the end, it is analyzed whether the setup / hold time is satisfied and how much margin there is.

(3) Examination of module division (Step 3 in FIG. 1)
EMI noise reaches a peak when the change in current consumption inside the IC per unit time becomes maximum. As a method of reducing the peak of EMI noise, the timing at which the current consumption changes transiently is eased by concentrating on each module divided in the LSI at the same time, and the peak of EMI noise is reduced. It can be lowered. Module division for this is step 3 in FIG.

  For example, in FIG. 2, flip-flops F.1 belonging to modules I, II, III, and IV surrounded by broken lines. F. It was found that the margin to the skew up to the setup / hold time is large. It is assumed that other modules not surrounded by a broken line satisfy the setup / hold time, but the margin is not large.

  In this case, modules I, II, III, and IV surrounded by a broken line are determined as candidates for divided modules.

(4) Insertion of clock skew setting circuit (step 4 in FIG. 1)
FIG. 3 shows a clock skew setting circuit 10 that is inserted immediately before the modules I, II, III, and IV that are candidate division modules after placement and routing. The clock skew setting circuit 10 includes, for example, first and second buffers 12 and 14 and three selectors 20, 22 and 24. The first and second buffers 12 and 14 and the three selectors 20, 22, and 24 delay the clock signal CLK, respectively.

  Of the clock signals A to D in FIG. 3, the clock signals A to C are obtained by delaying the clock CLK by the first buffer 12, but the clock signal A is output only through the selector 24, and the clock The signal B is output through the selectors 22 and 24, and the clock signal C is output through the selectors 20, 22, and 24. Like the clock signal C, the clock signal D output through the three selectors 20, 22, 24 is delayed in the second buffer 14 in addition to the first buffer 12. Accordingly, the delay amount of the clock signals A to D output from the selector 24 at the final stage is A <B <C <D, the delay amount of the clock signal D is the largest, and the delay amount of the clock signal A is The smallest.

  The control signals S1, S2, S3 for switching the three selectors 20, 22, 24 are output from the three logic circuits 30, 32, 34 to which they are input based on the logic of the two logic signals M1, M2.

  FIG. 4 is a truth table of the clock skew setting circuit 10 shown in FIG. 3. When the logic of the two logic signals M1 and M2 is fixed, the output X is fixed to any one of the clock signals A to D. Is done.

  Next, the position where the clock skew setting circuit 10 is to be inserted and the delay amount of the clock signal selected by the clock skew setting circuit 10 will be described.

  First, the positions where the clock skew setting circuit 10 can be inserted are the positions a to d shown in FIG. 2 corresponding to the modules I, II, III, and IV. Each of the positions a to d satisfies the following two requirements. One is that the skew can be individually corrected only for each of the modules I, II, III, and IV. This is because if the clock skew setting circuit 10 is inserted to affect a module having a small skew margin, the skew analysis must be performed again. The other is a further upstream position of the buffer located at the uppermost stream in the module. This is because the circuit scale capable of adjusting the skew can be maximized by inserting the clock skew setting circuit 10 at the position closest to the clock source, and this is effective in reducing the peak of EMI noise.

  Next, the delay amount of the clock signal selected by the clock skew setting circuit 10 will be described. What should be considered here is the size of the skew margin of each module analyzed in advance and the size of the circuit occupied by each module. As described above, the clock skew setting circuit 10 of FIG. 3 can select four types of skew amounts (clock signals A to D), but the selected skew amount can be within the range of the skew margin in each module. I must. Otherwise, the addition of the clock skew setting circuit 10 prevents a certain module from satisfying the setup / hold time. Note that the magnitude of the skew amount selected by each module (clock signals A to D) is not necessarily different.

  What is important is that when the skew by the clock skew setting circuit 10 is added in addition to the skew possessed by each module, as a result, the timing at which the consumption current changes transiently in each module is dispersed, resulting in EMI noise. Is to reduce the peak.

  Here, since the EMI noise depends on the current consumption flowing in the same period, it is also important to know the number of cells of each module.

  In the example of FIG. 2, it is assumed that the circuit scale is as follows. Note that the number of cells is the number of functional cells configured by basic cells. The number of modules I is 2,582, the number of basic cells is 20,597, the number of cells of module II is 6,103, the number of basic cells is 61,596, and the number of cells of module III is 10,585. The number of basic cells was 92,732, the number of cells of module IV was 1,138, and the number of basic cells was 9,485. Therefore, in terms of circuit scale, module IV <module I <module II <module III, where the maximum scale is module III and the minimum scale is module IV.

  As the skew amount setting, for example, when the maximum skew amount is set within the margin range for the largest module III, the clock skew setting circuit 10 adjusts so that the smallest skew amount is set for the next largest module II. Good. In this case, there is an option that the clock skew setting circuit 10 is not inserted into the module II. By maximizing the difference in skew amount between modules having a large circuit scale in this way, the peaks of EMI noise generated in each module are clearly separated on the time axis and do not overlap each other. Thereby, the peak of EMI noise can be reduced.

  Thereafter, the clock skew is set so that the difference in skew amount between modules I and II of module I is maximized, and finally the difference in skew amount between modules I and II of module IV is maximized. The selection of whether or not the setting circuit 10 is inserted and the amount of skew in the clock skew setting circuit 10 are executed.

  FIG. 5 shows a state in which the clock skew setting circuit 10 is inserted as an additional buffer. In FIG. 5, the flip-flop F. F. The clock skew setting circuit 10 is not inserted into the module having the sub-root buffer 42 under the condition that the skew amount allowed until 300 to 500 psec is set, and the module having the sub-root buffer 44 is inserted upstream of the sub-root buffer 44. A clock skew setting circuit 10 is inserted as an additional buffer.

(5) Secondary placement and routing (2ndP & R: Step 5 in FIG. 1)
The insertion and wiring of the clock skew setting circuit 20 described above is performed by secondary arrangement wiring.
Since the primary placement and routing has already been completed, the secondary placement and routing is performed manually using an open space in the primary placement and routing.

(6) Clock tree skew reanalysis (second step 2 in FIG. 1)
After secondary placement and routing, a second skew analysis is performed using a tool called a static timing analyzer (STA) in the same manner as in Step 2 described above. Thus, the skew from the clock source to the end is analyzed, and it is confirmed that the setup / hold time is satisfied in each clock tree. If it can be confirmed, the process ends (step 6 in FIG. 2). If there is a problem, steps 3 to 5 and step 2 are performed again.

(7) Effects of this Embodiment According to the design method as described above, as shown in FIG. F. Since the EMI noise having a large peak is dispersed on the time axis according to the circuit scale, the peak of the EMI noise of the entire IC can be reduced without overlapping the large EMI noise peaks.

  Although the present embodiment has been described in detail as described above, it will be easily understood by those skilled in the art that many modifications can be made without departing from the novel matters and effects of the present invention. Accordingly, all such modifications are intended to be included in the scope of the present invention. For example, a term described at least once together with a different term having a broader meaning or the same meaning in the specification or the drawings can be replaced with the different term in any part of the specification or the drawings.

It is a flowchart of the design method of the synchronous circuit which concerns on embodiment of this invention. It is a schematic diagram of a clock tree obtained by primary placement and routing. It is a circuit diagram which shows an example of a clock skew setting circuit. It is a characteristic view which shows the truth table of the circuit of FIG. It is a figure which shows the example of insertion of a clock skew setting circuit. It is a characteristic view which shows the EMI noise of each module distributed on the time axis by the design method of the embodiment.

Explanation of symbols

  10 clock skew setting circuit, 12, 14 first and second buffer, 20, 22, 24 selector, 30, 32, 34 gate circuit, 40 route buffer, 42, 44 sub route buffer

Claims (8)

A first step of inputting a given condition including a netlist and performing primary placement and routing of a synchronous circuit using an automatic placement and routing tool;
A second step of analyzing a skew, which is a difference in arrival time of the clock from the clock source to each end path, according to the clock tree of the synchronous circuit arranged and routed;
A third step in which the analyzed skew is divided into a plurality of modules having a margin with respect to the setup / hold time;
A fourth step of additionally inserting a clock skew setting circuit into at least one of the plurality of divided modules;
A fifth step of adding the clock skew setting circuit and performing secondary placement and routing;
A method for designing a synchronous circuit, comprising: In claim 1,
In the fourth step, the clock skew setting circuit is provided in at least one of the top two modules so that a maximum skew difference occurs between the top two modules having a large circuit scale among the plurality of modules. A method for designing a synchronous circuit, comprising inserting the synchronous circuit. In claim 2,
In the fourth step, the module having the third largest circuit scale among the plurality of modules has the third largest circuit scale so that the largest skew difference is generated with respect to each of the top two modules. A method for designing a synchronous circuit, wherein the clock skew setting circuit is inserted into a module having a large value. In claim 1,
The clock skew setting circuit has a variable skew amount according to a logic signal,
The method of designing a synchronous circuit, wherein the fourth step includes a step of setting a skew amount of the clock skew setting circuit for each module. In claim 4,
In the fourth step, the clock skew setting circuit is provided in at least one of the top two modules so that a maximum skew difference occurs between the top two modules having a large circuit scale among the plurality of modules. A method for designing a synchronous circuit, comprising: inserting and adjusting a skew amount of the clock skew setting circuit by the logic signal. In claim 5,
In the fourth step, the module having the third largest circuit scale among the plurality of modules has the third largest circuit scale so that the largest skew difference is generated with respect to each of the top two modules. A method of designing a synchronous circuit, wherein the clock skew setting circuit is inserted into a module having a large value, and a skew amount of the clock skew setting circuit is adjusted by the logic signal. In any one of Claims 1 thru | or 6.
The position at which the clock skew setting circuit is inserted into at least one of the plurality of modules is a position that does not cause a skew fluctuation to other modules, and is the most upstream of the at least one of the plurality of modules. A method for designing a synchronous circuit, which is a position further upstream of a buffer. In any one of Claims 1 thru | or 7,
After the fifth step, according to the clock tree to which the clock skew setting circuit is added, a skew that is a difference in arrival time of the clock from the clock source to each terminal path is analyzed, and the analyzed skew is compared with the setup / hold time. A method for designing a synchronous circuit, further comprising a sixth step of verifying whether or not a margin is provided.

Images