JP2008016496A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce the capacity between a gate and a drain in a semiconductor device having a DMOS transistor. <P>SOLUTION: The semiconductor device has: a plurality of second-conductivity-type impurity regions 22 that are formed on a semiconductor layer 20, function as a body region each, and are separated mutually; a first-conductivity-type impurity region 25 that is formed at one portion of the plurality of second-conductivity-type regions 22 and function as sources and drains; a gate insulation film 23 formed on the second-conductivity-type impurity region 22 positioned between the semiconductor layer 20 and the first-conductivity-type impurity region 25 and on the semiconductor layer 20 positioned among the plurality of second-conductivity-type impurity regions 22; and a semiconductor layer 24 that is formed on the gate insulation film 23 and functions as a gate electrode while impurities are introduced to the semiconductor layer 24. The semiconductor layer 24 has a non-doped region 24a where no impurities are introduced at the upper portion of the plurality of second-conductivity-type regions 22. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor device having a DMOS transistor and a method for manufacturing a semiconductor device. In particular, the present invention relates to a semiconductor device capable of reducing the capacitance between a gate and a drain or source and a method for manufacturing the same.

FIG. 5 is a cross-sectional view for explaining the structure of a conventional semiconductor device. The semiconductor device shown in this figure has a plurality of DMOS transistors. The gate oxide film 123 of the DMOS transistor is formed on the P-type silicon layer 120 on the N-type silicon substrate 110, and the gate electrode 124 is formed on the gate oxide film 123. An N-type body region 122 is formed in the silicon layer 120, and a P-type impurity region 125 that functions as a source is formed in the body region 122. A P-type buried layer 111 functioning as a drain is formed in the silicon substrate 110 located below the body region 122.
Thus, since the gate electrode 124 and the buried layer 111 are opposed to each other with the silicon layer 120 and the gate oxide film 123 interposed therebetween, a gate-drain capacitance is generated in the DMOS transistor.
JP-A-6-69508 (third paragraph and FIG. 2)

As described above, the DMOS transistor has a capacitance between the gate and the drain or source. For this reason, it has been difficult to improve the switching speed of the DMOS transistor.
The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a semiconductor device capable of reducing the capacitance between a gate and a drain or a source, and a method for manufacturing the same.

In order to solve the above problems, a semiconductor device according to the present invention includes a body region of a plurality of second conductivity type DMOS transistors formed on a first conductivity type semiconductor substrate or semiconductor layer, and
A first source or drain region of a first conductivity type formed in a part of each of the plurality of body regions;
A gate insulating film formed on the semiconductor substrate or semiconductor layer located between the plurality of first source or drain regions;
A gate electrode formed on the gate insulating film and made of a semiconductor layer;
A second source or drain region of the first conductivity type formed below the body region;
Comprising
The gate electrode has a non-doped region in which an impurity is introduced into a region located above the body region and no impurity is introduced into a region located above the body regions.

  According to this semiconductor device, since the non-doped region is formed in the gate electrode, this portion is depleted. For this reason, the area to which a voltage is applied in the gate electrode is reduced, and the capacitance between the gate electrode and the second source or drain region is reduced.

  When the semiconductor layer is a silicon layer, it is preferable to include a silicide layer formed on the silicon layer. In this way, even if a high resistance non-doped region is provided in the silicon layer, the entire resistance of the silicon layer can be reduced. This eliminates the need to increase the number of contact holes provided in the interlayer insulating film on the silicon layer.

A method of manufacturing a semiconductor device according to the present invention includes a step of forming body regions of a plurality of second conductivity type DMOS transistors on a first conductivity type semiconductor substrate or semiconductor layer;
Forming a gate insulating film on the semiconductor substrate or semiconductor layer;
Forming a gate electrode made of a semiconductor layer on the gate insulating film excluding a part of the body region; and
A step of introducing impurities into a region of the gate electrode located above the body region and not introducing impurities into a region located above the body regions.

  When the gate electrode is a silicon layer, after the step of introducing impurities into the gate electrode, a step of forming a metal layer on the gate electrode, and heating the gate electrode and the metal layer to thereby form the gate And a step of forming a silicide layer on the electrode.

Another method of manufacturing a semiconductor device according to the present invention includes a step of forming body regions of a plurality of second conductivity type DMOS transistors on a first conductivity type semiconductor substrate or semiconductor layer,
Forming a gate insulating film on the semiconductor substrate or semiconductor layer;
Forming a semiconductor film on the gate insulating film;
Introducing the impurity into a region of the semiconductor film located above the body region and not introducing the impurity into a region located above the body regions;
Forming a gate electrode by removing a portion of the semiconductor film located on a part of the body region;
Forming a source or drain region by introducing a first conductivity type impurity into the body region from which the semiconductor film has been removed.

  In this method of manufacturing a semiconductor device, when the semiconductor film is a silicon film, a step of forming a metal layer on the semiconductor film between the step of introducing impurities into the semiconductor film and the step of forming the gate electrode And heating the semiconductor film and the metal layer to form a silicide layer on the semiconductor film, and in the step of forming the gate electrode, the silicide layer and the semiconductor film Of these, it is preferable that a portion located on a part of the body region is removed.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. 1 and 2 are cross-sectional views for explaining a method for manufacturing a semiconductor device according to an embodiment of the present invention. The semiconductor device manufactured by this method has a plurality of DMOS transistors.

  First, as shown in FIG. 1A, a resist pattern (not shown) is formed on a silicon substrate 10 of a first conductivity type (for example, P type), and a first pattern is formed on the silicon substrate 10 using this resist pattern as a mask. Conductive impurities are introduced. As a result, a buried layer 12 of the first conductivity type is formed in the silicon substrate 10. Thereafter, the resist pattern is removed.

  Next, a resist pattern (not shown) is formed on the silicon substrate 10, and a second conductivity type (for example, N-type) impurity is introduced into the silicon substrate 10 using the resist pattern as a mask. As a result, the second conductivity type buried layer 11 is formed in the silicon substrate 10. Thereafter, the resist pattern is removed.

  Next, a second conductivity type silicon layer 20 is epitaxially grown on the silicon substrate 10. Next, a resist pattern (not shown) is formed on the silicon layer 20, and a second conductivity type impurity is introduced into the silicon layer 20 using the resist pattern as a mask. As a result, a diffusion layer 21 of the second conductivity type is formed in the silicon layer 20. The diffusion layer 21 is located on a part of the buried layer 11 and is electrically connected to the buried layer 11. The diffusion layer 21 and the buried layer 11 function as the drain of the DMOS transistor.

  Next, a resist pattern (not shown) is formed on the silicon layer 20, and a first conductivity type impurity is introduced into the silicon layer 20 using the resist pattern as a mask. Thereby, a diffusion layer 20b of the first conductivity type is formed in the silicon layer 20. The diffusion layer 20 b is located on the buried layer 12 and is electrically connected to the buried layer 12. By the diffusion layer 20 b and the buried layer 12, the region where the DMOS transistor is formed in the silicon substrate 10 and the silicon layer 20 is electrically isolated from other regions. Thereafter, the resist pattern is removed.

Next, a resist pattern (not shown) is formed on the silicon layer 20, and a first conductivity type impurity is introduced into the silicon layer 20 using the resist pattern as a mask. The dose amount of the impurity is, for example, 2 × 10 ¹³ / cm ² . As a result, a plurality of body regions 22 of the DMOS transistor are formed in the silicon layer 20 located above the buried layer 11. Thereafter, the resist pattern is removed.

  Next, a mask film (not shown) having a silicon nitride film is formed on the silicon layer 20 by a CVD method, and the silicon layer 20 is thermally oxidized using the mask film as a mask. As a result, an element isolation film 20 a is formed on the silicon layer 20. Thereafter, the mask film is removed.

  Next, the silicon layer 20 is thermally oxidized. Thus, the gate oxide film 23 of the DMOS transistor is formed on the silicon layer 20 over the entire element region where the plurality of DMOS transistors are formed. Next, a polysilicon film is formed on the entire surface including the gate oxide film 23, and this polysilicon film is patterned. As a result, the gate electrode 24 of the DMOS transistor is formed on the gate oxide film 23. The gate electrode 24 is formed on the edge of the body region 22 and above the silicon layer 20 positioned around the body region 22 and above the silicon layer 20 positioned between the body regions 22. Thus, the gate electrode 24 is connected between the plurality of DMOS transistors.

  Next, as shown in FIG. 1B, a photoresist film 70 is formed on part of the gate electrode 24 and part of the body region 22, and the element isolation film 20a, the gate electrode 24, and the photoresist film 70 are formed. As a mask, impurities of the second conductivity type are introduced. As a result, the second conductivity type impurity is introduced into a part of each of the plurality of body regions 22, and the second conductivity type impurity region 25 serving as the source of the DMOS transistor is formed. Further, the impurity concentration in the upper part of the diffusion layer 21 is increased. When viewed from a direction perpendicular to the silicon layer 20, the impurity region 25 has a non-doped region into which the second conductivity type impurity is not introduced at the center. Thus, the impurity region 25 has, for example, a ring shape when viewed from a direction perpendicular to the silicon layer 20.

  In this impurity introduction step, the second conductivity type impurity is introduced into the gate electrode 24 to have conductivity. However, since the region of the gate electrode 24 located above the body region 22 is covered with the photoresist film 70 except for the vicinity of the body region 22, impurities are not introduced, and the non-doped region 24a Become.

  Thereafter, as shown in FIG. 2A, the photoresist film 70 is removed. Next, a photoresist film 71 is formed on the entire surface except on the diffusion layer 20b and the non-doped region located at the center of the impurity region 25, and impurities of the first conductivity type are introduced using the photoresist film 71 as a mask. As a result, the first conductivity type impurity region 26 is formed at the center of the impurity region 25, and the impurity concentration of the upper layer of the diffusion layer 20b is increased.

  Thereafter, as shown in FIG. 2B, the photoresist film 70 is removed. Next, an insulating film (for example, a silicon oxide film) is formed on the entire surface including the gate electrode 24, and this insulating film is etched back. Thereby, the sidewall of the gate electrode 24 is covered with the sidewall. Further, the portion of the gate oxide film 23 that is not covered with the gate electrode 24 is removed.

  Next, a metal film (for example, a W film, a Ti film, a Co film, or a Ni film) is formed on the entire surface including the gate electrode 24, and the metal film and the gate electrode 24 are heat-treated. Thereby, a silicide layer 27 is formed on the entire surface of the gate electrode 24. Thereafter, the non-silicided metal layer is removed.

  The semiconductor device manufactured by the above-described method has a buried layer 11 that functions as a drain of a DMOS transistor on a silicon substrate 10. A silicon layer 20 is formed on the silicon substrate 10. In the silicon layer 20, a plurality of body regions 22 that are separated from each other are formed. Part of the body region 22 is formed by introducing a first conductivity type impurity, and an impurity region 25 that functions as a source of the DMOS transistor is formed. The gate oxide film 23 is formed on the body region 22 located between the impurity region 25 and the silicon layer 20 and on the silicon layer 20 located between the plurality of body regions 22. The gate electrode 24 is formed on the gate oxide film 23.

  The gate electrode 24 has a non-doped region 24 a into which no impurity is introduced above the plurality of body regions 22. For this reason, the gate electrode 24 is depleted in the portion located between the plurality of body regions 22. Therefore, the gate / drain capacitance of the DMOS transistor is reduced, and the switching speed of the DMOS transistor is increased.

  Further, since the silicide layer 27 is formed on the gate electrode 24, the entire surface of the gate electrode 24 has a low resistance even when the high resistance non-doped region 24a is formed between the plurality of body regions 22. Can be Therefore, it is not necessary to increase the number of contact holes (not shown) provided in the interlayer insulating film (not shown) on the gate electrode 24.

  Each of FIGS. 3 and 4 is a cross-sectional view for explaining a method for manufacturing a semiconductor device according to the second embodiment. Hereinafter, the same components as those in the first embodiment are denoted by the same reference numerals, and description thereof is omitted.

  First, as shown in FIG. 3A, the buried layers 11 and 12 are formed in the silicon substrate 1. Next, a silicon layer 20 and diffusion layers 20b and 21, a plurality of body regions 22 of the DMOS transistor, an element isolation film 20a, and a gate oxide film 23 are formed. These forming methods are the same as those in the first embodiment.

  Next, a polysilicon film 24 c is formed on the entire surface including the element isolation film 20 a and the gate oxide film 23. Next, a region located above the plurality of body regions 22 in the polysilicon film 24 c is covered with the silicon oxide film 72 except for the vicinity of the body region 22. Next, a second conductivity type impurity is introduced into the polysilicon film 24c by using, for example, thermal diffusion or ion implantation using the silicon oxide film 72 as a mask. Thereby, the resistance of the polysilicon film 24c is reduced, and the non-doped region 24a is formed.

  Thereafter, the silicon oxide film 72 is removed as shown in FIG. Next, a metal film (for example, a W film, a Ti film, a Co film, or a Ni film) is formed on the polysilicon film 24c, and the metal film and the polysilicon film 24c are heat-treated. As a result, a silicide layer 27 is formed on the entire surface of the polysilicon film 24c. Thereafter, the non-silicided metal layer is removed.

  Next, as shown in FIG. 4A, a resist pattern (not shown) is formed on the polysilicon film 24c, and the polysilicon film 24c is etched using the resist pattern as a mask. Thereby, the polysilicon film 24c is selectively removed, and the gate electrode 24 is formed. Thereafter, the resist pattern is removed.

Next, as shown in FIG. 4B, impurity regions 25 and 26 are formed. These forming methods are the same as those in the first embodiment. In the present embodiment, the sidewall 24b is not formed.
As described above, also in the second embodiment, the same effect as that in the first embodiment can be obtained.

  Note that the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the spirit of the present invention.

FIGS. 4A and 4B are cross-sectional views for explaining a method for manufacturing a semiconductor device according to the first embodiment. FIGS. (A), (B) is sectional drawing for demonstrating the next process of FIG. 9A and 9B are cross-sectional views for explaining a method for manufacturing a semiconductor device according to a second embodiment. (A), (B) is sectional drawing for demonstrating the next process of FIG. Sectional drawing for demonstrating the structure of the conventional semiconductor device.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10,110 ... Silicon substrate, 11, 12, 111 ... Embedded layer, 20, 120 ... Silicon layer, 20a ... Element isolation film, 20b, 21 ... Diffusion layer, 22, 122 ... Body region, 23, 123 ... Gate oxidation Films 24, 124 ... gate electrodes, 24a ... non-doped regions, 24b ... sidewalls, 24c ... polysilicon films, 25, 26, 125 ... impurity regions, 27 ... silicide layers, 70, 71 ... photoresist films, 72 ... oxidation Silicon film

Claims (6)

Body regions of a plurality of second conductivity type DMOS transistors formed on the first conductivity type semiconductor substrate or semiconductor layer;
A first source or drain region of a first conductivity type formed in a part of each of the plurality of body regions;
A gate insulating film formed on the semiconductor substrate or semiconductor layer located between the plurality of first source or drain regions;
A gate electrode formed on the gate insulating film and made of a semiconductor layer;
A second source or drain region of the first conductivity type formed below the body region;
Comprising
The semiconductor device, wherein the gate electrode has a non-doped region in which impurities are introduced into a region located above the body region and no impurity is introduced in a region located above the body regions. The semiconductor layer is a silicon layer;
The semiconductor device according to claim 1, further comprising a silicide layer formed on the silicon layer. Forming a plurality of second conductivity type DMOS transistor body regions on a first conductivity type semiconductor substrate or semiconductor layer;
Forming a gate insulating film on the semiconductor substrate or semiconductor layer;
Forming a gate electrode made of a semiconductor layer on the gate insulating film excluding a part of the body region; and
A step of introducing impurities into a region of the gate electrode located above the body region and not introducing impurities into a region located above the body regions;
A method for manufacturing a semiconductor device comprising: The gate electrode is a silicon layer;
After introducing the impurity into the gate electrode,
Forming a metal layer on the gate electrode;
Forming a silicide layer on the gate electrode by heating the gate electrode and the metal layer;
A method for manufacturing a semiconductor device according to claim 3, comprising: Forming a plurality of second conductivity type DMOS transistor body regions on a first conductivity type semiconductor substrate or semiconductor layer;
Forming a gate insulating film on the semiconductor substrate or semiconductor layer;
Forming a semiconductor film on the gate insulating film;
Introducing the impurity into a region of the semiconductor film located above the body region and not introducing the impurity into a region located above the body regions;
Forming a gate electrode by removing a portion of the semiconductor film located on a part of the body region;
Forming a source or drain region by introducing a first conductivity type impurity into the body region from which the semiconductor film has been removed;
A method for manufacturing a semiconductor device comprising: The semiconductor film is a silicon film;
Between the step of introducing impurities into the semiconductor film and the step of forming the gate electrode,
Forming a metal layer on the semiconductor film;
Forming a silicide layer on the semiconductor film by heating the semiconductor film and the metal layer;
Comprising
The method for manufacturing a semiconductor device according to claim 5, wherein in the step of forming the gate electrode, a portion of the silicide layer and the semiconductor film located on a part of the body region is removed.

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