JP2008005882A - Computer for game machine, game machine, and game machine control method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide gradation control technologies capable of improving the smoothness of the gradation expression of LEDs mounted in a game machine. <P>SOLUTION: A peripheral control CPU of a peripheral control board 420 in the pachinko machine 10 selects a gradation value table 540 stored in a modulated light storage part 4215 according to the progress of a game (a step S8222), selects an array table 560 stored in the modulated light storage part 4215 (a step S8224), generates gradation pattern data 580 based on the combination of selected gradation value table 540 and array table 560 (a step S870), and transmits the generated gradation pattern data 580 as a command to control a panel illumination board 430. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a gradation control technique for controlling the light emission luminance of a light emitting diode (hereinafter referred to as “LED”) provided in a gaming machine.

  In recent years, gaming machines such as pachinko machines and slot machines have been used with LEDs in combination with a liquid crystal display (hereinafter referred to as “LCD”) for displaying moving images in order to enhance the fun of gaming. is there. In general, since it is difficult to realize the gradation control of the LED by increasing or decreasing the current value of the LED, the LED gradation control is performed by switching the pulse width of the current supplied to the LED to emit light from the LED. PWM control (Pulse Width Modulation Control) for adjusting the brightness is used, and gradation control by PWM control is also performed in LEDs used in gaming machines. As a situation peculiar to gaming machines, LED PWM control is synchronized with the LCD image rewriting cycle in order to enhance the fun of the game by linking the effects of LCD image display and LED gradation control. Done.

  Conventionally, as one of the gradation control technologies for LEDs in gaming machines, LED current pulses per image rewrite cycle are converted into unit time interrupt units of a central processing unit (hereinafter referred to as “CPU”). There was a method to change in. In this method, for example, when the image rewriting cycle of the LCD is 16 milliseconds (hereinafter referred to as “ms”) and the periodic interrupt cycle of the CPU is 2 ms, the pulse width is set to “0 ms”, “ It is possible to control the gradation of the LED in 9 gradations (including extinguishing) by changing in units of 2 ms of “2 ms”, “4 ms”,..., “14 ms”, “16 ms”. In gradation control in which the pulse width is changed in units of scheduled interrupts, the fineness of the gradation change of the LED depends on the periodic interrupt period that can be executed by the CPU per image rewriting period of the LCD. Patent Document 1 below discloses a conventional gradation control technique in a gaming machine.

JP 2003-190410 A

  Despite the demand for multi-gradation that achieves the light emission luminance of the LED with smooth gradation expression in the gaming machine, the conventional gradation control technology is synchronized with the LCD image rewriting cycle. In order to realize multi-gradation of LEDs, it is necessary to set the periodic interrupt cycle to be shorter within the limited processing capability of the CPU. It was difficult.

  In view of the above-described problems, an object of the present invention is to provide a gradation control technique capable of improving the smoothness of gradation expression of LEDs provided in a gaming machine.

  In order to solve the above-described problem, the gaming machine computer according to the present invention changes the emission luminance of the light emitting diode to a plurality of gradation values by switching the pulse width of the driving current for the light emitting diode provided in the gaming machine. A computer for a gaming machine that controls a gradation control circuit, a gradation value table storage means for storing a plurality of gradation value tables each specifying some of the plurality of gradation values, and the gradation value An array table storage means for storing a plurality of array tables each defining an array for arranging the gradation values specified in the table, and at least one of the plurality of gradation value tables is used for game progress in the gaming machine. According to the progress of the game in the gaming machine, the gradation value table selecting means to select according to the at least one of the plurality of arrangement tables Array table selection means for selecting, pattern data generation means for generating gradation pattern data in which the gradation values specified in the selected gradation value table are arranged according to the arrangement specified in the selected arrangement table; Command transmission means for transmitting the generated gradation pattern data to the gradation control circuit as a command for controlling the gradation control circuit. According to the gaming machine computer described above, the gradation pattern data based on the combination of the gradation value table and the array table is output from the gaming machine computer to the gradation control circuit without having to synchronize with the periodic interrupt cycle. Therefore, it is possible to suppress an increase in processing load on the gaming machine computer due to the multi-gradation of LEDs. As a result, the smoothness of the gradation expression of the LEDs provided in the gaming machine can be improved.

  The gaming machine computer described above can also take the following modes. For example, the gradation value table generating means for generating a new gradation value table and the gradation value table for updating the stored existing gradation value table to the generated new gradation value table. Update means. Thereby, the computer for gaming machines can generate gradation pattern data that realizes various gradation expressions by LEDs by updating the gradation value table as the game progresses.

  Furthermore, it may further comprise an array table generating means for generating a new array table and an array table updating means for updating the stored existing array table to the generated new array table. Accordingly, the gaming machine computer can generate gradation pattern data that realizes various gradation expressions by the LEDs by updating the arrangement table according to the progress of the game.

  Further, it may include a mode determining unit that determines a playback mode of the generated light emission pattern data, and a mode command unit that commands the determined playback mode to the gradation control circuit. Thus, the gaming machine computer can realize various gradation expressions by the LED using the same gradation pattern data by determining the reproduction mode of the gradation pattern data according to the progress of the game. For example, the light emission pattern reproduction mode includes at least one of a reproduction mode in which the light emission pattern is repeatedly reproduced and a reproduction mode in which the last gradation value in the light emission pattern is maintained after the light emission pattern is reproduced in a single shot. It is also good.

  In order to solve the above-described problems, the gaming machine control method according to the present invention switches the emission width of the light emitting diode to a plurality of gradation values by switching the pulse width of the driving current for the light emitting diode provided in the gaming machine. A gaming machine control method for controlling a gradation control circuit to be changed by a gaming machine computer, wherein the gaming machine computer has a plurality of gradation value tables each designating some of the plurality of gradation values. A step of storing, a step of storing a plurality of arrangement tables each defining an arrangement in which the gaming machine computer arranges the gradation values designated in the gradation value table, and the gaming machine computer includes the plurality of gaming machines. Selecting at least one of the gradation value tables according to the progress of the game in the gaming machine, and the gaming machine computer, A step of selecting at least one of the plurality of arrangement tables according to the progress of the game in the gaming machine, and the computer for the gaming machine selects a gradation value designated in the selected gradation value table, A step of generating gradation pattern data arranged in accordance with an arrangement defined in the selected arrangement table; and the gaming machine computer uses the generated gradation pattern data as a command for controlling the gradation control circuit. And a step of transmitting to the gradation control circuit. According to the above gaming machine control method, the gradation pattern data based on the combination of the gradation value table and the array table is output from the gaming machine computer to the gradation control circuit without being synchronized with the periodic interrupt cycle. Therefore, it is possible to suppress an increase in processing load on the gaming machine computer due to the multi-gradation of LEDs. As a result, the smoothness of the gradation expression of the LEDs provided in the gaming machine can be improved.

  Note that the aspect of the present invention is not limited to a gaming machine computer or a gaming machine control method, but includes a variety of gaming machines including the gaming machine computer of the present invention, a computer program for controlling a gradation control circuit, and the like. It is possible to apply to the aspect of this. Note that gaming machines to which the present invention is applied include pachinko machines and slot machines.

  In order to further clarify the configuration and operation of the present invention described above, a gaming machine to which the present invention is applied will be described below.

A. Configuration of the pachinko machine 10:
A configuration of the pachinko machine 10 that is one of the embodiments of the present invention will be described. FIG. 1 is a front view showing the overall configuration of the pachinko machine 10. The pachinko machine 10 includes an outer frame 20 fixed to a so-called island facility of a pachinko store, an inner frame 30 fitted into the outer frame 20, and a gaming panel that is fitted near the center of the inner frame 30 to play a game ball. 40, a glass frame 50 having a glass plate covering the front surface of the game panel 40 and pivotally attached to the inner frame 30 so as to be openable and closable, and a card unit 80 for accepting rental of game balls by a prepaid card.

  The gaming panel 40 of the pachinko machine 10 includes a winning opening 44 for receiving a winning game ball, an LCD unit 42 for displaying an image as a game effect, and a plurality of light emitting diodes (LEDs) 462 that emit light as a game effect. An illumination unit 46, an effect drive unit 45 that moves a character doll as an effect of the game, and an effect sensor 47 that senses the infrared rays of the hand held by the player in order to allow the player to select an effect mode of the game. The winning opening 44 includes a gaming ball sensor 442 that detects a game ball that has won the winning opening 44 and a winning opening driver 444 that expands or contracts the introduction path of the gaming ball to the winning opening 44. In the present embodiment, the game ball sensor 442 includes an eddy current type sensor, the winning opening driving unit 444 includes a mechanism that drives a solenoid (not shown) as a power source, and the effect driving unit 45 includes steps. A mechanism for driving a motor (not shown) as a power source is included. In this embodiment, the LCD unit 42 includes a liquid crystal display (LCD), and further includes a liquid crystal control board having an electronic circuit that outputs a video signal to the LCD and controls image display on the LCD.

  The glass frame 50 of the pachinko machine 10 includes a speaker 55 that outputs high-frequency sound as a game effect, and an electrical decoration unit 56 that includes a plurality of light emitting diodes (LEDs) 562 that emit light as a game effect. The inner frame 30 of the pachinko machine 10 includes a handle 32 that receives an operation by the player for launching a game ball on the game panel 40, a speaker 34 that outputs a low-frequency sound as a game effect, and a game to the player. In order to select an effect mode, an effect sensor 36 that detects button input from the player is provided.

  FIG. 2 is a block diagram showing an electrical schematic configuration of the pachinko machine 10. The pachinko machine 10 controls the progress of the game based on the input from the game ball sensor 442, and the production of each part according to the progress of the game based on the main command that is an instruction from the main control board 410 A peripheral control board 420 that controls the brightness, a panel illumination board 430 that controls the luminance gradation of the LED 462 based on a gradation command that is an instruction from the peripheral control board 420, and various signals from the peripheral control board 420 10 from the peripheral distribution board 440 distributed to each part, a frame lighting board 450 for controlling the luminance gradation of the LED 562 based on an instruction from the peripheral control board 420 via the peripheral distribution board 440, and the main control board 410 A payout control board 310 that controls payout of game balls based on a payout command as an instruction. The circuit boards of the main control board 410, the peripheral control board 420, the panel electric decoration board 430, the peripheral distribution board 440, the frame electric decoration board 450, and the payout control board 310 are the back surfaces (not shown) of the inner frame 30 shown in FIG. ).

  In the present embodiment, the main control board 410, the peripheral control board 420, and the payout control board 310 include a gaming machine computer designed exclusively for gaming machines, and a CPU for executing various computing processes and a computing process of the CPU. Read-only memory (hereinafter referred to as “ROM”) that pre-stores prescribed programs, random access memory (hereinafter referred to as “RAM”) that temporarily stores data handled by the CPU, etc. And an electronic circuit on which electronic components corresponding to the function of each circuit board are mounted. In this embodiment, the panel illumination board 430, the peripheral distribution board 440, and the frame illumination board 450 are each a large scale integrated circuit (Large Scale Integration, hereinafter referred to as “LSI”) corresponding to the function of each circuit board. An electronic circuit on which electronic components corresponding to the function of the circuit board are mounted is provided.

  The main command transmitted from the main control board 410 to the peripheral control board 420 includes information for instructing basic effects relating to the game such as so-called “big hit” and “out of play”. The peripheral control board 420 that has received the main command from the main control board 410 performs effects performed by the effect execution units such as the LCD unit 42, the LED 462, the LED 562, the speaker 34, the speaker 55, and the effect drive unit 45 based on the main command. And outputs various signals according to each production execution unit. The signal from the peripheral control board 420 to the LCD unit 42 includes a liquid crystal command for instructing the LCD unit 42 of the content of the video to be displayed. The signal from the peripheral control board 420 to the panel illumination board 430 includes a gradation command that specifies the light emission mode of the LED 462. In this embodiment, the transfer of the liquid crystal command from the peripheral control board 420 to the LCD unit 42 is executed in accordance with 16 ms that is the screen update timing of the LCD unit 42. In this embodiment, signals from the peripheral control board 420 including the liquid crystal command to the panel lighting board 430 are transferred from the peripheral control board 420 to the panel at a transfer rate of 250 kilobits per second (hereinafter referred to as “bps”). Serial transfer to the illumination board 430 is performed.

A-1. Detailed configuration of peripheral control board 420 in pachinko machine 10:
FIG. 3 is a block diagram mainly showing an electrical configuration of the peripheral control board 420 in the pachinko machine 10. The peripheral control board 420 includes a gaming machine computer, and includes a peripheral control CPU 4210 that executes arithmetic processing for controlling effects according to the progress of the game, and a watchdog timer (Watchdog Timer) that monitors the operating state of the peripheral control CPU 4210. (Hereinafter referred to as “WDT”) 4211, a ROM 4212 that preliminarily stores a program that prescribes arithmetic processing of the peripheral control CPU 4210, a RAM 4214 that temporarily stores data handled by the peripheral control CPU 4210, and a light emission mode of the LED 462 A dimming storage unit 4215 for storing data used for the purpose, and a bus 4216 for connecting the peripheral control CPU 4210 to each circuit unit in the peripheral control board 420 so as to exchange data. In the present example, the dimming storage unit 4215 of the peripheral control board 420 is configured by a RAM different from the RAM 4214. However, as another embodiment, the dimming storage unit 4215 may be configured by the RAM 4214.

  FIG. 4 is an explanatory diagram showing details of the light control storage unit 4215 in the peripheral control board 420. The dimming storage unit 4215 defines a gradation value table 540 that specifies some of the gradation values that can be controlled by the panel illumination board 430 and an array that arranges the gradation values specified in the gradation value table 540. Pattern generation table that designates the arrangement table 560, the gradation pattern data 580 indicating the manner in which the gradation value of the LED 452 is changed, the gradation value table 540 used to generate the gradation pattern data 580, and the arrangement table 560 520 are stored. In this embodiment, the data stored in the dimming storage unit 4215 includes initial data transferred from the ROM 4212 when the pachinko machine 10 is powered on, and data that is appropriately updated by the peripheral control CPU 4210 as the game progresses. Including.

  FIG. 5 is an explanatory diagram schematically showing a plurality of gradation value tables 540 stored in the dimming storage unit 4215 of the peripheral control board 420. Each of the gradation value tables 540 of the dimming storage unit 4215 specifies the gradation value table number 5410 for specifying each of the gradation value tables 540 and each of the gradation values specified in the gradation value table 540. A gradation number 5420 and a gradation value 5430 in which light emission luminance is specified with a pulse width that can be controlled by the panel electrical decoration substrate 430 are provided. In the present embodiment, an integer from “0” to “7” is assigned to the gradation value table number 5410 of the dimming storage unit 4215, and a total of eight gradation value tables 540 are included in the dimming storage unit. 4215 is stored. In this embodiment, an integer from “0” to “31” is assigned to each gradation value table 540 to the gradation number 5420 of the light control storage unit 4215, and the total per one gradation value table 540 is the total. Thirty-two gradation values are set. In this embodiment, the gradation value 5430 of the dimming storage unit 4215 is set to any one of pulse widths of “1 μs” from “0 μs” to “4000 μs” that can be controlled by the panel electrical decoration board 430. .

  FIG. 6 is an explanatory diagram schematically showing a plurality of arrangement tables 560 stored in the dimming storage unit 4215 of the peripheral control board 420. Each of the arrangement tables 560 of the dimming storage unit 4215 includes an arrangement table number 5610 that identifies each of the arrangement tables 560, an arrangement number 5620 that indicates the order in which the gradation values 5430 designated in the gradation value table 540 are arranged, And a corresponding gradation number 5630 indicating the gradation number 5420 of the gradation value table 540 associated with the array number 5620. In this embodiment, integers from “0” to “2” are assigned to the array table number 5610 of the dimming storage unit 4215, and a total of three array tables 560 are stored in the dimming storage unit 4215. The In the present embodiment, an integer from “0” to “89” is assigned to the array number 5620 of the dimming storage unit 4215 for each array table 560, and a total of 90 gradation values per array table 560 are assigned. An array composed of 5430 is set. In this embodiment, an integer from “0” to “31” indicating the gradation number 5420 of the gradation value table 540 is set in the corresponding gradation number 5630 of the dimming storage unit 4215.

  FIG. 7 is an explanatory diagram showing the pattern generation table 520 stored in the dimming storage unit 4215 of the peripheral control board 420. The pattern generation table 520 of the dimming storage unit 4215 includes a port number 5210 for specifying each output terminal that outputs a drive current to the LED 462 in the panel illumination board 430, and a gradation value table 540 associated with the port number 5210. Is provided with a gradation value table number 5220 for specifying the array table and an array table number 5230 for specifying the array table 560 associated with the port number 5210. Thereby, the combination of the gradation value table 540 and the arrangement table 560 is specified for each output terminal of the panel electrical decoration board 430.

  In the present embodiment, an integer from “0” to “63” is assigned to the port number 5210 of the pattern generation table 520 corresponding to 64, which is the total number of output terminals of the panel illumination board 430. . In this embodiment, an integer from “0” to “7” corresponding to the gradation value table number 5410 of the gradation value table 540 is set in the gradation value table number 5220 of the pattern generation table 520. The In this embodiment, an integer from “0” to “2” corresponding to the array table number 5610 of the array table 560 is set in the array table number 5230 of the pattern generation table 520. In the example shown in FIG. 7, the gradation pattern of the terminal corresponding to the port number 5210 of “0” is the gradation value specified in the gradation value table 540 specified by the gradation value table number 5410 of “0”. A pattern in which 5430 are arranged in accordance with the array table 560 specified by the array table number 5610 of “0” is shown. In the example shown in FIG. 7, the gradation pattern of the terminal corresponding to the port number 5210 of “1” is the gradation value specified in the gradation value table 540 specified by the gradation value table number 5410 of “0”. A pattern in which 5430 are arranged in accordance with the arrangement table 560 specified by the arrangement table number 5610 of “1” is shown. In the example shown in FIG. 7, the gradation pattern of the terminal corresponding to the port number 5210 of “62” is the gradation value specified in the gradation value table 540 specified by the gradation value table number 5410 of “1”. A pattern in which 5430 are arranged in accordance with the array table 560 specified by the array table number 5610 of “0” is shown.

  The pattern generation table 520 in FIG. 7 is a data specifying the details of the gradation pattern data 580 generated based on the pattern generation table 520, and the start of specifying the start point of the gradation pattern in the array element number 5620 of the array table 560. And an end array number 5250 that specifies an end point of the gradation pattern among the array numbers 5620 of the array table 560. In the present embodiment, an integer from “0” to “89” corresponding to the array number 5620 of the array table 560 is set in the start array number 5240 and the end array number 5250 of the pattern generation table 520. In the example shown in FIG. 7, the gradation pattern of the terminal corresponding to the port number 5210 of “0” is the corresponding gradation number 5630 in the order of the array number 5620 from “0” to “3” specified in the array table 560. The pattern which arranged is shown. In the example shown in FIG. 7, the gradation pattern of the terminal corresponding to the port number 5210 of “1” is the corresponding gradation number 5630 in the order of the array numbers 5620 from “29” to “74” specified in the array table 560. The pattern which arranged is shown. In the example shown in FIG. 7, the gradation pattern of the terminal corresponding to the port number 5210 of “3” starts from “0” after reaching “89” from “87” in the array number 5620 specified in the array table 560. A pattern in which corresponding gradation numbers 5630 are arranged in the order of reaching “6” is shown.

  The pattern generation table 520 of FIG. 7 is a data that specifies the details of the gradation pattern data 580 generated based on the pattern generation table 520, and is used when the gradation pattern data 580 is reproduced on the panel illumination board 430. It further includes a gradation step value 5260 that defines the degree of reproduction speed at which the gradation value in the gradation pattern is shifted to the next gradation value, that is, the number of times the same gradation value is repeated. In this embodiment, the gradation step value 5260 of the pattern generation table 520 is set to any integer from “0” to “63”, and the value set to the gradation step value 5260 is “n”. Then, after reproduction of “(n + 1) × 4” ms per gradation value, ie, “(n + 1)” reproduction per gradation value, reproduction of the next gradation value is performed. Is done. In the example illustrated in FIG. 7, the gradation pattern of the terminal corresponding to the port number 5210 of “0” indicates a pattern in which “2 (= 1 + 1)” reproduction is performed per gradation value, “1”. The gradation pattern of the terminal corresponding to the port number 5210 of “” indicates a pattern in which “57 (= 56 + 1)” reproduction is performed per gradation value.

  The pattern generation table 520 of FIG. 7 includes a mode number 5270 that specifies the reproduction mode of the gradation pattern data 580 reproduced on the panel electrical decoration board 430, and the gradation value table 540 when the mode number 5270 is “0”. And a mode 0 gradation number 5280 specifying the gradation number 5420. In this embodiment, the mode number 5270 of the pattern generation table 520 is set to any integer from “0” to “2”. In this embodiment, the mode 0 gradation number 5280 of the pattern generation table 520 is set to any integer from “0” to “31” indicating the gradation number 5420 of the gradation value table 540.

  In this embodiment, when the mode number 5270 is “0”, the gradation pattern that maintains the gradation value 5430 corresponding to the gradation number 5420 of the gradation value table 540 specified by the mode 0 gradation number 5280. Data 580 is reproduced by the panel illumination board 430. In the example shown in FIG. 7, the gradation pattern data 580 of the terminal corresponding to the port number 5210 of “2” is “31” in the gradation value table 540 specified by the gradation value table number 5410 of “7”. A gradation pattern maintaining a gradation value 5430 corresponding to the gradation number 5420 is shown. In this embodiment, when the mode number 5270 is “1”, the panel illumination board 430 executes a reproduction mode in which the gradation pattern data 580 is repeatedly reproduced. In this embodiment, when the mode number 5270 is “2”, a reproduction mode in which the last gradation value in the gradation pattern is sustained after the gradation pattern data 580 is reproduced once is displayed on the panel lighting. Performed by the substrate 430.

  Returning to the description of FIG. 3, the peripheral control board 420 exchanges data with the LCD unit 42 and the main control interface 4222 that receives data from the main control board 410 as an interface with other circuit boards in the pachinko machine 10. A liquid crystal interface 4224, an electrical decoration interface 4226 for exchanging data with the panel electrical decoration board 430, and a distribution interface 4228 for exchanging data with the peripheral distribution board 440 are provided. In this embodiment, the main control interface 4222, the liquid crystal interface 4224, and the distribution interface 4228 are parallel interfaces that exchange signals in a parallel transfer system, and the electrical decoration interface 4226 is a serial interface that exchanges signals in a serial transfer system. . The illumination interface 4226 includes a serial transfer buffer 4227 that stores data to be serially transferred. When the peripheral control CPU 4210 stores data in the serial transfer buffer 4227, the electrical decoration interface 4226 serially transfers the stored data to the panel electrical decoration board 430. The data serially transferred to the panel illumination board 430 by the illumination interface 4226 includes the gradation pattern data 580 stored in the light adjustment storage unit 4215.

  The peripheral control board 420 serves as a buffer memory for storing data exchanged with other circuit boards, and a main command reception buffer 4230 for temporarily storing the main command received from the main control board 410, and the LCD unit 42. A liquid crystal command transmission buffer 4250 that temporarily stores a liquid crystal command before being transmitted to the sensor, a sensor input reception buffer 4240 that temporarily stores sensor input data received from the panel illumination board 430 and the peripheral distribution board 440, and a floor Lighting control buffers 4262 and 4264 for temporarily storing light control data relating to gray scale control such as a gray scale command including the gray scale pattern data 580 before transmission to the panel electrical decoration board 430, frame electrical decoration board 450, and effects Various data for driving the drive unit 45, the speaker 34, the speaker 55, etc. And a distribution transmission buffer 4270 for temporarily storing before sending to 40. In this embodiment, the main command reception buffer 4230, liquid crystal command transmission buffer 4250, sensor input reception buffer 4240, electrical transmission buffer 4262, electrical transmission buffer 4264, and distributed transmission buffer 4270 employ a ring buffer configuration. . In the present embodiment, the dimming data is transferred from the peripheral control board 420 to the panel lighting board 430 using a double buffer system in which two lighting transmission buffers 4262 and 4264 are used alternately. Details of the operation of the peripheral control board 420 will be described later.

A-2. Detailed configuration of panel illumination board 430 in pachinko machine 10:
FIG. 8 is a block diagram mainly showing an electrical configuration of the gradation control LSI 4300 mounted on the panel electrical decoration board 430 in the pachinko machine 10. The gradation control LSI 4300 of the panel illumination board 430 has a gradation control function for controlling the light emission luminance of the LED 462 to change to a plurality of gradation values, and a sensor input function for receiving an input from the effect sensor 47. The integrated circuit is realized as a main function of the decorative board 430, and is mounted on the panel electric decoration board 430 together with other electronic components.

  The gradation control LSI 4300 serves as an interface with the peripheral control board 420, and a serial transfer circuit 4310 for exchanging data with the peripheral control board 420 by serial transfer, and access from the peripheral control board 420 via the serial transfer circuit 4310. And an access management circuit 4320 for management. The access management circuit 4320 of the gradation control LSI 4300 operates as a command receiving unit that receives gradation commands from the peripheral control board 420 via the serial transfer circuit 4310. The gradation control LSI 4300 further includes a noise removal circuit 4312 that removes noise of an input signal input from the peripheral control board 420 to the serial transfer circuit 4310. In this embodiment, the noise removal circuit 4312 samples the input signal from the peripheral control board 420 four times at a sampling rate of 50 nanoseconds (hereinafter referred to as “ns”), When all the values are “0”, the value “0” is output to the serial transfer circuit 4310, and when all four consecutively sampled values are “1”, the value “1” is serially transferred. Output to the circuit 4310. In this embodiment, when the four values sampled consecutively do not match, the noise removal circuit 4312 outputs the value that matched four times last time to the serial transfer circuit 4310.

  The gradation control LSI 4300 includes an output terminal 4360 and an input / output terminal 4370 for outputting a drive current to the LED 462 as connection terminals connected to the LED 462 and the effect sensor 47. The input / output terminal 4370 has a function as an input port for receiving sensor inputs from various sensors in addition to a function as an output port for outputting a drive current to the LED. In this embodiment, the input / output terminal 4370 functions as an output port that outputs a drive current to the LED 462 when connected to the LED 462, and from the effect sensor 47 when connected to the effect sensor 47. It functions as an input port that accepts sensor inputs.

  The gradation control LSI 4300 includes a gradation pattern storage unit 4350 that stores gradation pattern data 580 included in the gradation command received from the peripheral control board 420, and gradation pattern data 580 stored in the gradation pattern storage unit 4350. And a pulse control circuit 4355 for supplying the LED drive current with the pulse width switched in accordance with the LED 462.

  In this embodiment, the gradation command received from the peripheral control board 420 includes data indicating the memory address assigned to the storage area of the gradation pattern storage unit 4350 and data to be stored at the memory address. The access management circuit 4320 executes writing of data into the gradation pattern storage unit 4350 based on the gradation command, so that gradation pattern data 580 is configured in the gradation pattern storage unit 4350. In the present embodiment, the gradation pattern data 580 of the gradation pattern storage unit 4350 is stored with initial data based on the gradation command received from the peripheral control board 420 when the pachinko machine 10 is turned on, and according to the progress of the game. And updated as appropriate based on the gradation command from the peripheral control board 420.

  In this embodiment, the gradation pattern data 580 stored in the gradation pattern storage unit 4350 is set for each of the output terminal 4360 and the input / output terminal 4370. Specifically, since the gradation control LSI 4300 of this embodiment has a total of 64 ports including 56 output terminals 4360 and 8 input / output terminals 4370, the gradation pattern storage unit 4350 includes Stores 64 gradation pattern data 580 corresponding to each of the 64 terminals.

  In this embodiment, the pulse control circuit 4355 of the gradation control LSI 4300 is a logic circuit configured by combining a plurality of up / down counters and a plurality of registers. In this embodiment, the pulse control circuit 4355 of the gradation control LSI 4300 has a pulse width of 4000 microseconds (hereinafter referred to as “μs”), that is, an LED driving current per 4 ms from “0 μs” to “4000 μs”. It can be controlled in units of “1 μs”. In the present embodiment, the light emission luminance of the LED 462 becomes brighter as the value of the pulse width of the LED drive current increases. For example, when the pulse width is “0 μs”, the light emission luminance of the LED 462 is in the darkest off state, and when the pulse width is “4000 μs”, the light emission luminance of the LED 462 is in the brightest light emission state.

  The gradation control LSI 4300 serves as a sensor input unit that receives sensor inputs, an input management circuit 4340 that manages sensor inputs from the input / output terminal 4370, and a direction register that stores a flag that specifies an input / output state at the input / output terminal 4370. 4342 and an input register 4344 for storing data input to the input / output terminal 4370. The input management circuit 4340 switches the input / output state of the input / output terminal 4370 based on the flag stored in the direction register 4342 and stores the data input to the input / output terminal 4370 in the input state in the input register 4344. The flag of the direction register 4342 is stored by the access management circuit 4320 in accordance with a command from the peripheral control board 420. The sensor input data of the input register 4344 is transferred to the peripheral control board 420 via the serial transfer circuit 4310 and the access management circuit 4320 in accordance with a command from the peripheral control board 420.

B. Operation of the pachinko machine 10:
B-1. Operation of peripheral control board 420:
FIG. 9 is a flowchart showing a peripheral control process executed by the peripheral control CPU 4210 of the peripheral control board 420. The peripheral control CPU 4210 of the peripheral control board 420 starts the peripheral control process of FIG. 9 when the peripheral control board 420 is powered on.

  When the peripheral control CPU 4210 of the peripheral control board 420 starts the peripheral control process of FIG. 9, after the initial setting (step S410), is the 16 ms flag indicating the progress of the peripheral control process set to “1”? It is determined whether or not (step S420). In this embodiment, the 16 ms flag is set to “1” at the initial setting (step S410).

  If the 16 ms flag is set to “1” (step S420), the peripheral control CPU 4210 sets the 16 ms flag to “0” (step S430), and then is in steady processing indicating the progress of the peripheral control processing. The flag is set to “1” (step S440). In this embodiment, the steady processing flag is set to “0” at the time of initial setting (step S410). After the steady processing flag is set to “1” (step S440), the peripheral control CPU 4210 executes 16 ms steady processing (step S460) performed at 16 ms intervals. After the 16 ms steady process (step S460) is executed, the peripheral control CPU 4210 sets the steady process flag to “0” and determines whether the 16 ms flag is set to “1” (step S420). The process from is repeated.

  10 and 11 are flowcharts showing details of the 16 ms steady process (step S640) in the peripheral control process (FIG. 9). When the peripheral control CPU 4210 of the peripheral control board 420 starts the 16 ms steady process (step S640), it increments a process counter indicating the number of executions of the 16 ms steady process (step S4601). In this embodiment, the process counter is set to “0” at the time of initial setting (step S410). After the process counter is incremented (step S4601), the peripheral control CPU 4210 starts a processing time timer that measures the elapsed time of the 16 ms steady process (step S640) (step S4602), and enables monitoring of the peripheral control CPU 4210 by the WDT 4211. (Step S4604). Thereafter, when the peripheral control CPU 4210 determines that the pachinko machine 10 is in a state of undergoing a shipping inspection (step S4606), the peripheral control CPU 4210 executes a test process corresponding to the shipping inspection (step S4608).

  On the other hand, if it is determined that it is not in the state of shipping inspection (step S4606), the peripheral control CPU 4210 uses the sensor input data stored in the input register 4344 of the gradation control LSI 4300 in the panel illumination board 430 as the illumination. The sensor input data acquired through the interface 4226 is stored in the sensor input reception buffer 4240 (step S4610). Thereafter, the peripheral control CPU 4210 instructs the electrical interface 4226 to start data transfer for transferring the data stored in the electrical transmission buffers 4262 and 4264 to the panel electrical substrate 430 (step S4620).

  Thereafter, the peripheral control CPU 4210 transfers the sound source data defining the sound output from the speakers 34 and 55 to the speakers 34 and 55 via the distribution interface 4228 (step S4632). In the present embodiment, every time the 16 ms steady process (step S640) is executed, the sound source data in the speakers 34 and 55 is constantly overwritten by transferring the sound source data to the speakers 34 and 55. As a result, even if the sound source data is destroyed due to electrical noise, the sound source data can be quickly restored.

  After the sound source data is overwritten (step S4632), the peripheral control CPU 4210 inspects the operation state of the LCD unit 42 based on the signal received from the LCD unit 42 via the liquid crystal interface 4224 (step S4634), and the LCD unit 42. If the operation state is abnormal, the RAM (not shown) that stores the video data built in the LCD unit 42 is cleared (step S4636).

  After the operation state of the LCD unit 42 is inspected (steps S4634 and S4636), the peripheral control CPU 4210 analyzes the main command received from the main control board 410 and stored in the main command reception buffer 4230 (step S4640). ). Thereafter, the peripheral control CPU 4210 performs a payout state determination process (step S4645) for analyzing data received from the payout control board 310 via the main control board 410 in order to reflect the payout state of the game ball on the LCD unit 42 and the LED 562. Execute. Thereafter, the peripheral control CPU 4210 executes a sensor analysis process (step S4650) for analyzing sensor input data from a magnetic sensor (not shown) stored in the sensor input reception buffer 4240. Thereafter, the peripheral control CPU 4210 executes effect button analysis processing (step S4655) for analyzing the sensor input data of the effect sensors 36 and 47 stored in the sensor input reception buffer 4240.

  Thereafter, the peripheral control CPU 4210 executes a transfer data preparation process (step S4660) for storing data to be transferred to the panel illumination board 430 and the peripheral distribution board 440 in the illumination transmission buffers 4262 and 4264 and the distribution transmission buffer 4270. In the present embodiment, in the transfer data preparation process (step S4660), the dimming data transferred to the panel illumination board 430 is stored in the illumination transmission buffer 4262 when the process counter is odd, and the process counter is even. Is stored in the illumination transmission buffer 4264. Details of the process relating to the light control data in the transfer data preparation process (step S4660) will be described later.

  After finishing the transfer data preparation process (step S4660), the peripheral control CPU 4210 disables monitoring of the peripheral control CPU 4210 by the WDT 4211 (step S4670). Thereafter, when the data transfer to the panel illumination board 430 by the illumination interface 4226 is completed (step S4680), the peripheral control CPU 4210 uses the amount of data corresponding to the remaining processing time based on the value of the processing time timer to change the panel illumination. Transfer of the overwrite data to the board 430 is instructed to the electrical decoration interface 4226 (step S4690), and the 16 ms steady process (FIGS. 10 and 11, step S640) is terminated. In this embodiment, the overwrite data transferred according to the remaining processing time includes gradation pattern data 580 stored in the gradation pattern storage unit 4350 of the panel electrical decoration board 430.

  FIGS. 12 and 13 are flowcharts showing the dimming data preparation process executed in the transfer data preparation process (step S4660) of the 16 ms steady process (FIG. 10). The dimming data preparation process (FIGS. 12 and 13) generates new gradation pattern data 580 for updating the gradation pattern data 580 stored in the gradation pattern storage unit 4350 of the panel electrical decoration board 430. This is a process for storing the generated new gradation pattern data 580 in the illumination transmission buffers 4262 and 4264. The peripheral control CPU 4210 of the peripheral control board 420 executes the dimming data preparation process (FIGS. 12 and 13) as one of the processes included in the transfer data preparation process (step S4660) of the 16 ms steady process (FIG. 10). .

  When the peripheral control CPU 4210 of the peripheral control board 420 starts the dimming data preparation process (FIGS. 12 and 13), it refers to the analysis result of the main command analyzed in the command analysis process (step S4640) (step S805). Thereafter, when the peripheral control CPU 4210 determines that the pattern generation table 520 stored in the dimming storage unit 4215 needs to be updated based on the analysis result of the main command (step S810), the peripheral control CPU 4210 stores the pattern generation table 520 in the main command. A generation table update process is performed to update according to the analysis result (step S820). Details of the generation table update process (step S820) will be described later.

  After finishing the process related to the update of the pattern generation table 520 (steps S810 and S820), the peripheral control CPU 4210 selects one of the gradation value tables 540 stored in the dimming storage unit 4215 based on the analysis result of the main command. Is determined to be updated (step S830), a gradation value table update process for newly generating a gradation value table 540 to be updated according to the analysis result of the main command is executed (step S840).

  After that, if the peripheral control CPU 4210 determines that any of the array table 560 stored in the dimming storage unit 4215 needs to be updated based on the analysis result of the main command (step S850), the analysis result of the main command Then, an array table update process for newly generating an array table 560 to be updated is executed (step S860). Thereafter, the peripheral control CPU 4210 executes a gradation pattern generation process (step S870) for generating new gradation pattern data 580. Details of the gradation pattern generation process (step S870) will be described later.

  After finishing the gradation pattern generation process (step S870), the peripheral control CPU 4210 sets the process counter to an odd number according to the value of the process counter incremented in the 16 ms steady process (step S4601 in FIG. 10) (step S880). In this case, the illumination transmission buffer 4262 is selected (step S882), and when the process counter is an even number, the illumination transmission buffer 4264 is selected (step S884). As a result, a different illumination transmission buffer is selected from the data stored in the transfer data preparation process (step S4660) in the 16 ms steady process (step S640) that ended last time.

  FIG. 14 is an explanatory diagram schematically illustrating storage areas of the illumination transmission buffers 4262 and 4264 included in the peripheral control board 420. The illumination transmission buffers 4262 and 4264 are written by a transfer counter area Ac that stores a counter that manages the transfer of data to the serial transfer buffer 4227 of the illumination interface 4226, and dimming data preparation processing (FIGS. 12 and 13). And a transfer data area Ad for storing the modulated light control data. In the transfer counter area Ac, the light counter Cw indicating the total number of dimming data written in the transfer data area Ad by the dimming data preparation process (FIGS. 12 and 13) and the dimming data in the transfer data area Ad are displayed on the panel. In order to perform serial transfer to the illumination board 430, a read counter Cr indicating the number of dimming data transferred to the serial transfer buffer 4227 of the illumination interface 4226 is stored.

  In the example shown in FIG. 14, k (k is a natural number) dimming data D0 to Dk is stored in the transfer data area Ad, and the write counter Cw in the transfer counter area Ac is the total number of dimming data D0 to Dk. The read counter Cr in the transfer counter area Ac has a value of “0” indicating that the dimming data is not yet delivered to the serial transfer buffer 4227. In the present embodiment, each of the dimming data D0 to Dk is 8-byte data.

  Returning to the description of FIGS. 12 and 13, the peripheral control CPU 4210 selects the illumination transmission buffer (steps S882 and S884), and then generates the generated gradation pattern data 580 in the transfer data area Ad of the selected illumination transmission buffer. The dimming data including is stored (step S890). Thereafter, the peripheral control CPU 4210 sets the total number of dimming data stored in the transfer data area Ad in the write counter Cw (step S892), resets the read counter Cr to “0” (step S894), and sets the dimming data. The preparation process (FIGS. 12 and 13) ends.

  FIG. 15 is a flowchart showing details of the generation table update process (step S820) in the dimming data preparation process (FIG. 12). When the peripheral control CPU 4210 of the peripheral control board 420 starts the generation table update process (step S820) of FIG. 15, it determines whether or not the data included in the pattern generation table 520 needs to be updated for each port number 5210 (step S820). (S8202, S8204, S8250, S8255) and the processing for all of the port numbers 5210, the generation table update processing (step S820) is terminated (step S8250). When it is determined that the data included in the pattern generation table 520 needs to be updated (step S8204), the peripheral control CPU 4210 selects the mode number 5270 based on the analysis result of the main command (step S8210).

  When the selected mode number 5270 is “1” or “2” (step S8215), the peripheral control CPU 4210, based on the analysis result of the main command, the gradation value table number 5220, the array table number 5230, and the start array number 5240, end arrangement number 5250, and gradation step value 5260 are selected (steps S8222, S8224, S8226, S8227, and S8228). Thereafter, the peripheral control CPU 4210 updates the pattern generation table 520 by writing the selected data in the corresponding column of the pattern generation table 520 in the dimming storage unit 4215 (step S8240).

  On the other hand, when the mode number 5270 is “0” (step S8215), the peripheral control CPU 4210 selects the gradation value table number 5220 and the 0 mode gradation number 5280 based on the analysis result of the main command (step S8232). , S8236). Thereafter, the peripheral control CPU 4210 updates the pattern generation table 520 by writing the selected data in the corresponding column of the pattern generation table 520 in the dimming storage unit 4215 (step S8240).

  FIG. 16 is a flowchart showing details of the gradation pattern generation process (step S870) in the dimming data preparation process (FIG. 12). When the peripheral control CPU 4210 of the peripheral control board 420 starts the gradation pattern generation process (step S820) of FIG. 16, it is necessary to update the corresponding gradation pattern data 580 for each port number 5210 of the pattern generation table 520. Is determined (steps S8702, S8704, S8780, S8785), and after all the gradation pattern data 580 have been processed, the gradation pattern generation process (step S870) is terminated (step S8780).

  If at least one of the pattern generation table 520, the gradation value table 540, and the array table 560 is updated and it is determined that the corresponding gradation pattern data 580 needs to be updated (step S8704), the peripheral control CPU 4210 Refers to the mode number 5270 of the pattern generation table 520 corresponding to the target port number 5210, and determines whether or not the mode number 5270 is “0” (step S8710).

  When the mode number 5270 is not “0”, that is, when the mode number 5270 is “1” or “2”, the peripheral control CPU 4210 has the gradation value table number 5220 and the array table number 5230 of the pattern generation table 520. , The gradation value table 540 and the array table 560 corresponding to the target port number 5210 are specified (steps S8722 and S8724). Thereafter, the peripheral control CPU 4210 refers to the pattern generation table 520 to specify the start array number 5240, the end array number 5250, and the gradation step value 5260 corresponding to the target port number 5210 (steps S8732, S8734, and S8742). . Thereafter, the peripheral control CPU 4210 sets the gradation pattern data 580 in which the gradation values 5430 of the gradation value table 540 are arranged in the order of the array number 5620 of the array table 560 corresponding to the start array number 5240 to the end array number 5250. It generates (step S8744), and stores the generated gradation pattern data 580 in the dimming storage unit 4215 (step S8770). In the present embodiment, the gradation pattern data 580 stored in the dimming storage unit 4215 includes a mode number 5820.

  FIG. 17 shows an example of how the gradation pattern data 580 is generated by the gradation pattern generation processing (step S870) when the mode number 5270 of the gradation pattern data 580 is “1” or “2”. It is explanatory drawing. As shown in FIG. 17, the gradation pattern data 580 stored in the dimming storage unit 4215 is obtained by referring to the port number 5810 for identifying each of the output terminal 4360 and the input / output terminal 4370 and the pattern generation table 520. The specified mode number 5820, a reproduction order 5830 indicating the order in which the gradation values constituting the gradation pattern are reproduced, and a reproduction gradation value 5840 indicating the gradation values constituting the gradation pattern by a pulse width are provided. .

  The example of FIG. 17 shows a state where the gradation pattern data 580 is generated based on the gradation command corresponding to the port number 5210 of “0” stored in the pattern generation table 520 shown in FIG. In the example illustrated in FIG. 7, the pattern generation table 520 includes data with a gradation value table number 5220 of “0” and data with an array table number 5230 of “0” as data corresponding to the port number 5210 of “0”. Data having a start array number 5240 of “0”, data having an end array number 5250 of “3”, data having a gradation step value 5260 of “1”, and data having a mode number of 5270 of “1”. Including.

  Returning to the description of FIG. 17, the peripheral control CPU 4210 determines that the mode number 5270 is “1” (step S8710), and then the gradation value table 540 specified by the gradation value table number 5410 of “0”. Is specified (step S8722), and the array table 560 specified by the array table number 5610 of “0” is specified (step S8724). Thereafter, since the corresponding gradation number 5630 corresponding to the array number 5620 of “0” that is the start array number 5240 is “0” (step S8732), the peripheral control CPU 4210 sets the gradation number 5420 of “0”. “0” stored in the corresponding gradation value 5430 is stored in the reproduction gradation value 5840 (step S8744). At this time, the peripheral control CPU 4210 stores the gradation value 5430 in the reproduction gradation value 5840 “n + 1” times when the gradation step value 5260 is “n” (step S8744). In the example of FIG. 17, since the gradation step value 5260 is “1”, the peripheral control CPU 4210 stores the gradation value 5430 as the reproduction gradation value 5840 “2” times, thereby obtaining gradation pattern data. The reproduction gradation value 5840 corresponding to the reproduction order “0” and “1” of 580 stores “0” designated as the gradation value 5430, respectively. Thereafter, the peripheral control CPU 4210 generates the gradation pattern data 580 by performing the same processing on the subsequent array number 5620 up to “3” which is the end array number 5250 (step S8744).

  Returning to the description of FIG. 16, on the other hand, when the mode number 5270 is “0” (step S8710), the peripheral control CPU 4210 refers to the gradation value table number 5220 in the pattern generation table 520, and sets the target port. The gradation value table 540 corresponding to the number 5210 is specified (step S8762). Thereafter, the peripheral control CPU 4210 refers to the pattern generation table 520 to identify the mode 0 gradation number 5280 corresponding to the target port number 5210 (step S8764). Thereafter, the peripheral control CPU 4210 generates gradation pattern data 580 including the gradation value 5430 of the gradation value table 540 corresponding to the mode 0 gradation number 5280 (step S8766), and adjusts the generated gradation pattern data 580. It stores in the optical storage unit 4215 (step S8770). In the present embodiment, the gradation pattern data 580 stored in the dimming storage unit 4215 includes a mode number 5820.

  FIG. 18 is an explanatory diagram showing an example of how the gradation pattern data 580 is generated by the pattern generation process (step S870) when the mode number 5270 of the gradation pattern data 580 is “0”. The example of FIG. 18 shows how the gradation pattern data 580 is generated based on the gradation command corresponding to the port number 5210 of “2” stored in the pattern generation table 520 shown in FIG. In the example illustrated in FIG. 7, the gradation command corresponding to the port number 5210 of “2” includes the data whose gradation value table number 5220 is “7”, the data whose mode number 5270 is “0”, and the mode 0 floor. The key number 5280 includes data “31”.

  Returning to the description of FIG. 18, the peripheral control CPU 4210 determines that the mode number 5270 is “0” (step S8710), and then the gradation value table 540 specified by the gradation value table number 5410 of “7”. Is specified (step S8762). Thereafter, the peripheral control CPU 4210 specifies that the mode 0 gradation number 5280 is “31” (step S8764). Thereafter, the peripheral control CPU 4210 stores “2500” designated as the gradation value 5430 corresponding to the gradation number 5420 indicating “31”, which is the same as the mode 0 gradation number 5280, in the reproduction gradation value 5840 (step S8766). ).

  FIG. 19 is a flowchart showing main command interrupt processing executed by the peripheral control CPU 4210 of the peripheral control board 420. When the peripheral control CPU 4210 of the peripheral control board 420 receives an interrupt signal from the main control board 410 (step S510), it temporarily suspends the process being executed and starts the main command interrupt process of FIG. Thereafter, the peripheral control CPU 4210 stores the main command from the main control board 410 in the main command reception buffer 4230 via the main control interface 4222 (step S520), and then ends the main command interrupt processing of FIG. Thereafter, the peripheral control CPU 4210 resumes the execution of the process interrupted when the main command interrupt process of FIG. 19 is started.

  FIG. 20 is a flowchart showing transfer buffer empty interrupt processing executed by the peripheral control CPU 4210 of the peripheral control board 420. When the peripheral control CPU 4210 of the peripheral control board 420 receives a buffer empty signal indicating that the serial transfer of the data stored in the serial transfer buffer 4227 has been completed (step S610), the peripheral control CPU 4210 temporarily suspends the processing being executed. 20 transfer buffer empty interrupt processing is started. In this embodiment, the peripheral control CPU 4210 preferentially executes the main command interrupt process of FIG. 19 over the transfer buffer empty interrupt process of FIG.

  The peripheral control CPU 4210 receives the buffer empty signal (step S610), and then according to the value of the process counter incremented in the 16 ms steady process (FIGS. 10 and 11, step S4601) (step S620), the process counter If it is even, the illumination transmission buffer 4262 is selected (step S624), and if the process counter is odd, the illumination transmission buffer 4264 is selected (step S622). As a result, the illumination transmission buffer on which data is stored by the transfer data preparation process (step S4660) in the 16 ms steady process (step S640) that has been completed last time is selected.

  After the peripheral transmission CPU 4210 selects the illumination transmission buffer (steps S622 and S624), whether or not the value of the read counter Cr is larger than the value of the write counter Cw in the selected illumination transmission buffer, that is, the transfer data area Ad. It is determined whether or not all the dimming data stored in is transferred to the serial transfer buffer 4227 (step S630). If the value of the read counter Cr is larger than the value of the write counter Cw, the peripheral control CPU 4210 ends the transfer buffer empty interrupt process of FIG. Thereafter, the peripheral control CPU 4210 resumes the execution of the process interrupted when the transfer buffer empty interrupt process of FIG. 20 is started.

  On the other hand, when the value of the read counter Cr is smaller than the value of the write counter Cw, the peripheral control CPU 4210 reads out the dimming data indicated by the value of the read counter Cr (step S640). In the example of FIG. 14, when the value of the read counter Cr is “0”, the dimming data D0 of the transfer data area Ad is read, and when the value of the read counter Cr is “1”, the transfer data When the dimming data D1 of the area Ad is read and the value of the read counter Cr is “k”, the dimming data Dk of the transfer data area Ad is read.

  Returning to the description of FIG. 20, the peripheral control CPU 4210 reads the dimming data (step S640), and then confirms that the serial transfer buffer 4227 of the electrical interface 4226 is free (step S650). The peripheral control CPU 4210 confirms that the serial transfer buffer 4227 is empty (step S650), and then stores the read dimming data in the serial transfer buffer 4227 (step S660). Thereafter, the peripheral control CPU 4210 increments the value of the read counter Cr (step S670), and ends the transfer buffer empty interrupt process of FIG. Thereafter, the peripheral control CPU 4210 resumes the execution of the process interrupted when the transfer buffer empty interrupt process of FIG. 20 is started.

  FIG. 21 is a flowchart showing a 2 ms timer interrupt process executed by the peripheral control CPU 4210 of the peripheral control board 420. The peripheral control CPU 4210 of the peripheral control board 420 suspends the current process when the 2 ms timer for measuring the start timing of the 2 ms timer interrupt process (FIG. 21) indicates that 2 ms has elapsed, and performs the 2 ms timer interrupt process of FIG. To start. In this embodiment, the peripheral control CPU 4210 preferentially executes the transfer buffer empty interrupt process (FIG. 20) and the main command interrupt process (FIG. 19) over the 2 ms timer interrupt process of FIG.

  When the 2 ms timer interrupt process (FIG. 21) is started, the peripheral control CPU 4210 executes a motor output process (step S710), a sensor input process (step S720), and a liquid crystal command transmission process (step S730). In this embodiment, when the peripheral control CPU 4210 determines that the pachinko machine 10 is undergoing a shipping inspection (step S706), motor output processing (step S710), sensor input processing (step S720), and liquid crystal command transmission The execution of the process (step S730) is cancelled.

  In the motor output process (step S710), among the data stored in the distribution transmission buffer 4270 in the transfer data preparation process (step S4660 in FIG. 10), the motor output data for driving the effect driving unit 45 is distributed via the distribution interface 4228. The process which transmits to the effect drive part 45 is included. The sensor input process (step S720) includes a process of reading various sensor input data stored in the sensor input reception buffer 4240 into the RAM 4214. The liquid crystal command transmission process (step S730) includes a process of transmitting data stored in the liquid crystal command transmission buffer 4250 to the LCD unit 42 via the liquid crystal interface 4224. Details of the liquid crystal command transmission process (step S730) will be described later.

  The peripheral control CPU 4210 resets the 2 ms timer after the motor output process (step S710), the sensor input process (step S720), and the liquid crystal command transmission process (step S730) (step S740). Thereafter, the peripheral control CPU 4210 determines whether or not 16 ms has elapsed since the start of the 16 ms steady process (step S460 in FIG. 9, FIG. 10 and FIG. 11) executed last time (step S750). If 16 ms has elapsed (step S750), the peripheral control CPU 4210 sets the 16 ms flag to “1” (step S755). Thereafter, the peripheral control CPU 4210, when the steady processing flag is set to “0”, that is, when the 16 ms steady processing (step S460 in FIG. 9, FIG. 10 and FIG. 11) is not in the middle of execution (step S760). The backup process (S765) is executed. In this embodiment, in the backup process (S765), the work area of the peripheral control CPU 4210 is stored in a storage device (not shown) provided with a backup power source. On the other hand, when 16 ms has not elapsed (step S750), when the steady processing flag is set to “1” (step S760), or when the backup processing (S765) is completed, the peripheral control CPU 4210 After finishing the 2 ms timer interrupt process (FIG. 21), the execution of the process interrupted when starting the 2 ms timer interrupt process (FIG. 21) is resumed.

  FIG. 22 is a flowchart showing details of the liquid crystal command transmission process (step S730) in the 2 ms timer interrupt process (FIG. 21). When the peripheral control CPU 4210 starts the liquid crystal command transmission process (FIG. 22, step S730), if the liquid crystal ACK signal output when the LCD unit 42 receives the liquid crystal command times out (step S7310), the LCD unit 42 A liquid crystal command retransmission process (step S7320) for retransmitting the previously transmitted liquid crystal command is executed. Thereafter, if the liquid crystal interface 4224 is not transmitting a liquid crystal command (step S7340) and the liquid crystal command transmission buffer 4250 is updated (step S7350), the peripheral control CPU 4210 displays the liquid crystal for the LCD unit 42. A transmission disclosure process (step S7360) for instructing the liquid crystal interface 4224 to start transmitting a command is executed. When the liquid crystal interface 4224 is transmitting a liquid crystal command (step S7340), when the liquid crystal command transmission buffer 4250 is not updated (step S7350), when the transmission start process (step S7360) is finished, the peripheral control CPU 4210 Finishes the liquid crystal command transmission process (FIG. 22, step S730).

B-2. Operation of panel illumination board 430:
The pulse control circuit 4355 of the gradation control LSI 4300 outputs an LED drive current to the output terminal 4360 and the input / output terminal 4370 based on the gradation pattern data 580 stored in the gradation pattern storage unit 4350. In this embodiment, the operation of the pulse control circuit 4355 is realized based on a hardware configuration in which a plurality of up / down counters and a plurality of registers included in the pulse control circuit 4355 are combined.

  FIG. 23 is an explanatory diagram showing an example of the LED drive current output by the pulse control circuit 4355 of the gradation control LSI 4300 when the mode number 5820 of the gradation pattern data 580 is “0”. The gradation pattern data 580 shown in the example of FIG. 23 is associated with data indicating “30” in the port number 5810, data indicating “0” in the mode number 5820, and the reproduction order 5830 indicating “0”. The reproduction gradation value 5840 includes data indicating “1500”.

  The pulse control circuit 4355 of the gradation control LSI 4300 drives the LED to the output terminal 4360 or the input / output terminal 4370 corresponding to “30” indicated by the port number 5810 based on the gradation pattern data 580 shown in the example of FIG. Output current. When the gradation pattern data 580 shown in FIG. 23 stored in the gradation pattern storage unit 4350 is updated, the pulse control circuit 4355 updates the reproduction gradation value 5840 until the gradation pattern data 580 is updated next time. The LED driving current having a pulse width of “1500” μs shown in FIG. 4 is repeatedly output every 4 ms (timing t100, t110,...).

  FIG. 24 is an explanatory diagram showing an example of the LED drive current output by the pulse control circuit 4355 of the gradation control LSI 4300 when the mode number 5820 of the gradation pattern data 580 is “1”. The gradation pattern data 580 shown in the example of FIG. 24 is associated with data indicating “31” in the port number 5810, data indicating “1” in the mode number 5820, and the reproduction order 5830 indicating “0”. Data indicating “500” in the reproduction gradation value 5840, data indicating “1500” in the reproduction gradation value 5840 associated with the reproduction order 5830 indicating “1”, and reproduction order 5830 indicating “2”. It includes data indicating “2500” in the associated reproduction gradation value 5840 and data indicating “3500” in the reproduction gradation value 5840 associated with the reproduction order 5830 indicating “3”.

  The pulse control circuit 4355 of the gradation control LSI 4300 drives the LED to the output terminal 4360 or the input / output terminal 4370 corresponding to “31” indicated by the port number 5810 based on the gradation pattern data 580 shown in the example of FIG. Output current. When the gradation pattern data 580 shown in FIG. 24 stored in the gradation pattern storage unit 4350 is updated, the pulse control circuit 4355 indicates the reproduction gradation value 5840 in association with the reproduction order 5830 indicating “0”. The LED driving current having a pulse width of “500” μs is output (timing t200). After that, the pulse control circuit 4355 outputs LED drive currents having pulse widths of “1500” μs, “2500” μs, and “3500” μs every 4 ms in ascending order of the value of the reproduction order 5830 (timing t210, t220, t230). After the LED drive currents having the pulse widths corresponding to all of the reproduction orders 5830 are output, the pulse control circuit 4355 increases the value of the reproduction order 5830 in ascending order until the gradation pattern data 580 is updated next. LED driving current having a pulse width of “μs”, “1500” μs, “2500” μs, and “3500” μs is repeatedly output every 4 ms (timing t240, t250, t260, t270, t280, t290,...).

  FIG. 25 is an explanatory diagram showing an example of the LED drive current output by the pulse control circuit 4355 of the gradation control LSI 4300 when the mode number 5820 of the gradation pattern data 580 is “2”. The gradation pattern data 580 illustrated in the example of FIG. 25 is associated with data indicating “32” in the port number 5810, data indicating “2” in the mode number 5820, and the reproduction order 5830 indicating “0”. Data indicating “500” in the reproduction gradation value 5840, data indicating “1500” in the reproduction gradation value 5840 associated with the reproduction order 5830 indicating “1”, and reproduction order 5830 indicating “2”. It includes data indicating “2500” in the associated reproduction gradation value 5840 and data indicating “3500” in the reproduction gradation value 5840 associated with the reproduction order 5830 indicating “3”.

  The pulse control circuit 4355 of the gradation control LSI 4300 drives the LED to the output terminal 4360 or the input / output terminal 4370 corresponding to “32” indicated by the port number 5810 based on the gradation pattern data 580 shown in the example of FIG. Output current. When the gradation pattern data 580 shown in FIG. 25 stored in the gradation pattern storage unit 4350 is updated, the pulse control circuit 4355 indicates the reproduction gradation value 5840 in association with the reproduction order 5830 indicating “0”. The LED driving current having a pulse width of “500” μs is output (timing t300). Thereafter, the pulse control circuit 4355 outputs an LED drive current having a pulse width of “1500” μs, “2500” μs, and “3500” μs every 4 ms in ascending order of the value of the reproduction order 5830 (timing t310, t320, t330). After the LED drive current having the pulse width corresponding to all of the reproduction orders 5830 is output, the pulse control circuit 4355 is the largest value in the reproduction order 5830 and last until the gradation pattern data 580 is updated next time. The LED drive current having a pulse width of “3500” μs corresponding to the reproduction order 5830 of “3” outputted in (3) is repeatedly outputted every 4 ms (timing t340, t350, t360, t370, t380, t390,...).

  According to the pachinko machine 10 described above, it is not necessary to synchronize the gradation pattern data 580 based on the combination of the gradation value table 540 and the arrangement table 560 with the period of the 2 ms timer interruption process (FIG. 21) that is a scheduled interruption. Since it can output from the peripheral control board 420 to the panel electrical decoration board 430, the increase in the processing load accompanying the multi-gradation of the LED 462 in the peripheral control CPU 4210 of the peripheral control board 420 can be suppressed. As a result, the smoothness of gradation expression of the LED 462 provided in the pachinko machine 10 can be improved.

  Further, the peripheral control CPU 4210 of the peripheral control board 420 updates at least one of the gradation value table 540 and the arrangement table 560 according to the progress of the game (FIG. 12, steps S840 and S860), so that various floors by the LEDs 462 can be used. Gradation pattern data 580 that realizes key expression can be generated. Further, the peripheral control CPU 4210 of the peripheral control board 420 determines the reproduction mode of the gradation pattern data 580 according to the progress of the game (FIG. 15, step S8210), and the LED 462 uses the same gradation pattern data 580. A variety of gradation expressions can be realized.

C. Other embodiments:
As mentioned above, although embodiment of this invention was described, this invention is not limited to such embodiment at all, Of course, it can implement with various forms within the range which does not deviate from the meaning of this invention. is there. For example, the present invention may be applied to a gaming machine provided with an LED, and can be applied not only to a pachinko machine but also to a gaming machine such as an arrangement ball or a slot machine. In this embodiment, the gradation control LSI 4300 is mounted on the panel decoration board 430. However, the gradation control LSI 4300 is mounted on the frame decoration board 450 in the same manner as the panel decoration board 430. Also good. Further, the numbers of the gradation value table 540 and the arrangement table 560 may be one or more, and are not limited to the numbers in the present embodiment.

  In each of the gradation value tables 540, gradation values 5430 can be set in various patterns. For example, the gradation value 5430 is set in the range from the gradation value “0” to the gradation value “4000” in the two gradation value tables 540, and one gradation value table 540 includes the gradation values of the first half portion. In the other half tone value table 540, the tone of the first half is coarse and the tone of the second half is dense. The same arrangement table 560 may be used to realize gradation pattern data 580 with different gradation variation density patterns. Further, by using one gradation value table 540 in which the arrangement of the gradation values 5430 in the other gradation value table 540 is reversed, the same arrangement table 560 is used for each gradation value table 540. You may implement | achieve the gradation pattern data 580 with the opposite gradation change.

  In this embodiment, the peripheral control board 420 generates the entire gradation pattern data 580 in a lump (FIG. 16, step S870), and generates the gradation pattern data 580 composed of a series of gradation values as panel lighting. Although it was decided to serially transfer to the board 430 (FIG. 13, step S890), as another embodiment, the peripheral control board 420 is adapted to the output of the LED drive current in the pulse control circuit 4355 of the panel illumination board 430, One gradation value to be output from each output terminal may be generated one by one, and the generated gradation value of each output terminal may be serially transferred to the panel illumination board 430 one by one. Thereby, the storage capacities of the light control storage unit 4215 and the gradation pattern storage unit 4350 can be suppressed.

1 is a front view showing an overall configuration of a pachinko machine 10. FIG. 2 is a block diagram showing an electrical schematic configuration of a pachinko machine 10. FIG. 4 is a block diagram mainly showing an electrical configuration of a peripheral control board 420 in the pachinko machine 10. FIG. It is an explanatory view showing details of the light control storage unit 4215 in the peripheral control board 420. It is explanatory drawing which shows typically the some gradation value table 540 memorize | stored in the light control memory | storage part 4215 of the peripheral control board | substrate 420. FIG. It is explanatory drawing which shows typically the some arrangement | sequence table 560 memorize | stored in the light control memory | storage part 4215 of the peripheral control board | substrate 420. FIG. It is explanatory drawing which shows the pattern production | generation table 520 memorize | stored in the light control memory | storage part 4215 of the periphery control board | substrate 420. FIG. 4 is a block diagram mainly showing an electrical configuration of a gradation control LSI 4300 mounted on a panel illumination board 430 in the pachinko machine 10. FIG. 10 is a flowchart showing a peripheral control process executed by a peripheral control CPU 4210 of the peripheral control board 420. It is a flowchart which shows the detail of 16 ms regular process (step S640) in a periphery control process (FIG. 9). It is a flowchart which shows the detail of 16 ms regular process (step S640) in a periphery control process (FIG. 9). It is a flowchart which shows the light control data preparation process performed in the transfer data preparation process (step S4660) of a 16 ms regular process (FIG. 10). It is a flowchart which shows the light control data preparation process performed in the transfer data preparation process (step S4660) of a 16 ms regular process (FIG. 10). It is explanatory drawing which shows typically the memory area of the electrical decoration transmission buffers 4262 and 4264 with which the peripheral control board | substrate 420 is provided. It is a flowchart which shows the detail of the production | generation table update process (step S820) in a light control data preparation process (FIG. 12). It is a flowchart which shows the detail of the gradation pattern production | generation process (step S870) in a light control data preparation process (FIG. 12). FIG. 11 is an explanatory diagram showing an example of a state in which gradation pattern data 580 is generated by gradation pattern generation processing (step S870) when the mode number 5270 of the gradation pattern data 580 is “1” or “2”. FIG. 10 is an explanatory diagram showing an example of a state in which gradation pattern data 580 is generated by pattern generation processing (step S870) when the mode number 5270 of the gradation pattern data 580 is “0”. 10 is a flowchart showing main command interrupt processing executed by the peripheral control CPU 4210 of the peripheral control board 420. 10 is a flowchart showing transfer buffer empty interrupt processing executed by the peripheral control CPU 4210 of the peripheral control board 420. 10 is a flowchart showing a 2 ms timer interrupt process executed by the peripheral control CPU 4210 of the peripheral control board 420. It is a flowchart which shows the detail of the liquid-crystal command transmission process (step S730) in a 2 ms timer interruption process (FIG. 21). FIG. 45 is an explanatory diagram showing an example of an LED drive current output by the pulse control circuit 4355 of the gradation control LSI 4300 when the mode number 5820 of the gradation pattern data 580 is “0”. FIG. 38 is an explanatory diagram showing an example of an LED drive current output by the pulse control circuit 4355 of the gradation control LSI 4300 when the mode number 5820 of the gradation pattern data 580 is “1”. FIG. 45 is an explanatory diagram illustrating an example of an LED drive current output by the pulse control circuit 4355 of the gradation control LSI 4300 when the mode number 5820 of the gradation pattern data 580 is “2”.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 ... Pachinko machine 20 ... Outer frame 30 ... Inner frame 32 ... Handle 34 ... Speaker 36 ... Production sensor 40 ... Game panel 42 ... LCD unit 44 ... Winning port 442 ... Game ball sensor 444 ... Winning port drive unit 45 ... Production drive unit 46 ... Electric decoration 462 ... LED
47 ... Production sensor 50 ... Glass frame 55 ... Speaker 56 ... Illumination part 562 ... LED
DESCRIPTION OF SYMBOLS 80 ... Card unit 310 ... Discharge control board 410 ... Main control board 420 ... Peripheral control board 4210 ... Peripheral control CPU
4211 ... WDT
4212 ... ROM
4214 ... RAM
4215: Dimming storage unit 4216 ... Bus 4222 ... Main control interface 4224 ... Liquid crystal interface 4226 ... Electrical decoration interface 4227 ... Serial transfer buffer 4228 ... Distribution interface 4230 ... Main command reception buffer 4240 ... Sensor input reception buffer 4250 ... Liquid crystal command transmission buffer 4262, 4264: electrical decoration transmission buffer 4270: distribution transmission buffer 430: panel electrical circuit board 4300: gradation control LSI
4310 ... Serial transfer circuit 4312 ... Noise removal circuit 4320 ... Access management circuit 4340 ... Input management circuit 4342 ... Direction register 4344 ... Input register 4350 ... Tone pattern storage unit 4355 ... Pulse control circuit 4360 ... Output terminal 4370 ... Input / output terminal 440 ... Peripheral distribution board 450 ... Frame illumination board 520 ... Pattern generation table 5210 ... Port number 5220 ... Tone value table number 5230 ... Array table number 5240 ... Start array number 5250 ... End array number 5260 ... Gradation step value 5270 ... Mode Number 5280 ... Mode 0 gradation number 540 ... gradation value table 5410 ... gradation value table number 5420 ... gradation number 5430 ... gradation value 560 ... array table 5610 ... array table number 5620 ... array number 5630 ... corresponding gradation number 580 ... gradation pattern data 5810 ... port number 5820 ... mode number 5830 ... reproduction order 5840 ... reproduction gradation value Ac ... transfer counter area Ad ... transfer data area Cr ... read counter Cw ... write counter D0 to Dk ... Dimming data

Claims (7)

A computer for a gaming machine that controls a gradation control circuit that changes a light emission luminance of the light emitting diode to a plurality of gradation values by switching a pulse width of a driving current for the light emitting diode provided in the gaming machine,
Gradation value table storage means for storing a plurality of gradation value tables respectively designating some of the plurality of gradation values;
Array table storage means for storing a plurality of array tables each defining an array in which the specified gradation values are arranged in the gradation value table;
A gradation value table selecting means for selecting at least one of the plurality of gradation value tables according to the progress of the game in the gaming machine;
An arrangement table selecting means for selecting at least one of the plurality of arrangement tables according to the progress of the game in the gaming machine;
Pattern data generating means for generating gradation pattern data in which the gradation values specified in the selected gradation value table are arranged in accordance with the arrangement defined in the selected arrangement table;
A gaming machine computer comprising: command transmission means for transmitting the generated gradation pattern data to the gradation control circuit as a command for controlling the gradation control circuit. The gaming machine computer according to claim 1, further comprising:
A gradation value table generating means for generating a new gradation value table;
A computer for gaming machines, comprising: a stored gradation value table, and a gradation value table updating unit that updates the generated new gradation value table. The computer for gaming machines according to claim 1 or 2, further comprising:
An array table generating means for generating a new array table;
A gaming machine computer comprising: an array table updating unit that updates the stored existing array table to the generated new array table. A gaming machine computer according to any one of claims 1 to 3, further comprising:
A mode determining means for determining a playback mode of the generated light emission pattern data;
A gaming machine computer comprising: mode indicating means for instructing the gradation control circuit to determine the determined playback mode.   The reproduction mode of the light emission pattern data is at least one of a reproduction mode in which the light emission pattern data is repeatedly reproduced and a reproduction mode in which the last gradation value in the light emission pattern data is maintained after the light emission pattern data is reproduced once. The computer for gaming machines according to claim 4 including:   A gaming machine comprising the gaming machine computer according to any one of claims 1 to 5. A gaming machine control method for controlling a gradation control circuit for changing a light emission luminance of a light emitting diode to a plurality of gradation values by switching a pulse width of a driving current for the light emitting diode provided in the gaming machine by a computer for the gaming machine Because
The gaming machine computer storing a plurality of gradation value tables respectively designating some of the plurality of gradation values;
Storing a plurality of arrangement tables each defining an arrangement in which the computer for gaming machines arranges the gradation values specified in the gradation value table;
The gaming machine computer selecting at least one of the plurality of gradation value tables according to the progress of the game in the gaming machine;
The gaming machine computer selecting at least one of the plurality of arrangement tables according to a game progress in the gaming machine;
The game machine computer generating gradation pattern data in which the gradation values specified in the selected gradation value table are arranged according to the arrangement specified in the selected arrangement table;
A gaming machine control method comprising: the gaming machine computer transmitting the generated gradation pattern data to the gradation control circuit as a command for controlling the gradation control circuit.

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