JP2008004592A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device capable of isolating an L-IGBT from a low breakdown-voltage integrated circuit by pn junction separation easily and reliably when integrating the L-IGBT and the low breakdown-voltage integrated circuit into one chip. <P>SOLUTION: An n-type hole block region 400 is provided between the L-IGBT 390 and the low breakdown-voltage integrated circuit 410 on a p-type semiconductor substrate 10. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor device in which a high breakdown voltage element and a low breakdown voltage element are integrated and a method for manufacturing the same.

  In recent years, pn junction isolation and dielectric isolation are often used as element isolation techniques in semiconductor devices. In particular, when a high-voltage transistor such as a lateral high-voltage insulated gate bipolar transistor (hereinafter referred to as L-IGBT) used for high-current switching and its control circuit unit are integrated on a single chip, as a method of separating them, insulation characteristics However, excellent dielectric separation is often used. However, when using general dielectric isolation, in order to avoid malfunction during switching and to obtain high reliability, it is necessary to separate each element into separate island regions by dielectric, It will be disadvantageous in terms of integration.

  Therefore, a semiconductor device proposed in Patent Document 1 as an approach for improving the degree of integration will be described with reference to a cross-sectional view of FIG.

  In the configuration of the conventional semiconductor device shown in FIG. 12, an SOI (Silicon On Insulator) substrate in which one main surface of the Si substrate 512 on which the insulating film 740 is formed and one main surface of the Si support substrate 511 are bonded together is used. . A control circuit 911 including an L-IGBT 891 which is a high breakdown voltage element and a low breakdown voltage element is formed on the SOI substrate. In the conventional semiconductor device shown in FIG. 12, a bipolar transistor is exemplified as the low breakdown voltage element used in the control circuit 911. However, the low breakdown voltage element is not limited to this.

Specifically, the L-IGBT 891 and the control circuit 911 include a plurality of island regions (P-type semiconductor regions) 513 surrounded by an insulating film region 741 and an insulating film 740 that reach the insulating film 740 from the surface of the SOI substrate. Each is formed above. In order to stabilize the characteristics of the insulating film interface, ap ⁺ type region (high concentration P type semiconductor region) 920 is formed between each P type semiconductor region 513 and each of the insulating film 740 and the insulating film region 741. The p ⁺ type region 920 is grounded.

On the surface portion of the P-type semiconductor region 513 where the L-IGBT 891 is provided, the n-type drift region 521 and the p ⁺ -type base region 531 are formed in contact with each other. A p ⁺ -type collector region 561 is formed at the center of the surface portion of the n-type drift region 521, and an n ⁺ -type emitter region is provided at a position separated from the n-type drift region 521 in the surface portion of the p ⁺ -type base region 531. 551 and p ⁺ -type base contact region 881 are formed in contact with each other. Further, a gate insulating film 571 is formed from at least the end portion of the n-type drift region 521 to a predetermined portion of the p ⁺ -type base region 531, and the gate electrode 581 is extended on the gate insulating film 571. . Further, ^{p +} -type on the collector region 561 is a collector electrode 601 is formed so as to be connected to the ^{p +} -type collector region 561, ^{n +} -type emitter region 551 and on the ^{p +} -type base contact region 881 on the the An emitter electrode 591 is formed so as to connect to both regions.

A pair of n-type well regions 641 are formed on the surface portion of the P-type semiconductor region 513 where the control circuit 911 is provided so as to sandwich the p ⁺ -type channel stopper region 611.

On the surface portion of one n-type well region 641, a p-type well region 651 and one n ⁺ -type region 661 are formed separately. On the surface portion of the p-type well region 651, a p ⁺ -type region 671 and another n ⁺ -type region 661 are formed apart from each other. The on p ⁺ -type region 671 and the base electrode 683 is formed so as to be connected with the ^{p +} -type region 671, on the ^{n +} -type region 661 in the p-type well region 651 with the ^{n +} -type region 661 An emitter electrode 684 is formed so as to be connected, and a collector electrode 685 is formed on the n ⁺ -type region 661 outside the p-type well region 651 so as to be connected to the n ⁺ -type region 661. Thus, an NPN bipolar transistor is formed on one n-type well region 641.

On the surface of the other n-well region 641, an n ⁺ -type region 661 and a pair of p ⁺ -type regions 671 are formed separately from each other. On one ^{p +} -type region 671 is a collector electrode 693 is formed so as to be connected with the ^{p +} -type region 671, so that on top the other ^{p +} -type region 671 is connected to the ^{p +} -type region 671 an emitter electrode 694 are formed, on the ^{n +} -type region 661 base electrode 695 so as to be connected to the ^{n +} -type region 661 is formed on. Thus, a PNP bipolar transistor is formed on the other n-type well region 641.

  An interlayer film 711 is formed so as to cover the L-IGBT 891 and the control circuit 911 and the upper part of each electrode protrudes, and a protective film 721 is formed on the interlayer film 711 including above each electrode.

  Next, the operation of the conventional semiconductor device will be described.

  In the L-IGBT 891, when a high voltage is applied to the collector electrode 601 in the off state, the n-type drift region 521 and the p-type semiconductor region 513 are in a reverse-biased state. As the depletion layer expands toward, the electric field becomes uniform, thereby realizing a high breakdown voltage characteristic.

  On the other hand, when a voltage equal to or higher than the threshold is applied to the gate electrode 581, the channel region immediately below the gate electrode 581 is inverted, and the L-IGBT 891 is turned on. In the ON state, a large amount of holes are injected from the collector region 561 into the n-type drift region 521, thereby conducting conductivity modulation, and a large current flows from the collector region 561 toward the emitter region 551.

Here, since the L-IGBT 891 is surrounded by the insulating film 740, the insulating film region 741, and the p ⁺ -type region 920, a large amount of holes generated at the time of reaching the control circuit 911 including the low breakdown voltage element. Without being completely absorbed by the ground.

As described above, in the conventional semiconductor device shown in FIG. 12, the electrical influence on the low breakdown voltage element of the L-IGBT can be reliably prevented by dielectric separation.
Japanese Patent No. 2788269

In general, when dielectric isolation is used, the area required for isolation is larger than when pn junction isolation is used. On the other hand, in the semiconductor device having the conventional structure shown in FIG. 12, although the degree of integration can be increased, the insulating film interface p for realizing substrate bonding, trench formation, and stable breakdown voltage characteristics can be obtained. A complicated process such as arrangement of the ⁺ type layer is required. These cause an increase in process cost as compared with the case where pn junction isolation is used. That is, in the conventional method using dielectric isolation, in order to solve the problem that the degree of integration increases, a complicated and expensive process is required as compared with the case where pn junction isolation is used. It is.

  The present invention solves the above-described problems, and a semiconductor device capable of easily and reliably separating an L-IGBT and an integrated circuit portion including a low breakdown voltage element using pn junction isolation, and It aims at providing the manufacturing method.

  In order to achieve the above object, a semiconductor device according to the present invention is a semiconductor device in which a lateral insulated gate bipolar transistor and a low breakdown voltage integrated circuit are formed on a first conductivity type semiconductor region, A second conductivity type hole block region to which a predetermined bias is applied is formed between the lateral insulated gate bipolar transistor and the low breakdown voltage integrated circuit in the conductivity type semiconductor region.

  The low withstand voltage integrated circuit means an integrated circuit composed of circuit elements with a withstand voltage of up to about 30V, for example. The predetermined bias applied to the second conductivity type hole block region is a bias of about 5 to 30 V, for example.

  According to the semiconductor device of the present invention, the depletion layer spreads from the pn junction by applying a reverse bias to the pn junction between the second conductivity type hole block region and the first conductivity type semiconductor region. It is possible to prevent a hole generated when the gate bipolar transistor, that is, the L-IGBT is turned on, from entering the low voltage integrated circuit.

  Further, since the structure of the semiconductor device of the present invention is a structure obtained without using an SOI substrate, a trench, or the like, the semiconductor device of the present invention can be provided by a simple and inexpensive process.

  In the semiconductor device of the present invention, the lateral insulated gate bipolar transistor has a second conductivity type drift region formed in the first conductivity type semiconductor region, and the low breakdown voltage integrated circuit includes the first conductivity type semiconductor region. The second conductivity type hole block region has the same impurity concentration as at least one of the second conductivity type drift region and the second conductivity type well region. It is preferable to have a gradient. In this case, the second conductivity type hole block region can be formed in the same process as at least one of the second conductivity type drift region of the L-IGBT and the second conductivity type well region of the low breakdown voltage integrated circuit. The second conductivity type hole block region can be easily arranged without increasing the number of steps.

  In the semiconductor device of the present invention, a trench is formed between the lateral insulated gate bipolar transistor and the low breakdown voltage integrated circuit in the first conductivity type semiconductor region, and the second conductivity type hole block region includes the first conductivity type hole block region. Preferably, it is formed below the trench in the one conductivity type semiconductor region. In this case, since the second conductivity type hole block region can be formed in the deep position of the first conductivity type semiconductor region using the trench, higher isolation characteristics can be realized.

  In the semiconductor device of the present invention, the low voltage integrated circuit controls switching of the lateral insulated gate bipolar transistor, and a voltage applied to the second conductivity type hole block region controls switching of the lateral insulated gate bipolar transistor. The power supply voltage is preferably the same as the power supply voltage of the low withstand voltage integrated circuit to be controlled. If it does in this way, the effect of the above-mentioned present invention can be acquired, without arranging especially the terminal for impressing voltage to the 2nd conductivity type hole block field.

  In the semiconductor device of the present invention, a lateral high breakdown voltage having a drain drift region serving as the second conductivity type hole block region between the lateral insulated gate bipolar transistor and the low breakdown voltage integrated circuit in the first conductivity type semiconductor region. A field effect transistor is preferably formed. In this way, it is possible to prevent the holes generated when the L-IGBT is turned on from entering the low voltage integrated circuit, and at the same time, the following effects are obtained. That is, the lateral high breakdown voltage field effect transistor is turned on even when the L-IGBT on-current does not flow or is small as in the case where the collector voltage of the L-IGBT is not higher than the built-in voltage. Compared with the case, it is possible to realize a reduction in on-resistance when the on-current of the IGBT does not flow or is small. Therefore, for example, in a switching power supply device using the semiconductor device of the present invention, conduction loss can be minimized over a wide range from a low output state to a high output state.

  The withstand voltage of the lateral high withstand voltage field effect transistor is about the same as the withstand voltage of the L-IGBT, for example, about 800V. However, the breakdown voltage of the lateral high breakdown voltage field effect transistor is not particularly limited as long as it is larger than the breakdown voltage of the low breakdown voltage integrated circuit operating at a breakdown voltage of about 30 V at the maximum. Can be set.

  A switching power supply device according to the present invention is a switching power supply device using the semiconductor device of the present invention, and includes a transformer having a primary winding, a secondary winding, and an auxiliary winding, and the primary of the transformer The winding is connected to the lateral insulated gate bipolar transistor, the auxiliary winding of the transformer is connected to the low voltage integrated circuit, the voltage applied to the auxiliary winding and the second conductivity type hole block The voltage applied to the region is the same.

  According to the switching power supply device of the present invention, a higher voltage can be applied to the second conductive compared to the case where the same voltage as the power supply voltage of the low voltage integrated circuit that controls the switching of the L-IGBT is applied to the second conductive type hole block region. Since it can be applied to the mold hole block region, it is possible to further expand the depletion layer, thereby realizing higher isolation characteristics.

  A method of manufacturing a semiconductor device according to the present invention is a method of manufacturing a semiconductor device in which a lateral insulated gate bipolar transistor and a low breakdown voltage integrated circuit are formed on a first conductivity type semiconductor region. Forming a second conductivity type drift region of the lateral insulated gate bipolar transistor in the region; and a second conductivity type well region of an element included in the low voltage integrated circuit in the first conductivity type semiconductor region. And forming a second conductivity type hole block region to which a predetermined bias is applied between the lateral insulated gate bipolar transistor and the low breakdown voltage integrated circuit in the first conductivity type semiconductor region. The step (c) is performed simultaneously with at least one of the step (a) and the step (b).

  That is, in the method for manufacturing a semiconductor device of the present invention, when the semiconductor device of the present invention is manufactured, the second conductivity type hole block region is used as the second conductivity type drift region of the L-IGBT and the low breakdown voltage integrated circuit. Since it is formed in the same step as at least one of the two conductivity type well regions, the semiconductor device of the present invention can be provided by a simple and inexpensive process.

  According to the present invention, since the second conductivity type hole block region is provided between the L-IGBT and the low breakdown voltage integrated circuit in the first conductivity type semiconductor region, the second conductivity type hole block region and the first conductivity type semiconductor region are provided. By applying a reverse bias to the pn junction between the two, a depletion layer can be expanded from the pn junction. Therefore, it is possible to easily and reliably prevent the holes generated when the L-IGBT is turned on from entering the low voltage integrated circuit. That is, the L-IGBT and the low breakdown voltage integrated circuit can be easily and reliably separated using pn junction isolation.

(Switching power supply device of the present invention)
Hereinafter, an example of a switching power supply apparatus in which a semiconductor device according to each embodiment of the present invention to be described later is used will be described in detail with reference to the circuit diagram of FIG.

  The semiconductor device 320 of the present invention used in the switching power supply device shown in FIG. 1 has an L-IGBT 390 and a control circuit 410 (hereinafter referred to as a low voltage integrated circuit 410) composed of low voltage elements. . In addition, the semiconductor device 320 includes an L-IGBT 390 input terminal 323 (hereinafter referred to as a collector terminal 323), an auxiliary winding voltage input terminal 324 (hereinafter referred to as a VCC terminal 324), an internal circuit power supply terminal as external input terminals. 325 (hereinafter referred to as VDD terminal 325) and at least four terminals of GND terminal 326 (also serving as an output terminal of L-IGBT 390) of low voltage integrated circuit 410.

  The low-voltage integrated circuit 410 is connected to the gate of the L-IGBT 390, and one end of the primary winding 341 of the transformer 340 is connected to the collector terminal 323 of the L-IGBT 390.

  The low withstand voltage integrated circuit 410 detects the load state of the resistor 335 for supplying a starting current to its internal power supply, and the output on the secondary side (the rear stage of the transformer 340, that is, the power supply output side), and the detected information is low. A photocoupler 355 that transmits to the withstand voltage integrated circuit 410 is connected. In addition, one end of the auxiliary winding 343 of the transformer 340 is connected to the low voltage integrated circuit 410 via the VCC terminal 324 and the diode 329. A capacitor 327 is connected in parallel with the auxiliary winding 343, and the other end of the auxiliary winding 343 is grounded.

  The switching power supply device shown in FIG. 1 includes, for example, input terminals 331 and 332 for inputting a commercial AC power supply voltage. The AC power supply voltage input from the input terminals 331 and 332 is rectified and smoothed by the primary side rectifying / smoothing circuit 330 including the bridge diode 333 and the electrolytic capacitor 334 to generate a DC voltage.

  Between the input and output (between the input terminals 331 and 332 and the output terminals 353 and 354) in the switching power supply device shown in FIG. 1, a primary winding 341, a secondary winding 342, and an auxiliary winding 343 are configured. A transformer 340 is disposed, and the transformer 340 insulates the primary side (input side, that is, the low voltage integrated circuit 410 side) from the secondary side.

  On the secondary side of the switching power supply device shown in FIG. 1, the second DC voltage smaller than the absolute value of the DC voltage is generated from the DC voltage generated by the primary side rectifying and smoothing circuit 330. A diode 350 for rectifying and smoothing the secondary output voltage, an electrolytic capacitor 351, a secondary control circuit 352 for supplying a stable output voltage to the output terminals 353 and 354, and a secondary control circuit A photocoupler 355 for transmitting the signal 352 to the primary side is arranged.

  The operation of the switching power supply device of the present invention configured as described above is as follows.

  When an AC power supply voltage is applied to the input terminals 331 and 332 of the switching power supply device shown in FIG. 1, the input AC power supply voltage is rectified and smoothed in the primary side rectifying and smoothing circuit 330, and thereby the DC voltage Vin. Is generated.

  Vin is applied to the collector terminal 323 of the semiconductor device 320 through the primary winding 341 of the transformer 340. Then, a starting constant current (supplied from the primary side rectifying / smoothing circuit 330) is supplied to the VCC terminal 324 through the resistor 335 and the low withstand voltage integrated circuit 410, whereby the capacitor 327 connected to the VCC terminal 324 is charged. As a result, the VCC voltage rises. The low-breakdown-voltage integrated circuit 410 has a built-in regulator that operates so that the VDD voltage becomes constant. A part of the startup constant current charges the capacitor 328 connected to the VDD terminal 325, Thus, the VDD voltage can be raised to a constant voltage.

  As described above, when the VCC voltage and the VDD voltage rise and the VDD voltage reaches the starting voltage of the low voltage integrated circuit 410, the switching operation of the L-IGBT 390 is started. Here, the VDD voltage as the starting voltage is a constant voltage of about 8V, for example. When the switching operation of the L-IGBT 390 is started, energy is supplied to each winding of the transformer 340. When energy is supplied to the transformer 340, the current flowing through the secondary winding 342 is rectified and smoothed by the diode 350 and the electrolytic capacitor 351, and starts to supply the output voltage Vo. After that, the switching operation of the L-IGBT 390 is repeated, whereby the output voltage Vo gradually increases. When the output voltage Vo reaches the voltage value set by the secondary side control circuit 352, the photocoupler 355 is connected to the semiconductor device. The information is fed back to the 320 low voltage integrated circuit 410, and the collector current flowing through the L-IGBT 390 which is a switching element is reduced. By performing such negative feedback, the output voltage Vo is stabilized.

  The current flowing through the primary side auxiliary winding 343 is rectified by a diode 329 connected between the VCC terminal 324 and the primary side auxiliary winding 343 and a capacitor 327 connected in parallel with the primary side auxiliary winding 343. And is supplied to the semiconductor device 320 through the VCC terminal 324. That is, the internal circuit power supply voltage of the semiconductor device 320 can be supplied from the auxiliary winding 343. In other words, the auxiliary winding 343 is used as an auxiliary power source for the semiconductor device 320.

  After the switching power supply device shown in FIG. 1 is started, the low voltage integrated circuit 410 controls the auxiliary power supply voltage from the primary side auxiliary winding 343 or the charging current to the capacitor 327, so that the L-IGBT 390 For example, a voltage of 10 to 20 V is always applied to the VCC terminal 324 when the switch is on.

(First embodiment)
Hereinafter, a semiconductor device and a manufacturing method thereof according to a first embodiment of the present invention will be described with reference to the drawings.

  FIG. 2 is a cross-sectional view of the semiconductor device according to the first embodiment, and FIG. 3 is a plan view of the semiconductor device according to the first embodiment. 2 is a cross-sectional view taken along the line A-A 'in FIG. In FIG. 3, some component elements (for example, an element isolation interval between the L-IGBT 390 and the n-type hole block region 400 or between the L-IGBT 390 and the low breakdown voltage integrated circuit 410 (the field insulating film 40 The illustration of (width) etc. is omitted.

As shown in FIG. 2, an L-IGBT 390 is formed on one region (high breakdown voltage region) of a p-type semiconductor substrate 10 (impurity concentration is about 1 × 10 ¹⁴ / cm ^3, for example), and the p-type semiconductor substrate A low-voltage integrated circuit 410 composed of low-voltage elements is formed on the other area of 10.

  A feature of this embodiment is that an n-type hole block region 400 is provided between the L-IGBT 390 and the low-breakdown-voltage integrated circuit 410 in the p-type semiconductor substrate 10.

Specifically, as shown in FIG. 2, a p ⁺ type collector region 60 (impurity concentration is, for example, 1 × 10 ¹⁸ to 1 × 10 ²⁰⁾ is formed on the surface portion of the formation region of the L-IGBT 390 in the p type semiconductor substrate 10. / a cm about ^3), and the ^{p +} -type collector region 60 surrounds n-type drift region 20 (impurity concentration is, for example, ^{1 × 10 15 ~1 × 10 16} / cm 3 or so) is formed. In addition, in the formation region of the L-IGBT 390 in the surface portion of the p-type semiconductor substrate 10, an n ⁺ -type emitter region 50 (impurity concentration is, for example, 1 × 10 ¹⁸ to 1) is spaced from the n-type drift region 20. × ¹⁰ approximately 20 / cm ³⁾ with is formed, ^{the p +} -type base contact as viewed from the ^{n +} -type emitter region 50 adjacent to the ^{n +} -type emitter region 50 on the opposite side of the ^{p +} -type collector region 60 Region 380 (impurity concentration is, for example, about 1 × 10 ¹⁸ to 1 × 10 ²⁰ / cm ³ ) is formed. Further, the p-type base region 30 (impurity concentration is, for example, 1 × 10 ¹⁶ to 1 × 10 ¹⁷ / cm ³⁾ so as to surround the n ⁺ -type emitter region 50 and the p ⁺ -type base contact region 380 and be in contact with the n-type drift region 20. Is formed to a depth of about several μm. A field insulating film 40 is selectively formed on the n-type drift region 20. A gate insulating film 70 is formed on the surface of the p-type semiconductor substrate 10 from at least the end of the n-type drift region 20 to a predetermined portion of the p-type base region 30, and the gate electrode 80 is formed on the gate insulating film 70. It is extended. Further, n ⁺ -type on the emitter region 50 and p ⁺ -type base contact region 380 with an emitter electrode 90 connected with the both areas are formed, the p ⁺ -type collector on the p ⁺ -type collector region 60 A collector electrode 100 connected to the region 60 is formed.

Then, the surface portion of the forming region of the low-voltage integrated circuits 410 in the p-type semiconductor substrate 10, as shown in FIG. 2, ^{p +} -type channel stopper region 110 (the impurity concentration is, for example, 1 × ¹⁰ 16 to 1 × 10 ^A pair of n-type well regions 140 (impurity concentration is, for example, about 1 × 10 ¹⁵ to 1 × 10 ¹⁶ / cm ³ ) are formed so as to sandwich about ¹⁷ / cm ³ . A field insulating film 40 is formed so as to cover the p ⁺ type channel stopper region 110.

A p-type well region 150 (impurity concentration is about 1 × 10 ¹⁶ to 1 × 10 ¹⁷ / cm ³ ) and one n ⁺ -type region 160 are formed on the surface of one n-type well region 140 of the low-voltage integrated circuit 410. (Impurity concentration is, for example, about 1 × 10 ¹⁸ to 1 × 10 ²⁰ / cm ³ ). A p ⁺ type region 170 (impurity concentration is, for example, about 1 × 10 ¹⁸ to 1 × 10 ²⁰ / cm ³ ) and another n ⁺ type region 160 are formed apart from each other on the surface portion of the p type well region 150. Yes. A base electrode 180 is formed on the p ⁺ type region 170 in the p type well region 150 so as to be connected to the p ⁺ type region 170, and on the n ⁺ type region 160 in the p type well region 150. the ^{n +} emitter electrode 181 so as to be connected to the type region 160 is formed, a collector electrode 182 as on the p-type well region 150 outside the ^{n +} -type region 160 is connected to the ^{n +} -type region 160 Is formed. Thus, an NPN bipolar transistor is formed on one n-type well region 140.

On the surface portion of the other n-type well region 140 of the low withstand voltage integrated circuit 410, an n ⁺ -type region 160 and a pair of p ⁺ -type regions 170 are formed separately from each other. On one ^{p +} -type region 170 is a collector electrode 190 so as to be connected with the ^{p +} -type region 170 is formed, so that on top the other ^{p +} -type region 170 is connected to the ^{p +} -type region 170 an emitter electrode 191 are formed, on the ^{n +} -type region 160 base electrode 192 so as to be connected to the ^{n +} -type region 160 is formed on. Thus, a PNP bipolar transistor is formed on the other n-type well region 140.

  In this embodiment, an NPN bipolar transistor and a PNP bipolar transistor are illustrated as low breakdown voltage elements used in the low breakdown voltage integrated circuit 410. However, the low breakdown voltage elements are not limited to this, and a general BiCMOS is used. (Bipolar complementary metal oxide semiconductor) Other elements used in the circuit may be used.

Next, the p-type semiconductor between the surface portion of the formation region of the n-type hole block region 400 in the p-type semiconductor substrate 10, that is, between the formation region (high breakdown voltage region) of the L-IGBT 390 and the formation region of the low breakdown voltage integrated circuit 410. An n ⁺ -type region 130 (impurity concentration is about 1 × 10 ¹⁸ to 1 × 10 ²⁰ / cm ³ ) and an n-type hole block layer 120 (impurity concentration is 1 × 10 10) surrounding the n ⁺ -type region 130 on the surface of the substrate 10. ¹⁵ to 1 × 10 ¹⁶ / cm ³ and a depth of about 10 μm). Further, a hole blocking voltage application electrode 200 so as to be connected to the ^{n +} -type region 130 on the ^{n +} -type region 130 is formed.

In addition, between the n-type hole block region 400 and the L-IGBT 390 in the p-type semiconductor substrate 10 and between the n-type hole block region 400 and the low breakdown voltage integrated circuit 410 in the p-type semiconductor substrate 10, p ⁺ type is provided. A channel stopper region 110 is formed, and a field insulating film 40 is formed so as to cover each p ⁺ type channel stopper region 110.

  Further, an interlayer film 210 is formed so as to cover the L-IGBT 390, the low breakdown voltage integrated circuit 410, and the n-type hole block region 400, and a protective film 220 is formed on the interlayer film 210. The emitter electrode 90, the collector electrode 100, the base electrode 180, the emitter electrode 181, the collector electrode 182, the collector electrode 190, the emitter electrode 191, the base electrode 192, and the hole blocking voltage application electrode 200 are formed so as to penetrate the interlayer film 210, respectively. Has been.

  In the present embodiment, the n-type hole block layer 120 is preferably formed simultaneously with at least one of the n-type drift region 20 of the L-IGBT 390 and the n-type well region 140 of the low voltage integrated circuit 410. . In this way, the n-type hole block layer 120 can be easily formed without increasing the number of steps. In this case, the semiconductor device of the present embodiment is different from the conventional semiconductor device shown in FIG. 12, for example, in order to realize element isolation between the L-IGBT and the low breakdown voltage integrated circuit. Instead of providing a region (such as the insulating film region 741 in FIG. 12), an impurity layer having the same impurity concentration gradient as that of the drift region of the L-IGBT or the well region of the low breakdown voltage integrated circuit is used.

In the present embodiment, for example, as shown in a plan view (chip surface view) of FIG. 3, a hole block voltage application electrode 200 (not shown) on the n ⁺ type region 130 in the n type hole block region 400 and For example, a pad 360 that is electrically connected via an Al wiring (not shown) is provided, and the pad 360 is electrically connected to the VDD terminal (internal circuit power supply terminal) 325 or the VCC terminal 324 in the switching power supply device shown in FIG. It is preferable to connect to. In this way, the effect of this embodiment described later can be obtained without specially arranging a terminal for applying a voltage to the n-type hole block region 400. Here, when the pad 360 is electrically connected to the VCC terminal 324, a higher voltage is applied to the n-type hole block region 400 than when the pad 360 is electrically connected to the VDD terminal 325. Therefore, the effect of this embodiment described later can be exhibited more remarkably.

  In this embodiment, the withstand voltage of the L-IGBT 390 is, for example, 800 V, and the magnitude of the voltage applied to the collector terminal 323 is, for example, about 700 V when off, and, for example, about several V to 10 V when on. Further, the low withstand voltage integrated circuit 410 is composed of, for example, a circuit element having a withstand voltage of 30 V or less, and the magnitude of the voltage applied to the VDD terminal (internal circuit power supply terminal) 325 is constant within a range of about 6 V to 8 V, for example. Voltage (always). That is, the formation region of the n-type hole block region 400 including the n-type hole block layer 120 and the like is provided on the formation region side of the low breakdown voltage integrated circuit 410. The magnitude of the voltage applied to the VCC terminal (auxiliary winding voltage input terminal) 324 is determined depending on the voltage of the secondary winding 342 and the winding ratio. It is in the range of about 20V (in this embodiment, about 20V), and is in the range of about 5V to 30V, for example, depending on the output status. That is, during normal operation, the voltage applied to the VCC terminal 324 is approximately the same as or higher than the voltage applied to the VDD terminal 325. However, unlike the voltage applied to the VDD terminal 325, the voltage applied to the VCC terminal 324 varies depending on the output status.

  The operation of the semiconductor device of this embodiment shown in FIGS. 2 and 3 will be described below.

  When a high voltage (for example, about 600 V) is applied to the collector electrode 100 in the off state in the L-IGBT 390, the n-type drift region 20 and the p-type semiconductor substrate 10 are in a reverse bias state, and the respective junctions thereof As the depletion layer spreads toward the inside, the electric field becomes uniform, thereby realizing high breakdown voltage characteristics.

In the conventional semiconductor device shown in FIG. 12, since dielectric isolation is used for element isolation between the L-IGBT and the low breakdown voltage integrated circuit, the insulating film interface (the P-type semiconductor region 513 and the insulating film 740 and the insulating film) A countermeasure (formation of the p ⁺ -type region 920) for a problem such as an increase in leakage at the interface with each of the film regions 741 was necessary. On the other hand, in the semiconductor device of this embodiment, pn junction isolation by the n-type hole block region 400 is used for element isolation between the L-IGBT and the low breakdown voltage integrated circuit. No countermeasure is required.

On the other hand, when a voltage equal to or higher than the threshold is applied to the gate electrode 80, the channel region immediately below the gate electrode 80 is inverted, and the L-IGBT 390 is turned on. When turned on, a large amount of holes are injected from the p ⁺ -type collector region 60 into the n-type drift region 20, whereby conductivity is modulated, and a large current flows from the p ⁺ -type collector region 60 to the n ⁺ -type emitter region 50. Flowing.

  At this time, the voltage applied to the hole block voltage application electrode 200 is set to the same voltage as the power supply voltage (that is, the internal circuit power supply terminal (VDD terminal) 325) of the low voltage integrated circuit 410 shown in FIG. If so, a depletion layer 230 having a thickness of about several tens of μm spreads from the junction surface between the p-type semiconductor substrate 10 and the n-type hole blocking layer 120 to the p-type semiconductor substrate 10 side. Therefore, when the thickness of the depletion layer 230 is combined with the thickness of the n-type hole blocking layer 120 (about 10 μm), the holes present in the region of the depth of 20 μm or more in the p-type semiconductor substrate 10 are also affected. Can be prevented from entering the low voltage integrated circuit 410 from the L-IGBT 390.

By the way, in the semiconductor device according to the present embodiment, the distance between the p ⁺ -type collector region 60 and the n ⁺ -type emitter region 50 is 80 μm, the applied voltage to the gate electrode 80 is 8 V, and the collector voltage is applied to the collector electrode 100. Is set to 8V, and the inventors of the present application have examined the hole density distribution in the cross-sectional structure by two-dimensional simulation, and found that the low withstand voltage integrated circuit 410 is particularly around the p-type base region 30 having a depth of about several μm. It has become clear that the halls that are trying to invade are concentrated. On the other hand, as described above, in the semiconductor device according to the present embodiment, since the movement of holes existing in a region having a depth of 20 μm or more in the p-type semiconductor substrate 10 can be prevented, the high breakdown voltage in which the L-IGBT 390 is disposed. The region and the low withstand voltage integrated circuit 410 including low withstand voltage elements can be reliably electrically separated.

  In the present embodiment, the voltage applied to the hole block voltage application electrode 200 is set to a voltage common to the power supply voltage (that is, the internal circuit power supply terminal (VDD terminal) 325) of the low voltage integrated circuit 410 shown in FIG. Although set, the present invention is not limited to this. For example, the voltage applied to the hole block voltage application electrode 200 may be set to a voltage common to the voltage applied to the auxiliary winding 343 shown in FIG. 1 (voltage applied to the VCC terminal 324). In this case, by setting the voltage applied to the auxiliary winding 343 so as not to be equal to or lower than the power supply voltage of the low voltage integrated circuit 410, in other words, a voltage higher than the power voltage of the low voltage integrated circuit 410 is set. By applying to the hole block voltage application electrode 200, the depletion layer 230 can be further expanded, and thus higher separation characteristics can be realized. Specifically, by setting the voltage applied to the auxiliary winding 343 to 20 V, for example, the depletion layer 230 is formed on the p-type semiconductor substrate 10 side from the junction surface between the p-type semiconductor substrate 10 and the n-type hole blocking layer 120. Can be expanded by about 16 μm or more. In this case, when the thickness of the depletion layer 230 and the thickness of the n-type hole blocking layer 120 (about 10 μm) are combined, the holes present in the region of the depth of 26 μm or more in the p-type semiconductor substrate 10 are also affected. Holes can be prevented from entering the low voltage integrated circuit 410 from the L-IGBT 390, and high isolation characteristics can be realized.

  As described above, according to the semiconductor device of this embodiment, a depletion layer is formed from the pn junction by applying a reverse bias to the pn junction between the p-type semiconductor substrate 10 and the n-type hole block layer 120. Since 230 spreads, it is possible to prevent the holes generated when the L-IGBT 390 is turned on from entering the low voltage integrated circuit 410. That is, it is possible to reliably prevent an electrical influence on the low voltage element of the low voltage integrated circuit 410 when the L-IGBT 390 is on.

  Moreover, since the structure of the semiconductor device of this embodiment is a structure obtained without using an SOI substrate, a trench, or the like, the semiconductor device of this embodiment can be provided by a simple and inexpensive process.

  Hereinafter, a method for manufacturing the semiconductor device of this embodiment shown in FIGS. 2 and 3 will be described. 4 (a), 4 (b), 5 (a), and 5 (b) are cross-sectional views showing respective steps of the method of manufacturing the semiconductor device of the present embodiment. 4 (a), 4 (b) and FIGS. 5 (a), 5 (b), the same components as those of the semiconductor device of the present embodiment shown in FIGS. The duplicated explanation is omitted.

  First, as shown in FIG. 4A, an n-type impurity such as phosphorus is ion-implanted into a predetermined region of the p-type semiconductor substrate 10 using, for example, a resist mask 370 to thermally diffuse the impurity. As a result, the n-type drift region 20 of the L-IGBT 390, the n-type hole block layer 120 of the n-type hole block region 400, and the n-type well region 140 of the low withstand voltage integrated circuit 410 are formed. The n-type drift region 20, the n-type hole block layer 120, and the n-type well region 140 each have a depth of about 10 μm.

Next, after removing the resist mask 370, as shown in FIG. 4B, for example, a resist or the like (not shown) is used as a mask pattern on the surface of a predetermined region of the p-type semiconductor substrate 10, for example, After ion implantation of p-type impurities such as boron, the p-type base region 30 of the L-IGBT 390 and the p-type well region 150 of the low voltage integrated circuit 410 are formed, and then the p ⁺ -type channel stopper region 110 between the elements. Form. Next, for example, field oxidation is performed using SiN or the like (not shown) as a mask pattern, and thereafter, a process of removing the SiN mask by wet etching, and the like, thereby performing a field insulating film having a thickness of about 1.0 μm, for example. 40 is selectively formed on the p-type semiconductor substrate 10.

Next, as shown in FIG. 5A, dry oxidation at, for example, about 1100 ° C. is performed on the p-type semiconductor substrate 10 to at least cover the end portion of the n-type drift region 20 (covered with the field insulating film 40). A gate insulating film 70 having a thickness of, for example, about 500 mm is formed on the surface of the p-type semiconductor substrate 10 from a portion not formed) to a predetermined portion of the p-type base region 30. Thereafter, a polysilicon film having a thickness of, for example, 4000 mm is deposited on the p-type semiconductor substrate 10 including the gate insulating film 70 by, for example, LP (low pressure) -CVD (chemical vapor deposition) growth. The gate electrode 80 is formed by patterning the film. Next, for example, p-type impurities such as boron are selectively ion-implanted into the p-type semiconductor substrate 10 using, for example, a resist (not shown), the gate electrode 80, and the like as mask patterns. ^{The +} type collector region 60 and the p ⁺ type base contact region 380 and the p ⁺ type region 170 of the low withstand voltage integrated circuit 410 are formed. Further, for example, a resist used (not shown) and a gate electrode 80 or the like as a mask pattern, respectively, for example by selectively ion-implanting an n-type impurity such as arsenic into the p-type semiconductor substrate 10, L-IGBT390 of n ⁺ The n ⁺ -type region 130 of the n-type emitter block 50, the n-type hole block region 400, and the n ⁺ -type region 160 of the low withstand voltage integrated circuit 410 are formed.

Next, as shown in FIG. 5B, on the p-type semiconductor substrate 10, a high breakdown voltage region in which the L-IGBT 390 is disposed, a low breakdown voltage integrated circuit 410 composed of low breakdown voltage elements, and an n-type hole. An interlayer film 210 made of, for example, a CVD oxide film having a thickness of about 1.5 μm is deposited to cover the block region 400. Next, contact holes are selectively formed in the interlayer film 210 using a resist or the like (not shown) as a mask pattern. Thereafter, an emitter electrode 90 connected to the n ⁺ -type emitter region 50 and the p ⁺ -type base contact region 380 is formed by, for example, forming an AL-Si film on the interlayer film 210 so that the contact holes are embedded, Collector electrode 100 connected to p ⁺ type collector region 60, hole block voltage application electrode 200 connected to n ⁺ type region 130, base electrode 180, emitter electrode 181 and collector electrode 182 of an NPN bipolar transistor, and PNP bipolar A base electrode 192, an emitter electrode 191 and a collector electrode 190 of the transistor are formed. Next, a protective film 220 made of, for example, a SiN film is formed on the interlayer film 210.

  In the semiconductor device manufacturing method of the present embodiment, an NPN bipolar transistor and a PNP bipolar transistor are exemplified as the low breakdown voltage elements constituting the low breakdown voltage integrated circuit 410, but the low breakdown voltage elements are limited to this. Instead, a resistor used in a standard CMOS circuit, an Nch MOSFET (metal oxide semiconductor field-effect transistor), a Pch MOSFET, or the like may be formed as a low breakdown voltage element.

  According to the semiconductor device manufacturing method of the present embodiment described above, the n-type drift region 20, the n-type hole blocking layer 120, and the n-type well region 140 can be formed at the same time. Compared with this semiconductor device, it is not necessary to increase the number of processes in particular for junction separation formation. That is, when manufacturing the semiconductor device of this embodiment shown in FIGS. 2 and 3, the manufacturing process can be simplified and the process cost can be reduced.

  In addition, according to the method for manufacturing a semiconductor device of the present embodiment, a standard CMOS process is used as it is, and a control circuit (low-voltage integrated circuit) including an L-IGBT arranged in a high-breakdown-voltage region and a low-breakdown-voltage element. ) And their isolation regions (hole block regions) can be easily formed without increasing the number of steps.

  In the semiconductor device manufacturing method of the present embodiment, the n-type hole block layer 120 is formed simultaneously with both the n-type drift region 20 and the n-type well region 140. Instead, the n-type hole block layer 120 is formed. May be formed simultaneously with either one of the n-type drift region 20 and the n-type well region 140.

(Second Embodiment)
Hereinafter, a semiconductor device and a manufacturing method thereof according to the second embodiment of the present invention will be described with reference to the drawings.

  FIG. 6 is a cross-sectional view of a semiconductor device according to the second embodiment. In FIG. 6, the same components as those in the first embodiment shown in FIG.

  The second embodiment is different from the first embodiment only in the configuration of the n-type hole block region, and the other L-IGBT and the low voltage integrated circuit are the same as those in the first embodiment. Therefore, hereinafter, the structure of the n-type hole block region 401 of this embodiment shown in FIG. 6 will be described.

As shown in FIG. 6, a low breakdown voltage integrated circuit 410 composed of a formation region of the n-type hole block region 401 on the surface portion of the p-type semiconductor substrate 10 (that is, a high breakdown voltage region where the L-IGBT 390 is disposed and a low breakdown voltage element). For example, a trench 250 having a width of 30 μm and a depth of 10 μm is formed. Then, below the trench 250 in the p-type semiconductor substrate 10, an n ⁺ -type region 131 (impurity concentration is about 1 × 10 ¹⁸ to 1 × 10 ²⁰ / cm ³ ) and an n-type hole block layer 121 surrounding the n ⁺ -type region 131. (For example, the impurity concentration is about 1 × 10 ¹⁵ to 1 × 10 ¹⁶ / cm ³ and the depth is about 10 μm). A part of the n-type hole block layer 121 is also formed near the wall surface of the trench 250 in the p-type semiconductor substrate 10. A hole blocking voltage application electrode 201 is formed on the n ⁺ type region 131 in the trench 250 so as to be connected to the n ⁺ type region 131. That is, the n-type hole block region 401 of this embodiment is formed below the trench 250.

  An interlayer film 212 is formed so as to cover the L-IGBT 390, the low breakdown voltage integrated circuit 410, and the n-type hole block region 401. The interlayer film 212 is formed so as to partially fill the trench 250. The emitter electrode 90, the collector electrode 100, the base electrode 180, the emitter electrode 181, the collector electrode 182, the collector electrode 190, the emitter electrode 191, the base electrode 192, and the hole blocking voltage application electrode 201 are formed so as to penetrate the interlayer film 212, respectively. Has been. A protective film 222 is formed on the interlayer film 212 so as to completely fill the trench 250.

  In the present embodiment, the n-type hole block layer 121 is preferably formed simultaneously with at least one of the n-type drift region 20 of the L-IGBT 390 and the n-type well region 140 of the low voltage integrated circuit 410. . In this way, the n-type hole block layer 121 can be easily formed without increasing the number of steps. In this case, the semiconductor device of the present embodiment is different from the conventional semiconductor device shown in FIG. 12, for example, in order to realize element isolation between the L-IGBT and the low breakdown voltage integrated circuit. Instead of providing a region (such as the insulating film region 741 in FIG. 12), an impurity layer having the same impurity concentration gradient as that of the drift region of the L-IGBT or the well region of the low breakdown voltage integrated circuit is used.

Further, in this embodiment, the hole block voltage application electrode 201 on the n ⁺ type region 131 of the n type hole block region 401 is connected to the VDD terminal 325 in the switching power supply device shown in FIG. 1 as in the first embodiment. Alternatively, it may be electrically connected to the VCC terminal 324.

  Hereinafter, the operation of the semiconductor device of this embodiment shown in FIG. 6 will be described.

  The operation of the semiconductor device of this embodiment is different from that of the first embodiment in that the trench 250 is provided so that when the L-IGBT 390 is turned on, the depth of the trench 250 is p. Even in a deeper region of the type semiconductor substrate 10, it is possible to prevent holes from entering from the L-IGBT 390 to the low voltage integrated circuit 410.

  Therefore, according to the semiconductor device of this embodiment, the following effects can be obtained in addition to the effects of the first embodiment. That is, in the first embodiment, for example, the voltage applied to the gate electrode 80 of the L-IGBT 390 is increased or the collector voltage applied to the collector electrode 100 of the L-IGBT 390 is increased. When the on-current per unit area of the L-IGBT 390 is further increased, a problem that holes easily flow from the L-IGBT 390 into the low voltage integrated circuit 410 occurs. On the other hand, in this embodiment, the hole from the L-IGBT 390 to the low withstand voltage integrated circuit 410 is adjusted by adjusting the depth of the trench 250 according to the magnitude of the on-current per unit area of the L-IGBT 390. Can be completely prevented.

  Hereinafter, a method for manufacturing the semiconductor device of this embodiment shown in FIG. 6 will be described. 7A, 7B, 8A, 8B, and 9 are cross-sectional views showing respective steps of the semiconductor device manufacturing method of the present embodiment. In FIGS. 7A, 7B, 8A, 8B, and 9, the semiconductor device of the first embodiment shown in FIGS. 2 and 3 or the semiconductor of the present embodiment shown in FIG. The same components as those of the apparatus are denoted by the same reference numerals, and redundant description is omitted.

  First, as shown in FIG. 7A, a trench 250 is selectively formed in the formation region of the n-type hole block region 401 in the surface portion of the p-type semiconductor substrate 10 using, for example, a resist mask (not shown). .

  Next, as shown in FIG. 7B, an n-type impurity such as phosphorus is ion-implanted into a predetermined region of the p-type semiconductor substrate 10 using, for example, a resist mask 371 to thermally diffuse the impurity. As a result, the n-type drift region 20 of the L-IGBT 390, the n-type hole block layer 121 of the n-type hole block region 401, and the n-type well region 140 of the low withstand voltage integrated circuit 410 are formed. The n-type hole block layer 121 is formed below the trench 250 and in the vicinity of the wall surface in the p-type semiconductor substrate 10. The n-type drift region 20, the n-type hole block layer 121, and the n-type well region 140 each have a depth of about 10 μm.

Next, after removing the resist mask 371, as shown in FIG. 8A, for example, using a resist or the like (not shown) as a mask pattern on the surface portion of a predetermined region of the p-type semiconductor substrate 10, for example, After ion implantation of p-type impurities such as boron, the p-type base region 30 of the L-IGBT 390 and the p-type well region 150 of the low voltage integrated circuit 410 are formed, and then the p ⁺ -type channel stopper region 110 between the elements. Form. Next, for example, field oxidation is performed using SiN or the like (not shown) as a mask pattern, and thereafter, a process of removing the SiN mask by wet etching, and the like, thereby performing a field insulating film having a thickness of about 1.0 μm, for example. 40 is selectively formed on the p-type semiconductor substrate 10.

Next, as shown in FIG. 8B, the p-type semiconductor substrate 10 is dry-oxidized at about 1100 ° C., for example, so that at least the end portion of the n-type drift region 20 (covered by the field insulating film 40) is formed. A gate insulating film 70 having a thickness of, for example, about 500 mm is formed on the surface of the p-type semiconductor substrate 10 from a portion not formed) to a predetermined portion of the p-type base region 30. Thereafter, a polysilicon film having a thickness of, for example, 4000 mm is deposited on the p-type semiconductor substrate 10 including the gate insulating film 70 by, for example, LP-CVD growth, and then the polysilicon film is patterned to form a gate. An electrode 80 is formed. Next, for example, p-type impurities such as boron are selectively ion-implanted into the p-type semiconductor substrate 10 using, for example, a resist (not shown), the gate electrode 80, and the like as mask patterns. ^{The +} type collector region 60 and the p ⁺ type base contact region 380 and the p ⁺ type region 170 of the low withstand voltage integrated circuit 410 are formed. Further, for example, a resist used (not shown) and a gate electrode 80 or the like as a mask pattern, respectively, for example by selectively ion-implanting an n-type impurity such as arsenic into the p-type semiconductor substrate 10, L-IGBT390 of n ⁺ The n ⁺ -type region 131 of the n-type emitter region 50, the n-type hole block region 401, and the n ⁺ -type region 160 of the low withstand voltage integrated circuit 410 are formed.

Next, as shown in FIG. 9, on the p-type semiconductor substrate 10, a high breakdown voltage region in which the L-IGBT 390 is disposed, a low breakdown voltage integrated circuit 410 including low breakdown voltage elements, and an n-type hole block region 401. For example, an interlayer film 212 made of a CVD oxide film having a thickness of about 1.5 μm is deposited. Next, contact holes are selectively formed in the interlayer film 212 using a resist or the like (not shown) as a mask pattern. Thereafter, an emitter electrode 90 connected to the n ⁺ -type emitter region 50 and the p ⁺ -type base contact region 380 is formed by forming, for example, an AL-Si film on the interlayer film 212 so that the contact holes are embedded, Collector electrode 100 connected to p ⁺ type collector region 60, hole block voltage applying electrode 201 connected to n ⁺ type region 131, base electrode 180, emitter electrode 181 and collector electrode 182 of an NPN bipolar transistor, and PNP bipolar A base electrode 192, an emitter electrode 191 and a collector electrode 190 of the transistor are formed. Next, a protective film 222 made of, for example, a SiN film is formed on the interlayer film 212.

  In the semiconductor device manufacturing method of the present embodiment, an NPN bipolar transistor and a PNP bipolar transistor are exemplified as the low breakdown voltage elements constituting the low breakdown voltage integrated circuit 410, but the low breakdown voltage elements are limited to this. Instead, a resistor, an Nch MOSFET, a Pch MOSFET, or the like used in a standard CMOS circuit may be formed as a low breakdown voltage element.

  According to the semiconductor device manufacturing method of the present embodiment described above, the n-type drift region 20, the n-type hole blocking layer 121, and the n-type well region 140 can be formed at the same time. Compared with this semiconductor device, it is not necessary to increase the number of processes in particular for junction separation formation. That is, when manufacturing the semiconductor device of this embodiment shown in FIG. 6, the manufacturing process can be simplified and the process cost can be reduced.

  In addition, according to the method for manufacturing a semiconductor device of the present embodiment, a standard CMOS process is used as it is, and a control circuit (low-voltage integrated circuit) including an L-IGBT arranged in a high-breakdown-voltage region and a low-breakdown-voltage element. ) And their isolation regions (hole block regions) can be easily formed without increasing the number of steps.

  In the semiconductor device manufacturing method of this embodiment, the n-type hole block layer 121 is formed simultaneously with both the n-type drift region 20 and the n-type well region 140. Instead, the n-type hole block layer 121 is formed. May be formed simultaneously with either one of the n-type drift region 20 and the n-type well region 140.

(Third embodiment)
Hereinafter, a semiconductor device and a manufacturing method thereof according to a third embodiment of the present invention will be described with reference to the drawings.

  FIG. 10 is a cross-sectional view of the semiconductor device according to the third embodiment, and FIG. 11 is a plan view of the semiconductor device according to the third embodiment. FIG. 10 is a cross-sectional view taken along line B-B ′ in FIG. 11. Moreover, in FIG. 11, illustration of a part of component is abbreviate | omitted. Further, in FIGS. 10 and 11, the same components as those of the first embodiment shown in FIGS.

As shown in FIG. 10, in the semiconductor device of this embodiment as well, in the same manner as in the first embodiment, a region (high breakdown voltage) of a p-type semiconductor substrate 10 (impurity concentration is about 1 × 10 ¹⁴ / cm ^3, for example). An L-IGBT 390 is formed on the region), and a low breakdown voltage integrated circuit 410 composed of low breakdown voltage elements is formed on the other region of the p-type semiconductor substrate 10.

  A feature of this embodiment is that, for example, a high breakdown voltage nchMOSFET 402 is provided as a lateral high breakdown voltage field effect transistor between the L-IGBT 390 and the low breakdown voltage integrated circuit 410 in the p-type semiconductor substrate 10. That is, the third embodiment is different from the first embodiment in that a high breakdown voltage nch-MOSFET 402 is provided in place of the n-type hole block region 400 of the first embodiment. The high breakdown voltage nch MOSFET 402 of this embodiment has an n-type drain drift region 22 that functions as an n-type hole block region. Hereinafter, the structure of the high breakdown voltage nch MOSFET 402 of this embodiment shown in FIG. 10 will be described.

As shown in FIG. 10, between the formation region of the high breakdown voltage nchMOSFET 402 on the surface portion of the p-type semiconductor substrate 10 (that is, between the high breakdown voltage region where the L-IGBT 390 is disposed and the low breakdown voltage integrated circuit 410 composed of low breakdown voltage elements). N ⁺ type drain region 53 (impurity concentration is, for example, about 1 × 10 ¹⁸ to 1 × 10 ²⁰ / cm ³ ) and n type drain drift region 22 (impurity) surrounding this n ⁺ type drain region 53 The concentration is, for example, about 1 × 10 ¹⁵ to 1 × 10 ¹⁶ / cm ³ ). Further, in the formation region of the high breakdown voltage nch MOSFET 402 on the surface portion of the p type semiconductor substrate 10, the n ⁺ type source region 54 (impurity) is formed on the low breakdown voltage integrated circuit 410 side with a space between the n type drain drift region 22. concentration, for example, with ^{1 × 10 18 ~1 × 10 20} / cm 3 or so) is formed, the ^{n +} -type source region 54 on the opposite side of the viewed from the ^{n +} -type source region 54 ^{n +} -type drain region 53 A p ⁺ type source contact region 382 (impurity concentration of about 1 × 10 ¹⁸ to 1 × 10 ²⁰ / cm ^3, for example) is formed so as to be adjacent to each other. The p-type base region 30 (impurity concentration is, for example, 1 × 10 ¹⁶ to 1 × 10 ¹⁷ / cm) so as to surround the n ⁺ -type source region 54 and the p ⁺ -type source contact region 382 and be in contact with the n-type drain drift region 22. ³ ) to a depth of about several μm. Further, in the formation region of the high breakdown voltage nch-MOSFET 402 on the surface portion of the p-type semiconductor substrate 10, the n ⁺ -type source region 52 (impurity concentration is on the L-IGBT 390 side with a space from the n-type drain drift region 22. For example, about 1 × 10 ¹⁸ to 1 × 10 ²⁰ / cm ³ ) are formed. The n ⁺ type source region 52 is formed so as to be in contact with the p ⁺ type base contact region 380 of the L-IGBT 390 and surrounded by the p type base region 30 of the L-IGBT 390.

A field insulating film 40 is selectively formed on the n-type drain drift region 22. A gate insulating film 72 is formed on the surface of the p-type semiconductor substrate 10 from at least both ends of the n-type drain drift region 22 to a predetermined portion of the p-type base region 30 adjacent to both sides. A gate electrode 82 is extended on 72. Here, at a location not shown, the gate electrode 82 is connected to the gate electrode 80 of the L-IGBT 390. Further, a source electrode 280 connected to both the n ⁺ type source region 54 and the p ⁺ type source contact region 382 is formed, and the n ⁺ type source region 52 and the p ⁺ type base of the L-IGBT 390 are formed. A source / emitter common electrode 270 connected to each of the regions is formed on the contact region 380 and the n ⁺ -type emitter region 50, and the n ⁺ -type drain region 53 and the n ⁺ -type drain region 53 are connected to the n ⁺ -type drain region 53. A drain electrode 290 to be connected is formed.

  Further, an interlayer film 210 is formed so as to cover the L-IGBT 390, the high breakdown voltage nch MOSFET 402 and the low breakdown voltage integrated circuit 410, and a protective film 220 is formed on the interlayer film 210. The emitter electrode 90, the collector electrode 100, the base electrode 180, the emitter electrode 181, the collector electrode 182, the collector electrode 190, the emitter electrode 191, the base electrode 192, the source / emitter common electrode 270, the source electrode 280, and the drain electrode 290 are interlayer films. 210 is formed so as to penetrate through 210.

In this embodiment, for example, as shown in the plan view of FIG. 11, the n ⁺ type drain region 53 and the p ⁺ type collector region 60 are set to a common potential, and the n ⁺ type emitter region 50 and the p ^{+ The +} type base contact region 380, the n ⁺ type source region 52, the n ⁺ type source region 54, and the p ⁺ type source contact region 382 are grounded.

  Furthermore, in the present embodiment, the n-type drain drift region 22 is preferably formed simultaneously with at least one of the n-type drift region 20 of the L-IGBT 390 and the n-type well region 140 of the low withstand voltage integrated circuit 410. .

  The operation of the semiconductor device of this embodiment shown in FIGS. 10 and 11 will be described below.

The operation of the semiconductor device of the present embodiment is different from that of the first embodiment in that the L-IGBT 390 (high withstand voltage region) and the low withstand voltage integrated circuit 410 are located when the L-IGBT 390 is turned on. The high breakdown voltage nch-MOSFET 402 arranged in the circuit is additionally operated. That is, when the L-IGBT 390 is turned on, the high breakdown voltage nch MOSFET 402 is also turned on. Here, as described above, the voltage applied to the drain electrode 290 is about 6 to 7 V which is the same as the voltage applied to the collector electrode 100 of the L-IGBT 390. When the above voltages are applied to the drain electrode 290 and the collector electrode 100, the drain drift region 22 surrounding the n ⁺ -type drain region 53 and the p-type semiconductor substrate 10 are in a reverse-biased state. A depletion layer 232 extends over a range of about 9 μm in depth toward the type semiconductor substrate 10. Thereby, an element isolation function similar to that of the n-type hole block layer 120 of the first embodiment can be realized.

  In the present embodiment, since the high breakdown voltage nch MOSFET 402 having the n type drain drift region 22 functioning as the n type hole block region is disposed, the high breakdown voltage nch MOSFET 402 is also turned on when the L-IGBT 390 is turned on. Compared with the semiconductor device according to the first or second embodiment, a larger current driving capability can be obtained. For this reason, according to this embodiment, in addition to the effect of 1st Embodiment, the following effects are acquired. That is, in particular, when the collector voltage of the L-IGBT 390 is lower than the built-in voltage, for example, 1 V or lower, no current flows through the L-IGBT 390 or the current becomes very small. Current flows. Therefore, for example, in the switching power supply device using the semiconductor device of this embodiment, the conduction loss can be minimized over a wide range from the low output state to the high output state.

  The present invention relates to a semiconductor device in which a high breakdown voltage element and a low breakdown voltage element are integrated and a manufacturing method thereof. For example, when applied to a switching power supply device, the high breakdown voltage element and the low breakdown voltage element are separated by pn junction isolation. Can be easily and reliably separated, and is very useful.

FIG. 1 is a circuit diagram showing an example of a switching power supply device in which a semiconductor device according to each embodiment of the present invention is used. FIG. 2 is a cross-sectional view of the semiconductor device according to the first embodiment of the present invention. FIG. 3 is a plan view of the semiconductor device according to the first embodiment of the present invention. FIGS. 4A and 4B are cross-sectional views showing respective steps of the method for manufacturing the semiconductor device according to the first embodiment of the present invention. 5A and 5B are cross-sectional views showing the respective steps of the method for manufacturing the semiconductor device according to the first embodiment of the present invention. FIG. 6 is a sectional view of a semiconductor device according to the second embodiment of the present invention. FIGS. 7A and 7B are cross-sectional views showing respective steps of the method for manufacturing the semiconductor device according to the second embodiment of the present invention. FIGS. 8A and 8B are cross-sectional views showing respective steps of the method for manufacturing the semiconductor device according to the second embodiment of the present invention. FIG. 9 is a cross-sectional view showing each step of the semiconductor device manufacturing method according to the second embodiment of the present invention. FIG. 10 is a sectional view of a semiconductor device according to the third embodiment of the present invention. FIG. 11 is a plan view of a semiconductor device according to the third embodiment of the present invention. FIG. 12 is a cross-sectional view of a conventional semiconductor device.

Explanation of symbols

10 p-type semiconductor substrate 20 n-type drift region 22 n-type drain drift region 30 p-type base region 40 field insulating film 50, 52 n ⁺ -type emitter region 53 n ⁺ -type drain region 54 n ⁺ -type source region 60 p ⁺ -type collector Region 70, 72 Gate insulating film 80, 82 Gate electrode 90 Emitter electrode 100 Collector electrode 110 p ⁺ type channel stopper region 120, 121 n type hole blocking layer 130, 131 n ⁺ type region 140 n type well region 150 p type well region 160 n ⁺ -type region 170 p ⁺ -type region 180 base electrode 181 emitter electrode 182 a collector electrode 190 a collector electrode 191 an emitter electrode 192 a base electrode 200, 201 hole blocking voltage application electrode 210, 212 interlayer film 220, 222 protective film 30,231,232 depletion 250 trench 270 semiconductor device 323 L-IGBT of the input terminals of the source / emitter common electrode 280 source electrode 290 drain electrode 320 for a switching power supply apparatus (collector terminal)
324 Auxiliary winding voltage input terminal (VCC terminal)
325 Internal circuit power supply terminal (VDD terminal)
326 GND terminal 327, 328 Capacitor 329 Diode 330 Primary side rectifying and smoothing circuit 331, 332 Input terminal 333 Bridge diode 334 Electrolytic capacitor 335 Resistance 340 Transformer 341 Primary winding 342 Secondary winding 343 Auxiliary winding 350 Diode 351 Electrolytic capacitor 352 Secondary Secondary control circuit 353, 354 Output terminal 355 Photocoupler 360 Pad 370 Resist mask 371 Resist mask 380 p ⁺ type base contact region 382 p ⁺ type source contact region 390 L-IGBT
400, 401 n-type hole block region 402 High breakdown voltage nch MOSFET
410 Low-breakdown voltage integrated circuit 511 Si support substrate 512 Si substrate 513 P-type semiconductor region 521 n-type drift region 531 p ⁺ -type base region 551 n ⁺ -type emitter region 561 p ⁺ -type collector region 571 Gate insulating film 581 Gate electrode 591 Emitter electrode 601 collector electrode 611 p ⁺ type channel stopper region 641 n type well region 651 p type well region 661 n ⁺ type region 671 p ⁺ type region 683 base electrode 684 emitter electrode 685 collector electrode 693 collector electrode 694 emitter electrode 695 base electrode 711 interlayer Film 721 Protective film 740 Insulating film 741 Insulating film region 881 p ⁺ type base contact region 891 L-IGBT
911 Control circuit 920 High concentration P-type semiconductor region

Claims (7)

A semiconductor device in which a lateral insulated gate bipolar transistor and a low breakdown voltage integrated circuit are formed on a first conductivity type semiconductor region,
A semiconductor in which a second conductivity type hole block region to which a predetermined bias is applied is formed between the lateral insulated gate bipolar transistor and the low breakdown voltage integrated circuit in the first conductivity type semiconductor region. apparatus. The semiconductor device according to claim 1,
The lateral insulated gate bipolar transistor has a second conductivity type drift region formed in the first conductivity type semiconductor region,
The low withstand voltage integrated circuit includes an element having a second conductivity type well region formed in the first conductivity type semiconductor region,
The semiconductor device according to claim 1, wherein the second conductivity type hole block region has the same impurity concentration gradient as at least one of the second conductivity type drift region and the second conductivity type well region. The semiconductor device according to claim 1 or 2,
A trench is formed between the lateral insulated gate bipolar transistor and the low breakdown voltage integrated circuit in the first conductivity type semiconductor region;
The semiconductor device according to claim 1, wherein the second conductivity type hole block region is formed below the trench in the first conductivity type semiconductor region. The semiconductor device according to any one of claims 1 to 3,
The low withstand voltage integrated circuit controls the switching of the lateral insulated gate bipolar transistor,
A voltage applied to the second conductivity type hole block region is the same as a power supply voltage of the low breakdown voltage integrated circuit for controlling switching of the lateral insulated gate bipolar transistor. The semiconductor device according to claim 1,
A lateral high breakdown voltage field effect transistor having a drain drift region serving as the second conductivity type hole block region is formed between the lateral insulated gate bipolar transistor and the low breakdown voltage integrated circuit in the first conductivity type semiconductor region. A semiconductor device characterized by comprising: A switching power supply device using the semiconductor device according to claim 1,
A transformer having a primary winding, a secondary winding and an auxiliary winding;
The primary winding of the transformer is connected to the lateral insulated gate bipolar transistor;
The auxiliary winding of the transformer is connected to the low voltage integrated circuit,
The switching power supply device, wherein a voltage applied to the auxiliary winding and a voltage applied to the second conductivity type hole block region are the same. A method of manufacturing a semiconductor device in which a lateral insulated gate bipolar transistor and a low breakdown voltage integrated circuit are formed on a first conductivity type semiconductor region,
A step (a) of forming a second conductivity type drift region of the lateral insulated gate bipolar transistor in the first conductivity type semiconductor region;
(B) forming a second conductivity type well region of an element included in the low withstand voltage integrated circuit in the first conductivity type semiconductor region;
Forming a second conductivity type hole block region to which a predetermined bias is applied between the lateral insulated gate bipolar transistor and the low breakdown voltage integrated circuit in the first conductivity type semiconductor region,
The method of manufacturing a semiconductor device, wherein the step (c) is performed simultaneously with at least one of the step (a) and the step (b).

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