JP2007528123A5 - - Google Patents

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Publication number
JP2007528123A5
JP2007528123A5 JP2006537994A JP2006537994A JP2007528123A5 JP 2007528123 A5 JP2007528123 A5 JP 2007528123A5 JP 2006537994 A JP2006537994 A JP 2006537994A JP 2006537994 A JP2006537994 A JP 2006537994A JP 2007528123 A5 JP2007528123 A5 JP 2007528123A5
Authority
JP
Japan
Prior art keywords
semiconductor region
semiconductor
raised
forming
gate electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2006537994A
Other languages
English (en)
Japanese (ja)
Other versions
JP2007528123A (ja
Filing date
Publication date
Priority claimed from DE10351008A external-priority patent/DE10351008B4/de
Application filed filed Critical
Priority claimed from PCT/US2004/031038 external-priority patent/WO2005045924A1/en
Publication of JP2007528123A publication Critical patent/JP2007528123A/ja
Publication of JP2007528123A5 publication Critical patent/JP2007528123A5/ja
Pending legal-status Critical Current

Links

JP2006537994A 2003-10-31 2004-09-17 高さが異なる隆起したドレインおよびソース領域を有するトランジスタを形成するための先進技術 Pending JP2007528123A (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
DE10351008A DE10351008B4 (de) 2003-10-31 2003-10-31 Verfahren zur Herstellung von Transistoren mit erhöhten Drain- und Sourcegebieten mit unterschiedlicher Höhe sowie ein Halbleiterbauelement
US10/862,518 US7176110B2 (en) 2003-10-31 2004-06-07 Technique for forming transistors having raised drain and source regions with different heights
PCT/US2004/031038 WO2005045924A1 (en) 2003-10-31 2004-09-17 An advanced technique for forming transistors having raised drain and source regions with different height

Publications (2)

Publication Number Publication Date
JP2007528123A JP2007528123A (ja) 2007-10-04
JP2007528123A5 true JP2007528123A5 (de) 2007-11-22

Family

ID=34575412

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2006537994A Pending JP2007528123A (ja) 2003-10-31 2004-09-17 高さが異なる隆起したドレインおよびソース領域を有するトランジスタを形成するための先進技術

Country Status (4)

Country Link
JP (1) JP2007528123A (de)
KR (1) KR101130331B1 (de)
GB (1) GB2422488B (de)
WO (1) WO2005045924A1 (de)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060252191A1 (en) * 2005-05-03 2006-11-09 Advanced Micro Devices, Inc. Methodology for deposition of doped SEG for raised source/drain regions
DE102005030583B4 (de) * 2005-06-30 2010-09-30 Advanced Micro Devices, Inc., Sunnyvale Verfahren zur Herstellung von Kontaktisolationsschichten und Silizidgebieten mit unterschiedlichen Eigenschaften eines Halbleiterbauelements und Halbleiterbauelement

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US616582A (en) * 1898-12-27 Victor odqtjist and john c
US690636A (en) * 1900-12-19 1902-01-07 Joseph Coldwell Warp stop-motion for looms.
US5030582A (en) * 1988-10-14 1991-07-09 Matsushita Electric Industrial Co., Ltd. Method of fabricating a CMOS semiconductor device
JP2964925B2 (ja) * 1994-10-12 1999-10-18 日本電気株式会社 相補型ｍｉｓ型ｆｅｔの製造方法
JP2000124327A (ja) * 1998-10-14 2000-04-28 Toshiba Corp 半導体装置及びその製造方法
US6235568B1 (en) * 1999-01-22 2001-05-22 Intel Corporation Semiconductor device having deposited silicon regions and a method of fabrication
TW497120B (en) * 2000-03-06 2002-08-01 Toshiba Corp Transistor, semiconductor device and manufacturing method of semiconductor device
JP2002026313A (ja) * 2000-07-06 2002-01-25 Hitachi Ltd 半導体集積回路装置およびその製造方法
JP2002043567A (ja) * 2000-07-27 2002-02-08 Mitsubishi Electric Corp 半導体装置およびその製造方法
JP2002231908A (ja) * 2001-02-06 2002-08-16 Mitsubishi Electric Corp 半導体装置の製造方法

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