JP2007515066A - 固相エピタキシャル再成長を用いて接合の漏損を低減させた半導体基板及び同半導体基板の生産方法 - Google Patents

固相エピタキシャル再成長を用いて接合の漏損を低減させた半導体基板及び同半導体基板の生産方法 Download PDF

Info

Publication number
JP2007515066A
JP2007515066A JP2006544622A JP2006544622A JP2007515066A JP 2007515066 A JP2007515066 A JP 2007515066A JP 2006544622 A JP2006544622 A JP 2006544622A JP 2006544622 A JP2006544622 A JP 2006544622A JP 2007515066 A JP2007515066 A JP 2007515066A
Authority
JP
Japan
Prior art keywords
semiconductor device
producing
amorphous layer
region
semiconductor substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP2006544622A
Other languages
English (en)
Japanese (ja)
Other versions
JP2007515066A5 (https=
Inventor
バルトロミエイ、ジェイ．パウラク
レイモンド、ジェイ．ダフィー
リチャード、リンゼイ
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Koninklijke Philips NV
Original Assignee
Koninklijke Philips NV
Koninklijke Philips Electronics NV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Koninklijke Philips NV, Koninklijke Philips Electronics NV filed Critical Koninklijke Philips NV
Publication of JP2007515066A publication Critical patent/JP2007515066A/ja
Publication of JP2007515066A5 publication Critical patent/JP2007515066A5/ja
Withdrawn legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P30/00—Ion implantation into wafers, substrates or parts of devices
    • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H10P30/202—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping characterised by the semiconductor materials
    • H10P30/204—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping characterised by the semiconductor materials into Group IV semiconductors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0223—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate
    • H10D30/0227—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/601—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/29—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by the substrates
    • H10P14/2901—Materials
    • H10P14/2902—Materials being Group IVA materials
    • H10P14/2905—Silicon, silicon germanium or germanium
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/38—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by treatments done after the formation of the materials
    • H10P14/3802—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P30/00—Ion implantation into wafers, substrates or parts of devices
    • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H10P30/208—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping of electrically inactive species
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P30/00—Ion implantation into wafers, substrates or parts of devices
    • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H10P30/21—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping of electrically active species
    • H10P30/212—Through-implantation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P30/00—Ion implantation into wafers, substrates or parts of devices
    • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H10P30/28—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping characterised by an annealing step, e.g. for activation of dopants

Landscapes

  • Insulated Gate Type Field-Effect Transistor (AREA)
JP2006544622A 2003-12-18 2004-12-02 固相エピタキシャル再成長を用いて接合の漏損を低減させた半導体基板及び同半導体基板の生産方法 Withdrawn JP2007515066A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP03104781 2003-12-18
PCT/IB2004/052644 WO2005062354A1 (en) 2003-12-18 2004-12-02 A semiconductor substrate with solid phase epitaxial regrowth with reduced junction leakage and method of producing same

Publications (2)

Publication Number Publication Date
JP2007515066A true JP2007515066A (ja) 2007-06-07
JP2007515066A5 JP2007515066A5 (https=) 2008-01-24

Family

ID=34707259

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2006544622A Withdrawn JP2007515066A (ja) 2003-12-18 2004-12-02 固相エピタキシャル再成長を用いて接合の漏損を低減させた半導体基板及び同半導体基板の生産方法

Country Status (6)

Country Link
US (1) US8187959B2 (https=)
EP (1) EP1697978A1 (https=)
JP (1) JP2007515066A (https=)
CN (1) CN100477092C (https=)
TW (1) TW200525762A (https=)
WO (1) WO2005062354A1 (https=)

Families Citing this family (47)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101673673B (zh) * 2009-09-22 2013-02-27 上海宏力半导体制造有限公司 外延片形成方法及使用该方法形成的外延片
US8421162B2 (en) 2009-09-30 2013-04-16 Suvolta, Inc. Advanced transistors with punch through suppression
US8273617B2 (en) 2009-09-30 2012-09-25 Suvolta, Inc. Electronic devices and systems, and methods for making and using the same
US8530286B2 (en) 2010-04-12 2013-09-10 Suvolta, Inc. Low power semiconductor transistor structure and method of fabrication thereof
US8569128B2 (en) 2010-06-21 2013-10-29 Suvolta, Inc. Semiconductor structure and method of fabrication thereof with mixed metal types
US8759872B2 (en) 2010-06-22 2014-06-24 Suvolta, Inc. Transistor with threshold voltage set notch and method of fabrication thereof
US8404551B2 (en) 2010-12-03 2013-03-26 Suvolta, Inc. Source/drain extension control for advanced transistors
US8461875B1 (en) 2011-02-18 2013-06-11 Suvolta, Inc. Digital circuits having improved transistors, and methods therefor
US8525271B2 (en) 2011-03-03 2013-09-03 Suvolta, Inc. Semiconductor structure with improved channel stack and method for fabrication thereof
US8748270B1 (en) 2011-03-30 2014-06-10 Suvolta, Inc. Process for manufacturing an improved analog transistor
US8796048B1 (en) 2011-05-11 2014-08-05 Suvolta, Inc. Monitoring and measurement of thin film layers
US8999861B1 (en) 2011-05-11 2015-04-07 Suvolta, Inc. Semiconductor structure with substitutional boron and method for fabrication thereof
US8811068B1 (en) 2011-05-13 2014-08-19 Suvolta, Inc. Integrated circuit devices and methods
US8569156B1 (en) 2011-05-16 2013-10-29 Suvolta, Inc. Reducing or eliminating pre-amorphization in transistor manufacture
US8735987B1 (en) 2011-06-06 2014-05-27 Suvolta, Inc. CMOS gate stack structures and processes
US8995204B2 (en) 2011-06-23 2015-03-31 Suvolta, Inc. Circuit devices and methods having adjustable transistor body bias
US8629016B1 (en) 2011-07-26 2014-01-14 Suvolta, Inc. Multiple transistor types formed in a common epitaxial layer by differential out-diffusion from a doped underlayer
US8748986B1 (en) 2011-08-05 2014-06-10 Suvolta, Inc. Electronic device with controlled threshold voltage
WO2013022753A2 (en) 2011-08-05 2013-02-14 Suvolta, Inc. Semiconductor devices having fin structures and fabrication methods thereof
US8614128B1 (en) 2011-08-23 2013-12-24 Suvolta, Inc. CMOS structures and processes based on selective thinning
US8645878B1 (en) 2011-08-23 2014-02-04 Suvolta, Inc. Porting a circuit design from a first semiconductor process to a second semiconductor process
US8713511B1 (en) 2011-09-16 2014-04-29 Suvolta, Inc. Tools and methods for yield-aware semiconductor manufacturing process target generation
US9236466B1 (en) 2011-10-07 2016-01-12 Mie Fujitsu Semiconductor Limited Analog circuits having improved insulated gate transistors, and methods therefor
US8895327B1 (en) 2011-12-09 2014-11-25 Suvolta, Inc. Tipless transistors, short-tip transistors, and methods and circuits therefor
US8819603B1 (en) 2011-12-15 2014-08-26 Suvolta, Inc. Memory circuits and methods of making and designing the same
US8883600B1 (en) 2011-12-22 2014-11-11 Suvolta, Inc. Transistor having reduced junction leakage and methods of forming thereof
US8599623B1 (en) 2011-12-23 2013-12-03 Suvolta, Inc. Circuits and methods for measuring circuit elements in an integrated circuit device
US8970289B1 (en) 2012-01-23 2015-03-03 Suvolta, Inc. Circuits and devices for generating bi-directional body bias voltages, and methods therefor
US8877619B1 (en) 2012-01-23 2014-11-04 Suvolta, Inc. Process for manufacture of integrated circuits with different channel doping transistor architectures and devices therefrom
US9093550B1 (en) 2012-01-31 2015-07-28 Mie Fujitsu Semiconductor Limited Integrated circuits having a plurality of high-K metal gate FETs with various combinations of channel foundation structure and gate stack structure and methods of making same
US9406567B1 (en) 2012-02-28 2016-08-02 Mie Fujitsu Semiconductor Limited Method for fabricating multiple transistor devices on a substrate with varying threshold voltages
US8863064B1 (en) 2012-03-23 2014-10-14 Suvolta, Inc. SRAM cell layout structure and devices therefrom
US9299698B2 (en) 2012-06-27 2016-03-29 Mie Fujitsu Semiconductor Limited Semiconductor structure with multiple transistors having various threshold voltages
US8637955B1 (en) 2012-08-31 2014-01-28 Suvolta, Inc. Semiconductor structure with reduced junction leakage and method of fabrication thereof
US9112057B1 (en) 2012-09-18 2015-08-18 Mie Fujitsu Semiconductor Limited Semiconductor devices with dopant migration suppression and method of fabrication thereof
US9041126B2 (en) 2012-09-21 2015-05-26 Mie Fujitsu Semiconductor Limited Deeply depleted MOS transistors having a screening layer and methods thereof
US8846510B2 (en) * 2012-10-15 2014-09-30 Taiwan Semiconductor Manufacturing Company, Ltd. Method and structure to boost MOSFET performance and NBTI
CN104854698A (zh) 2012-10-31 2015-08-19 三重富士通半导体有限责任公司 具有低变化晶体管外围电路的dram型器件以及相关方法
US8816754B1 (en) 2012-11-02 2014-08-26 Suvolta, Inc. Body bias circuits and methods
US9093997B1 (en) 2012-11-15 2015-07-28 Mie Fujitsu Semiconductor Limited Slew based process and bias monitors and related methods
US9070477B1 (en) 2012-12-12 2015-06-30 Mie Fujitsu Semiconductor Limited Bit interleaved low voltage static random access memory (SRAM) and related methods
US9112484B1 (en) 2012-12-20 2015-08-18 Mie Fujitsu Semiconductor Limited Integrated circuit process and bias monitors and related methods
US9268885B1 (en) 2013-02-28 2016-02-23 Mie Fujitsu Semiconductor Limited Integrated circuit device methods and models with predicted device metric variations
US9299801B1 (en) 2013-03-14 2016-03-29 Mie Fujitsu Semiconductor Limited Method for fabricating a transistor device with a tuned dopant profile
US9478571B1 (en) 2013-05-24 2016-10-25 Mie Fujitsu Semiconductor Limited Buried channel deeply depleted channel transistor
US9710006B2 (en) 2014-07-25 2017-07-18 Mie Fujitsu Semiconductor Limited Power up body bias circuits and methods
US9319013B2 (en) 2014-08-19 2016-04-19 Mie Fujitsu Semiconductor Limited Operational amplifier input offset correction with transistor threshold voltage adjustment

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5223445A (en) * 1990-05-30 1993-06-29 Matsushita Electric Industrial Co., Ltd. Large angle ion implantation method
JPH0521448A (ja) * 1991-07-10 1993-01-29 Sharp Corp 半導体装置の製造方法
US5858864A (en) * 1994-09-13 1999-01-12 Lsi Logic Corporation Process for making group IV semiconductor substrate treated with one or more group IV elements to form barrier region capable of inhibiting migration of dopant materials in substrate
JPH08203842A (ja) * 1995-01-30 1996-08-09 Sony Corp 半導体装置の製造方法
JPH11168069A (ja) * 1997-12-03 1999-06-22 Nec Corp 半導体装置の製造方法
US6074937A (en) * 1997-12-18 2000-06-13 Advanced Micro Devices, Inc. End-of-range damage suppression for ultra-shallow junction formation
US6063682A (en) 1998-03-27 2000-05-16 Advanced Micro Devices, Inc. Ultra-shallow p-type junction having reduced sheet resistance and method for producing shallow junctions
US6362063B1 (en) * 1999-01-06 2002-03-26 Advanced Micro Devices, Inc. Formation of low thermal budget shallow abrupt junctions for semiconductor devices
US6432802B1 (en) * 1999-09-17 2002-08-13 Matsushita Electronics Corporation Method for fabricating semiconductor device
US6251757B1 (en) * 2000-02-24 2001-06-26 Advanced Micro Devices, Inc. Formation of highly activated shallow abrupt junction by thermal budget engineering
US6645838B1 (en) * 2000-04-10 2003-11-11 Ultratech Stepper, Inc. Selective absorption process for forming an activated doped region in a semiconductor
US6380044B1 (en) * 2000-04-12 2002-04-30 Ultratech Stepper, Inc. High-speed semiconductor transistor and selective absorption process forming same
US6521502B1 (en) * 2000-08-07 2003-02-18 Advanced Micro Devices, Inc. Solid phase epitaxy activation process for source/drain junction extensions and halo regions
US6849528B2 (en) * 2001-12-12 2005-02-01 Texas Instruments Incorporated Fabrication of ultra shallow junctions from a solid source with fluorine implantation
US6555439B1 (en) * 2001-12-18 2003-04-29 Advanced Micro Devices, Inc. Partial recrystallization of source/drain region before laser thermal annealing
CN1286157C (zh) * 2002-10-10 2006-11-22 松下电器产业株式会社 半导体装置及其制造方法
US6936505B2 (en) * 2003-05-20 2005-08-30 Intel Corporation Method of forming a shallow junction
TWI314768B (en) * 2003-09-04 2009-09-11 United Microelectronics Corp Method of manufacturing metal-oxide-semiconductor transistor
WO2005064662A2 (en) * 2003-12-22 2005-07-14 Koninklijke Philips Electronics N.V. A semiconductor substrate with solid phase epitaxial regrowth with reduced depth of doping profile and method of producing same

Also Published As

Publication number Publication date
TW200525762A (en) 2005-08-01
WO2005062354A1 (en) 2005-07-07
CN100477092C (zh) 2009-04-08
CN1894777A (zh) 2007-01-10
EP1697978A1 (en) 2006-09-06
US20090140242A1 (en) 2009-06-04
US8187959B2 (en) 2012-05-29

Similar Documents

Publication Publication Date Title
US8187959B2 (en) Semiconductor substrate with solid phase epitaxial regrowth with reduced junction leakage and method of producing same
US6682980B2 (en) Fabrication of abrupt ultra-shallow junctions using angled PAI and fluorine implant
US7118980B2 (en) Solid phase epitaxy recrystallization by laser annealing
US5766969A (en) Multiple spacer formation/removal technique for forming a graded junction
US6008099A (en) Fabrication process employing a single dopant implant for formation of a drain extension region and a drain region of an LDD MOSFET using enhanced lateral diffusion
EP1068637A1 (en) Reduced channel length lightly doped drain transistor using a sub-amorphous large tilt angle implant to provide enhanced lateral diffusion
US7833886B2 (en) Method of producing a semiconductor element in a substrate
US20060284249A1 (en) Impurity co-implantation to improve transistor performance
US8101487B2 (en) Method for fabricating semiconductor devices with shallow diffusion regions
US20080311732A1 (en) Method for Forming Non-Amorphous, Ultra-Thin Semiconductor Devices Using Sacrificial Implantation Layer
US6117719A (en) Oxide spacers as solid sources for gallium dopant introduction
US9087772B2 (en) Device and method for forming sharp extension region with controllable junction depth and lateral overlap
KR100212010B1 (ko) 반도체 소자의 트랜지스터 제조방법
JP3744895B2 (ja) Ｃｍｏｓ型半導体装置の製造方法
WO2005096357A1 (ja) 半導体装置の製造方法
US7348229B2 (en) Method of manufacturing a semiconductor device and semiconductor device obtained with such a method
US8357595B2 (en) Semiconductor substrate with solid phase epitaxial regrowth with reduced depth of doping profile and method of producing same
KR100422326B1 (ko) 반도체 소자의 제조방법
JPH07321313A (ja) 半導体デバイスの製造方法
KR101013544B1 (ko) 반도체 소자의 제조방법
WO2005062352A1 (en) A semiconductor substrate with solid phase epitaxial regrowth with reduced junction leakage and method of producing same

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20071129

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20071129

A711 Notification of change in applicant

Free format text: JAPANESE INTERMEDIATE CODE: A711

Effective date: 20080619

A761 Written withdrawal of application

Free format text: JAPANESE INTERMEDIATE CODE: A761

Effective date: 20091013