JP2007324163A - Inspection method of semiconductor element - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an inspection method of a semiconductor element in which inspection efficiency can be enhanced. <P>SOLUTION: The method for inspecting semiconductor elements arranged on a semiconductor wafer comprises a defective position inspection step for performing inspection only of semiconductor elements existing in at least two linear directions, on a plane where the semiconductor elements are arranged; a step for specifying a defective region where a defective semiconductor element exists on the semiconductor wafer, based on the position of a semiconductor element which is specified to be defective at the defective position specifying step; and a main inspection step for performing inspection only for a specified defective region. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to an inspection method for inspecting semiconductor elements arranged on a semiconductor wafer in a semiconductor element manufacturing process.

  A conventional semiconductor element such as a solid-state imaging element is formed by performing processes such as an exposure process, a development process, and an etching process on one surface of a substantially disk-shaped semiconductor wafer. At this time, the semiconductor elements are formed on the semiconductor wafer in a predetermined arrangement such as a lattice shape.

  In the manufacturing process of semiconductor elements, defects and defects may occur when multiple treatments are performed on each semiconductor element. Therefore, all types of inspections necessary to ensure the performance of the semiconductor elements are performed. It is necessary to carry out semiconductor elements. Examples of such defect inspection of semiconductor elements include the following Patent Documents 1 to 3.

JP-A-9-145627 JP-A-11-219997 JP 2003-7779 A

  However, when inspecting a semiconductor element on a semiconductor wafer, it is necessary to perform the same inspection for all the semiconductor elements. Even in the case of a configuration in which a single or a plurality of semiconductor elements are measured simultaneously, the inspection efficiency is constant. There was room for improvement because it could not be improved. Further, as defects generated in the semiconductor element, for example, uneven coating of the color filter affects the semiconductor element existing in a predetermined region on the peripheral side of the semiconductor wafer due to spin coating applied to the semiconductor wafer. However, there is no effect on the semiconductor elements existing in other regions. As described above, since there is a tendency that many defects are found only in a semiconductor element existing in a partial region of the semiconductor wafer in the manufacturing process of the semiconductor element, inspecting all the semiconductor elements improves the inspection efficiency. Since this is not preferable, there has been a demand for optimization in which a predetermined area is an inspection target.

  The present invention has been made in view of the above circumstances, and an object thereof is to provide a method for inspecting a semiconductor element capable of improving inspection efficiency.

  The object of the present invention is an inspection method for inspecting semiconductor elements arranged on a semiconductor wafer, and inspects only semiconductor elements existing in at least two linear directions on the surface on which the semiconductor elements are arranged. A defect location inspection step, and a defect region identification step for identifying a defect region in which a semiconductor element having a defect exists on the semiconductor wafer based on a position of the semiconductor element identified as a defect in the defect location inspection step; And a main inspection step of performing inspection only on the identified defective area. This is achieved by a method for inspecting a semiconductor device.

  According to the present invention, only the semiconductor elements existing in two linear directions among the semiconductor elements arranged on the semiconductor wafer are inspected, and the defect area is identified after the defect area is identified from the position of the defective semiconductor element. Inspection is performed only on the defective area. In this way, even if there is a tendency that many defects are found only in the semiconductor elements existing in a partial region of the semiconductor wafer in the manufacturing process of the semiconductor element, it is not necessary to inspect all the semiconductor elements, and the defective region The inspection time can be shortened by making only the semiconductor elements present in the inspection object to be inspected, and the inspection efficiency can be improved.

  In the present invention, it is preferable that a predetermined inspection is omitted for the identified defective area or an area other than the defective area. By doing so, the time required for the inspection can be further shortened, and the inspection efficiency is improved.

  ADVANTAGE OF THE INVENTION According to this invention, the test | inspection method of the semiconductor element which can improve test | inspection efficiency can be provided.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
FIG. 1 is a diagram for explaining a semiconductor element inspection method according to the present invention. Hereinafter, as a semiconductor element of the present embodiment, a solid-state imaging element will be described as an example, but the invention is not particularly limited thereto. Although not shown, the solid-state imaging device includes, for example, a photoelectric conversion unit such as a photodiode formed on a semiconductor substrate, and a charge transfer unit that transfers charges generated in the photoelectric conversion unit, and each of the photoelectric conversion units One of RGB color filters is formed above.

  As shown in FIG. 1, a chip T having a configuration of a solid-state imaging device is exposed on one surface (upper surface in FIG. 1) of a substantially disk-shaped semiconductor wafer W made of a silicon substrate or the like. It is formed by performing processes such as processes.

  The chips T are arranged in a lattice pattern with the adjacent chips and dicing lines L as boundaries in a state in which the semiconductor wafer is viewed in plan. The chip arrangement pattern is not particularly limited as long as the semiconductor wafer is arranged in a predetermined pattern in a plan view.

  An inspection mechanism for inspecting semiconductor elements has a defect by inputting image data detected by the tester 11 that detects image data of the arranged semiconductor elements and the tester 11, and analyzing the input image data. And a processing unit 12 that executes a process of extracting a thing. Further, the inspection mechanism may include a storage unit such as a memory for storing image data input from the tester 11. As the processing unit 12, for example, an arithmetic processing device such as a personal computer can be used. Alternatively, as the tester 11, a detection device that has both the function of detecting image data from a semiconductor element and the function of the processing unit 12 may be used.

  The tester 11 includes a detection unit for acquiring image data from each of the semiconductor elements arranged on the semiconductor wafer W. Note that the tester 11 may be configured to acquire image data of each of the semiconductor elements by the detection unit, or may be configured to acquire image data of a plurality of semiconductor elements at the same time.

  The detection unit of the tester 11 is configured to be drive-controllable in a two-dimensional direction parallel to the upper surface of the semiconductor wafer W.

  Next, the procedure of the inspection method of this embodiment will be described. In the present embodiment, a procedure for inspecting a luminance defect of an image caused by uneven coating such as a color filter will be described as an example. In the inspection of the luminance defect, the irradiation light is constantly supplied from the light source fixed toward the imaging area of the chip, and the luminance is calculated based on the image data acquired from the chip at this time.

  FIG. 2 is a diagram showing the procedure of the inspection method. 3, 5 and 6 are views showing the semiconductor wafer in plan view. FIG. 4 is a graph showing the luminance distribution of the semiconductor element.

  First, only the semiconductor elements existing on a predetermined straight line on the surface on which the chips (semiconductor elements) T arranged on the semiconductor wafer W are arranged are inspected (step S11). This process is referred to as a defect position inspection process.

  In the present embodiment, as shown in FIG. 3, along the four straight lines D1, D2, D3, and D4 in the semiconductor wafer W, image data is acquired by the tester 11 for each of the chips T existing on the straight lines. Perform a luminance test. Specifically, first, for the chips T existing on the straight line D1, the luminance inspection of the chips T is sequentially performed in the direction of the straight line D1. After the luminance inspection of all the chips T existing on the straight line D1 is completed, the luminance inspection of the chips T existing on the straight line D2 is sequentially performed along the arrow direction of the straight line D2. Similarly, the luminance inspection of the chip T is performed along the straight lines D3 and D4.

In this embodiment, in the defect position inspection process, the chips T existing on the four straight lines are inspected. However, if the chips T existing on the at least two straight lines are inspected, they are defined by these straight lines as will be described later. Can be defined.
In the present embodiment, the straight line D1 and the straight line D3 are in a positional relationship orthogonal to each other, and the straight line D2 and the straight line D4 are in a positional relationship orthogonal to each other. In general, in a disk-shaped semiconductor wafer, the performance is likely to change between the peripheral side and the center side because of the processing technique applied in the manufacturing process. For this reason, as in this embodiment, a plurality of straight lines intersect with each other in the vicinity of the center in a plan view of the semiconductor wafer, and the linear directions to be inspected are each defined radially so that the chips T arranged on the semiconductor wafer are aligned. The performance can be checked more accurately.

  At this time, the luminance data of each chip T acquired by the tester 11 is input to the processing unit 12, and the processing unit 12 detects the luminance distribution for each chip T based on the luminance data.

  As shown in FIG. 4, in a chip with uniform luminance, the luminance distribution has a predetermined range of width C. However, in a chip in which a defect is partially generated, the luminance distribution exceeds the predetermined width C. A luminance distribution appears in the range. In other words, the width C of the luminance distribution takes an abnormal range in the semiconductor element located at the boundary of the region where the defect occurs. Therefore, the luminance distribution is analyzed, and if the luminance distribution width C is within a predetermined threshold range, no defect is present. On the other hand, the luminance distribution width C exceeds a predetermined threshold range. Is defective, and the chip T is determined to be defective.

  The position of the chip T determined to be a defect is stored in the storage unit of the processing unit 12 as position information represented by coordinates in which the surface of the semiconductor wafer on which the chip T is arranged is a two-dimensional space, for example. In this embodiment, a luminance defect is detected at the chips at positions P11 and P12 on the straight line D1, a luminance defect is detected at the chips at positions P21 and P22 on the straight line D2, and the chips at positions P31 and P32 on the straight line D3. It is assumed that a luminance defect is detected and a luminance defect is detected at the chips at positions P41 and P42 on the straight line D4.

  Next, based on the positions P11, 12, P21, 22, P31, 32, P41, 42 of the chips identified as defective as described above, defects having defective chips on the semiconductor wafer W exist. A defect area specifying step for specifying an area is performed (step S12).

  In the present embodiment, application unevenness of the color filter, which is one of the causes of luminance defects, is assumed. In general, since a color filter material layer is formed by spin coating, a color filter has been recognized to have unevenness due to the peripheral edge of the semiconductor wafer becoming thick due to centrifugal force during rotation of the semiconductor wafer. For this reason, as shown in FIG. 6, a substantially circumferential line including the positions P11, 12, P21, 22, P31, 32, P41, 42 of the defective chip is used as a boundary line, and the outer peripheral side of this boundary line. A chip present in the region A can be defined as a defective region having a high possibility of being defective. On the other hand, for the chip existing in the region B on the inner peripheral side from the boundary line including the defective chip positions P11, 12, P21, 22, P31, 32, P41, 42, this inspection is performed assuming that there is no defect. Can be omitted.

  After the defect area is specified, the main inspection process (step S13) for executing a predetermined inspection is performed only for the specified defect area A.

  Usually, in the manufacturing process of a semiconductor element, inspection is performed for several tens or more kinds of inspection items for all the chips T, but by specifying the defect area A for each predetermined performance as in this embodiment. It is preferable to omit a predetermined inspection for the chip T existing in the specified defect area A or the area B other than the defect area A. By doing so, the time required for the inspection can be further shortened, and the inspection efficiency is improved.

  In the manufacturing method of the present embodiment, only the semiconductor elements existing in two linear directions among the semiconductor elements (chips T) arranged on the semiconductor wafer W are inspected, so that the defect is detected from the position of the defective semiconductor element. After the area is specified, the inspection is executed only for the specified defective area. In this way, even if there is a tendency that many defects are found only in the semiconductor elements existing in a partial region of the semiconductor wafer in the manufacturing process of the semiconductor element, it is not necessary to inspect all the semiconductor elements, and the defective region The inspection time can be shortened by making only the semiconductor elements present in the inspection object to be inspected, and the inspection efficiency can be improved.

It is a figure explaining the test | inspection method of the semiconductor element concerning this invention. It is a figure which shows the procedure of an inspection method. It is a figure which shows the state which planarly viewed the semiconductor wafer. It is a graph which shows the luminance distribution of a semiconductor element. It is a figure which shows the state which planarly viewed the semiconductor wafer. It is a figure which shows the state which planarly viewed the semiconductor wafer.

Explanation of symbols

T chip (semiconductor element)
W Semiconductor wafer

Claims (2)

An inspection method for inspecting semiconductor elements arranged on a semiconductor wafer,
A defect position inspection process for inspecting only semiconductor elements existing in at least two linear directions on the surface where the semiconductor elements are arranged;
In the defect position inspection step, a defect region specifying step for specifying a defect region in which a semiconductor element having a defect on the semiconductor wafer exists based on the position of the semiconductor element specified to be a defect;
And a main inspection step for inspecting only the specified defective area. 2. The method for inspecting a semiconductor device according to claim 1, wherein a predetermined inspection is omitted for the identified defective area or an area other than the defective area.

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