WO2012135513A1

WO2012135513A1 - Method of manufacturing semiconductor devices

Info

Publication number: WO2012135513A1
Application number: PCT/US2012/031235
Authority: WO
Inventors: Xin Song; Leonard LABUA; Michael PLISINSKI
Original assignee: Rudolph Technologies, Inc.
Priority date: 2011-03-31
Filing date: 2012-03-29
Publication date: 2012-10-04
Also published as: TWI564981B; TW201308461A

Abstract

A method of manufacturing semiconductor devices having a consistently higher yield is herein disclosed. Defects identified on unpatterned and patterned substrates are accurately positioned and aligned with respect to one another. Better informed process control decisions may be made based upon the properly aligned defects, which are typically expressed in one or more wafer maps.

Description

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES

TECHNICAL FIELD

[01] The present invention relates generally to the fabrication of semiconductor devices and methods for managing such fabrication. More specifically, the present invention relates to methods for improving the likelihood that semiconductor devices obtained from a fabrication process will function as specified upon completion.

BACKGROUND

[02] The processes used to manufacture semiconductor devices involve many steps, are highly complex and extremely expensive. The requisite large investments in terms of infrastructure, materials and time militate in favor of careful control of the yield of the semiconductor fabrication processes. Identifying process excursions and material defects early in the fabricating process at a time when problems can be ameliorated via re-work or by selectively scrapping portions or all of a semiconductor substrate or group of substrates is desirable.

[03] Defects in the semiconductor substrate are often detected by means of optical inspection. Other forms of metrology and inspection may also be used to identify defects. Examples of techniques useful for identifying defects in process excursions include, but are not limited to optical inspection and/or detection at various wavelengths of light and at various resolutions, ellipsometry, reflectometry, scatterometry, opto-acoustic techniques, e- beam inspection, scanning electron microscopy, atomic force microscopy, infrared microscopy, UV microscopy, interferometric techniques, and visible light microscopy.

[04] By way of definition, the term "defect" will be used to broadly refer to any feature or characteristic of a semiconductor substrate that is undesirable. A feature or characteristic is undesirable if it reduces the operability of a semiconductor device or group of semiconductor devices on one or more substrates in which the feature or characteristic appears. A feature or characteristic is also undesirable where it tends to reduce a yield of a semiconductor fabrication process. Yield is defined as the ratio of semiconductor devices of acceptable quality to the number of semiconductor devices that were started. Based on these definitions it may be possible for a feature or characteristic to be a defect in some circumstances and not in others. Where a feature or characteristic such as contamination, particles, dose/exposure errors, defocus errors, layer thickness variation, or cracks reduce the yield of a semiconductor process by rendering one or more semiconductor devices unreliable or unworkable, that feature or characteristic will be considered defect. Where a feature or characteristic does not negatively affect the yield of a semiconductor fabrication process or where the negative effect on yield is acceptable, the feature or characteristic may not be considered a defect.

[05] One can appreciate a careful and continuous monitoring of features and characteristics of all types is important to be able to distinguish between features and characteristics that are defects and those that are not but which might become defects under changed conditions, i.e. different applications or processing conditions. In addition to monitoring the semiconductor fabricator process, careful tracking of features and characteristics and measurements of yield are used to inform the design and specification of semiconductor devices.

[06] One problem encountered in monitoring features and characteristics is that it may be difficult to spatially align a defect that occurs or appears early in the semiconductor fabrication process with patterns or semiconductor devices that may appear on a semiconductor substrate later in the process. It is also desirable to ensure that an early defect can be confidently located with respect to a specific semiconductor device in which the feature or characteristic is present. This can be particularly difficult for a feature or characteristic is present before a pattern(s) on the substrate against which the locations of the feature or characteristic can be compared or validated. What is more, any errors introduced in locating features and characteristics can be compounded where the semiconductor devices being manufactured are quite small. It is possible in these instances to incorrectly associate a defect with a semiconductor device or devices in which the defect is not present. Process engineers responsible for many maintaining and monitoring a semiconductor fabrication process will often fail an over-large number of semiconductor devices in order to avoid accidentally including or identifying for full processing semiconductor devices that may be defective. Being able to confidently determine the location of a defect and accurately identify semiconductor devices, and only those semiconductor devices, that are affected by the defect is key to improving the yield of a semiconductor fabrication process. [07] By properly identifying and tracking features or characteristics and by enabling the accurate positioning of such things, it is possible to produce a semiconductor device that is much more likely to be functional and to have a lower cost when put into operation.

[08] Accordingly, there is a need for some way in which a defect of a semiconductor substrate can be properly associated with its correct location on a semiconductor substrate. It would also be advantageous to ensure that a defect is properly associated with the semiconductor device or devices that are affected by the defect.

SUMMARY

[09] One method for manufacturing semiconductor devices of high quality and high profitability involves ensuring that all defects identified on a substrate have their position accurately identified. This this embodiment of the present invention starts with inspecting an unpattemed substrate to identify one or more defects on the substrate, if any are present. The position and orientation of each defect found on the substrate is recorded. Later, a subsequent processing step is performed on the substrate. Generally this results in some form of pattern being formed on the substrate. This and now-patterned substrate is inspected and defects, if any, are identified and their positions and orientations are recorded. Given that at least a portion of the defects identified on the unpattemed substrate will be found on the now- patterned substrate, it is possible to spatially align those defects found on the unpattemed substrate with those defects found on the now-patterned substrate. This alignment produces a positional transformation that may be used to modify the recorded positions of the defects found on either of the unpattemed or patterned substrates. Fig. 4 schematically illustrates how respective patterns of defects may be aligned using a derived positional transformation identified as an offset in an X. direction, an offset in a wide direction, and a rotational offset Theta.

[10] Once accurate alignment has taken place, process control determinations may be made with more confidence. Subsequently, semiconductor fabrication processes operate at higher yields and are more profitable.

BRIEF DESCRIPTION OF THE DRAWINGS

[11] Fig. 1 is a schematic view of an optical system that may be used as part of the present invention. [12] Fig. 2a is a schematic representation of a substrate having an alignment feature referred to as a flat formed therein.

[13] Fig. 2b is a schematic representation of a substrate having an alignment feature referred to as a notch formed therein.

[14] Fig. 3 is a schematic representation of a substrate having a pattern formed thereon.

[15] Fig. 4 is a schematic representation illustrating a positional transformation between patterns of defects identified on a substrate at different process steps.

DETAILED DESCRIPTION

[16] In the following detailed description, reference is made to the accompanying drawings that form a part hereof, and in which is shown, by way of illustration, specific embodiments in which the invention may be practiced. In the drawings, like numerals describe substantially similar components throughout the several views. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention. Other embodiments may be utilized and structural, logical, and electrical changes may be made without departing from the scope of the present invention. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present invention is defined only by the appended claims and equivalents thereof.

[17] Alignment of defects identified on unpattemed substrates with semiconductor devices that are later formed on the same substrates starts with the step of identifying defects on both the patterned and unpattemed substrates. Fig. 1 illustrates schematically one type of inspection or metrology system that may be used to identify defects on a substrate S The optical inspection system 10 illustrated in Fig. 1 is similar to the type of inspection system described in claimed in US patent number 6,826,298, the subject matter of which is incorporated herein in its entirety.

[18] The optical inspection system 10 includes a camera 14 and an illuminator 12 that are constructed and arranged to capture an image or images of a substrate S light from the illuminator 12 is directed onto an optical axis of the camera 14 along path 16. Note that path 16 is in the illustration of Fig. 1 in optical fiber. However, radiation from illuminator 12 may be directed onto an optical axis of the camera 14 using turning mirrors or other optical elements (not shown) types that are commonly available and known to those skilled in the art. A beam splitter 18 couples light radiation from the illuminator 12 into an optical axis of the camera 14 such that the light from the illuminator 12 is incident on the substrate S and at a substantially normal incidence. Light is returned from the substrate S to a suitable sensor (not shown) of the camera 14, which captures an image of the substrate S Note that the camera 14 may be of any useful configuration and may include any useful type of sensor, including sensors that capture data that might be referred to as an image but which is not viewable in the traditional sense in which photographs are viewable. For example, the camera 14 may be an area scan camera, a line scan camera, or an array of point sensors. Suitable sensors may include, but are not limited to, charged-coupled devices (CCD), complementary metal-oxide semiconductor sensors (CMOS), intensified charge-coupled device (ICCD) sensors, photomultiplier tube (PMT), and photodiode sensors of various types.

[19] In addition to illuminator 12, an additional or alternative illuminator 13 may be provided. In general, illuminator 12 is used for what is typically referred to a brightfield illumination. Illuminator 13, which directs light at any useful wavelength toward the substrate S at a low, grazing angle that would not normally be reflected along the optical axis of the camera 14, is adapted for what is commonly referred to as dark field illumination.

[20] In some embodiments, images of substrates S may be analyzed or assessed on an image by image basis, on a regional basis (i.e. as groups of images), on a pixel by pixel basis, as groups of pixels, or on a concatenated basis in which all images of a substrate S are analyzed or assessed together. In one embodiment, images of an entire substrate S may be stitched together to form one large image of the entire substrate S In another embodiment, images and similar data may be recorded together in a data structure that represents the entire substrate S without stitching each individual image together. In these latter embodiments, such a data structure is often referred to as a wafer.- In addition to arranging images of the entire substrate S with respect to one another, additional information about the substrate S may be recorded. Examples of this type of information include a location of one or more defects that may have been identified on the substrate. Other useful information that may be recorded in a wafer map includes the metrology data, such as layer thickness or critical dimension. Those skilled in the art will readily understand the nature and extent of information that may be saved in a wafer map.

[21] Figs. 2a and 2b illustrate schematically two wafer map representations of a substrate S. In Fig. 2a the substrate S is a semiconductor wafer having an alignment structure called a flat 20 formed in one edge. The flat 20 is used by an automated system to properly align the substrate S with an inspection, metrology, or processing system. Fig. 2b illustrates a substrate S having a notch 22 that serves the same purpose as the flat 20 illustrated in Fig. 2a. Each of these substrates illustrated in Figs. 2a and 2b are substantially unpattemed in that they have not had any formal structure formed thereon. It can be seen however that each of the substrates S illustrated in Figs. 2a and 2b has a number of defects D thereon. As described above, these defects D may be chips, cracks, particles, discolorations, scratches or other unwanted features formed into or deposited upon the surface of the substrates S.

[22] Unpattemed substrates S such as those illustrated in Figs. 2a and 2b are typically inspected and/or analyzed before being processed. It is this inspection and analysis that is used to identify identifies defects D shown in the Figures. Provided that each of the substrate S is of acceptable quality, that is the nature, size, density, and/or gross number of defects D found on a substrate S is acceptable to a process engineer responsible for managing the semiconductor fabrication process, the unpattemed substrate S will be subjected to subsequent semiconductor fabrication processes. These processes may include, but are not limited to, etching, grinding, deposition, washing, inspection, metrology, and the like. In addition to furthering the progress of an unpattemed substrate S towards a fully patterned substrate S, each step in the fabrication process may introduce additional defects. Accordingly, it is common practice for substrates S to be inspected or analyzed multiple times during the fabrication process.

[23] Fig. 3 illustrates a substrate S that has been at least partially patterned. As can be seen, individual semiconductor devices 26 have been formed on the substrate S. The wafer map representation of the substrate S in Fig. 3 also includes information concerning defects D identified on the substrate S. It has been found that in general, at least a portion of the defects D found on a patterned substrate S will correspond to defects D found on an unpattemed substrates such as those illustrated in Figs. 2a and 2b. However, because of the inherent uncertainty involved in the location of defects D found an unpattemed wafers, it is undesirable to simply concatenate information obtained from an unpattemed substrate S with information obtained from a patterned substrate S into a single wafer map. Rather, it is preferable to match a pattern formed by defects D found on an unpattemed substrate S with a pattern of defects D found on a patterned substrate S. In doing so, one may obtain a positional transform that may be used to properly align images and/or data from an unpattemed substrate with images and/or data from a patterned substrate. In describing the relative assessment of patterned an unpattemed substrates, it is important to keep in mind that one is to compare the same substrate at its multiple stages in the semiconductor fabrication process. In other words, defects identified on an unpattemed substrate S are aligned with defects found on the same substrate S after it has been patterned, which defects are essentially the same defects. Note that the term "patterned" as used herein has broad meaning and refers to any process step but may change the structure of the substrate S.

[24] The alignment of defects D identified on an unpattemed substrate S with defects D^' found on the same substrate S at a later, patterned state may be accomplished using any suitable intensity or feature-based alignment or registration algorithm. Some examples include, but are not limited to, spatial pattern matching algorithms such as RANSAC and frequency-domain pattern matching algorithms such as phase correlation methods. Having obtained a positional translation, typically in an X, Y, and Θ notation though vector and other notations may also be used, one may modify the previously assigned position of defects D identified on an unpattemed substrate S so as to align them with the same defects D that are viewable on a later stage patterned substrate S. In other words, the defects identified on the unpattemed substrate S are aligned with themselves after intermediate process steps have been performed on the substrate S. Typically the alignment of data is performed by modifying the identified position of defects in a wafer map that represents the unpattemed substrate S While it is also possible to modify data in wafer maps representing patterned substrates S, it is typically the case that fewer steps would be required to modify the wafer map representative of an unpattemed substrate S.

[25] It must be pointed out that many of the defects identified on an unpattemed substrate S may not be viewable after that substrate has been patterned or otherwise subjected to subsequent processing steps. In one embodiment a process engineer may identify a subset of defects D found on an unpattemed substrate S that will be used as fiducials for alignment purposes. This identification or selection process may be made on any of a number of criteria including, but not limited to the location of a defect, its size, aspect ratio, or any other suitable criteria, keeping in mind that these criteria will generally be related to the likelihood of that effect appearing on the substrate S after later processing steps have been performed. In other embodiments, alignment or registration algorithms will use all identified defects from a patterned and unpattemed substrate for alignment purposes. In those embodiments where all identified defects are used for alignment purposes, certain restrictions may be placed upon the algorithms to prevent incorrect alignments. For example, where the largest expected offset between patterns of defects is 200 μ, positional transformations that require a shift of more than 200 μ may be omitted from the set of possible solutions. Similar limitations may be placed on rotational transformations.

[26] While it is possible to perform alignments as described above repeatedly, it is often the case that one will only need to perform an alignment between a pattern of defects that has been identified on an unpatterned substrate and a pattern of defects that has been identified on a patterned substrate once.

[27] In addition to aligning patterns of defects found on unpatterned and patterned substrates, a step of the present invention may also be used to identify variation between inspection systems. For example, comparing a wafer map that identifies the position of defects on a patterned or unpatterned substrate with a wafer map of the same substrate that purports to identify the position of the identical defects on the substrate may identify differences between respective inspection systems. This is particularly useful when different inspection systems are used at different points in the fabrication process for a semiconductor device. Where the same inspection system is used on substrates at respective steps in the fabrication process, the images of the substrate will be subject to the same optical aberrations and distortions. Accordingly, it is often the case that only alignment will be required. However, or inspection systems from different manufacturers are used or where different models of inspection systems are used, respectively for maps may be formed based on differing types and degrees of optical aberration and distortion. In this instance, alignment may take place between wafer maps produced by respective inspection systems. Furthermore, this alignment may be performed as between defect patterns found on unpatterned and patterned substrates or between defect patterns found on respective patterned substrates.

[28] Once alignment has been accomplished, a process engineer responsible for managing the fabrication of semiconductor devices on a substrate S may more confidently assess the quality of a substrate S and the semiconductor devices 26 formed thereon. Further, better alignment may allow yield management systems (YMS), automatic defect classification systems (ADC), and electronic data analysis (EDA) systems to more accurately identify defects, identify process excursions, determine root causes, modify process scheduling, re-work substrates, and determine pass/fail status for individual semiconductor devices, for semiconductor devices on portions of a substrate, and for all of the semiconductor devices on a substrate. As a result, the output of a semiconductor fabrication process or system that utilizes the present invention may have a higher yield, be of higher quality, and be more profitable.

CONCLUSION

[29] While various examples were provided above, the present invention is not limited to the specifics of the examples. Although specific embodiments of the present invention have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that any arrangement that is calculated to achieve the same purpose may be substituted for the specific embodiments shown. Many adaptations of the invention will be apparent to those of ordinary skill in the art. Accordingly, this application is intended to cover any adaptations or variations of the invention. It is manifestly intended that this invention be limited only by the following claims and equivalents thereof.

Claims

What is claimed is:

A method of manufacturing a semiconductor device comprising:

inspecting a substantially unpattemed substrate to identify one or more defects, if any are present;

recording a position for each of at least a portion of any identified defects found on the substantially unpattemed substrate;

performing a processing step on the substrate to form at least a portion of a pattern thereon;

inspecting the now-patterned substrate to identify one or more defects thereon, if any are present;

recording a position for each of at least a portion of any identified defects found on the now-patterned substrate; and,

aligning a spatial pattern defined by the at least a portion of any identified defects found on the substantially unpattemed substrate with a spatial pattern defined by the at least a portion of any identified defects found on the now-patterned substrate, the alignment of the respective spatial patterns of identified defects providing a positional transform between the position of defects identified on the substantially unpattemed substrate and the at least a portion of a pattern formed on the substrate.

The method of manufacturing a semiconductor device of claim 1 comprising:

providing an x, y positional offset and an angular offset to define a positional

transform for identifying the position of a defect identified on the substantially unpattemed substrate in terms of the position of the subsequently formed at least partial pattern formed on the substrate.

The method of claim 2 further comprising:

modifying a predefined process step, the modified process step being subsequently applied to the semiconductor substrate, the modification of the predefined process step being based at least in part on the aligning step. The method of claim 2 further comprising:

modifying a predefined process step, the modified process step being subsequently applied to at least one semiconductor device on the semiconductor substrate, the modification of the predefined process step being based at least in part on the aligning step.

The method of claim 2 further comprising:

omitting a semiconductor device formed on a semiconductor substrate from additional processing based at least in part on the aligning step.

The method of claim 2 further comprising:

performing, subsequent to the aligning step, at least one processing step on a set of semiconductor devices identified at least in part on the aligning step.

A method of manufacturing semiconductor devices in which an output of the manufacturing method is obtained, at least in part, by aligning identified defects identified on a substantially unpattemed substrate with defects found on the same, subsequently patterned substrate.

The method of claim 7 wherein the aligning step is used, at least in part, to omit a number of semiconductor devices from further processing, a balance of the semiconductor devices being subjected to subsequent processing having a generally higher perceived quality than those semiconductor devices omitted from further processing.

The method of claim 7 wherein the aligning step is used, at least in part, to subject a number of semiconductor devices to further processing, the further processed semiconductor devices having a perceived quality that is approximately the same as those semiconductor devices omitted from further processing.

A method of manufacturing a semiconductor device comprising:

identifying defects on a substrate at two or more stages in a manufacturing process; representing the defects found on the substrate at the two or more stages in the

manufacturing process has respective wafer maps; aligning the defects in at least two of the respective wafer maps to ensure proper alignment and identification of defects.

The method of manufacturing a semiconductor device of claim 10 comprising:

aligning defects identified in a wafer map representative of an unpattemed substrate with defects identified in a wafer map representative of a patterned substrate, both wafer maps being derived from the same substrate.

The method of manufacturing a semiconductor device of claim 11 comprising:

aligning defects identified in a wafer map representative of an unpattemed substrate with defects identified in a wafer map representative of a patterned substrate, both wafer maps being derived from the same substrate, the aligning step further identifying a position of each aligning defect with respect to the pattern formed on the patterned substrate.